August 2010 - U-Boot

[U-Boot] [PATCH 6/8] APM82xxx: Add SRAM support
by tmarri＠apm.com 30 Aug '10

30 Aug '10

From: Tirumala Marri <tmarri(a)apm.com> This patch adds L2Cache/SRAM and OCM register definitions. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- arch/powerpc/include/asm/ppc4xx-isram.h | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac..b723401 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||\ + defined(CONFIG_APM82XXX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) ||\ + defined(CONFIG_APM82XXX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -60,7 +62,7 @@ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ -- 1.6.1.rc3

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[U-Boot] [PATCH 1/8] APM82xxx: Add CPU support
by tmarri＠apm.com 30 Aug '10

30 Aug '10

From: Tirumala Marri <tmarri(a)apm.com> APM82XXX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri(a)apm.com> --- arch/powerpc/cpu/ppc4xx/cpu.c | 35 +++++++++++++++++++++++++++++++-- arch/powerpc/cpu/ppc4xx/cpu_init.c | 9 ++++--- arch/powerpc/cpu/ppc4xx/start.S | 10 +++++++- arch/powerpc/include/asm/processor.h | 1 + 4 files changed, 46 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065c..5fe5d8c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -80,7 +80,8 @@ static int pci_async_enabled(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ - !defined(CONFIG_405) && !defined(CONFIG_405EX) + !defined(CONFIG_405) && !defined(CONFIG_405EX) && \ + !defined(CONFIG_APM82XXX) int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) @@ -250,6 +251,21 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM82XXX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -285,7 +301,7 @@ int checkcpu (void) uint pvr = get_pvr(); ulong clock = gd->cpu_clk; char buf[32]; -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || defined(CONFIG_APM82XXX) u32 reg; #endif @@ -304,6 +320,8 @@ int checkcpu (void) #if defined(CONFIG_XILINX_440) puts("IBM PowerPC 4"); +#elif defined(CONFIG_APM82XXX) + puts("APM PowerPC APM82"); #else puts("AMCC PowerPC 4"); #endif @@ -316,7 +334,7 @@ int checkcpu (void) #if defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) puts("60"); -#else +#elif !defined(CONFIG_APM82XXX) puts("40"); #endif #endif @@ -598,7 +616,18 @@ int checkcpu (void) puts("GX Rev. A"); strcpy(addstr, "No Security support"); break; +#if defined(CONFIG_APM82XXX) + case PVR_APM82XXX_RA: + mfsdr(SDR0_ECID3, reg); + if (reg & 0x00200000) + puts("181 Rev. A"); + if (reg & 0x00100000) + strcpy(addstr, "No Security support"); + else + strcpy(addstr, "Security support"); + break; +#endif case PVR_VIRTEX5: puts("x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..2308051 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SYS_PLL_RECONFIG #define CONFIG_SYS_PLL_RECONFIG 0 #endif - #if defined(CONFIG_440EPX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) static void reset_with_rli(void) @@ -222,13 +221,15 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) ||\ + defined(CONFIG_460EX) || defined(CONFIG_APM82XXX) u32 val; #endif reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if (defined(CONFIG_405EP) || defined(CONFIG_405EX)) && \ + !defined(CONFIG_SYS_4xx_GPIO_TABLE) && !defined(CONFIG_APM82XXX) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -384,7 +385,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM82XXX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..9cb818d 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -700,7 +700,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM82XXX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -728,7 +729,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) ||\ + defined(CONFIG_460GT) || defined(CONFIG_APM82XXX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -752,7 +754,11 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ +#if defined(CONFIG_APM82XXX) /* APM82XXX only has 32KB of OCM */ + ori r1,r1,0x0784 /* 32k */ +#else ori r1,r1,0x0984 /* 64k */ +#endif mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2e..c58492d 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM82XXX_RA 0x12C41C80 /* APM82XXX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 -- 1.6.1.rc3

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Re: [U-Boot] [ELDK] Not able to Uncompress Multi Image
by Detlev Zundel 30 Aug '10

30 Aug '10

Hi Zoolu, > I am trying to boot my mutli image ( Kernel + Ramdisk) on my target and i am > not able to boot beyond below given log. I can not see > (Uncompressing Multi-File Image ... OK) .. OK does not come up. I guess > the image is hung while uncompressing the image ??? But to my surprise the > same image boots on a different board with all same hardware. So the problem > is only with this board i guess any pointer on this would be of great help. Do you use the same U-Boot versions on both the "good" and the "bad" board? It's because in the last time we reworked the boot process thoroughly and the multi-image file is deprecated in favour of the "FIT" images (cf. doc/uImage.FIT). So maybe the non-working board has a U-Boot with a problem in the multi-image file handling... > ----------------------------------------------------------------------------------------------------------------------------------------------------------- > Load address: 0x4000000 > Loading: ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################################# > ################################################## > done > Bytes transferred = 2583735 (276cb7 hex) > ## Booting image at 04000000 ... > Image Name: Boot Image > Image Type: PowerPC Linux Multi-File Image (gzip compressed) > Data Size: 2583671 Bytes = 2.5 MB > Load Address: 00000000 > Entry Point: 00000000 > Contents: > Image 0: 1268075 Bytes = 1.2 MB > Image 1: 1315583 Bytes = 1.3 MB > Verifying Checksum ... OK > Uncompressing Multi-File Image ... > > ------------------------------------------------------------------------------------------------------------------------------------------------ > Thanks & Regards, > Zoolu Apart from that, you should use the U-Boot mailing list more appropriate for such topics (I added a CC and set f'up). Thanks Detlev -- A GNU manual should give a good introduction to a beginner reading through from the start, and should also provide all the details that hackers want. --- GNU Coding Standards -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu(a)denx.de

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Re: [U-Boot] android fastboot support on U-boot
by Bas Mevissen 30 Aug '10

30 Aug '10

Resend, forgot to copy the list. > On Mon, 30 Aug 2010 11:31:06 +0200, Detlev Zundel <dzu(a)denx.de> wrote: >> Hi shulin, >> >>> Now I working on porting android fastboot protocol to U-boot,does >>> somebody add fastboot protocol patches to U-boot? >> >> Can yopu please tell me what the "the android fastboot" protocol is? >> > http://android-dls.com/wiki/index.php?title=Fastboot "Fastboot is protocol used to update the flash filesystem in Android devices from a host over USB. It allows flashing of unsigned partition images." I was already wondering how feasible it would be to have a board with USB slave behave like an USB memory stick to flash the firmware by simply copying a file from the host to it. -- Bas

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[U-Boot] [PATCH V4 0/4] Improve I2C for orion5x, kirkwood and ED Mini V2
by Albert Aribaud 30 Aug '10

30 Aug '10

SUMMARY: This patchset improves the driver for the Marvell TWSI interface found on orion5x and kirkwood SoCs and adds I2C support to the orion5x-based ED Mini V2 board. The mvtwsi driver is a complete rewrite, 50% shorter in source code lines, 25% smaller in object size, much simpler and way faster than the kirkwood_i2c driver it replaces. PATCH SET: Patch 1 removes dependencies on kirwkood_i2c from suen3, the only board that mentioned it. Patch 2 renames the driver from kirkwood_i2c to mvtwsi. Patch 3 replaces the old code with the new one. Patch 4 adds support for I2C in orion5x-based ED Mini V2. TESTS: This driver has been tested on an ED Mini V2 with basic u-boot i2c commands, on an 5C372a RTC and an HT24LC08 1 KB eeprom (read+write). HISTORY: V1: Initial submission as an addition rather than a replacement. V2: Fixed copyright line. Made mvtwsi a replacement for kirkwood_i2c. Made patches checkpatch-clean: 0 errors, 0 warnings. Various cosmetic changes. Removed useless i2c_end() function. V3: Reduced line lengths below 78 characters. Removed blank line after function description block comment. V4: Changed CONFIG_I2C_DRIVER_MVTWSI into CONFIG_I2C_MVTWSI. Really fixed copyright line. Added and documented kirkwood support. Shortened extended_slave_address into xtnd_slave_addr. Added explanation on default/init baudrate value. Moved I2C config settings under #ifdef CONFIG_CMD_I2C. Albert Aribaud (4): suen3: remove CONFIG_HARD_I2C and related defines i2c: rename kirkwood_i2c to mvtwsi i2c: rewrite mvtwsi, support orion5x and kirkwood edminiv2: add I2C support using mvtwsi driver drivers/i2c/Makefile | 2 +- drivers/i2c/kirkwood_i2c.c | 496 -------------------------------------------- drivers/i2c/mvtwsi.c | 428 ++++++++++++++++++++++++++++++++++++++ include/configs/edminiv2.h | 11 + include/configs/km_arm.h | 8 - 5 files changed, 440 insertions(+), 505 deletions(-) delete mode 100644 drivers/i2c/kirkwood_i2c.c create mode 100644 drivers/i2c/mvtwsi.c

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[U-Boot] [PATCH] fix the c_size, in CSD Version 2.0, it's 22 bits
by Xiangfu Liu 30 Aug '10

30 Aug '10

Signed-off-by: Xiangfu Liu <xiangfu(a)openmobilefree.net> --- include/mmc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/mmc.h b/include/mmc.h index fcb237e..b913a60 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -189,12 +189,12 @@ struct mmc_csd u8 tran_speed; u16 ccc:12, read_bl_len:4; + u32 c_size:22; u64 read_bl_partial:1, write_blk_misalign:1, read_blk_misalign:1, dsr_imp:1, rsvd2:2, - c_size:12, vdd_r_curr_min:3, vdd_r_curr_max:3, vdd_w_curr_min:3, -- 1.7.0.4

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[U-Boot] TQM834x CFI flash question: Support for 1 or 2 flash banks?
by Stefan Roese 30 Aug '10

30 Aug '10

Hi Marian, I'm in the process of cleaning up some of the CFI driver defines/implementation hacks, such as CONFIG_SYS_MAX_FLASH_BANKS_DETECT. While doing this I noticed that the TQM834x port uses this define and sets it to 2 (via the tqm834x_num_flash_banks variable) if a 2nd chip is detected. But I fail to see how this could really work, since the board port doesn't provide a 2nd base address via the an entry in the CONFIG_SYS_FLASH_BANKS_LIST define, where the probing of the 2nd bank should be done in the common CFI driver. I know that the board port was done quite some time ago, but perhaps you do remember some details. Has this ever been tested with 2 banks on this board? If yes, how? Could be that I'm missing something. Please enlighten me. :) Thanks. Cheers, Stefan -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office(a)denx.de

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[U-Boot] android fastboot support on U-boot
by shulin.zhou 30 Aug '10

30 Aug '10

hi, Now I working on porting android fastboot protocol to U-boot,does somebody add fastboot protocol patches to U-boot? shulin

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[U-Boot] u-boot
by Ò»ºÅ º« 30 Aug '10

30 Aug '10

hi, i would like to subscribe the news about u-boot ,thank you.

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[U-Boot] [PATCH] ARMV7: S5P: rename the member of gpio structure
by Minkyu Kang 30 Aug '10

30 Aug '10

Typically we declare the name of gpio structure to "gpio", so it was duplicated around the name. (e.g: gpio->gpio_a) This patch modified the naming that is removing "gpio_". Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 172 +++++++++++++++--------------- board/samsung/goni/goni.c | 8 +- board/samsung/smdkc100/smdkc100.c | 2 +- 3 files changed, 91 insertions(+), 91 deletions(-) diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 9a7faed..2df33a6 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -33,96 +33,96 @@ struct s5p_gpio_bank { }; struct s5pc100_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c; - struct s5p_gpio_bank gpio_d; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_k0; - struct s5p_gpio_bank gpio_k1; - struct s5p_gpio_bank gpio_k2; - struct s5p_gpio_bank gpio_k3; - struct s5p_gpio_bank gpio_l0; - struct s5p_gpio_bank gpio_l1; - struct s5p_gpio_bank gpio_l2; - struct s5p_gpio_bank gpio_l3; - struct s5p_gpio_bank gpio_l4; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c; + struct s5p_gpio_bank d; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank l3; + struct s5p_gpio_bank l4; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; struct s5pc110_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c0; - struct s5p_gpio_bank gpio_c1; - struct s5p_gpio_bank gpio_d0; - struct s5p_gpio_bank gpio_d1; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_mp0_1; - struct s5p_gpio_bank gpio_mp0_2; - struct s5p_gpio_bank gpio_mp0_3; - struct s5p_gpio_bank gpio_mp0_4; - struct s5p_gpio_bank gpio_mp0_5; - struct s5p_gpio_bank gpio_mp0_6; - struct s5p_gpio_bank gpio_mp0_7; - struct s5p_gpio_bank gpio_mp1_0; - struct s5p_gpio_bank gpio_mp1_1; - struct s5p_gpio_bank gpio_mp1_2; - struct s5p_gpio_bank gpio_mp1_3; - struct s5p_gpio_bank gpio_mp1_4; - struct s5p_gpio_bank gpio_mp1_5; - struct s5p_gpio_bank gpio_mp1_6; - struct s5p_gpio_bank gpio_mp1_7; - struct s5p_gpio_bank gpio_mp1_8; - struct s5p_gpio_bank gpio_mp2_0; - struct s5p_gpio_bank gpio_mp2_1; - struct s5p_gpio_bank gpio_mp2_2; - struct s5p_gpio_bank gpio_mp2_3; - struct s5p_gpio_bank gpio_mp2_4; - struct s5p_gpio_bank gpio_mp2_5; - struct s5p_gpio_bank gpio_mp2_6; - struct s5p_gpio_bank gpio_mp2_7; - struct s5p_gpio_bank gpio_mp2_8; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank mp0_1; + struct s5p_gpio_bank mp0_2; + struct s5p_gpio_bank mp0_3; + struct s5p_gpio_bank mp0_4; + struct s5p_gpio_bank mp0_5; + struct s5p_gpio_bank mp0_6; + struct s5p_gpio_bank mp0_7; + struct s5p_gpio_bank mp1_0; + struct s5p_gpio_bank mp1_1; + struct s5p_gpio_bank mp1_2; + struct s5p_gpio_bank mp1_3; + struct s5p_gpio_bank mp1_4; + struct s5p_gpio_bank mp1_5; + struct s5p_gpio_bank mp1_6; + struct s5p_gpio_bank mp1_7; + struct s5p_gpio_bank mp1_8; + struct s5p_gpio_bank mp2_0; + struct s5p_gpio_bank mp2_1; + struct s5p_gpio_bank mp2_2; + struct s5p_gpio_bank mp2_3; + struct s5p_gpio_bank mp2_4; + struct s5p_gpio_bank mp2_5; + struct s5p_gpio_bank mp2_6; + struct s5p_gpio_bank mp2_7; + struct s5p_gpio_bank mp2_8; struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; /* functions */ diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 060d5d1..4336729 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -67,7 +67,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1); + gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -80,11 +80,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2); + gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE); + gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X); + gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0); diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index bb72fd1..31e8d9e 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -41,7 +41,7 @@ static void smc9115_pre_init(void) (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); -- 1.7.0.4

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