July 2010 - U-Boot

[U-Boot] [PATCH 1/2] mmc: omap3: make local symbols static
by Grazvydas Ignotas 13 Aug '10

13 Aug '10

Make driver local variables and functions static and remove them from the arch header. Signed-off-by: Grazvydas Ignotas <notasas(a)gmail.com> --- arch/arm/include/asm/arch-omap3/mmc.h | 9 --------- drivers/mmc/omap3_mmc.c | 33 +++++++++++++++++---------------- 2 files changed, 17 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/mmc.h b/arch/arm/include/asm/arch-omap3/mmc.h index 196ffdc..3e3e631 100644 --- a/arch/arm/include/asm/arch-omap3/mmc.h +++ b/arch/arm/include/asm/arch-omap3/mmc.h @@ -230,13 +230,4 @@ typedef union { mmc_csd_reg_t Card_CSD; } mmc_resp_t; -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - #endif /* MMC_H */ diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 96c0e65..dc331a0 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -32,7 +32,7 @@ #include <asm/io.h> #include <asm/arch/mmc.h> -const unsigned short mmc_transspeed_val[15][4] = { +static const unsigned short mmc_transspeed_val[15][4] = { {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, @@ -50,7 +50,7 @@ const unsigned short mmc_transspeed_val[15][4] = { {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} }; -mmc_card_data cur_card_data; +static mmc_card_data cur_card_data; static block_dev_desc_t mmc_blk_dev; static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE; @@ -59,7 +59,7 @@ block_dev_desc_t *mmc_get_dev(int dev) return (block_dev_desc_t *) &mmc_blk_dev; } -unsigned char mmc_board_init(void) +static unsigned char mmc_board_init(void) { t2_t *t2_base = (t2_t *)T2_BASE; @@ -77,7 +77,7 @@ unsigned char mmc_board_init(void) return 1; } -void mmc_init_stream(void) +static void mmc_init_stream(void) { writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); @@ -92,7 +92,7 @@ void mmc_init_stream(void) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } -unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) +static unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) { unsigned int val; @@ -121,7 +121,7 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) return 1; } -unsigned char mmc_init_setup(void) +static unsigned char mmc_init_setup(void) { unsigned int reg_val; @@ -155,7 +155,7 @@ unsigned char mmc_init_setup(void) return 1; } -unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, +static unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, unsigned int *response) { unsigned int mmc_stat; @@ -191,7 +191,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, return 1; } -unsigned char mmc_read_data(unsigned int *output_buf) +static unsigned char mmc_read_data(unsigned int *output_buf) { unsigned int mmc_stat; unsigned int read_count = 0; @@ -232,7 +232,7 @@ unsigned char mmc_read_data(unsigned int *output_buf) return 1; } -unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +static unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) { unsigned char err; unsigned int argument = 0; @@ -343,7 +343,7 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) return 1; } -unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, +static unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, mmc_csd_reg_t *cur_csd) { mmc_extended_csd_reg_t ext_csd; @@ -397,9 +397,9 @@ unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, return 1; } -unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, - mmc_card_data *mmc_c, - unsigned long *output_buf) +static unsigned char omap_mmc_read_sect(unsigned int start_sec, + unsigned int num_bytes, mmc_card_data *mmc_c, + unsigned long *output_buf) { unsigned char err; unsigned int argument; @@ -435,7 +435,7 @@ unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, return 1; } -unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +static unsigned char configure_mmc(mmc_card_data *mmc_card_cur) { unsigned char ret_val; unsigned int argument; @@ -504,8 +504,9 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) return 1; } -unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, - void *dst) + +static unsigned long mmc_bread(int dev_num, unsigned long blknr, + lbaint_t blkcnt, void *dst) { omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, (unsigned long *) dst); -- 1.6.3.3

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[U-Boot] [PATCH] cfi_flash: flinfo: allow user interrupt in flash print info fn
by Kim Phillips 12 Aug '10

12 Aug '10

flashes getting larger, users more impatient. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- drivers/mtd/cfi_flash.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 3267c5d..38d0ca5 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1159,6 +1159,8 @@ void flash_print_info (flash_info_t * info) puts ("\n Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { + if (ctrlc()) + return; if ((i % 5) == 0) printf ("\n"); #ifdef CONFIG_SYS_FLASH_EMPTY_INFO -- 1.7.1.1

3 2

[U-Boot] Non standard CFI detection tweaks
by Rogan Dawes 12 Aug '10

12 Aug '10

Hi Stefan, I'm trying to add support for my D-Link DNS323 (Orion5x-based) to U-Boot, building on the efforts of Albert Aribaud. One place where I am struggling is with the detection of the flash chip. The flash part is a 8 MB Spansion S29GL064M90TFIR4, and the data sheet can be found at: http://www.spansion.com/Support/Datasheets/s29gl-m_00_b8_e.pdf It says: > This device enters the CFI Query mode when the system writes the CFI > Query command, 98h, to address 55h, any time the device is ready to > read array data. Testing this from the command line, however, shows that this is in fact NOT true. In fact, the write needs to occur at aah, not 55h. This may be influenced by the following paragraph from the manual: > Depending on the model number, the devices have an 8-bit wide data > bus only, 16-bit wide data bus only, or a 16-bit wide data bus that > can also function as an 8-bit wide data bus by using the BYTE# > input. And: > R4 = x8/x16 Looking at the debug logs from cfi_flash.c, I see the following output: fwc addr ff8000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff800020 is= ffff 5151 These lines are the closest to doing what appears to be needed for this part, in that the address being written to is correct, the address being read from is correct, the expected result is correct. The only thing that is not correct is the command to enter QRY mode. For this particular chip, the command is: mw.w 0xff8000aa 9800 (rather than 9898) (FWIW mw.b 0xff8000aa 98 also works fine to enter QRY mode) Having done that, the QRY results are present at 0xff800020: md.b ff800020 20 ff800020: 51 51 52 52 59 59 02 02 00 00 40 40 00 00 00 00 QQRRYY....@@.... ff800030: 00 00 00 00 00 00 27 27 36 36 00 00 00 00 04 04 ......''66...... Do you have any suggestions on the best way to modify cfi_flash.c to detect this chip? Regards, Rogan Dawes

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[U-Boot] [RFC][PATCH 17/19] arm cp15: setup mmu and enable dcache
by Heiko Schocher 11 Aug '10

11 Aug '10

This has been tested on at91sam9263 and STN8815. Again, I didn't check if it has bad effects on non-arm926 cores. Initially I had a "done" bit to only set up page tables at the beginning. However, since the aligmnent requirement was for the whole object file, this extra integer tool 16kB in BSS, so I chose to remove it. Also, note not all boards use PHYS_SDRAM, but it looks like it's the most used name (more than CONFIG_SYS_DRAM_BASE for example). rebased for full arm relocation from Heiko Schocher <hs(a)denx.de> Signed-off-by: Alessandro Rubini <rubini(a)gnudd.com> --- arch/arm/lib/cache-cp15.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 files changed, 38 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 62ed54f..11e64d8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -32,6 +32,36 @@ static void cp_delay (void) /* copro seems to need some delay between reading and writing */ for (i = 0; i < 100; i++) nop(); + asm volatile("" : : : "memory"); +} + +/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */ +static inline void mmu_setup(void) +{ + static u32 __attribute__((aligned(16384))) page_table[4096]; + int i; + u32 reg; + + /* Set up an identity-mapping for all 4GB, rw for everyone */ + for (i = 0; i < 4096; i++) + page_table[i] = i << 20 | (3 << 10) | 0x12; + /* Then, enable cacheable and bufferable for RAM only */ + for (i = PHYS_SDRAM >> 20; + i < ( PHYS_SDRAM + PHYS_SDRAM_SIZE) >> 20; + i++) { + page_table[i] = i << 20 | (3 << 10) | 0x1e; + } + /* Copy the page table address to cp15 */ + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (page_table) : "memory"); + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + /* and enable the mmu */ + reg = get_cr(); /* get control reg. */ + cp_delay(); + set_cr(reg | CR_M); + } /* cache_bit must be either CR_I or CR_C */ @@ -39,6 +69,9 @@ static void cache_enable(uint32_t cache_bit) { uint32_t reg; + /* The data cache is not active unless the mmu is enabled too */ + if (cache_bit == CR_C) + mmu_setup(); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -49,6 +82,11 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + if (cache_bit == CR_C) { + /* if disabling data cache, disable mmu too */ + cache_bit |= CR_M; + flush_cache(0, ~0); + } reg = get_cr(); cp_delay(); set_cr(reg & ~cache_bit); -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [PATCH] orion5x: allow overriding default mappings windows
by Albert Aribaud 10 Aug '10

10 Aug '10

Turn all ORION5X_DEF{ADR,SZ}_xxx macros into ORION5X_{ADR,SZ}_xxx and allow defining them from board code to override defaults. This is particularly useful for defining board-specific FLASH address and size in board header file rather than having to tweak orion5x code. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- arch/arm/cpu/arm926ejs/orion5x/cpu.c | 40 ++++++------ arch/arm/include/asm/arch-orion5x/cpu.h | 98 ++++++++++++++++++++++++------- 2 files changed, 97 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 03c6d06..a921e98 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void) (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; /* Window 0: PCIE MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM, ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, ORION5X_WIN_ENABLE), &winregs[0].ctrl); - writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); - writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); - writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); /* Window 1: PCIE IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO, ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, ORION5X_WIN_ENABLE), &winregs[1].ctrl); - writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); - writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); - writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + writel(ORION5X_ADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); /* Window 2: PCI MEM address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl); - writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + writel(ORION5X_ADR_PCI_MEM, &winregs[2].base); /* Window 3: PCI IO address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO, ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl); - writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + writel(ORION5X_ADR_PCI_IO, &winregs[3].base); /* Window 4: DEV_CS0 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl); - writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + writel(ORION5X_ADR_DEV_CS0, &winregs[4].base); /* Window 5: DEV_CS1 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl); - writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + writel(ORION5X_ADR_DEV_CS1, &winregs[5].base); /* Window 6: DEV_CS2 address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2, ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, ORION5X_WIN_ENABLE), &winregs[6].ctrl); - writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + writel(ORION5X_ADR_DEV_CS2, &winregs[6].base); /* Window 7: BOOT Memory address space */ - writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM, ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl); - writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + writel(ORION5X_ADR_BOOTROM, &winregs[7].base); return 0; } diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 22e2dd3..80717f8 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -75,35 +75,91 @@ enum orion5x_cpu_attrib { }; /* - * Default Device Address MAP BAR values + * Device Address MAP BAR values +/* + * All addresses and sizes not defined by board code + * will be given default values here. */ -#define ORION5X_DEFADR_PCIE_MEM 0x90000000 -#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 -#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 -#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) -#define ORION5X_DEFADR_PCIE_IO 0xf0000000 -#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 -#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 -#define ORION5X_DEFSZ_PCIE_IO (64*1024) +#if !defined (ORION5X_ADR_PCIE_MEM) +#define ORION5X_ADR_PCIE_MEM 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) +#define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) +#define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 +#endif + +#if !defined (ORION5X_SZ_PCIE_MEM) +#define ORION5X_SZ_PCIE_MEM (128*1024*1024) +#endif + +#if !defined (ORION5X_ADR_PCIE_IO) +#define ORION5X_ADR_PCIE_IO 0xf0000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) +#define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 +#endif + +#if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) +#define ORION5X_ADR_PCIE_IO_REMAP_HI 0 +#endif + +#if !defined (ORION5X_SZ_PCIE_IO) +#define ORION5X_SZ_PCIE_IO (64*1024) +#endif + +#if !defined (ORION5X_ADR_PCI_MEM) +#define ORION5X_ADR_PCI_MEM 0x98000000 +#endif + +#if !defined (ORION5X_SZ_PCI_MEM) +#define ORION5X_SZ_PCI_MEM (128*1024*1024) +#endif + +#if !defined (ORION5X_ADR_PCI_IO) +#define ORION5X_ADR_PCI_IO 0xf0100000 +#endif + +#if !defined (ORION5X_SZ_PCI_IO) +#define ORION5X_SZ_PCI_IO (64*1024) +#endif + +#if !defined (ORION5X_ADR_DEV_CS0) +#define ORION5X_ADR_DEV_CS0 0xfa000000 +#endif + +#if !defined (ORION5X_SZ_DEV_CS0) +#define ORION5X_SZ_DEV_CS0 (2*1024*1024) +#endif -#define ORION5X_DEFADR_PCI_MEM 0x98000000 -#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) +#if !defined (ORION5X_ADR_DEV_CS1) +#define ORION5X_ADR_DEV_CS1 0xf8000000 +#endif -#define ORION5X_DEFADR_PCI_IO 0xf0100000 -#define ORION5X_DEFSZ_PCI_IO (64*1024) +#if !defined (ORION5X_SZ_DEV_CS1) +#define ORION5X_SZ_DEV_CS1 (32*1024*1024) +#endif -#define ORION5X_DEFADR_DEV_CS0 0xfa000000 -#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) +#if !defined (ORION5X_ADR_DEV_CS2) +#define ORION5X_ADR_DEV_CS2 0xfa800000 +#endif -#define ORION5X_DEFADR_DEV_CS1 0xf8000000 -#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) +#if !defined (ORION5X_SZ_DEV_CS2) +#define ORION5X_SZ_DEV_CS2 (1*1024*1024) +#endif -#define ORION5X_DEFADR_DEV_CS2 0xfa800000 -#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) +#if !defined (ORION5X_ADR_BOOTROM) +#define ORION5X_ADR_BOOTROM 0xFFF80000 +#endif -#define ORION5X_DEFADR_BOOTROM 0xFFF80000 -#define ORION5X_DEFSZ_BOOTROM (512*1024) +#if !defined (ORION5X_SZ_BOOTROM) +#define ORION5X_SZ_BOOTROM (512*1024) +#endif /* * PCIE registers are used for SoC device ID and revision -- 1.6.4.4

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Re: [U-Boot] [PATCH 2/2] MPC8308ERDB: minimal support for devboard from Freescale
by Kim Phillips 10 Aug '10

10 Aug '10

On Thu, 24 Jun 2010 19:00:54 -0500 Kim Phillips <kim.phillips(a)freescale.com> wrote: > On Thu, 24 Jun 2010 23:36:49 +0400 > Ilya Yanok <yanok(a)emcraft.com> wrote: > > > Hi Kim, > > > > On 24.06.2010 22:00, Kim Phillips wrote: > > >> I've enabled icache and now the board sometimes resets twice after > > >> U-Boot 'reset' command: > > >> > > > > > >> (It doesn't always stop at "DRAM:" line but that position is most frequent) > > >> Maybe you have some ideas on this subject? > > >> > > > hmm, if it's only on soft-resets, can you try adding > > > HID0_ENABLE_INSTRUCTION_CACHE to CONFIG_SYS_HID0_INIT in addition to > > > _FINAL? Some cache state is preserved over a soft-reset... > > > > > > > Thanks for your advice but this doesn't help... turning icache on early causes a different pattern of bus accesses when fetching code, and this might trigger bus accesses that interfere with code that sets bus configuration registers, such as the acr. Can you test this patch please?: diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 15e2c18..613625d 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -36,6 +36,7 @@ COBJS-y += speed.o COBJS-y += interrupts.o COBJS-y += spd_sdram.o COBJS-y += ecc.o +COBJS-y += acr.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_FSL_SERDES) += serdes.o COBJS-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc83xx/acr.c b/arch/powerpc/cpu/mpc83xx/acr.c new file mode 100644 index 0000000..20315fc --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/acr.c @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +void single_cline_write(volatile void *addr, __be32 val) +{ + out_be32(addr, val); +} diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 83cba93..237fa48 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -30,6 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void single_cline_write(volatile void *addr, __be32 val); + #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -63,6 +65,7 @@ static void config_qe_ioports(void) */ void cpu_init_f (volatile immap_t * im) { + __be32 val; __be32 acr_mask = #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ ACR_PIPE_DEP | @@ -213,7 +216,8 @@ void cpu_init_f (volatile immap_t * im) memset ((void *) gd, 0, sizeof (gd_t)); /* system performance tweaking */ - clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); + val = __raw_readl(&im->arbiter.acr); + single_cline_write(&im->arbiter.acr, acr_val & (val & ~acr_mask)); clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 0b74a13..f01c462 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -51,6 +51,8 @@ SECTIONS .text : { arch/powerpc/cpu/mpc83xx/start.o (.text) + . = ALIGN(32); + arch/powerpc/cpu/mpc83xx/acr.o (.text) *(.text) *(.got1) . = ALIGN(16); Thanks, Kim

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[U-Boot] [PATCH CFI flash]: Workaround for Numonyx Axcell P33/P30 256-Mbit 65nm bug
by Philippe De Muyter 10 Aug '10

10 Aug '10

Hello Wolfgang & list, I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks. A working workaround is given, which I have applied and tested with success. Signed-off-by: Philippe De Muyter <phdm(a)macqel.be> --- drivers/mtd/cfi_flash.c | 27 ++++++++++++++++++++------- 1 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 3267c5d..0931137 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1347,16 +1347,29 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) switch (info->vendor) { case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sector, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + case CFI_CMDSET_INTEL_EXTENDED: { + unsigned short cmd; + if (prot) - flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_SET); + cmd = FLASH_CMD_PROTECT_SET; else + cmd = FLASH_CMD_PROTECT_CLEAR; + /* see errata + "Numonyx Axcell P33/P30 Specification Update" :) */ + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); + if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, + prot)) { + /* cmd must come before 20us after FLASH_CMD_PROTECT */ + /* Disable interrupts which might cause a timeout here */ + int flag = disable_interrupts (); flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_CLEAR); + FLASH_CMD_PROTECT); + flash_write_cmd (info, sector, 0, cmd); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + } + } break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: -- 1.6.3.3 -- Philippe De Muyter phdm at macqel dot be Tel +32 27029044 Macq Electronique SA rue de l'Aeronef 2 B-1140 Bruxelles Fax +32 27029077

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[U-Boot] [PATCH] Create a new driver for Atmel at91/avr MCI adapters that uses the u-boot mmc framework.
by Rob Emanuele 10 Aug '10

10 Aug '10

To use it on your platform add defines like these: #define CONFIG_MMC 1 #define CONFIG_GENERIC_MMC 1 #define CONFIG_GENERIC_ATMEL_MCI 1 /*change this for your cpu */ #define MMCI_BASE 0xFFF80000 Then create an init routine in your platform code: /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { /* This calls your code to clock the interface * and set the pins up, etc. */ mmc_hw_init(); /* This calls the atmel_mmc_init in gen_atmel_mci.c */ return atmel_mmc_init(bd); } Signed-off-by: Rob Emanuele <rob(a)emanuele.us> --- drivers/mmc/Makefile | 1 + drivers/mmc/gen_atmel_mci.c | 330 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 331 insertions(+), 0 deletions(-) create mode 100644 drivers/mmc/gen_atmel_mci.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 6fa04b8..1785253 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libmmc.a COBJS-$(CONFIG_GENERIC_MMC) += mmc.o +COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c new file mode 100644 index 0000000..9e3430a --- /dev/null +++ b/drivers/mmc/gen_atmel_mci.c @@ -0,0 +1,330 @@ +/* + * Copyright 2010, Rob Emanuele <rob(a)emanuele.us> + * + * Original Driver: + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include <hwconfig.h> +#include <mmc.h> +#include <part.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/byteorder.h> +#include <asm/arch/clk.h> +#include <asm/arch/memory-map.h> +#include "atmel_mci.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_MMC_CLK_OD +#define CONFIG_SYS_MMC_CLK_OD 150000 +#endif +#define MMC_DEFAULT_BLKLEN 512 + +void dump_cmd(uint cmdr, uint arg, uint status, const char* msg) +{ + printf("gen_atmel_mci: CMDR 0x%08x (%2u) ARGR 0x%08x (SR: 0x%08x) %s\n", + cmdr, cmdr&0x3F, arg, status, msg); +} + +/* Setup for MCI Clock and Block Size */ +static void mci_set_mode(unsigned long hz, unsigned long blklen) +{ + unsigned long bus_hz; + unsigned long clkdiv; + + if (hz > 0) { + bus_hz = get_mck_clk_rate(); + clkdiv = (bus_hz / hz) / 2 - 1; + } else { + clkdiv = ~0UL; + } + + printf("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); + + if (clkdiv & ~255UL) { + clkdiv = 255; + printf("mmc: clock %lu too low; setting CLKDIV to 255\n", + hz); + } + + blklen &= 0xfffc; + /* On some platforms RDPROOF and WRPROOF are ignored */ + mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen) + | MMCI_BIT(RDPROOF) + | MMCI_BIT(WRPROOF))); +} + +/* Return the CMDR with flags for a given command and data packet */ +static uint atmel_encode_cmd(struct mmc_cmd *cmd, struct mmc_data *data, uint* error_flags) +{ + uint cmdr = 0; + /* Default Flags for Errors */ + *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) | MMCI_BIT(RINDE) | MMCI_BIT(RTOE)); + + /* Default Flags for the Command */ + cmdr |= MMCI_BIT(MAXLAT); + + if (data) { + cmdr |= MMCI_BF(TRCMD,1); + + if (data->blocks > 1) { + cmdr |= MMCI_BF(TRTYP,1); + } + + if (data->flags & MMC_DATA_READ) + cmdr |= MMCI_BIT(TRDIR); + } + + if (cmd->resp_type & MMC_RSP_CRC) + *error_flags |= MMCI_BIT(RCRCE); + + if (cmd->resp_type & MMC_RSP_136) + cmdr |= MMCI_BF(RSPTYP,2); + else if (cmd->resp_type & MMC_RSP_BUSY) + cmdr |= MMCI_BF(RSPTYP,3); + else if (cmd->resp_type & MMC_RSP_PRESENT) + cmdr |= MMCI_BF(RSPTYP,1); + + return cmdr | MMCI_BF(CMDNB,cmd->cmdidx); +} + +static uint atmel_data_read(uint* data, uint error_flags) +{ + uint status; + do { + status = mmci_readl(SR); + if (status & (error_flags | MMCI_BIT(OVRE))) + goto io_fail; + } while (!(status & MMCI_BIT(RXRDY))); + + if (status & MMCI_BIT(RXRDY)) { + *data = mmci_readl(RDR); + status = 0; + } +io_fail: + return status; +} + +static uint atmel_data_write(uint* data, uint error_flags) +{ + uint status; + do { + status = mmci_readl(SR); + if (status & (error_flags | MMCI_BIT(UNRE))) + goto io_fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + mmci_writel(TDR,*data); + status = 0; + } +io_fail: + return status; +} + +/* + * Sends a command out on the bus and deals with the block data. + * Takes the mmc pointer, a command pointer, and an optional data pointer. + */ +static int +atmel_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + uint cmdr; + uint error_flags = 0; + uint status; + + /* Figure out the transfer arguments */ + cmdr = atmel_encode_cmd(cmd, data, &error_flags); + + /* Send the command */ + mmci_writel(ARGR,cmd->cmdarg); + mmci_writel(CMDR, cmdr); + +#if GEN_ATMEL_MCI_DEBUG + dump_cmd(cmdr, cmd->cmdarg, 0, "COMMAND Dbg Msg"); +#endif + + /* Wait for the command to complete */ + while (!((status = mmci_readl(SR)) & MMCI_BIT(CMDRDY))); + + if (status & error_flags) { + dump_cmd(cmdr, cmd->cmdarg, status, "COMMAND Failed"); + return COMM_ERR; + } + + /* Copy the response to the response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = mmci_readl(RSPR); + cmd->response[1] = mmci_readl(RSPR1); + cmd->response[2] = mmci_readl(RSPR2); + cmd->response[3] = mmci_readl(RSPR3); + } else + cmd->response[0] = mmci_readl(RSPR); + + /* transfer all of the blocks */ + if (data) { + uint word_count, block_count; + uint* ioptr; + uint sys_blocksize, dummy, i; + uint (*atmel_data_op)(uint* data, uint error_flags); + + if (data->flags & MMC_DATA_READ) { + atmel_data_op = atmel_data_read; + sys_blocksize = mmc->read_bl_len; + ioptr = (uint*)data->dest; + } else { + atmel_data_op = atmel_data_write; + sys_blocksize = mmc->write_bl_len; + ioptr = (uint*)data->src; + } + + status = 0; + for(block_count = 0; block_count < data->blocks && !status; block_count++) { + word_count = 0; + do { + status = atmel_data_op(ioptr,error_flags); + word_count++; + ioptr++; + } while(!status && word_count < (data->blocksize / 4)); +#if GEN_ATMEL_MCI_DEBUG + if (data->flags & MMC_DATA_READ) + { + char *mem_args[3]; + char mem_addr_str[16]; + char mem_len_str[16]; + printf("Command caused a block read for %u bytes (read %u bytes)\n", data->blocksize, word_count*4); + mem_args[0] = "md.l"; + sprintf(mem_addr_str,"0x%08x",(uint)(data->dest)); + mem_args[1] = mem_addr_str; + sprintf(mem_len_str,"0x%x",word_count); + mem_args[2] = mem_len_str; + printf("Dumping with: %s %s %s\n", mem_args[0], mem_args[1], mem_args[2]); + do_mem_md(NULL, 0, 3, mem_args); + } +#endif +#if GEN_ATMEL_MCI_DEBUG + if (!status && word_count < (sys_blocksize / 4)) + printf("sponging....\n"); +#endif + /* sponge the rest of a full block */ + while (!status && word_count < (sys_blocksize / 4)) { + status = atmel_data_op(&dummy,error_flags); + word_count++; + } + if (status) { + dump_cmd(cmdr, cmd->cmdarg, status, "XFER Failed"); + return COMM_ERR; + } + } + + /* Wait for Transfer End */ + i = 0; + do { + status = mmci_readl(SR); + + if (status & error_flags) { + dump_cmd(cmdr, cmd->cmdarg, status, "XFER DTIP Wait Failed"); + return COMM_ERR; + } + i++; + } while ((status & MMCI_BIT(DTIP)) && i < 10000); + if (status & MMCI_BIT(DTIP)) { + dump_cmd(cmdr, cmd->cmdarg, status, "XFER DTIP never unset, ignoring"); + } + } + + return 0; +} + +static void atmel_set_ios(struct mmc *mmc) +{ + /* Set the clock speed */ + mci_set_mode(mmc->clock, MMC_DEFAULT_BLKLEN); + + /* set the bus width and select slot A for this interface + * there is no capability for multiple slots on the same interface yet + */ + /* Bitfield SCDBUS needs to be expanded to 2 bits for 8-bit buses + */ + if (mmc->bus_width == 4) + mmci_writel(SDCR, MMCI_BF(SCDBUS,0x1)|MMCI_BF(SCDSEL,0x0)); + else + mmci_writel(SDCR, MMCI_BF(SCDBUS,0x0)|MMCI_BF(SCDSEL,0x0)); +} + +static int atmel_init(struct mmc *mmc) +{ + /* Initialize controller */ + mmci_writel(CR, MMCI_BIT(SWRST)); /* soft reset */ + mmci_writel(CR, MMCI_BIT(PWSDIS)); /* disable power save */ + mmci_writel(CR, MMCI_BIT(MCIEN)); /* enable mci */ + + /* Initial Time-outs */ + mmci_writel(DTOR, 0x5f); + /* Disable Interrupts */ + mmci_writel(IDR, ~0UL); + + /* Set defualt clocks and blocklen */ + mci_set_mode(CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + + return 0; +} + +static int atmel_initialize(bd_t *bis) +{ + struct mmc *mmc; + + mmc = malloc(sizeof(struct mmc)); + + sprintf(mmc->name, "Atmel MCI"); + /* We set this but atmel_mci.h makes use of MMCI_BASE directly */ + mmc->priv = (void *)MMCI_BASE; + mmc->send_cmd = atmel_send_cmd; + mmc->set_ios = atmel_set_ios; + mmc->init = atmel_init; + + /* need to be able to pass these in on a baord by board basis */ + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->host_caps = MMC_MODE_4BIT; + + /* High Speed Support? */ + + mmc->f_min = get_mck_clk_rate() / (2*(0xFF+1)); + mmc->f_max = get_mck_clk_rate() / (2); + + mmc_register(mmc); + + return 0; +} + +int atmel_mmc_init(bd_t *bis) +{ + return atmel_initialize(bis); +} -- 1.6.3.3

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[U-Boot] [PATCH] bug fix and cleanup for s3c44b0 serial driver
by Brian Cavagnolo 10 Aug '10

10 Aug '10

Specifically, don't dereference the URXH0 register twice; calculate the BRD based on the formula in the databook instead of using a messy switch statement; and migrate the BRD calculation to the hardware hardware header because it's board specific. Signed-off-by: Brian Cavagnolo <brian(a)cozybit.com> --- arch/arm/include/asm/arch-s3c44b0/hardware.h | 3 +- drivers/serial/serial_s3c44b0.c | 65 +------------------------- 2 files changed, 4 insertions(+), 64 deletions(-) diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h index 146e265..38ff32c 100644 --- a/arch/arm/include/asm/arch-s3c44b0/hardware.h +++ b/arch/arm/include/asm/arch-s3c44b0/hardware.h @@ -11,7 +11,8 @@ #define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) #define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) #define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) - +#define BRD(bps) (DIV_ROUND(CONFIG_S3C44B0_CLOCK_SPEED * 1000000, \ + (bps)*16) - 1) /*****************************/ /* CPU Wrapper Registers */ diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c index 95d0266..e6c535c 100644 --- a/drivers/serial/serial_s3c44b0.c +++ b/drivers/serial/serial_s3c44b0.c @@ -48,7 +48,7 @@ static int serial_flush_input(void) /* keep on reading as long as the receiver is not empty */ while(UTRSTAT0&0x01) { - tmp = REGB(URXH0); + tmp = URXH0; } return 0; @@ -70,68 +70,7 @@ static int serial_flush_output(void) void serial_setbrg (void) { - u32 divisor = 0; - - /* get correct divisor */ - switch(gd->baudrate) { - - case 1200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 3124; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 3905; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 9600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 390; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 487; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 19200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 194; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 243; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif - break; - - case 38400: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 97; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 121; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 57600: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 64; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 80; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - - case 115200: -#if CONFIG_S3C44B0_CLOCK_SPEED==66 - divisor = 32; -#elif CONFIG_S3C44B0_CLOCK_SPEED==75 - divisor = 40; -#else -# error CONFIG_S3C44B0_CLOCK_SPEED undefined -#endif /* break; */ - } + u32 divisor = BRD(gd->baudrate); serial_flush_output(); serial_flush_input(); -- 1.6.0.4

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[U-Boot] Too Much Email
by Moran, Jack 10 Aug '10

10 Aug '10

How can I go about configuring u-boot email to only send emails that pertain to a response to my question? Thanks Jack John M Moran General Dynamics C4S 77 "A" St. Needham, MA, 02494 Phone: 781-455-4071 Email: jack.moran(a)gdc4s.com

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