June 2010 - U-Boot

[U-Boot] [PATCH V2 0/10] PPC LBC/TLB cleanups; reginfo command for 85xx
by Becky Bruce 08 Jun '10

08 Jun '10

This somewhat random patch series got its start when I was asked to create a reginfo command for 85xx by one of the internal teams here at FSL to dump the BR/ORs, LAWs, and the TLBCAM entries. As I started doing that, I began to notice that there was a lot of duplicated and inconsistent code for manipulating the TLBs and LBC registers, which, in some cases, would have caused me to have to write extra code to make reginfo useful on multiple platforms. So I decided to clean this up. The bulk of these patches are just merges of duplicated code and renames of things to get to a consistent naming scheme. These really need to be picked up by a single maintainer, as there's a definite dependency chain here; I'll let Kumar and Wolfgang decide who wants it. Wolfgang, my makefile changes are going to conflict with your top-level makefile changes that are posted on the list but not yet in the tree - you should be able to just incorporate my changes, or you can poke me when yours are in the tree and I can deal with it. NOTE: Updated from the original version to incorporate feedback - removed unnecessary volatiles in the upmconfig code, made the definition of FSL_LBC dependent on 85xx/86xx/83xx, and moved the ohci readl/writel defs into a header. Diffstat below. Cheers, Becky MAKEALL | 2 + Makefile | 1 + arch/powerpc/cpu/mpc83xx/cpu.c | 66 ------------ arch/powerpc/cpu/mpc83xx/cpu_init.c | 53 ++-------- arch/powerpc/cpu/mpc83xx/nand_init.c | 4 +- arch/powerpc/cpu/mpc83xx/speed.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 78 +++----------- arch/powerpc/cpu/mpc85xx/cpu_init.c | 58 +---------- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 6 +- arch/powerpc/cpu/mpc85xx/speed.c | 5 +- arch/powerpc/cpu/mpc85xx/tlb.c | 70 ++++++++----- arch/powerpc/cpu/mpc86xx/cpu.c | 15 +--- arch/powerpc/cpu/mpc86xx/cpu_init.c | 55 +---------- arch/powerpc/cpu/mpc86xx/speed.c | 5 +- arch/powerpc/cpu/mpc8xxx/Makefile | 3 + arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 135 ++++++++++++++++++++++++ arch/powerpc/include/asm/config.h | 6 + arch/powerpc/include/asm/fsl_law.h | 1 + arch/powerpc/include/asm/fsl_lbc.h | 112 ++++++++++++-------- arch/powerpc/include/asm/immap_83xx.h | 13 ++- arch/powerpc/include/asm/immap_85xx.h | 46 +-------- arch/powerpc/include/asm/immap_86xx.h | 49 +-------- arch/powerpc/include/asm/mmu.h | 2 + board/atum8548/atum8548.c | 2 +- board/esd/vme8349/vme8349.c | 2 +- board/freescale/mpc8313erdb/sdram.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 2 +- board/freescale/mpc8349itx/mpc8349itx.c | 7 +- board/freescale/mpc8360emds/mpc8360emds.c | 6 +- board/freescale/mpc8360erdk/nand.c | 6 +- board/freescale/mpc8540ads/mpc8540ads.c | 8 +- board/freescale/mpc8541cds/mpc8541cds.c | 13 +-- board/freescale/mpc8544ds/mpc8544ds.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 13 +-- board/freescale/mpc8555cds/mpc8555cds.c | 12 +-- board/freescale/mpc8560ads/mpc8560ads.c | 8 +- board/freescale/mpc8568mds/mpc8568mds.c | 11 +-- board/freescale/mpc8569mds/mpc8569mds.c | 2 +- board/mpc8540eval/mpc8540eval.c | 6 +- board/pm854/pm854.c | 2 +- board/pm856/pm856.c | 2 +- board/sbc8349/sbc8349.c | 2 +- board/sbc8548/sbc8548.c | 20 +--- board/sbc8560/sbc8560.c | 6 +- board/sheldon/simpc8313/sdram.c | 2 +- board/sheldon/simpc8313/simpc8313.c | 2 +- board/socrates/socrates.c | 31 +++--- board/tqc/tqm834x/tqm834x.c | 8 +- board/tqc/tqm85xx/nand.c | 12 +- board/tqc/tqm85xx/tqm85xx.c | 35 +++--- board/xes/xpedite5170/xpedite5170.c | 10 +- board/xes/xpedite5200/xpedite5200.c | 11 +- board/xes/xpedite5370/xpedite5370.c | 9 +- common/cmd_reginfo.c | 5 + drivers/misc/fsl_law.c | 131 ++++++++++-------------- drivers/mtd/nand/fsl_elbc_nand.c | 18 ++-- drivers/usb/host/ohci-hcd.c | 11 -- drivers/usb/host/ohci.h | 13 +++ include/configs/MPC8313ERDB.h | 1 + include/configs/MPC8315ERDB.h | 1 + include/configs/MPC837XEMDS.h | 1 + include/configs/MPC8536DS.h | 1 + include/configs/MPC8540EVAL.h | 1 + include/configs/MPC8541CDS.h | 1 + include/configs/MPC8544DS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 1 + include/configs/MPC8569MDS.h | 1 + include/configs/MPC8572DS.h | 1 + include/configs/P1_P2_RDB.h | 1 + include/configs/P2020DS.h | 1 + include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + include/configs/SBC8540.h | 1 + include/configs/SIMPC8313.h | 1 + include/configs/TQM85xx.h | 1 + include/configs/XPEDITE5200.h | 1 + include/configs/XPEDITE5370.h | 2 + include/configs/sbc8548.h | 1 + include/configs/sbc8560.h | 1 + include/configs/socrates.h | 1 + include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + include/mpc85xx.h | 2 - nand_spl/board/freescale/mpc8536ds/nand_boot.c | 5 +- nand_spl/nand_boot_fsl_elbc.c | 4 +-

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[U-Boot] [PATCH 0/2] arm: Adding support for TI OMAP4430 SDP
by Aneesh V 08 Jun '10

08 Jun '10

The following series implements support for TI OMAP4430 SDP based TI OMAP4430. TI OMAP4430 is a Cortex-A9 based SOC from TI. OMAP4430 is a refrence board based on OMAP4430. The first patch in this series renames the cpu arm_cortexa8 to armv7 so that the existing cortexa8 code can be shared with cortexa9. Both A8 and A9 are based on armv7 architecture. The second patch adds minimal support for OMAP4430 SDP. With this patch OMAP4430 SDP boots up. Other features such as MMC, ethernet etc will be added in subsequent patches. Aneesh V (2): arm: renaming the cpu arm_cortexa8 to armv7 arm: cortexa9: adding support for TI OMAP4430 SDP Makefile | 28 ++- arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c | 0 .../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c | 0 .../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds | 0 .../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c | 0 .../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S | 0 .../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c | 0 .../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c | 0 .../{arm_cortexa8/omap3 => armv7/omap4}/Makefile | 7 +- .../{arm_cortexa8/s5pc1xx => armv7/omap4}/cache.S | 66 +++-- .../mx51/speed.c => armv7/omap4/lowlevel_init.S} | 40 ++- arch/arm/cpu/armv7/omap4/omap4.c | 97 +++++++ .../{arm_cortexa8/omap3 => armv7/omap4}/reset.S | 0 .../s5pc1xx/cpu_info.c => armv7/omap4/sys_info.c} | 51 ++-- .../{arm_cortexa8/omap3 => armv7/omap4}/timer.c | 48 ++-- .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/start.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds | 2 +- arch/arm/include/asm/arch-omap4/cpu.h | 89 ++++++ arch/arm/include/asm/arch-omap4/omap4.h | 142 ++++++++++ .../reset.S => include/asm/arch-omap4/sys_proto.h} | 38 ++-- .../cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile | 24 +- .../arm_cortexa8 => board/ti/sdp4430}/config.mk | 25 +- .../s5pc1xx/reset.S => board/ti/sdp4430/sdp.c | 57 +++-- include/configs/omap4_sdp4430.h | 280 ++++++++++++++++++++ 46 files changed, 817 insertions(+), 177 deletions(-) copy arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/lowlevel_init.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/lowlevel_init.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/reset.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/timer.c (100%) rename arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/Makefile (93%) copy arch/arm/cpu/{arm_cortexa8/s5pc1xx => armv7/omap4}/cache.S (73%) rename arch/arm/cpu/{arm_cortexa8/mx51/speed.c => armv7/omap4/lowlevel_init.S} (63%) create mode 100644 arch/arm/cpu/armv7/omap4/omap4.c copy arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/reset.S (100%) copy arch/arm/cpu/{arm_cortexa8/s5pc1xx/cpu_info.c => armv7/omap4/sys_info.c} (51%) rename arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap4}/timer.c (73%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/start.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds (97%) create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h rename arch/arm/{cpu/arm_cortexa8/omap3/reset.S => include/asm/arch-omap4/sys_proto.h} (58%) rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile (79%) rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/config.mk (54%) rename arch/arm/cpu/arm_cortexa8/s5pc1xx/reset.S => board/ti/sdp4430/sdp.c (58%) create mode 100644 include/configs/omap4_sdp4430.h

6 8

[U-Boot] [PATCH] [v2] powerpc: add support for the Freescale P1022DS reference board
by Timur Tabi 08 Jun '10

08 Jun '10

Add basic suport for the Freescale P1022DS reference board. Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur(a)freescale.com> --- v2: addresses most of Wolfgang's concerns. DIU support removed so that it can be reworked later This depends on the following patches: Move ICS CLK chip frequenty calculation code into a common board library fsl: add LAW target to fsl_pci_info structure MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 4 + arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc85xx/p1022_serdes.c | 166 +++++++++++ arch/powerpc/include/asm/fsl_serdes.h | 2 + board/freescale/common/Makefile | 1 + board/freescale/p1022ds/Makefile | 39 +++ board/freescale/p1022ds/config.mk | 14 + board/freescale/p1022ds/ddr.c | 106 +++++++ board/freescale/p1022ds/law.c | 21 ++ board/freescale/p1022ds/p1022ds.c | 284 ++++++++++++++++++ board/freescale/p1022ds/tlb.c | 76 +++++ include/configs/P1022DS.h | 473 +++++++++++++++++++++++++++++++ 14 files changed, 1189 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p1022_serdes.c create mode 100644 board/freescale/p1022ds/Makefile create mode 100644 board/freescale/p1022ds/config.mk create mode 100644 board/freescale/p1022ds/ddr.c create mode 100644 board/freescale/p1022ds/law.c create mode 100644 board/freescale/p1022ds/p1022ds.c create mode 100644 board/freescale/p1022ds/tlb.c create mode 100644 include/configs/P1022DS.h diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..4b059ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -437,6 +437,7 @@ Timur Tabi <timur(a)freescale.com> MPC8349E-mITX MPC8349 MPC8349E-mITX-GP MPC8349 + P1022DS P1022 Erik Theisen <etheisen(a)mindspring.com> diff --git a/MAKEALL b/MAKEALL index bb09627..0950578 100755 --- a/MAKEALL +++ b/MAKEALL @@ -406,6 +406,7 @@ LIST_85xx=" \ MPC8569MDS_NAND \ MPC8572DS \ MPC8572DS_36BIT \ + P1022DS \ P2020DS \ P2020DS_36BIT \ P1011RDB \ diff --git a/Makefile b/Makefile index 1445e8b..55426a7 100644 --- a/Makefile +++ b/Makefile @@ -2489,6 +2489,10 @@ MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8572DS powerpc mpc85xx mpc8572ds freescale +# Also works when the P1022DS is switched to P1013 mode +P1022DS_config: unconfig + @$(MKCONFIG) -t $(@:_config=) P1022DS powerpc mpc85xx p1022ds freescale + P2020DS_36BIT_config \ P2020DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS powerpc mpc85xx p2020ds freescale diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index f064fee..a481326 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -63,6 +63,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o +COBJS-$(CONFIG_P1022) += p1022_serdes.o COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c new file mode 100644 index 0000000..52e109b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -0,0 +1,166 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Author: Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {NONE, NONE, NONE, NONE}, + [0x02] = {NONE, NONE, NONE, NONE}, + [0x03] = {NONE, NONE, NONE, NONE}, + [0x04] = {NONE, NONE, NONE, NONE}, + [0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2}, + [0x09] = {PCIE1, NONE, NONE, NONE}, + [0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2}, + [0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, + [0x15] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x16] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x17] = {PCIE1, PCIE3, PCIE2, PCIE2}, + [0x18] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x19] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1}, + [0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2}, + [0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {PCIE3, PCIE3}, + [0x01] = {PCIE2, PCIE3}, + [0x02] = {SATA1, SATA2}, + [0x03] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x04] = {NONE, NONE}, + [0x06] = {SATA1, SATA2}, + [0x07] = {NONE, NONE}, + [0x09] = {PCIE3, PCIE2}, + [0x0a] = {SATA1, SATA2}, + [0x0b] = {NONE, NONE}, + [0x0d] = {PCIE3, PCIE2}, + [0x0e] = {SATA1, SATA2}, + [0x0f] = {NONE, NONE}, + [0x15] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x16] = {SATA1, SATA2}, + [0x17] = {NONE, NONE}, + [0x18] = {PCIE3, PCIE3}, + [0x19] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1a] = {SATA1, SATA2}, + [0x1b] = {NONE, NONE}, + [0x1c] = {PCIE3, PCIE3}, + [0x1d] = {SGMII_TSEC1, SGMII_TSEC2}, + [0x1e] = {SATA1, SATA2}, + [0x1f] = {NONE, NONE}, +}; + +/* + * A list of PCI and SATA slots + */ +enum slot_id { + SLOT_PCIE1 = 1, + SLOT_PCIE2, + SLOT_PCIE3, + SLOT_PCIE4, + SLOT_PCIE5, + SLOT_SATA1, + SLOT_SATA2 +}; + +/* + * This array maps the slot identifiers to their names on the P1022DS board. + */ +static const char *slot_names[] = { + [SLOT_PCIE1] = "Slot 1", + [SLOT_PCIE2] = "Slot 2", + [SLOT_PCIE3] = "Slot 3", + [SLOT_PCIE4] = "Slot 4", + [SLOT_PCIE5] = "Mini-PCIe", + [SLOT_SATA1] = "SATA 1", + [SLOT_SATA2] = "SATA 2", +}; + +/* + * This array maps a given SERDES configuration and SERDES device to the PCI or + * SATA slot that it connects to. This mapping is hard-coded in the FPGA. + */ +static u8 serdes_dev_slot[][SATA2 + 1] = { + [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, + [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, + [PCIE2] = SLOT_PCIE5 }, + [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, + [PCIE2] = SLOT_PCIE3 }, + [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, + [PCIE2] = SLOT_PCIE3, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1c] = { [PCIE1] = SLOT_PCIE1, + [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, + [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, + [0x1f] = { [PCIE1] = SLOT_PCIE1 }, +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + unsigned int i; + + debug("%s: dev = %d\n", __FUNCTION__, device); + debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg); + return 0; + } + + for (i = 0; i < SRDS1_MAX_LANES; i++) { + if (serdes1_cfg_tbl[srds_cfg][i] == device) + return 1; + if (serdes2_cfg_tbl[srds_cfg][i] == device) + return 1; + } + + return 0; +} + +/* + * Returns the name of the slot to which the PCIe or SATA controller is + * connected + */ +const char *serdes_slot_name(enum srds_prtcl device) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + enum slot_id slot = serdes_dev_slot[srds_cfg][device]; + const char *name = slot_names[slot]; + + if (name) + return name; + else + return "Nothing"; +} diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index d4839f4..2056532 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -45,4 +45,6 @@ enum srds_prtcl { int is_serdes_configured(enum srds_prtcl device); +const char *serdes_slot_name(enum srds_prtcl device); + #endif /* __FSL_SERDES_H */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index f62f623..eb15b71 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -42,6 +42,7 @@ COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o COBJS-${CONFIG_MPC8555CDS} += cds_pci_ft.o +COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile new file mode 100644 index 0000000..8ede2d6 --- /dev/null +++ b/board/freescale/p1022ds/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1022ds/config.mk b/board/freescale/p1022ds/config.mk new file mode 100644 index 0000000..4581d20 --- /dev/null +++ b/board/freescale/p1022ds/config.mk @@ -0,0 +1,14 @@ +# +# Copyright 2010 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c new file mode 100644 index 0000000..7ecfb3e --- /dev/null +++ b/board/freescale/p1022ds/ddr.c @@ -0,0 +1,106 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> + * Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int ret; + + /* + * The P1022 has only one DDR controller, and the board has only one + * DIMM slot. + */ + ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, + sizeof(ddr3_spd_eeprom_t)); + if (ret) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS1); + memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; /* Range: 0-8 */ + u32 cpo; /* Range: 2-31 */ + u32 write_data_delay; /* Range: 0-6 */ + u32 force_2T; +} board_specific_parameters_t; + +static const board_specific_parameters_t bsp[] = { +/* + * lo| hi| num| clk| cpo|wrdata|2T + * mhz| mhz|ranks|adjst| | delay| + */ + { 0, 333, 1, 5, 31, 3, 0}, + {334, 400, 1, 5, 31, 3, 0}, + {401, 549, 1, 5, 31, 3, 0}, + {550, 680, 1, 5, 31, 5, 0}, + {681, 850, 1, 5, 31, 5, 0}, + { 0, 333, 2, 5, 31, 3, 0}, + {334, 400, 2, 5, 31, 3, 0}, + {401, 549, 2, 5, 31, 3, 0}, + {550, 680, 2, 5, 31, 5, 0}, + {681, 850, 2, 5, 31, 5, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned long ddr_freq; + unsigned int i; + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < ARRAY_SIZE(bsp); i++) { + if (ddr_freq >= bsp[i].datarate_mhz_low && + ddr_freq <= bsp[i].datarate_mhz_high && + pdimm->n_ranks == bsp[i].n_ranks) { + popts->clk_adjust = bsp[i].clk_adjust; + popts->cpo_override = bsp[i].cpo; + popts->write_data_delay = bsp[i].write_data_delay; + popts->twoT_en = bsp[i].force_2T; + break; + } + } + + popts->half_strength_driver_enable = 1; + + /* Per AN4039, enable ZQ calibration. */ + popts->zq_en = 1; + + /* + * For wake-up on ARP, we need auto self refresh enabled + */ + popts->auto_self_refresh_en = 1; + popts->sr_it = 0xb; +} diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c new file mode 100644 index 0000000..b23b8f9 --- /dev/null +++ b/board/freescale/p1022ds/law.c @@ -0,0 +1,21 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> + * Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c new file mode 100644 index 0000000..62d0c3a --- /dev/null +++ b/board/freescale/p1022ds/p1022ds.c @@ -0,0 +1,284 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> + * Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <tsec.h> +#include <asm/fsl_law.h> +#include <asm/mp.h> +#include <netdev.h> +#include <i2c.h> + +#include "../common/ngpixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, 0x1000); + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* Set the pin muxing to enable ETSEC2. */ + clrbits_be32(&gur->pmuxcr2, 0x001F8000); + + return 0; +} + +int checkboard(void) +{ + u8 sw; + + puts("Board: P1022DS "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + + switch ((sw & PIXIS_LBMAP_MASK) >> 6) { + case 0: + printf ("vBank: %u\n", ((sw & 0x30) >> 4)); + break; + case 1: + printf ("NAND\n"); + break; + case 2: + case 3: + puts ("Promjet\n"); + break; + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing....\n"); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; + + puts(" DDR: "); + return dram_size; +} + +#define CONFIG_TFP410_I2C_ADDR 0x38 + +int misc_init_r(void) +{ + u8 temp; + + /* Enable the TFP410 Encoder */ + + temp = 0xBF; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n", temp); + + temp = 0x10; + if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + /* Verify if enabled */ + temp = 0; + if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) + return -1; + + debug("DVI Encoder Read: 0x%02x\n",temp); + + return 0; +} + +static void configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected) +{ + static int bus_number = 0; + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf(" PCIE%u connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + bus_number = fsl_pci_init_port(info, hose, bus_number); +} + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct fsl_pci_info pci_info; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + SET_STD_PCIE_INFO(pci_info, 1); + configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); + } else { + printf(" PCIE1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + SET_STD_PCIE_INFO(pci_info, 2); + configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); + } else { + printf(" PCIE2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + SET_STD_PCIE_INFO(pci_info, 3); + configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); + } else { + printf(" PCIE3: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ +#endif +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci0", &pcie1_hose); +#else + ft_fsl_pci_setup(blob, "pci0", NULL); +#endif + +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#else + ft_fsl_pci_setup(blob, "pci1", NULL); +#endif + +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); +#else + ft_fsl_pci_setup(blob, "pci2", NULL); +#endif + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_fdt_fixup(blob); +#endif +} +#endif + +#ifdef CONFIG_MP +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c new file mode 100644 index 0000000..e620112 --- /dev/null +++ b/board/freescale/p1022ds/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> + * Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* W**G* - Flash/promjet, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4K, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h new file mode 100644 index 0000000..c87966c --- /dev/null +++ b/include/configs/P1022DS.h @@ -0,0 +1,473 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Srikanth Srinivasan <srikanth.srinivasan(a)freescale.com> + * Timur Tabi <timur(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/freescale/common/ics307_clk.h" + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ +#define CONFIG_P1022 +#define CONFIG_P1022DS +#define CONFIG_MP /* support multiple processors */ + +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_PHYS_64BIT +#define CONFIG_ENABLE_36BIT_PHYS +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE +#define CONFIG_BTB + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x7fffffff + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */ +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */ +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */ + +/* DDR Setup */ +#define CONFIG_DDR_SPD +#define CONFIG_VERY_BIG_RAM +#define CONFIG_FSL_DDR3 + +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_SYS_SPD_BUS_NUM 1 +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable + * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull + +#define CONFIG_FLASH_BR_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ + +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM + +#define CONFIG_SYS_FLASH_BANKS_LIST \ + {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_FSL_NGPIXIS +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS 0xfffdf0000ull + +#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xE0 +#define PIXIS_LBMAP_ALTBANK 0x20 + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) + +/* Video */ +/* #define CONFIG_VIDEO */ +#ifdef CONFIG_VIDEO +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_TSEC_ENET +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_TSECV2 +#define CONFIG_NET_MULTI + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_HOSTNAME p1022ds +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define CONFIG_BOOTARGS + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uramdisk\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1022ds.dtb\0" \ + "bdev=sda3\0" \ + "diuregs=md e002c000 1d\0" \ + "dium=mw e002c01c\0" \ + "diuerr=md e002c014 1\0" \ + "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \ + "monitor=0-DVI\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif -- 1.7.0.1

1 1

[U-Boot] Problems flashing kernel
by Kristoffer Ericson 08 Jun '10

08 Jun '10

Greetings, Im having issues making flashing work on my platform. Earlier it responded that flash was not erased, but after doing : HP Jornada# erase 0x00080000 0x03BFFFFF it worked. When I do: HP Jornada# cp.b 0xC00080000 0x00080000 1296996 (<- my kernel size) Copy to flash... . (and just sits there) I tried to increase the timeout defines but it still uses exact same timeout (4096ms erase, 2ms buffer-write-timeout, 1ms write-timeout). Chip is being reported as: Bank # 1: CFI conformant FLASH (32 x 16) Size: 64MB in 259 Sectors Intel Extended command set, Manufacturer ID:0x89, Device ID:0x19 Erase timeout: 4096ms, write timeout:1ms Buffer write timeout: 2ms, buffer size: 64 bytes Best wishes Kristoffer

2 7

[U-Boot] Please Pull u-boot-ti/master
by s-paulraj＠ti.com 08 Jun '10

08 Jun '10

Tom, Please pull u-boot-ti/master. There are some more patches but those would not apply clean. Will send a separate pull request for them. I ran MAKEALL for all ARM 11 and CORTEX A8 boards. Thanks, Sandeep The following changes since commit 9bb3b3d4406c1e388a99f6fb189147d6a06cc2cf: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx are available in the git repository at: git://git.denx.de/u-boot-ti.git master Cyril Chemparathy (3): ARM1176: Coexist with other ARM1176 platforms ARM1176: TI: TNETV107X soc initial support TI: TNETV107X EVM initial support Delio Brignoli (1): DaVinci: Improve DaVinci SPI speed. Vaibhav Hiremath (5): OMAP3EVM: Added NAND support omap3: Calculate CS1 size only when SDRC is omap3: Consolidate SDRC related operations AM35x: Add support for AM3517EVM AM35x: Add support for EMIF4 MAINTAINERS | 8 + MAKEALL | 2 + Makefile | 6 + arch/arm/cpu/arm1176/cpu.c | 3 - arch/arm/cpu/arm1176/start.S | 65 +++- arch/arm/cpu/arm1176/tnetv107x/Makefile | 44 +++ arch/arm/cpu/arm1176/tnetv107x/aemif.c | 93 +++++ arch/arm/cpu/arm1176/tnetv107x/clock.c | 451 +++++++++++++++++++++++ arch/arm/cpu/arm1176/tnetv107x/init.c | 37 ++ arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 25 ++ arch/arm/cpu/arm1176/tnetv107x/mux.c | 334 +++++++++++++++++ arch/arm/cpu/arm1176/tnetv107x/timer.c | 122 ++++++ arch/arm/cpu/arm1176/tnetv107x/wdt.c | 180 +++++++++ arch/arm/cpu/arm_cortexa8/omap3/Makefile | 5 +- arch/arm/cpu/arm_cortexa8/omap3/board.c | 34 +-- arch/arm/cpu/arm_cortexa8/omap3/emif4.c | 168 +++++++++ arch/arm/cpu/arm_cortexa8/omap3/mem.c | 90 ----- arch/arm/cpu/arm_cortexa8/omap3/sdrc.c | 202 ++++++++++ arch/arm/cpu/arm_cortexa8/omap3/sys_info.c | 41 -- arch/arm/include/asm/arch-omap3/cpu.h | 25 ++ arch/arm/include/asm/arch-omap3/emif4.h | 79 ++++ arch/arm/include/asm/arch-omap3/mem.h | 13 + arch/arm/include/asm/arch-omap3/sys_proto.h | 3 +- arch/arm/include/asm/arch-tnetv107x/clock.h | 68 ++++ arch/arm/include/asm/arch-tnetv107x/emif_defs.h | 1 + arch/arm/include/asm/arch-tnetv107x/hardware.h | 173 +++++++++ arch/arm/include/asm/arch-tnetv107x/mux.h | 306 +++++++++++++++ arch/arm/include/asm/arch-tnetv107x/nand_defs.h | 38 ++ board/logicpd/am3517evm/Makefile | 46 +++ board/logicpd/am3517evm/am3517evm.c | 76 ++++ board/logicpd/am3517evm/am3517evm.h | 445 ++++++++++++++++++++++ board/logicpd/am3517evm/config.mk | 30 ++ board/ti/tnetv107xevm/Makefile | 49 +++ board/ti/tnetv107xevm/config.mk | 20 + board/ti/tnetv107xevm/sdb_board.c | 149 ++++++++ drivers/spi/davinci_spi.c | 77 +++-- include/configs/am3517_evm.h | 296 +++++++++++++++ include/configs/devkit8000.h | 2 + include/configs/omap3_beagle.h | 2 + include/configs/omap3_evm.h | 10 +- include/configs/omap3_overo.h | 2 + include/configs/omap3_pandora.h | 2 + include/configs/omap3_sdp3430.h | 2 + include/configs/omap3_zoom1.h | 2 + include/configs/omap3_zoom2.h | 2 + include/configs/smdk6400.h | 8 +- include/configs/tnetv107x_evm.h | 153 ++++++++ 47 files changed, 3764 insertions(+), 225 deletions(-) create mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile create mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c create mode 100644 arch/arm/cpu/arm1176/tnetv107x/wdt.c create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/emif_defs.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h create mode 100644 arch/arm/include/asm/arch-tnetv107x/nand_defs.h create mode 100644 board/logicpd/am3517evm/Makefile create mode 100644 board/logicpd/am3517evm/am3517evm.c create mode 100644 board/logicpd/am3517evm/am3517evm.h create mode 100644 board/logicpd/am3517evm/config.mk create mode 100644 board/ti/tnetv107xevm/Makefile create mode 100644 board/ti/tnetv107xevm/config.mk create mode 100644 board/ti/tnetv107xevm/sdb_board.c create mode 100644 include/configs/am3517_evm.h create mode 100644 include/configs/tnetv107x_evm.h

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[U-Boot] Gregory J Kelsey is out of the office.
by gjkelsey＠rockwellcollins.com 08 Jun '10

08 Jun '10

I will be out of the office starting 06/07/2010 and will not return until 06/09/2010. I will respond to your message when I return. Please contact my manager Colleen Becker 319-295-1567 if you require immediate attention.

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[U-Boot] [PATCH v4] TI: DaVinci: Prepare for da850 support
by Sudhakar Rajashekhara 08 Jun '10

08 Jun '10

DA850/OMAP-L138 is a new SoC from Texas Instruments (http://focus.ti.com/docs/prod/folders/print/omap-l138.html). This SoC is similar to DA830/OMAP-L137 in many aspects. Hence rename the da830 specific files and folders to da8xx to accommodate DA850/OMAP-L138. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj(a)ti.com> Acked-by: Ben Gardiner <bengardiner(a)nanometrics.ca> Reviewed-by: Wolfgang Denk <wd(a)denx.de> --- Makefile | 2 +- board/davinci/{da830evm => da8xxevm}/Makefile | 5 ++++- board/davinci/{da830evm => da8xxevm}/common.c | 0 board/davinci/{da830evm => da8xxevm}/common.h | 0 board/davinci/{da830evm => da8xxevm}/config.mk | 0 board/davinci/{da830evm => da8xxevm}/da830evm.c | 0 6 files changed, 5 insertions(+), 2 deletions(-) rename board/davinci/{da830evm => da8xxevm}/Makefile (93%) rename board/davinci/{da830evm => da8xxevm}/common.c (100%) rename board/davinci/{da830evm => da8xxevm}/common.h (100%) rename board/davinci/{da830evm => da8xxevm}/config.mk (100%) rename board/davinci/{da830evm => da8xxevm}/da830evm.c (100%) diff --git a/Makefile b/Makefile index c26e491..1fb4d21 100644 --- a/Makefile +++ b/Makefile @@ -2917,7 +2917,7 @@ cp1026_config: unconfig @board/armltd/integrator/split_by_variant.sh cp $@ da830evm_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs da830evm davinci davinci + @$(MKCONFIG) $(@:_config=) arm arm926ejs da8xxevm davinci davinci davinci_dvevm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci diff --git a/board/davinci/da830evm/Makefile b/board/davinci/da8xxevm/Makefile similarity index 93% rename from board/davinci/da830evm/Makefile rename to board/davinci/da8xxevm/Makefile index ee00057..56047dc 100644 --- a/board/davinci/da830evm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -27,7 +27,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := da830evm.o common.o +COBJS-y += common.o +COBJS-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o + +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/davinci/da830evm/common.c b/board/davinci/da8xxevm/common.c similarity index 100% rename from board/davinci/da830evm/common.c rename to board/davinci/da8xxevm/common.c diff --git a/board/davinci/da830evm/common.h b/board/davinci/da8xxevm/common.h similarity index 100% rename from board/davinci/da830evm/common.h rename to board/davinci/da8xxevm/common.h diff --git a/board/davinci/da830evm/config.mk b/board/davinci/da8xxevm/config.mk similarity index 100% rename from board/davinci/da830evm/config.mk rename to board/davinci/da8xxevm/config.mk diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da8xxevm/da830evm.c similarity index 100% rename from board/davinci/da830evm/da830evm.c rename to board/davinci/da8xxevm/da830evm.c -- 1.5.6

1 0

[U-Boot] [PATCH v4] Support for TI's DA850/OMAP-L138 platform
by Sudhakar Rajashekhara 08 Jun '10

08 Jun '10

This patch series adds support for TI's DA850/OMAP-L138 platform. I have reworked on this series after submitting updated version of the following patch: [PATCH v5] da830: Move common code out of da830evm.c file This series is dependant on the above patch. Sudhakar Rajashekhara (2): TI: DaVinci: Prepare for da850 support TI: DaVinci: Add board specific code for da850 EVM MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 5 +- arch/arm/include/asm/arch-davinci/hardware.h | 1 + board/davinci/{da830evm => da8xxevm}/Makefile | 6 +- board/davinci/{da830evm => da8xxevm}/common.c | 0 board/davinci/{da830evm => da8xxevm}/common.h | 0 board/davinci/{da830evm => da8xxevm}/config.mk | 0 board/davinci/{da830evm => da8xxevm}/da830evm.c | 0 board/davinci/da8xxevm/da850evm.c | 111 ++++++++++++++++++ include/configs/da850evm.h | 140 +++++++++++++++++++++++ 11 files changed, 265 insertions(+), 3 deletions(-) rename board/davinci/{da830evm => da8xxevm}/Makefile (90%) rename board/davinci/{da830evm => da8xxevm}/common.c (100%) rename board/davinci/{da830evm => da8xxevm}/common.h (100%) rename board/davinci/{da830evm => da8xxevm}/config.mk (100%) rename board/davinci/{da830evm => da8xxevm}/da830evm.c (100%) create mode 100644 board/davinci/da8xxevm/da850evm.c create mode 100644 include/configs/da850evm.h

1 0

[U-Boot] Fw:How can I use yaffs2 in uboot
by jackfriend 08 Jun '10

08 Jun '10

Thank you for your help NOW with absolute path can write and read (small files) but When I write large files,such as 50M (Nand flash size is 256M) Display yaffs: Could not allocate Tnodes yaffs: Could not allocate Tnodes yaffs: Could not allocate Tnodes ... (Many) and then restart my2440 # yls /fash yaffs: Mounting /flash yaffs: Could not allocate Tnodes Error mounting /flash, return value: -12 opendir failed

3 2

[U-Boot] [PATCH] add support for EMK TOP7000 CPU Module (3rd try)
by Reinhard Meyer (-VC) 08 Jun '10

08 Jun '10

Add support for EMK TOP7000 CPU Module Specifics: 1) create subdir board/emk/top7000 and files in it 2) create include/configs/top7000.h 3) update board/emk/common/vpd.c 4) add call to misc_init_r() to arch/avr32/lib/board.c 5) create arch/avr32/include/asm/unaligned.h to fix zlib.c compilation problem 6) update Makefile, MAINTAINERS, MAKEALL Signed-off-by: Reinhard Meyer <info(a)emk-elektronik.de> --- MAINTAINERS | 6 +- MAKEALL | 1 + Makefile | 3 + arch/avr32/include/asm/unaligned.h | 1 + arch/avr32/lib/board.c | 5 + board/emk/common/vpd.c | 71 +++++++++++- board/emk/top7000/Makefile | 41 +++++++ board/emk/top7000/config.mk | 3 + board/emk/top7000/top7000.c | 174 +++++++++++++++++++++++++++++ board/emk/top7000/u-boot.lds | 72 ++++++++++++ include/configs/top7000.h | 217 ++++++++++++++++++++++++++++++++++++ 11 files changed, 587 insertions(+), 7 deletions(-) create mode 100644 arch/avr32/include/asm/unaligned.h create mode 100644 board/emk/top7000/Makefile create mode 100644 board/emk/top7000/config.mk create mode 100644 board/emk/top7000/top7000.c create mode 100644 board/emk/top7000/u-boot.lds create mode 100644 include/configs/top7000.h diff --git a/MAINTAINERS b/MAINTAINERS index 7a13d28..a361be1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -311,7 +311,7 @@ Andrea "llandre" Marson <andrea.marson(a)dave-tech.it> PPChameleonEVB PPC405EP -Reinhard Meyer <r.meyer(a)emk-elektronik.de> +Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> TOP860 MPC860T TOP5200 MPC5200 @@ -919,6 +919,10 @@ Julien May <julien.may(a)miromico.ch> HAMMERHEAD AT32AP7000 +Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> + + TOP7000 AT32AP7000 + Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> ATSTK1000 AT32AP7xxx diff --git a/MAKEALL b/MAKEALL index 2527352..016f6ef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -874,6 +874,7 @@ LIST_avr32=" \ favr-32-ezkit \ hammerhead \ mimc200 \ + top7000 \ " ######################################################################### diff --git a/Makefile b/Makefile index c26e491..e57a4ca 100644 --- a/Makefile +++ b/Makefile @@ -3549,6 +3549,9 @@ hammerhead_config : unconfig mimc200_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x +top7000_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap top7000 emk at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/arch/avr32/include/asm/unaligned.h b/arch/avr32/include/asm/unaligned.h new file mode 100644 index 0000000..6cecbbb --- /dev/null +++ b/arch/avr32/include/asm/unaligned.h @@ -0,0 +1 @@ +#include <asm-generic/unaligned.h> diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 917ed6c..6be5ab0 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -337,6 +337,11 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) jumptable_init(); console_init_r(); +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r(); +#endif + s = getenv("loadaddr"); if (s) load_addr = simple_strtoul(s, NULL, 16); diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c index c2af219..d2c8af2 100644 --- a/board/emk/common/vpd.c +++ b/board/emk/common/vpd.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2003 - * Reinhard Meyer, EMK Elektronik GmbH, r.meyer(a)emk-elektronik.de + * (C) Copyright 2003-2010 + * EMK Elektronik GmbH & Co. KG, reinhard.meyer(a)emk-elektronik.de * * See file CREDITS for list of people who contributed to this * project. @@ -22,10 +22,9 @@ */ #include <common.h> - -/***************************************************************************** - * read "factory" part of EEPROM and set some environment variables - *****************************************************************************/ +#include <command.h> + +/* read "factory" part of EEPROM and set some environment variables */ void read_factory_r (void) { /* read 'factory' part of EEPROM */ @@ -70,6 +69,10 @@ void read_factory_r (void) /* search for our specific entry */ if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) { setenv ("ethaddr", (char *)(buf + 19)); +#if defined(CONFIG_TOP7000) + } else if (!strncmp ((char *) buf, "[RLA/lan2/Ethernet] ", 20)) { + setenv ("eth1addr", (char *)(buf + 20)); +#endif } else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) { setenv ("serial#", (char *)(buf + 15)); } else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) { @@ -77,3 +80,59 @@ void read_factory_r (void) } } } + +#if defined(CONFIG_TOP7000_VPD) && defined(CONFIG_SYS_FACT_ENTRY) +/* + * create VPD entries to EEPROM. + * IEEE assigned MAC adress range to EMK are 00:80:d9:xx:xx:xx + * EMK assigned MAC adress range for TOP7000 is 00:80:d9:0d:hh:ll + * Every TOP7000 can potentially use 2 MAC adresses. + * hh:ll is derived from the board serial number as follows: + * MAC0: hh:ll = (serialnumber-1)*2 + * MAC1: hh:ll = (serialnumber-1)*2+1 + * Serialnumbers are guaranteed to be unique in the range of 1 to + * 32768 max. + */ +int do_vpd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uchar buf[512]; + uchar *p; + int i; + u_int addr; + + if (argc != 3) + return 1; + + p = buf+2; + i = simple_strtoul(argv[1], NULL, 10); + if (i<1 || i>32766) + return 1; + + addr=(i-1)*2; + + p+=sprintf((char*)p, + "[RLA/lan/Ethernet] 00:80:d9:0d:%02x:%02x\n", + addr/256, addr%256); + addr++; + p+=sprintf((char*)p, + "[RLA/lan2/Ethernet] 00:80:d9:0d:%02x:%02x\n", + addr/256, addr%256); + p+=sprintf((char*)p, "[BOARD/SERIAL] %05d\n", i); + p+=sprintf((char*)p, "[BOARD/TYPE] %s\n", argv[2]); + + i = p-buf-2; + buf[0]=i; + buf[1]=i>>8; + if (eeprom_write (CONFIG_SYS_I2C_FACT_ADDR, + CONFIG_SYS_FACT_OFFSET, buf, i+2)) { + printf ("cannot write factory configuration\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD(vpd, 3, 0, do_vpd, + "enter vital product data", + "serialnumber type"); +#endif diff --git a/board/emk/top7000/Makefile b/board/emk/top7000/Makefile new file mode 100644 index 0000000..1fcf08b --- /dev/null +++ b/board/emk/top7000/Makefile @@ -0,0 +1,41 @@ +# +# (C) Copyright 2010 +# EMK Elektronik GmbH & Co. KG, reinhard.meyer(a)emk-elektronik.de +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o ../common/vpd.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/emk/top7000/config.mk b/board/emk/top7000/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/emk/top7000/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/emk/top7000/top7000.c b/board/emk/top7000/top7000.c new file mode 100644 index 0000000..171c7ee --- /dev/null +++ b/board/emk/top7000/top7000.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * EMK Elektronik GmbH & Co. KG, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <asm/arch/portmux.h> +#include <netdev.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_16BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 7, + .trp = 2, + .trcd = 2, + .tras = 5, + .txsr = 5, + /* 7.81 us */ + .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + /* 16 data, 26 address lines */ + portmux_enable_ebi(16, 26, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + +#if defined(CONFIG_MACB) + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); +#endif +#if defined(CONFIG_MMC) + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); +#endif +#if defined(CONFIG_ATMEL_SPI) + portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); +#endif +#ifdef CONFIG_CMD_I2C + /* set SCL and SDA to open drain gpio */ + portmux_select_gpio(PORTMUX_PORT_A,(1<<SDA_PIN), + PORTMUX_DIR_OUTPUT|PORTMUX_INIT_LOW|PORTMUX_OPEN_DRAIN); + portmux_select_gpio(PORTMUX_PORT_A,(1<<SCL_PIN), + PORTMUX_DIR_OUTPUT|PORTMUX_INIT_LOW|PORTMUX_OPEN_DRAIN); + /* initialize i2c. note: params ignored in SOFT I2C */ + i2c_init(0, 0); +#endif + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +int board_early_init_r(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + gd->bd->bi_phy_id[1] = 0x03; + return 0; +} + +int misc_init_r(void) +{ + /* read 'factory' part of EEPROM */ + extern void read_factory_r(void); + read_factory_r(); + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bi) +{ + int rc; + rc = macb_eth_initialize(0, + (void *)MACB0_BASE, bi->bi_phy_id[0]); + if (rc < 0) + return rc; + rc = macb_eth_initialize(1, + (void *)MACB1_BASE, bi->bi_phy_id[1]); + if (rc < 0) + return 1; + return 2; +} +#endif + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> + +#define DATAFLASH_CS_PIN GPIO_PIN_PA(3) + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + gpio_set_value(DATAFLASH_CS_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + gpio_set_value(DATAFLASH_CS_PIN, 1); +} +#endif /* CONFIG_ATMEL_SPI */ + +/* I2C access functions */ +#ifdef CONFIG_CMD_I2C + +int iic_read(void) +{ + return pio_get_input_value(GPIO_PIN_PA(SDA_PIN)); +} + +void iic_sda(int bit) +{ + pio_set_output_value(GPIO_PIN_PA(SDA_PIN),bit); +} + +void iic_scl(int bit) +{ + pio_set_output_value(GPIO_PIN_PA(SCL_PIN),bit); +} + +#endif /* CONFIG_CMD_I2C */ diff --git a/board/emk/top7000/u-boot.lds b/board/emk/top7000/u-boot.lds new file mode 100644 index 0000000..ffa119b --- /dev/null +++ b/board/emk/top7000/u-boot.lds @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2010 + * EMK Elektronik GmbH & Co. KG, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/top7000.h b/include/configs/top7000.h new file mode 100644 index 0000000..e509611 --- /dev/null +++ b/include/configs/top7000.h @@ -0,0 +1,217 @@ +/* + * (C) Copyright 2010 + * EMK Elektronik GmbH & Co. KG, reinhard.meyer(a)emk-elektronik.de + * + * Configuration settings for the TOP7000 CPU Module + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TOP7000 features/differences to ATNGW100: + * + * parallel FLASH upto 64MB (typically S29GL128/256/512Pxxxx) + * no serial FLASH (SPI not used) + * optional micro SD card for root and user file systems + * VPD and environment in I2C EEPROM + * kernel as image in parallel FLASH + * + * parallel FLASH partitioning: + * 00000000-00020000 128k U-Boot + * 00020000-00200000 2M-128k kernel + * 00200000-end root file system + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_TOP7000 1 +#define CONFIG_SYS_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CONFIG_SYS_POWER_MANAGER 1 +#define CONFIG_SYS_OSC0_HZ 20000000 +#define CONFIG_SYS_PLL0_DIV 1 +#define CONFIG_SYS_PLL0_MUL 7 +#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 +#define CONFIG_SYS_CLKDIV_CPU 0 +#define CONFIG_SYS_CLKDIV_HSB 1 +#define CONFIG_SYS_CLKDIV_PBA 2 +#define CONFIG_SYS_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CONFIG_SYS_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/mtdblock2 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "bootm 0xa0020000" + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_AUTOBOOT 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_I2C + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_XIMG + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PORTMUX_PIO 1 +#define CONFIG_SYS_NR_PIOS 5 +#define CONFIG_SYS_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CONFIG_SYS_DCACHE_LINESZ 32 +#define CONFIG_SYS_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 + +/* I2C configuration */ +#define CONFIG_SOFT_I2C 1 +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define SDA_PIN 6 +#define SCL_PIN 7 +#define I2C_SOFT_DECLARATIONS int iic_read(void);\ + void iic_sda(int);\ + void iic_scl(int); +#define I2C_ACTIVE +#define I2C_TRISTATE +#define I2C_READ iic_read() +#define I2C_SDA(bit) iic_sda(bit) +#define I2C_SCL(bit) iic_scl(bit) +#define I2C_DELAY udelay(3) + +/* EEPROM configuration */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_SIZE 0x2000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_MISC_INIT_R + +/* Environment settings */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_ENV_OFFSET 0x1000 +#define CONFIG_ENV_SIZE 0x0700 +#define CONFIG_ENV_OVERWRITE + +/* VPD settings */ +#define CONFIG_SYS_I2C_FACT_ADDR 0x57 +#define CONFIG_SYS_FACT_OFFSET 0x1800 +#define CONFIG_SYS_FACT_SIZE 0x0800 +/* define the next only if you want to allow users to enter VPD data */ +#define CONFIG_SYS_FACT_ENTRY 1 + +/* MAX 64MB S29GL512Pxxx, 512 sectors */ +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_SYS_FLASH_SIZE 0x4000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE +#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#define CONFIG_SYS_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CONFIG_SYS_PROMPT "top7000> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 + +#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) + +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */ -- 1.5.6.5

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