June 2010 - U-Boot

[U-Boot] [PATCH 1/2] NAND: show manufacturer and device ID for unknown chips
by Florian Fainelli 21 Jun '10

21 Jun '10

When the NAND part is not supported, it is useful to show the manufacturer and device ID to help debugging and reporting. Signed-off-by: Florian Fainelli <f.fainelli(a)gmail.com> --- diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 7171bdd..c1657de 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2652,8 +2652,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, } } - if (!type) + if (!type) { + printk(KERN_INFO "%s: unknown NAND device: Manufacturer ID :" + " 0x%02x, Chip ID: 0x%02x\n", __func__, + *maf_id, dev_id); return ERR_PTR(-ENODEV); + } if (!mtd->name) mtd->name = type->name;

3 2

[U-Boot] [PATCH v2] [U-BOOT] Zoom3: Add support for OMAP3630 Zoom3 board.
by Aldo Cedillo 21 Jun '10

21 Jun '10

From: Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> This patch gives basic funcionality to OMAP3630 Zoom3 board. Signed-off-by: Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/logicpd/zoom3/Makefile | 54 +++++++ board/logicpd/zoom3/config.mk | 33 +++++ board/logicpd/zoom3/debug_board.c | 66 +++++++++ board/logicpd/zoom3/led.c | 133 ++++++++++++++++++ board/logicpd/zoom3/zoom3.c | 201 ++++++++++++++++++++++++++ board/logicpd/zoom3/zoom3.h | 163 ++++++++++++++++++++++ board/logicpd/zoom3/zoom3_serial.c | 132 +++++++++++++++++ board/logicpd/zoom3/zoom3_serial.h | 76 ++++++++++ common/serial.c | 2 + include/configs/omap3_zoom3.h | 271 ++++++++++++++++++++++++++++++++++++ include/serial.h | 7 + 14 files changed, 1146 insertions(+), 0 deletions(-) create mode 100644 board/logicpd/zoom3/Makefile create mode 100644 board/logicpd/zoom3/config.mk create mode 100644 board/logicpd/zoom3/debug_board.c create mode 100644 board/logicpd/zoom3/led.c create mode 100644 board/logicpd/zoom3/zoom3.c create mode 100644 board/logicpd/zoom3/zoom3.h create mode 100644 board/logicpd/zoom3/zoom3_serial.c create mode 100644 board/logicpd/zoom3/zoom3_serial.h create mode 100644 include/configs/omap3_zoom3.h diff --git a/MAINTAINERS b/MAINTAINERS index 7a13d28..384dda9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -798,6 +798,10 @@ Alex Z lart SA1100 dnp1110 SA1110 +Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> + + omap3_zoom3 ARM CORTEX-A8 (OMAP3xx SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 2527352..8ebeaad 100755 --- a/MAKEALL +++ b/MAKEALL @@ -650,6 +650,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ + omap3_zoom3 \ smdkc100 \ " diff --git a/Makefile b/Makefile index c26e491..198ee67 100644 --- a/Makefile +++ b/Makefile @@ -3179,6 +3179,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3 +omap3_zoom3_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom3 logicpd omap3 + smdkc100_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx diff --git a/board/logicpd/zoom3/Makefile b/board/logicpd/zoom3/Makefile new file mode 100644 index 0000000..79c02ab --- /dev/null +++ b/board/logicpd/zoom3/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Aldo Cedillo <aldo.cedillo(a)ti.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-y += debug_board.o +COBJS-y += zoom3_serial.o +COBJS-$(CONFIG_STATUS_LED) += led.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +#defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/logicpd/zoom3/config.mk b/board/logicpd/zoom3/config.mk new file mode 100644 index 0000000..33f394b --- /dev/null +++ b/board/logicpd/zoom3/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2009 +# Texas Instruments, <www.ti.com> +# +# Zoom II uses OMAP3 (ARM-CortexA8) CPU +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 0x80000000 (bank0) +# 0xA0000000 (bank1) +# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/logicpd/zoom3/debug_board.c b/board/logicpd/zoom3/debug_board.c new file mode 100644 index 0000000..0cb84ed --- /dev/null +++ b/board/logicpd/zoom3/debug_board.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2010 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/gpio.h> + +#define DEBUG_BOARD_CONNECTED 1 +#define DEBUG_BOARD_NOT_CONNECTED 0 + +static int debug_board_connected = DEBUG_BOARD_CONNECTED; + +static void zoom3_debug_board_detect(void) +{ + int val = 0; + + /* + * TODO gpio 158 is UART1_RX, should we make a macro of this + * instead of the raw number? + */ + if (!omap_request_gpio(158)) { + /* + * GPIO to query for debug board + * 158 db board query + */ + omap_set_gpio_direction(158, 1); + val = omap_get_gpio_datain(158); + omap_free_gpio(158); + } + + if (!val) + debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; +} + +int zoom3_debug_board_connected(void) +{ + static int first_time = 1; + + if (first_time) { + zoom3_debug_board_detect(); + first_time = 0; + } + + return debug_board_connected; +} diff --git a/board/logicpd/zoom3/led.c b/board/logicpd/zoom3/led.c new file mode 100644 index 0000000..1871d79 --- /dev/null +++ b/board/logicpd/zoom3/led.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <status_led.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> + +static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; + +/* + * GPIO LEDs + * 173 red + * 154 blue + * 61 blue2 + */ +#define ZOOM3_LED_RED 173 +#define ZOOM3_LED_BLUE 154 +#define ZOOM3_LED_BLUE2 61 + +void red_LED_off(void) +{ + /* red */ + if (!omap_request_gpio(ZOOM3_LED_RED)) { + omap_set_gpio_direction(ZOOM3_LED_RED, 0); + omap_set_gpio_dataout(ZOOM3_LED_RED, 0); + } + + saved_state[STATUS_LED_RED] = STATUS_LED_OFF; +} + +void blue_LED_off(void) +{ + /* blue */ + if (!omap_request_gpio(ZOOM3_LED_BLUE)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE, 0); + } + + /* blue 2 */ + if (!omap_request_gpio(ZOOM3_LED_BLUE2)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 0); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; +} + +void red_LED_on(void) +{ + blue_LED_off(); + + /* red */ + if (!omap_request_gpio(ZOOM3_LED_RED)) { + omap_set_gpio_direction(ZOOM3_LED_RED, 0); + omap_set_gpio_dataout(ZOOM3_LED_RED, 1); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; +} + +void blue_LED_on(void) +{ + red_LED_off(); + + /* blue */ + if (!omap_request_gpio(ZOOM3_LED_BLUE)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE, 1); + } + + /* blue 2 */ + if (!omap_request_gpio(ZOOM3_LED_BLUE2)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 1); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) + blue_LED_off(); + else + blue_LED_on(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_LED_off(); + else + red_LED_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == state) + blue_LED_on(); + else + blue_LED_off(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_LED_on(); + else + red_LED_off(); + } +} diff --git a/board/logicpd/zoom3/zoom3.c b/board/logicpd/zoom3/zoom3.c new file mode 100644 index 0000000..f5a8201 --- /dev/null +++ b/board/logicpd/zoom3/zoom3.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2010 Texas Instruments <www.ti.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Derived from Zoom2 code by + * Tom Rix <Tom.Rix(a)windriver.com> + * + * Derived from Zoom1 code by + * Nishanth Menon <nm(a)ti.com> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "zoom3.h" +#include "zoom3_serial.h" + + +/* + * This is the zoom3, board specific, gpmc configuration for the + * quad uart on the debug board. The more general gpmc configurations + * are setup at the cpu level in vim arch/arm/cpu/armv7/omap3/mem.c + * + * The details of the setting of the serial gpmc setup are not available. + * The values were provided by another party. + */ +static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { + 0x00011000, + 0x001f1f01, + 0x00080803, + 0x1d091d09, + 0x041f1f1f, + 0x1d0904c4, 0 +}; + +/* Used to track the revision of the board */ +static zoom3_revision revision = ZOOM3_REVISION_UNKNOWN; + +/* + * Routine: zoom3_get_version + * Description: Return the revision of the Zoom3 this code is running on. + */ +zoom3_revision zoom3_get_revision(void) +{ + return revision; +} + +/* + * Routine: zoom3_identify + * Description: Detect which version of Zoom3 we are running on. + */ +void zoom3_identify(void) +{ + /* + * To check for production board vs beta board, + * check if gpio 94 is clear. + * + * No way yet to check for alpha board identity. + * Alpha boards were produced in very limited quantities + * and they are not commonly used. The are mentioned here + * only for completeness. + */ + if (!omap_request_gpio(94)) { + unsigned int val; + + omap_set_gpio_direction(94, 1); + val = omap_get_gpio_datain(94); + omap_free_gpio(94); + + if (val) + revision = ZOOM3_REVISION_BETA; + else + revision = ZOOM3_REVISION_PRODUCTION; + } + + puts("Board revision "); + + switch (revision) { + case ZOOM3_REVISION_PRODUCTION: + puts("Production\n"); + break; + case ZOOM3_REVISION_BETA: + puts("Beta\n"); + break; + default: + puts("Unknown\n"); + break; + } +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + u32 *gpmc_config; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* Configure console support for zoom3 */ + gpmc_config = gpmc_serial_TL16CP754C; + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], + SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); + + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM3; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP36XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure zoom board specific configurations + */ +int misc_init_r(void) +{ + zoom3_identify(); + #if (CONFIG_TWL4030_POWER) + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + #endif + dieid_num_r(); + + /* + * Board reset + * The board is reset by holding the large button + * on the top right side of the main board + * for eight seconds + * + * There are reported problems of some beta boards + * continously resetting. For those boards, disable resetting. + */ + #if (CONFIG_TWL4030_POWER) + if (ZOOM3_REVISION_PRODUCTION <= zoom3_get_revision()) + twl4030_power_reset_init(); + #endif + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuratino Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_ZOOM3(); +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_LAN91C96 + rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); +#endif + return rc; +} +#endif diff --git a/board/logicpd/zoom3/zoom3.h b/board/logicpd/zoom3/zoom3.h new file mode 100644 index 0000000..7ef4af0 --- /dev/null +++ b/board/logicpd/zoom3/zoom3.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2010 Texas Instruments + * + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Derived from: board/omap3/zoom2/zoom2.h + * Tom Rix <Tom.Rix(a)windriver.com> + * + * Derived from: board/omap3/zoom1/zoom1.h + * Nishanth Menon <nm(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_ZOOM3_H_ +#define _BOARD_ZOOM3_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 Zoom3", + "NAND", +}; + +typedef enum { + ZOOM3_REVISION_UNKNOWN = 0, + ZOOM3_REVISION_ALPHA, + ZOOM3_REVISION_BETA, + ZOOM3_REVISION_PRODUCTION +} zoom3_revision; + +zoom3_revision zoom3_get_revision(void); + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_ZOOM3() \ + /* SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ +/* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ +/* IDCC modem Power On */\ + MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ + MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ +/* GPMC CS7 has LAN9211 device */\ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ +/* GPMC CS3 has Serial TL16CP754C device */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ +/* Toggle Reset pin of TL16CP754C device */\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ + udelay(10);\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ +/* LEDS */\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */ + +#endif /* _BOARD_ZOOM3_H_ */ diff --git a/board/logicpd/zoom3/zoom3_serial.c b/board/logicpd/zoom3/zoom3_serial.c new file mode 100644 index 0000000..e50c6dc --- /dev/null +++ b/board/logicpd/zoom3/zoom3_serial.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c + * + */ + +#include <common.h> +#include <serial.h> +#include <ns16550.h> +#include <asm/arch/cpu.h> +#include "zoom3_serial.h" + +int quad_init_dev(unsigned long base) +{ + /* + * The Quad UART is on the debug board. + * Check if the debug board is attached before using the UART + */ + if (zoom3_debug_board_connected()) { + NS16550_t com_port = (NS16550_t) base; + int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / + CONFIG_BAUDRATE; + /* + * Zoom3 has a board specific initialization of its UART. + * This generic initialization has been copied from + * drivers/serial/ns16550.c. The macros have been expanded. + * + * Do the following instead of + * NS16550_init (com_port, clock_divisor); + */ + com_port->ier = 0x00; + + /* + * On Zoom3 board Set pre-scalar to 1 + * CLKSEL is GND => MCR[7] is 1 => preslr is 4 + * So change the prescl to 1 + */ + com_port->lcr = 0xbf; + com_port->fcr |= 0x10; + com_port->mcr &= 0x7f; + + /* This is generic ns16550.c setup */ + com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; + com_port->dll = 0; + com_port->dlm = 0; + com_port->lcr = UART_LCR_8N1; + com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; + com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | + UART_FCR_TXSR; + com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = UART_LCR_8N1; + } + + /* + * We have to lie here, otherwise the board init code will hang + * on the check + */ + return 0; +} + +void quad_putc_dev(unsigned long base, const char c) +{ + if (zoom3_debug_board_connected()) { + if (c == '\n') + quad_putc_dev(base, '\r'); + + NS16550_putc((NS16550_t) base, c); + } else { + usbtty_putc(c); + } +} + +void quad_puts_dev(unsigned long base, const char *s) +{ + if (zoom3_debug_board_connected()) { + while ((s != NULL) && (*s != '\0')) + quad_putc_dev(base, *s++); + } else { + usbtty_puts(s); + } +} + +int quad_getc_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) + return NS16550_getc((NS16550_t) base); + + return usbtty_getc(); +} + +int quad_tstc_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) + return NS16550_tstc((NS16550_t) base); + + return usbtty_tstc(); +} + +void quad_setbrg_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) { + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / + CONFIG_BAUDRATE; + + NS16550_reinit((NS16550_t) base, clock_divisor); + } +} + +QUAD_INIT(0) +QUAD_INIT(1) +QUAD_INIT(2) +QUAD_INIT(3) diff --git a/board/logicpd/zoom3/zoom3_serial.h b/board/logicpd/zoom3/zoom3_serial.h new file mode 100644 index 0000000..f581a7f --- /dev/null +++ b/board/logicpd/zoom3/zoom3_serial.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef ZOOM3_SERIAL_H +#define ZOOM3_SERIAL_H + +extern int zoom3_debug_board_connected(void); + +#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom3 serial chip address */ + +#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE +#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) +#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) +#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) + +#define S(a) #a +#define N(a) S(quad##a) +#define U(a) S(UART##a) + +#define QUAD_INIT(n) \ +int quad_init_##n(void) \ +{ \ + return quad_init_dev(QUAD_BASE_##n); \ +} \ +void quad_setbrg_##n(void) \ +{ \ + quad_setbrg_dev(QUAD_BASE_##n); \ +} \ +void quad_putc_##n(const char c) \ +{ \ + quad_putc_dev(QUAD_BASE_##n, c); \ +} \ +void quad_puts_##n(const char *s) \ +{ \ + quad_puts_dev(QUAD_BASE_##n, s); \ +} \ +int quad_getc_##n(void) \ +{ \ + return quad_getc_dev(QUAD_BASE_##n); \ +} \ +int quad_tstc_##n(void) \ +{ \ + return quad_tstc_dev(QUAD_BASE_##n); \ +} \ +struct serial_device zoom3_serial_device##n = \ +{ \ + N(n), \ + U(n), \ + quad_init_##n, \ + NULL, \ + quad_setbrg_##n, \ + quad_getc_##n, \ + quad_tstc_##n, \ + quad_putc_##n, \ + quad_puts_##n, \ +}; + +#endif /* ZOOM3_SERIAL_H */ diff --git a/common/serial.c b/common/serial.c index fceabfa..2a644ba 100644 --- a/common/serial.c +++ b/common/serial.c @@ -92,6 +92,8 @@ struct serial_device *__default_serial_console (void) #endif #elif defined(CONFIG_OMAP3_ZOOM2) return ZOOM2_DEFAULT_SERIAL_DEVICE; +#elif defined(CONFIG_OMAP3_ZOOM3) + return ZOOM3_DEFAULT_SERIAL_DEVICE; #else #error No default console #endif diff --git a/include/configs/omap3_zoom3.h b/include/configs/omap3_zoom3.h new file mode 100644 index 0000000..e70f1cf --- /dev/null +++ b/include/configs/omap3_zoom3.h @@ -0,0 +1,271 @@ +/* + * (C) Copyright 2006-2010 Texas Instruments. + * + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * Nishanth Menon <nm(a)ti.com> + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Configuration settings for the TI OMAP3630 Zoom 3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP36XX 1 /* which is a 36XX */ +#define CONFIG_OMAP3_ZOOM3 1 /* working with a Zoom3 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock defines */ +#define V_OSCK 2600000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +/* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + * Zoom3 uses the TL16CP754C on the debug board + */ +#define CONFIG_SERIAL_MULTI 1 + +/* + * 0 - 1 : first USB with respect to the left edge of the debug board + * 2 - 3 : second USB with respect to the left edge of the debug board + */ +#define ZOOM3_DEFAULT_SERIAL_DEVICE (&zoom3_serial_device0) + +#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_REG_SIZE (-2) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200} + +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* DDR - Use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_BLUE 0 /* Check what color is used */ +#define STATUS_LED_RED 1 /* when using 3630 */ +/* Blue */ +#define STATUS_LED_BIT STATUS_LED_BLUE +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ +#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ +#endif +#define CONFIG_OMAP3_GPIO_3 /* board revision */ +#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "Zoom3" + +/* Commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_FAT /* FAT support */ +#undef CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH + +/* + * Board NAND info + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_PROMPT "OMAP3 Zoom3 #" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* Memset from start of memory to 31MB */ +#define OMAP36XX_SDRC_CS0 OMAP34XX_SDRC_CS0 /* It's the same as in 34XX */ +#define CONFIG_SYS_MEMTEST_START (OMAP36XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP36XX_SDRC_CS0 + 0x01f00000) +/* The default load address is the start of memory */ +#define CONFIG_SYS_LOAD_ADDR (OMAP36XX_SDRC_CS0) +/* Everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define OMAP36XX_GPT2 OMAP34XX_GPT2 /* It's the same as in 34XX */ +#define CONFIG_SYS_TIMERBASE (OMAP36XX_GPT2) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using these settings + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/* + * Physical memory map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not */ + /* be populated */ +#define PHYS_SDRAM_1 OMAP36XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) +#define PHYS_SDRAM_2 OMAP36XX_SDRC_CS1 + +/* SDRAM bank allocation method */ +#define SDRC_R_B_C + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT **** */ +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_blash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ + diff --git a/include/serial.h b/include/serial.h index 6513d8e..236e5d1 100644 --- a/include/serial.h +++ b/include/serial.h @@ -66,6 +66,13 @@ extern struct serial_device zoom2_serial_device2; extern struct serial_device zoom2_serial_device3; #endif +#if defined(CONFIG_OMAP3_ZOOM3) +extern struct serial_device zoom3_serial_device0; +extern struct serial_device zoom3_serial_device1; +extern struct serial_device zoom3_serial_device2; +extern struct serial_device zoom3_serial_device3; +#endif + extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; extern struct serial_device serial_stuart_device; -- 1.6.3.3

2 1

[U-Boot] [PATCH 1/3] add support for arm926ejs-based pollux CPU
by Brian Cavagnolo 21 Jun '10

21 Jun '10

Signed-off-by: Brian Cavagnolo <brian(a)cozybit.com> Signed-off-by: Andrey Yurovsky <yurovsky(a)gmail.com> --- arch/arm/cpu/arm926ejs/pollux/Makefile | 51 ++++++++ arch/arm/cpu/arm926ejs/pollux/reset.S | 49 ++++++++ arch/arm/cpu/arm926ejs/pollux/timer.c | 190 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-pollux/clkpwr.h | 83 +++++++++++++ arch/arm/include/asm/arch-pollux/gpio.h | 143 ++++++++++++++++++++++ arch/arm/include/asm/arch-pollux/reg.h | 39 ++++++ arch/arm/include/asm/arch-pollux/timer.h | 59 +++++++++ arch/arm/include/asm/arch-pollux/uart.h | 105 ++++++++++++++++ 8 files changed, 719 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pollux/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pollux/reset.S create mode 100644 arch/arm/cpu/arm926ejs/pollux/timer.c create mode 100644 arch/arm/include/asm/arch-pollux/clkpwr.h create mode 100644 arch/arm/include/asm/arch-pollux/gpio.h create mode 100644 arch/arm/include/asm/arch-pollux/reg.h create mode 100644 arch/arm/include/asm/arch-pollux/timer.h create mode 100644 arch/arm/include/asm/arch-pollux/uart.h diff --git a/arch/arm/cpu/arm926ejs/pollux/Makefile b/arch/arm/cpu/arm926ejs/pollux/Makefile new file mode 100644 index 0000000..32803ff --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/Makefile @@ -0,0 +1,51 @@ +# (C) Copyright 2010 cozybit, Inc +# Brian Cavagnolo <brian(a)cozybit.com> +# +# Derived from versatile cpu support: +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o +SOBJS = reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/pollux/reset.S b/arch/arm/cpu/arm926ejs/pollux/reset.S new file mode 100644 index 0000000..a66a89f --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/reset.S @@ -0,0 +1,49 @@ +/* (C) Copyright 2010 cozybit, Inc + * Brian Cavagnolo <brian(a)cozybit.com> + * + * Derived from versatile cpu support: + * + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c b/arch/arm/cpu/arm926ejs/pollux/timer.c new file mode 100644 index 0000000..fc6c699 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/timer.c @@ -0,0 +1,190 @@ +/* (C) Copyright 2010 cozybit, Inc + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc + * + * Derived from versatile cpu support: + * + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/reg.h> +#include <asm/arch/timer.h> + +#ifndef CONFIG_SYS_TIMERBASE +#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE" +#endif +#define TIMERBASE CONFIG_SYS_TIMERBASE + +#define TIMER_LOAD_VAL 0xffffffff + +static ulong inline read_timer(void) +{ + REG32(TIMERBASE + TMRCONTROL) |= (1<<LDCNT); + return REG32(TIMERBASE + TMRMATCH); +} + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + REG32(TIMERBASE + TMRCLKENB) = (1<<TCLKMODE)|(1<<TCLKGENENB); + REG32(TIMERBASE + TMRCOUNT) = 0; + REG32(TIMERBASE + TMRMATCH) = TIMER_LOAD_VAL; + REG32(TIMERBASE + TMRCONTROL) |= (1<<RUN); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked(); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = read_timer(); /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = read_timer(); /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/arch/arm/include/asm/arch-pollux/clkpwr.h b/arch/arm/include/asm/arch-pollux/clkpwr.h new file mode 100644 index 0000000..d6e97d2 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/clkpwr.h @@ -0,0 +1,83 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" <yurovsky(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CLKPWR_H__ +#define __CLKPWR_H__ + +/* Clock and Power Control Registers */ +#define CLKPWR_BASE 0xC000F000 +#define CLKMODEREG (CLKPWR_BASE + 0x000) +#define PLLSETREG0 (CLKPWR_BASE + 0x004) +#define PLLSETREG1 (CLKPWR_BASE + 0x008) +#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040) +#define RTCWAKEUPENB (CLKPWR_BASE + 0x044) +#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048) +#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C) +#define GPIOPEND (CLKPWR_BASE + 0x050) +#define INTPENDSPAD (CLKPWR_BASE + 0x058) +#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C) +#define INTENB (CLKPWR_BASE + 0x060) +#define PWRMODE (CLKPWR_BASE + 0x07C) +#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100) +#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104) +#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108) +#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C) +#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110) +#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114) +#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118) + +/* Clock Mode Register (CLKMODEREG) */ +#define PLLPWDN1 30 +#define CLKSELBCLK 24 +#define CLKDIV1BCLK 20 +#define CLKDIV2CPU0 6 +#define CLKSELCPU0 4 +#define CLKDIVCPU0 0 + +/* PLL0/PLL1 Setting Register (PLLSETREG0/PLLSETREG1) */ +#define PDIV 18 +#define MDIV 8 +#define SDIV 0 + +/* convenience macro for setting PLL */ +#define PLL_REG(m, p, s) \ + (((unsigned int)(m) << MDIV) | \ + ((unsigned int)(p) << PDIV) | \ + ((unsigned int)(s) << SDIV)) + +/* Power Mode Control Register (PWRMODE) */ +#define CHGPLL 15 +#define GPIOSWRSTENB 13 +#define SWRST 12 +#define LASTPWRMODE 4 +#define CURPWRMODE 0 + +/* Interrupt Pending & Scratch Pad Register (INTPENDSPAD) */ +#define BATFW 14 +#define GPIORESETW 13 +#define WATCHDOGRSTW 12 +#define POWERONRSTW 11 + +#endif /* __CLKPWR_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/gpio.h b/arch/arm/include/asm/arch-pollux/gpio.h new file mode 100644 index 0000000..f6ddd1b --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/gpio.h @@ -0,0 +1,143 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" <yurovsky(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +/* GPIO registers */ +#define GPIO_BASE 0xC000A000 + +#define GPIOAOUT (GPIO_BASE + 0x00) +#define GPIOAOUTENB (GPIO_BASE + 0x04) +#define GPIOADETMODE0 (GPIO_BASE + 0x08) +#define GPIOADETMODE1 (GPIO_BASE + 0x0C) +#define GPIOAINTENB (GPIO_BASE + 0x10) +#define GPIOADET (GPIO_BASE + 0x14) +#define GPIOAPAD (GPIO_BASE + 0x18) +#define GPIOAPUENB (GPIO_BASE + 0x1C) +#define GPIOAALTFN0 (GPIO_BASE + 0x20) +#define GPIOAALTFN1 (GPIO_BASE + 0x24) + +#define GPIOBOUT (GPIO_BASE + 0x40) +#define GPIOBOUTENB (GPIO_BASE + 0x44) +#define GPIOBDETMODE0 (GPIO_BASE + 0x48) +#define GPIOBDETMODE1 (GPIO_BASE + 0x4C) +#define GPIOBINTENB (GPIO_BASE + 0x50) +#define GPIOBDET (GPIO_BASE + 0x54) +#define GPIOBPAD (GPIO_BASE + 0x58) +#define GPIOBPUENB (GPIO_BASE + 0x5C) +#define GPIOBALTFN0 (GPIO_BASE + 0x60) +#define GPIOBALTFN1 (GPIO_BASE + 0x64) + +#define GPIOCOUT (GPIO_BASE + 0x80) +#define GPIOCOUTENB (GPIO_BASE + 0x84) +#define GPIOCDETMODE0 (GPIO_BASE + 0x88) +#define GPIOCDETMODE1 (GPIO_BASE + 0x8C) +#define GPIOCINTENB (GPIO_BASE + 0x90) +#define GPIOCDET (GPIO_BASE + 0x94) +#define GPIOCPAD (GPIO_BASE + 0x98) +#define GPIOCPUENB (GPIO_BASE + 0x9C) +#define GPIOCALTFN0 (GPIO_BASE + 0xA0) +#define GPIOCALTFN1 (GPIO_BASE + 0xA4) + +/* GPIO Alive Registers */ +#define GPIO_ALIVE_BASE 0xC0019000 +#define ALIVEPWRGATEREG (GPIO_ALIVE_BASE + 0x00) +#define ALIVEGPIORSTREG (GPIO_ALIVE_BASE + 0x04) +#define ALIVEGPIOSETREG (GPIO_ALIVE_BASE + 0x08) +#define ALIVEGPIOREADREG (GPIO_ALIVE_BASE + 0x0C) +#define ALIVESCRATCHRSTREG (GPIO_ALIVE_BASE + 0x10) +#define ALIVESCRATCHSETREG (GPIO_ALIVE_BASE + 0x14) +#define ALIVESCRATCHREADREG (GPIO_ALIVE_BASE + 0x18) + +/* Alive GPIO Gate Register (ALIVEGPIOGATEREG) */ +#define NPOWERGATING 0 + +/* Alive GPIO Register bit names + * same for ALIVEGPIORSTREG, ALIVEGPIOSETREG and ALIVEGPIOREADREG + */ +#define VDDPWRONSET 7 + +/* Alive GPIO Read Register (ALIVEGPIOREADREG) */ +#define VDDPWRTOGGLE 8 + +/* Current settings */ +#define GPIO_CURRENT_BASE 0xC000F100 +#define GPIOAPADSTRENGTH_L (GPIO_CURRENT_BASE + 0x00) +#define GPIOAPADSTRENGTH_H (GPIO_CURRENT_BASE + 0x04) +#define GPIOAPBDSTRENGTH_L (GPIO_CURRENT_BASE + 0x08) +#define GPIOAPBDSTRENGTH_H (GPIO_CURRENT_BASE + 0x0C) +#define GPIOAPCDSTRENGTH_L (GPIO_CURRENT_BASE + 0x10) +#define GPIOAPCDSTRENGTH_H (GPIO_CURRENT_BASE + 0x14) + +/* Convenience macros for generating pin configurations for ALTFNn registers */ +#define ALTFN0_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2)) +#define ALTFN0_PIN_MASK(pin) ALTFN0_PIN_CFG(pin, 0x3) +#define ALTFN1_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2-32)) +#define ALTFN1_PIN_MASK(pin) ALTFN1_PIN_CFG(pin, 0x3) + + +enum gpio_port { + GPIO_PORT_A = 0, + GPIO_PORT_B, + GPIO_PORT_C, + GPIO_PORT_ALV, +}; + +/* Each pin can take one of three different functions */ +enum gpio_function { + GPIO_GPIOFN = 0, + GPIO_ALT1, + GPIO_ALT2, + GPIO_RESERVED, +}; + +/* Each port has 32 pins */ +enum gpio_pin { + GPIO_PIN0 = 0, GPIO_PIN1, GPIO_PIN2, GPIO_PIN3, GPIO_PIN4, GPIO_PIN5, + GPIO_PIN6, GPIO_PIN7, GPIO_PIN8, GPIO_PIN9, GPIO_PIN10, GPIO_PIN11, + GPIO_PIN12, GPIO_PIN13, GPIO_PIN14, GPIO_PIN15, GPIO_PIN16, GPIO_PIN17, + GPIO_PIN18, GPIO_PIN19, GPIO_PIN20, GPIO_PIN21, GPIO_PIN22, GPIO_PIN23, + GPIO_PIN24, GPIO_PIN25, GPIO_PIN26, GPIO_PIN27, GPIO_PIN28, GPIO_PIN29, + GPIO_PIN30, GPIO_PIN31, +}; + +/* Each pin can interrupt on one of four different events */ +enum gpio_interrupt_mode { + GPIO_IMODE_LOW_LEVEL = 0, + GPIO_IMODE_HIGH_LEVEL = 1, + GPIO_IMODE_FALLING_EDGE = 2, + GPIO_IMODE_RISING_EDGE = 3, +}; + +/* Each pin can drive with configurable current */ +enum gpio_current { + GPIO_CURRENT_2MA = 0, + GPIO_CURRENT_4MA = 1, + GPIO_CURRENT_6MA = 2, + GPIO_CURRENT_8MA = 3, +}; + +#endif /* __GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/reg.h b/arch/arm/include/asm/arch-pollux/reg.h new file mode 100644 index 0000000..fba6216 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/reg.h @@ -0,0 +1,39 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" <yurovsky(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REG_H__ +#define __REG_H__ + +/* register access and manipulation helper macros */ +#define REG8(addr) (*((volatile unsigned char *)(addr))) +#define REG16(addr) (*((volatile unsigned short *)(addr))) +#define REG32(addr) (*((volatile unsigned long *)(addr))) + +#define BIT_SET(v,b) ((v) |= (1<<(b))) +#define BIT_CLR(v,b) ((v) &= ~(1<<(b))) +#define IS_SET(v,b) ((v) & (1<<(b))) +#define IS_CLR(v,b) !((v) & (1<<(b))) + +#endif /* __REG_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/timer.h b/arch/arm/include/asm/arch-pollux/timer.h new file mode 100644 index 0000000..35a3363 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/timer.h @@ -0,0 +1,59 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" <yurovsky(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +/* Timer base addresses */ +#define TIMER0_BASE 0xC0001800 +#define TIMER1_BASE 0xC0001880 +#define TIMER2_BASE 0xC0001900 +#define TIMER3_BASE 0xC0001980 +#define TIMER4_BASE 0xC0001A00 + +/* Timer register offsets */ +#define TMRCOUNT 0x00 +#define TMRMATCH 0x04 +#define TMRCONTROL 0x08 +#define TMRCLKENB 0x40 +#define TMRCLKGEN 0x44 + +/* Timer Control Register n (TMRCONTROLn) */ +#define LDCNT 6 +#define INTPEND 5 +#define TINTENB 4 +#define RUN 3 +#define WDENB 2 +#define SETCLK 0 + +/* Timer Clock Generation Enable Register n (TMRCLKENBn) */ +#define TCLKMODE 3 +#define TCLKGENENB 2 + +/* Timer Clock Generation Control Register n (TMRCLKGENn) */ +#define TCLKDIV 4 +#define TCLKSRCSEL 1 + +#endif /* __TIMER_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/uart.h b/arch/arm/include/asm/arch-pollux/uart.h new file mode 100644 index 0000000..2b69a01 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/uart.h @@ -0,0 +1,105 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo <brian(a)cozybit.com> + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" <yurovsky(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UART_H__ +#define __UART_H__ + +/* UART base addresses */ +#define UART0_BASE 0xC0016000 +#define UART1_BASE 0xC0016080 +#define UART2_BASE 0xC0016800 +#define UART3_BASE 0xC0016880 + +/* UART register offsets */ +#define LCON 0x00 +#define UCON 0x02 +#define FCON 0x04 +#define MCON 0x06 +#define TRSTATUS 0x08 +#define ESTATUS 0x0A +#define FSTATUS 0x0C +#define MSTATUS 0x0E +#define THB 0x10 +#define RHB 0x12 +#define BRD 0x14 +#define TIMEOUTREG 0x16 +#define INTSTATUSREG 0x18 +#define UARTCLKENB 0x40 +#define UARTCLKGEN 0x44 + +/* UART register bit definitions */ + +/* LCON Register */ +#define SYNC_PENDCLR 7 +#define SIR_MODE 6 +#define PARITY_MODE 3 +#define STOPBIT 2 +#define WORD_LEN 0 + +/* UCON Register */ +#define TX_INT 9 +#define RX_INT 8 +#define RX_TIMEOUT 7 +#define RX_ERRSTATUS 6 +#define LOOPBACK_MODE 5 +#define SEND_BREAK 4 +#define TRANS_MODE 2 +#define RECEIVE_MODE 0 + +/* FCON Register */ +#define TX_FIFO_TRIGGER 6 +#define RX_FIFO_TRIGGER 4 +#define TX_FIFO_RESET 2 +#define RX_FIFO_RESET 1 +#define FIFO_EN 0 + +/* MCON Register */ +#define HALF_CH_ENB 7 +#define SCRXENB 6 +#define SCTXENB 5 +#define AFC 4 +#define DTR_ACTIVE 1 +#define RTS_ACTIVE 0 + +/* FSTATUS Register */ +#define RX_FIFO_ERROR 10 +#define TX_FIFO_FULL 9 +#define RX_FIFO_FULL 8 +#define TX_FIFO_COUNT 4 +#define RX_FIFO_COUNT 0 + +/* TRSTATUS */ +#define TRANSMITTER_EMPTY 2 +#define TRANSMIT_BUFFER_EMPTY 1 +#define RECEIVE_BUFFER_DATA_READY 0 + +/* UARTCLKENB */ +#define UARTCLKGENENB 2 + +/* UARTCLKGEN */ +#define UARTCLKDIV 4 +#define UARTCLKSRCSEL 1 + +#endif /* __UART_H__ */ -- 1.6.0.4

2 7

[U-Boot] Accessing 64bit address
by Ronny D 21 Jun '10

21 Jun '10

I am using ppc440 based board. Board is having 64bit memory controll register. To access the memory controll region i have added one tlb entry i.e tlbentry( 0xc70e0000, SZ_64K, 0xc70e0000, 0xf, AC_R|AC_X|AC_W|SA_I) What is the way to access the 64bit register in u-boot?

1 0

[U-Boot] [PATCH v2 1/2] cpuat91: convert to new at91 soc architecture
by Eric Bénard 21 Jun '10

21 Jun '10

convert the board to the new soc architecture update default config i2c upgrade taken from eb_cpux9k2.h & board/BuS/eb_cpux9k2/cpux9k2.c Signed-off-by: Eric Bénard <eric(a)eukrea.com> --- v2 : send to Tom Rix's new email Makefile | 2 +- board/eukrea/cpuat91/cpuat91.c | 53 ++++++++++++++++----------------------- include/configs/cpuat91.h | 45 +++++++++++++++++++++++---------- 3 files changed, 54 insertions(+), 46 deletions(-) diff --git a/Makefile b/Makefile index c26e491..ffc749d 100644 --- a/Makefile +++ b/Makefile @@ -2693,7 +2693,7 @@ CPUAT91_RAM_config \ CPUAT91_config : unconfig @mkdir -p $(obj)include @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91rm9200 + @$(MKCONFIG) -a cpuat91 arm arm920t cpuat91 eukrea at91 csb637_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200 diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 0017962..cd4d42c 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Eukrea Electromatique <www.eukrea.com> + * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com> * Eric Benard <eric(a)eukrea.com> * based on at91rm9200dk.c which is : * (C) Copyright 2002 @@ -27,13 +27,11 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <ks8721.h> -#endif +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_pmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,31 +59,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_DRIVER_ETHER) -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = ks8721_initphy; - p_phyops->IsPhyConnected = ks8721_isphyconnected; - p_phyops->GetLinkSpeed = ks8721_getlinkspeed; - p_phyops->AutoNegotiate = ks8721_autonegotiate; -} - -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ #ifdef CONFIG_DRIVER_AT91EMAC - int board_eth_init(bd_t *bis) { int rc = 0; @@ -93,3 +67,20 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + writel(1 << AT91_ID_PIOA, &pmc->pcer); + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); +} +#endif diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 049298c..b012782 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -1,5 +1,5 @@ /* - * CPUAT91 by (C) Copyright 2006 Eric Benard + * CPUAT91 by (C) Copyright 2006-2010 Eric Benard * eric(a)eukrea.com * * Configuration settings for the CPUAT91 board. @@ -23,15 +23,12 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AT91_LEGACY +#ifndef _CONFIG_CPUAT91_H +#define _CONFIG_CPUAT91_H #ifdef CONFIG_CPUAT91_RAM #define CONFIG_SKIP_LOWLEVEL_INIT 1 #define CONFIG_SKIP_RELOCATE_UBOOT 1 -#define CONFIG_CPUAT91 1 #else #define CONFIG_BOOTDELAY 1 #endif @@ -43,6 +40,7 @@ #define CONFIG_ARM920T 1 #define CONFIG_AT91RM9200 1 +#define CONFIG_CPUAT91 1 #undef CONFIG_USE_IRQ #define USE_920T_MMU 1 @@ -89,16 +87,36 @@ #undef CONFIG_USART0 #undef CONFIG_USART1 -#define CONFIG_HARD_I2C 1 +#undef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C 1 +#define AT91_PIN_SDA (1<<25) +#define AT91_PIN_SCL (1<<26) + +#define CONFIG_SYS_I2C_INIT_BOARD 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr); +#define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder); +#define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0) +#define I2C_SDA(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWD, &pio->pioa.codr); +#define I2C_SCL(bit) \ + if (bit) \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \ + else \ + writel(AT91_PMX_AA_TWCK, &pio->pioa.codr); + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) -#if defined(CONFIG_HARD_I2C) -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#endif #define CONFIG_BOOTP_BOOTFILESIZE 1 #define CONFIG_BOOTP_BOOTPATH 1 @@ -117,10 +135,8 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NFS -#if defined(CONFIG_HARD_I2C) #define CONFIG_CMD_EEPROM 1 #define CONFIG_CMD_I2C 1 -#endif #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 @@ -148,6 +164,7 @@ #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #if defined(CONFIG_CMD_USB) #define CONFIG_USB_OHCI_NEW 1 @@ -230,4 +247,4 @@ "flashboot=run ramargs;bootm 10040000\0" \ "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ "bootm 21000000\0" -#endif /* __CONFIG_H */ +#endif /* _CONFIG_CPUAT91_H */ -- 1.6.3.3

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[U-Boot] [PATCH][Net] Write MAC address automatically on MACB-based boards
by Ben Warren 21 Jun '10

21 Jun '10

Also, remove all calls to eth_init() in boards that use MACB Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- Please note: this is untested, but compiles cleanly board/afeb9260/afeb9260.c | 7 ------- board/atmel/at91cap9adk/at91cap9adk.c | 7 ------- board/atmel/at91sam9260ek/at91sam9260ek.c | 7 ------- board/atmel/at91sam9263ek/at91sam9263ek.c | 7 ------- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 7 ------- board/calao/sbc35_a9g20/sbc35_a9g20.c | 7 ------- board/eukrea/cpu9260/cpu9260.c | 7 ------- board/ronetix/pm9263/pm9263.c | 7 ------- drivers/net/macb.c | 23 +++++++++++++++-------- 9 files changed, 15 insertions(+), 64 deletions(-) diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 4652672..3c37557 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -167,13 +167,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index 258d1ea..2ab8bc2 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -339,13 +339,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index ed47360..64c6d17 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -179,13 +179,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 5cd7aa7..91efc07 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -284,13 +284,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index edfb627..ad7d5f7 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -278,13 +278,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index da34b40..9df45c0 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -177,13 +177,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index af8a4a2..61b6c33 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -200,13 +200,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 23ea154..86bdbf5 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -380,13 +380,6 @@ int dram_init(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { -#ifdef CONFIG_MACB - /* - * Initialize ethernet HW addr prior to starting Linux, - * needed for nfsroot - */ - eth_init(gd->bd); -#endif } #endif diff --git a/drivers/net/macb.c b/drivers/net/macb.c index dcb8850..6a58a37 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -439,8 +439,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) { struct macb_device *macb = to_macb(netdev); unsigned long paddr; - u32 hwaddr_bottom; - u16 hwaddr_top; int i; /* @@ -469,12 +467,6 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) macb_writel(macb, RBQP, macb->rx_ring_dma); macb_writel(macb, TBQP, macb->tx_ring_dma); - /* set hardware address */ - hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); - macb_writel(macb, SA1T, hwaddr_top); - /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ @@ -521,6 +513,20 @@ static void macb_halt(struct eth_device *netdev) macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); } +static int macb_write_hwaddr(struct eth_device *dev) +{ + struct macb_device *macb = to_macb(dev); + u32 hwaddr_bottom; + u16 hwaddr_top; + + /* set hardware address */ + hwaddr_bottom = cpu_to_le32(*((u32 *)dev->enetaddr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = cpu_to_le16(*((u16 *)(dev->enetaddr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + return 0; +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; @@ -554,6 +560,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; + netdev->write_hwaddr = macb_write_hwaddr; /* * Do some basic initialization so that we at least can talk -- 1.6.0.4

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[U-Boot] [PATCH] [v3] tsec: fix the return value for tsec_eth_init()
by Timur Tabi 21 Jun '10

21 Jun '10

The Ethernet initialization functions are supposed to return the number of devices initialized, so fix tsec_eth_init() so that they returns the number of TSECs initialized, instead of just zero. This is safe because the return value is currently ignored by all callers, but now they don't have to ignore it. In general, if an function initializes only one device, then it should return a negative number if there's an error. If it initializes more than one device, then it should never return a negative number. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- drivers/net/tsec.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3e4c3bd..c62ff82 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -95,14 +95,23 @@ static struct tsec_info_struct tsec_info[] = { #endif }; +/* + * Initialize all the TSEC devices + * + * Returns the number of TSEC devices that were initialized + */ int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num) { int i; + int ret, count = 0; - for (i = 0; i < num; i++) - tsec_initialize(bis, &tsecs[i]); + for (i = 0; i < num; i++) { + ret = tsec_initialize(bis, &tsecs[i]); + if (ret > 0) + count += ret; + } - return 0; + return count; } int tsec_standard_init(bd_t *bis) -- 1.7.0.1

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[U-Boot] [PATCH] uli526x: drop newlines from device name
by Mike Frysinger 21 Jun '10

21 Jun '10

Device names should not contain non-printable characters like newlines. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/net/uli526x.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 9477851..56eee7b 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -225,7 +225,7 @@ int uli526x_initialize(bd_t *bis) iobase &= ~0xf; dev = (struct eth_device *)malloc(sizeof *dev); - sprintf(dev->name, "uli526x#%d\n", card_number); + sprintf(dev->name, "uli526x#%d", card_number); db = (struct uli526x_board_info *) malloc(sizeof(struct uli526x_board_info)); -- 1.7.1

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[U-Boot] [PATCH] net: warn about spaces in device names
by Mike Frysinger 21 Jun '10

21 Jun '10

Some commands operate on eth device names (like 'mii'), but those cannot be passed on the command line as one argument. So detect devices like these and warn about them so someone will fix it. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- net/eth.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/net/eth.c b/net/eth.c index b650a20..40e66e5 100644 --- a/net/eth.c +++ b/net/eth.c @@ -225,6 +225,9 @@ int eth_initialize(bd_t *bis) puts (" [PRIME]"); } + if (strchr(dev->name, ' ')) + puts("\nWarning: eth device name has a space!\n"); + eth_getenv_enetaddr_by_index(eth_number, env_enetaddr); if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { -- 1.7.1

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[U-Boot] [PATCH] AX88180: switch to common mii.h header
by Mike Frysinger 21 Jun '10

21 Jun '10

No compiled code change here, just drop the local PHY defines in favor of the common standard ones. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/net/ax88180.c | 31 ++++++++++++++++--------------- drivers/net/ax88180.h | 48 ++---------------------------------------------- 2 files changed, 18 insertions(+), 61 deletions(-) diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index 6e788a0..fa2e212 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -41,6 +41,7 @@ #include <command.h> #include <net.h> #include <malloc.h> +#include <linux/mii.h> #include "ax88180.h" /* @@ -112,10 +113,10 @@ static int ax88180_phy_reset (struct eth_device *dev) { unsigned short delay_cnt = 500; - ax88180_mdio_write (dev, BMCR, (PHY_RESET | AUTONEG_EN)); + ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); /* Wait for the reset to complete, or time out (500 ms) */ - while (ax88180_mdio_read (dev, BMCR) & PHY_RESET) { + while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { udelay (1000); if (--delay_cnt == 0) { printf ("Failed to reset PHY!\n"); @@ -265,10 +266,10 @@ static int ax88180_phy_initial (struct eth_device *dev) #endif { priv->PhyAddr = phyaddr; - priv->PhyID0 = ax88180_mdio_read(dev, PHYIDR0); + priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1); switch (priv->PhyID0) { - case MARVELL_88E1111_PHYIDR0: + case MARVELL_88E1111_PHYSID0: debug("ax88180: Found Marvell 88E1111 PHY." " (PHY Addr=0x%x)\n", priv->PhyAddr); @@ -282,7 +283,7 @@ static int ax88180_phy_initial (struct eth_device *dev) return 1; - case CICADA_CIS8201_PHYIDR0: + case CICADA_CIS8201_PHYSID0: debug("ax88180: Found CICADA CIS8201 PHY" " chipset. (PHY Addr=0x%x)\n", priv->PhyAddr); @@ -321,20 +322,20 @@ static void ax88180_media_config (struct eth_device *dev) /* Waiting 2 seconds for PHY link stable */ for (i = 0; i < 20000; i++) { - bmsr_val = ax88180_mdio_read (dev, BMSR); - if (bmsr_val & LINKOK) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_LSTATUS) { break; } udelay (100); } - bmsr_val = ax88180_mdio_read (dev, BMSR); + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); - if (bmsr_val & LINKOK) { - bmcr_val = ax88180_mdio_read (dev, BMCR); + if (bmsr_val & BMSR_LSTATUS) { + bmcr_val = ax88180_mdio_read (dev, MII_BMCR); - if (bmcr_val & AUTONEG_EN) { + if (bmcr_val & BMCR_ANENABLE) { /* * Waiting for Auto-negotiation completion, this may @@ -343,8 +344,8 @@ static void ax88180_media_config (struct eth_device *dev) debug ("ax88180: Auto-negotiation is " "enabled. Waiting for NWay completion..\n"); for (i = 0; i < 50000; i++) { - bmsr_val = ax88180_mdio_read (dev, BMSR); - if (bmsr_val & AUTONEG_COMPLETE) { + bmsr_val = ax88180_mdio_read (dev, MII_BMSR); + if (bmsr_val & BMSR_ANEGCOMPLETE) { break; } udelay (100); @@ -357,10 +358,10 @@ static void ax88180_media_config (struct eth_device *dev) /* Get real media mode here */ switch (priv->PhyID0) { - case MARVELL_88E1111_PHYIDR0: + case MARVELL_88E1111_PHYSID0: RealMediaMode = get_MarvellPHY_media_mode(dev); break; - case CICADA_CIS8201_PHYIDR0: + case CICADA_CIS8201_PHYSID0: RealMediaMode = get_CicadaPHY_media_mode(dev); break; default: diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h index 77bab5f..c793e92 100644 --- a/drivers/net/ax88180.h +++ b/drivers/net/ax88180.h @@ -63,9 +63,9 @@ struct ax88180_private { /* Max Rx Jumbo size is 15K Bytes */ #define MAX_RX_SIZE 0x3C00 -#define MARVELL_88E1111_PHYIDR0 0x0141 +#define MARVELL_88E1111_PHYSID0 0x0141 -#define CICADA_CIS8201_PHYIDR0 0x000F +#define CICADA_CIS8201_PHYSID0 0x000F #define MEDIA_AUTO 0 #define MEDIA_1000FULL 1 @@ -276,50 +276,6 @@ struct ax88180_private { #define SOFTRST_NORMAL 0x00000003 #define SOFTRST_RESET_MAC 0x00000002 -/* External PHY Register Definition */ -#define BMCR 0x0000 - #define LINE_SPEED_MSB 0x0040 - #define DUPLEX_MODE 0x0100 - #define RESTART_AUTONEG 0x0200 - #define POWER_DOWN 0x0800 - #define AUTONEG_EN 0x1000 - #define LINE_SPEED_LSB 0x2000 - #define PHY_RESET 0x8000 - - #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ - DUPLEX_MODE) - #define BMCR_SPEED_1000 LINE_SPEED_MSB - #define BMCR_SPEED_100 LINE_SPEED_LSB - #define BMCR_SPEED_10 0x0000 - - #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) - #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) - #define BMCR_100HALF BMCR_SPEED_100 - #define BMCR_10FULL DUPLEX_MODE - #define BMCR_10HALF 0x0000 -#define BMSR 0x0001 - #define LINKOK 0x0004 - #define AUTONEG_ENABLE_STS 0x0008 - #define AUTONEG_COMPLETE 0x0020 -#define PHYIDR0 0x0002 -#define PHYIDR1 0x0003 -#define ANAR 0x0004 - #define ANAR_PAUSE 0x0400 - #define ANAR_100FULL 0x0100 - #define ANAR_100HALF 0x0080 - #define ANAR_10FULL 0x0040 - #define ANAR_10HALF 0x0020 - #define ANAR_8023BIT 0x0001 -#define ANLPAR 0x0005 -#define ANER 0x0006 -#define AUX_1000_CTRL 0x0009 - #define ENABLE_1000HALF 0x0100 - #define ENABLE_1000FULL 0x0200 - #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) -#define AUX_1000_STATUS 0x000A - #define LP_1000HALF 0x0400 - #define LP_1000FULL 0x0800 - /* Marvell 88E1111 Gigabit PHY Register Definition */ #define M88_SSR 0x0011 #define SSR_SPEED_MASK 0xC000 -- 1.7.1

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