June 2010 - U-Boot

[U-Boot] Does U-boot supports Spansion S29GL512P NOR Flash?
by prakash bedge 10 Mar '12

10 Mar '12

Hi, In U-boot I am not seeing the support for Spansion S29GL512P NOR flash. This chip is CFI compliant so I believe the common CFI driver should work with this chip. Does U-boot supports S29GL512P NOR flash or I have to implement the functionality to support S29GL512P? If anyone has tried with S29GL512P NOR flash please share the experiecne. Thanks & Regards, Prakash

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[U-Boot] U-boot running on DDR fails to detect the CFI compliant flash
by prakash bedge 15 Feb '12

15 Feb '12

Hi Stefan, In October 09 month, I had asked whether U-boot supports M29W128GH, a CFI compilant chip and I got a yes reply. Please refer below URL for reference. http://www.mail-archive.com/u-boot@lists.denx.de/msg24531.html. So I have used Uboot for my PPC440 based board. When I flashed U-boot on flash and then run the Uboot in DDR then U-boot running on DDR fails to detect CFI chip M29W128GH (16M x 8 mode). flash_detect_cfi function gives error that flash not found. I have added debug statements for temporary debug purpose. Please see the below error I am getting. The CFI query address looks different in below code and not as per ST make M29W128GH specs. PCIMW. static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; debug ("1__flash detect cfi\n"); /* We do not yet know what kind of commandset to use, so we issue the reset command in both Intel and AMD variants, in the hope that AMD flash roms ignore the Intel command. */ flash_write_cmd (info, 0, 0, AMD_CMD_RESET); flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); debug ("2__flash detect cfi\n"); for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); debug ("3__flash detect cfi\n"); if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); /* UART Output */ U-Boot 2009.08 (Jan 15 2010 - 16:44:40) DRAM: Meminfo.ptrCDBs: 0xc00174e0 512 MB (ECC is ON, 400 MHz, CL 7) Top of RAM usable for U-Boot at: 20000000 Reserving 174k for U-Boot at: 1ffd4000 Reserving 1040k for malloc() at: 1fed0000 Reserving 128 Bytes for Board Info at: 1fecff80 Reserving 64 Bytes for Global Data at: 1fecff40 Stack Pointer at: 1fecff28 New Stack Pointer is: 1fecff28 after watchdog reset after watchdog reset 2 after memcpy befor relocate addr_sp = 1fecff28, id = 1fecff40, addr = 1ffd4000 Now running in RAM - U-Boot at: 1ffd4000 FLASH: flash detect cfi 1__flash detect cfi fwc addr ff000000 cmd f0 f0 8bit x 8 bit Entering into First Write First Write is done fwc addr ff000000 cmd ff ff 8bit x 8 bit Entering into First Write First Write is done 2__flash detect cfi fwc addr ff000055 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000555 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 1__flash detect cfi fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000000 cmd ff 00ff 16bit x 16 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 fwc addr ff000aaa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr ff000000 cmd ff ffffffff 32bit x 8 bit 2__flash detect cfi fwc addr ff000154 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 fwc addr ff001554 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 1__flash detect cfi fwc addr ff000000 cmd f0 00f000f0 32bit x 16 bit fwc addr ff000000 cmd ff 00ff00ff 32bit x 16 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 fwc addr ff001554 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 1__flash detect cfi fwc addr ff000000 cmd f0 000000f0 32bit x 32 bit fwc addr ff000000 cmd ff 000000ff 32bit x 32 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 fwc addr ff001554 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 1__flash detect cfi fwrite addr ff000000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit fwrite addr ff000000 cmd ff ffffffffffffffff 64 bit x 8 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 fwrite addr ff002aa8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 1__flash detect cfi fwrite addr ff000000 cmd f0 00f000f000f000f0 64 bit x 16 bit fwrite addr ff000000 cmd ff 00ff00ff00ff00ff 64 bit x 16 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 fwrite addr ff002aa8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 1__flash detect cfi fwrite addr ff000000 cmd f0 000000f0000000f0 64 bit x 32 bit fwrite addr ff000000 cmd ff 000000ff000000ff 64 bit x 32 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 fwrite addr ff002aa8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 1__flash detect cfi fwrite addr ff000000 cmd f0 00000000000000f0 64 bit x 64 bit fwrite addr ff000000 cmd ff 00000000000000ff 64 bit x 64 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 fwrite addr ff002aa8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFE8AFF flash_protect ON: from 0xFFFA0000 to 0xFFFBFFFF *** failed *** ### ERROR ### Please RESET the board ### What should be the cause. It would be really helpful if someone who have face this kind of issues can give some inputs. TIA. Regards, Prakash

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[U-Boot] [RFC] CDC Ethernet support + USB Gadget in U-boot
by Remy Bohmer 19 Jan '12

19 Jan '12

Hello All, We (Thomas Smits and I) have been working on CDC Ethernet support in U-boot. We ported the Linux Gadget and CDC Ethernet driver to U-boot and added support for the Atmel AT91SAM9261-EK kit. Support for other cores can be added easily. Although it is still work in progress, it is already working stable. I also have a patch for adding RNDIS support on top of this series, but that is not finished/stable yet. The series is quite huge, and still in development, so I decided to not post this series inline. I made the tree public via the U-boot-usb tree, 'cdc' branch ( http://git.denx.de/?p=u-boot/u-boot-usb.git;a=shortlog;h=refs/heads/cdc) I would like to stabilise this code in a separate branch until it is mature enough for mainline integration, I will keep this branch always ahead mainline. So, any comments on this code are welcome! But, even more welcome are patches on top of it to make it even better and add more board support for it. Kind Regards, Remy

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[U-Boot] [PATCH] arm/pxa: fix and cleanup of pxa_mem_setup macro v2
by Mikhail Kshevetskiy 17 Nov '11

17 Nov '11

WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy(a)gmail.com> --- arch/arm/include/asm/arch-pxa/macro.h | 82 ++++++++++++++++++++++----------- board/vpac270/lowlevel_init.S | 2 +- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 1f1759b..e2ddfe9 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,11 +102,15 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_… */ -.macro pxa_mem_setup +.macro pxa2xx_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -149,51 +153,68 @@ */ /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. + * Before accessing MDREFR we need a valid DRI field. + * Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. + * Optionaly we can set MDREFR[KxFREE] bits. + * So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) + * fields from the config. + * + * WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits + * are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. + * While the synchronous flash banks are being configured, the SDRAM + * banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* - * 6) Initialize SDRAM + * 6) Initialize SDRAM, + * If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K1RUN] bits + * must be set. Also we must properly configure MDREFR[K1DB2] and + * MDREFR[K2DB2] in this case. + * + * WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ +#if (CONFIG_SYS_MDREFR_VAL & (MDREFR_K1RUN | MDREFR_K2RUN)) + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] + bic r6, #MDREFR_SLFRSH str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] orr r6, #MDREFR_E1PIN str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] +#endif /* * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure @@ -209,6 +230,7 @@ str r4, [r3, #MDCNFG_OFFSET] ldr r4, [r3, #MDCNFG_OFFSET] +#if (CONFIG_SYS_MDREFR_VAL & (MDREFR_K1RUN | MDREFR_K2RUN)) /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ pxa_wait_ticks 0x300 @@ -226,7 +248,7 @@ .endr /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). + * 9) Set custom MDCNFG[DEx] bits to enable required SDRAM partitions */ ldr r5, =CONFIG_SYS_MDCNFG_VAL @@ -238,19 +260,25 @@ ldr r4, [r3, #MDCNFG_OFFSET] /* - * 10) Write MDMRS. + * 10) Write to MDMRS register to trigger an MRS command to + * all enabled banks of SDRAM. For each SDRAM partition pair + * that has one or both partitions enabled, this forces a pass + * through the MRS state and a return to NOP. */ ldr r4, =CONFIG_SYS_MDMRS_VAL str r4, [r3, #MDMRS_OFFSET] ldr r4, [r3, #MDMRS_OFFSET] +#endif /* - * 11) Enable APD + * 11) Optionaly enable auto-power-down by setting MDREFR[APD] + * + * WARNING: APD bit is usually set. */ ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD + and r6, r7, #MDREFR_APD orr r4, r4, r6 str r4, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S index ec0d12c..a327ebd 100644 --- a/board/vpac270/lowlevel_init.S +++ b/board/vpac270/lowlevel_init.S @@ -32,7 +32,7 @@ lowlevel_init: pxa_gpio_setup pxa_wait_ticks 0x8000 - pxa_mem_setup + pxa2xx_mem_setup pxa_wakeup pxa_intr_setup pxa_clock_setup -- 1.7.1

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[U-Boot] Uboot for Mips
by Rahanesh 13 Sep '11

13 Sep '11

Hi All, I am currently working on MIPS board. I have a 32MB RAM. The address that is shown in uboot when i type bdinfo if 0x80000000 and size is 0x1000000(16MB). I want to increase the size to 32 MB as board has 32 MB RAM. Interesting Finding: When i write any data to 0x80000000 the same data is being written into 0x81000000. Same for all address in the range (data in 0x80000000 - 0x80ffffff is same as 0x81000000 - 0x81ffffff ). It seems that there is a dual mapping . What might be the reason? Please help -- View this message in context: http://www.nabble.com/Uboot-for-Mips-tp24366921p24366921.html Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] [PATCH 1/4 v3] musb: Use name based initialization for musb_config
by Ajay Kumar Gupta 06 Jul '11

06 Jul '11

Changed musb_config initialization for omap3.c, davinci.c and da8xx.c using name of structure fields. This would cause the uninitialized field to be null by default and thus would help in avoiding to init some flags required to be set only for a few selected platforms. CC: Remy Bohmer <linux(a)bohmer.net> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- No change from v2. drivers/usb/musb/da8xx.c | 6 +++--- drivers/usb/musb/davinci.c | 6 +++--- drivers/usb/musb/omap3.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index 40bfe44..617d88e 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -27,9 +27,9 @@ /* MUSB platform configuration */ struct musb_config musb_cfg = { - (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, - DA8XX_USB_OTG_TIMEOUT, - 0 + .regs = (struct musb_regs *)DA8XX_USB_OTG_CORE_BASE, + .timeout = DA8XX_USB_OTG_TIMEOUT, + .musb_speed = 0, }; /* diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index 8fbadc9..f56f2df 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -28,9 +28,9 @@ /* MUSB platform configuration */ struct musb_config musb_cfg = { - (struct musb_regs *)MENTOR_USB0_BASE, - DAVINCI_USB_TIMEOUT, - 0 + .regs = (struct musb_regs *)MENTOR_USB0_BASE, + .timeout = DAVINCI_USB_TIMEOUT, + .musb_speed = 0, }; /* MUSB module register overlay */ diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index 3bfd0a0..785629c 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -36,9 +36,9 @@ static int platform_needs_initialization = 1; struct musb_config musb_cfg = { - (struct musb_regs *)MENTOR_USB0_BASE, - OMAP3_USB_TIMEOUT, - 0 + .regs = (struct musb_regs *)MENTOR_USB0_BASE, + .timeout = OMAP3_USB_TIMEOUT, + .musb_speed = 0, }; /* -- 1.6.2.4

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[U-Boot] convention for SPI dummy data?
by wolfgang＠leila.ping.de 13 Jun '11

13 Jun '11

Hi, I have finally got MMC/SD working on my coldfire board and would like to send some patches. However, one of the things I had to change was the dummy data sent out by SPI for read-only transactions. The original driver had all zeros, for SD/MMC all ones (0xFF) is needed. Is such a change acceptable, or is there any configuration option/flag I could use? Regards, Wolfgang

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[U-Boot] [PATCH] Kirkwood: boards cleanup for deprecated CONFIG_CMD_AUTOSCRIPT
by Prafulla Wadaskar 01 Jun '11

01 Jun '11

CONFIG_CMD_AUTOSCRIPT support is deprecated and non-existing This clean up patch removes the references for Marvell boards Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- include/configs/mv88f6281gtw_ge.h | 1 - include/configs/openrd_base.h | 1 - include/configs/rd6281a.h | 1 - include/configs/sheevaplug.h | 1 - 4 files changed, 0 insertions(+), 4 deletions(-) diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h index 96b4d1c..a7db659 100644 --- a/include/configs/mv88f6281gtw_ge.h +++ b/include/configs/mv88f6281gtw_ge.h @@ -91,7 +91,6 @@ */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h index 88f27ba..7e915e4 100644 --- a/include/configs/openrd_base.h +++ b/include/configs/openrd_base.h @@ -96,7 +96,6 @@ */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h index 3d8e25c..8ad359d 100644 --- a/include/configs/rd6281a.h +++ b/include/configs/rd6281a.h @@ -90,7 +90,6 @@ */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index fc401a8..c7695fe 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -90,7 +90,6 @@ */ #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ #include <config_cmd_default.h> -#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_FAT -- 1.5.3.3

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[U-Boot] git merge summary
by Alexander Holler 11 Mar '11

11 Mar '11

Hello, may I ask if there is reason why merge commits don't have a summary? I find those summaries (enabled with git config [--global] merge.summary true) very hand to see what was changed with the merge commit. Regards, Alexander

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[U-Boot] Atmel AT91 USB DFU and USB device port driver
by Krishna Pattabiraman 12 Feb '11

12 Feb '11

Hi All, I am currently developing a USB DFU feature for at91sam9263 board. I have to develop the driver for USB device port. I looked the uboot-usb git cdc branch it has a at91_udc.c driver it doesnt contain the udc_* api implementations. I found a earlier post where it was discussed. http://www.mail-archive.com/u-boot@lists.denx.de/msg08709.html Can any point give me a pointer to implement it or the implementations if exist. Bye, Krishna.

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