May 2010 - U-Boot

[U-Boot] Can't start Linux if U-Boot built with CONFIG_WATCHDOG
by Matthew Lear 26 Aug '15

26 Aug '15

Hello all, I've added watchdog support based on U-Boot (git) for the m68k coldfire mcf54455evb platform. I've fed the patch to the maintainer to help in development. However, I am unable to start my m68k w/MMU coldfire Linux kernel from U-Boot if U-Boot is built with CONFIG_WATCHDOG regardless if the watchdog_enable(), watchdog_reset() and watchdog_disable() functions touch hardware or not. I initially thought this was a problem with enabling the watchdog somehow (ie when Linux started, some hw configuration in the device was getting upset or corrupted etc resulting in the failure), but when I commented out the code from the above functions that actually accesses the hw (ie to enable, kick and disable the watchdog timer hw block), Linux is still unable to start. In fact, I don't think Linux actually gets started! That's the problem. If I rebuild the same U-Boot code base with CONFIG_WATCHDOG undefined, Linux can start just fine. As far as I can tell, there are no functional differences in building U-Boot with or without CONFIG_WATCHDOG enabled when the functions above are stubs and do absolutely nothing at all. If I build U-Boot with debug, what I see is as follows: ## Transferring control to Linux (at address 40020000) ... BIV ...and then the board is dead. I occasionally see something like the following from U-Boot: *** Unexpected exception *** Vector Number: 4 Format: 04 Fault Status: 0 PC: 4fdbfdc8 SR: 00002700 SP: 4fd72a64 D0: 00000004 D1: 000003f9 D2: 4fdb4202 D3: 004fa3da D4: 00000000 D5: 4fdc7c8c D6: 122c0034 D7: 4fd82f76 A0: 4033cb98 A1: 4025aa39 A2: 40020000 A3: 4fdbfdc8 A4: 00000000 A5: 4fdc5800 A6: 4fd72afb *** Please Reset Board! *** The 'BIV' is relevant because in my 2.6.29 kernel src arch/m68k/include/asm/bootinfo_mm.h, BOOTINFOV_MAGIC is defined to be 0x4249561A which is BIV^Z. This ascii text is located in the kernel image header info: >From arch/m68k/coldfire/head.S: .section ".text.head","ax" ENTRY(_stext) bras 1f /* Jump over bootinfo version numbers */ .long BOOTINFOV_MAGIC .long 0 And from U-Boot itself: -> md ${loadaddr} 40010000: 27051956 97342d7d 4a54afd5 00300000 '..V.4-}JT...0.. 40010010: 40020000 40020000 8a006fc1 050c0200 @...@.....o..... 40010020: 4c696e75 78204b65 726e656c 20496d61 Linux Kernel Ima 40010030: 67650000 00000000 00000000 00000000 ge.............. 40010040: 60084249 561a0000 00004ef9 40304000 `.BIV.....N.@0@. I suspect that the failure of starting Linux is caused by some mismatch in data structures (or versions there of) shared/copied between Linux and U-Boot and that this data has somehow changed when U-Boot is built with CONFIG_WATCHDOG #defined. However, I can't find any evidence of this in the U-Boot code base. The bras instruction above must be key and I suspect that this is the area causing the problem. Can anybody offer any advice / explanation of what exactly could be going on and why? I wouldn't have expected that defining CONFIG_WATCHDOG would change anything as fundamental as this. Apologies for the cross-post (U-Boot and m68k kernel dev) but I hope to get opinions/feedback/help from both communities. Any assistance very much appreciated indeed. Many thanks, -- Matt

2 1

[U-Boot] [PATCH] fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
by Kumar Gala 30 Aug '13

30 Aug '13

sys_eeprom.c: In function 'do_mac': sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules sys_eeprom.c: In function 'mac_read_from_eeprom': sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/sys_eeprom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ae5304a..3e1e332 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -78,12 +78,14 @@ static int has_been_read = 0; #ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif #ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif /** -- 1.6.0.6

2 1

[U-Boot-Users] minimum bdi config to read flash on 85xx
by robert lazarski 28 May '13

28 May '13

Hi all, On our custom 8548 board, we can't read our flash correctly. We have one 1Gb bank of spansion S29GL01GP flash and we get: atum>mdh 0xf8000000 0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 The big problem we have now: is this a hardware issue or a bdi config issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone help us track our flash issues down to be hardware, config file, or some combination? The hardware guys think the board is fine. We've been deep into the manuals of both the 8548 and the bdi and can't find anything wrong. Here's the config, thanks for any help! ;bdiGDB configuration file for ATUM 8548 ;--------------------------------------------------- ; [INIT] ; ; ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001d ;LAWAR0 : DDR 1GB WM32 0xe0000C28 0xf8000000 ;LAWBAR1 : @0xf8000000 WM32 0xe0000C30 0x8040001a ;LAWAR1 : Local Bus 128MB for S29GL01GP ; ; Setup Flash chip select WM32 0xe0005000 0xf8001001 ;BR0 WM32 0xe0005004 0xf8000E65 ;OR0 ; CS0_BNDS WM32 0xe0002000 0x0000000f ; DDR CS0 ; CS0_CONFIG WM32 0xe0002080 0x80000102 ; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; TIMING_CFG_1 WM32 0xe0002108 0x38355322 ; TIMING_CFG_2 WM32 0xe000210C 0x039048c7 ; DDR_SDRAM_MODE WM32 0xe0002118 0x00000432 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x05150100 ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000000 ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 DELAY 200 ; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xc3000000 ;================= end flash programming ===================== ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 5000 ;let U-boot code setup the system STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [REGS] FILE $reg8548.def [HOST] IP 10.101.43.10 FILE vmlinux.8548 FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e500.bin PROMPT atum> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes - 1Gb BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin FORMAT BIN 0xF8000000 ERASE 0xF8000000 ;erase sector 0 [REGS] FILE $reg8548.def

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[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

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[U-Boot] Read-only env variables
by Joe Hershberger 15 Jan '13

15 Jan '13

Hi u-boot, I see u-boot supports readonly serial# and ethaddr, but I have a few other variables that I need to be read-only. I'm planning to implement a generic list of variables that cannot be changed or deleted. I'm interested to know what sort of specification people would find most appropriate. My current thought is to follow the same delimiter as the env itself, i.e. null separated list with double null terminator. This list would then be defined in the board config header. It also seems that you should be able to specify simple access rules for each variable name perhaps using "=<val>" after each var name where <val> could have constants (probably numbers for performance, but could be string literals) to define modes. Right now I'm thinking read-only, create-only, change-default, and change-only (i.e no delete) are the modes that make sense. I'm also interested if anyone would be opposed to simply using this new specification of readonly vars to implement the serial# and ethaddr protection. The CONFIG_HAS_UID is a bit odd... should that be available in general for read-only vars? Comments? Thanks, -Joe

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[U-Boot] ERROR: CTL:TIMEOUT - USB porting issue for UBoot on S3C2450
by dongdaking 23 Nov '12

23 Nov '12

Hi, I am porting UBoot on S3C2450 and has an USB issue. Here is an error message: ERROR: CTL:TIMEOUT USB device not responding, giving up (status=20) 2 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found The problem seems submit_common_msg couldn't get description of USB flash memory device Could I have help? Please tell me if you had this issue before. Thank you for your helping Here is a log data usb start (Re)start USB... USB: INFO: aligned ghcca c3e4f900 DEBUG: USB HC reset_hc usb-smdk2450: ctrl = 0x9F ; DEBUG: OHCI controller usb-smdk2450 state DEBUG: control: 0x0000008f HCFS=operational IE PLE CBSR=3 DEBUG: cmdstatus: 0x00000000 SOC=0 DEBUG: intrstatus: 0x00000044 RHSC SF DEBUG: intrenable: 0x00000053 RHSC UE WDH SO DEBUG: hcca frame #0000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS scanning bus for devices... New Device 0 start 0st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 start 1st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 start 2st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 set address 1 usb_control_msg: request: 0x5, requesttype: 0x0 value 0x1 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000500 0001 0000 0000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x12 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0100 0000 0012 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:18/18 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x200 index 0x0 length 0x8 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0008 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:8/8 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x200 index 0x0 length 0x19 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0019 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:25/25 stat:0x0 get_conf_no 0 Result 25, wLength 25 if 0, ep 0 ##EP epmaxpacketin[1] = 2 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0 value 0x1 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000900 0001 0000 0000 INFO: WR:status 0x10000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 new device strings: Mfr=0, Product=1, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x300 index 0x0 length 0xFF INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0300 0000 00ff DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:255/255 stat:0x0 USB device number 1 default language ID 0x409 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x301 index 0x409 length 0xFF INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0301 0409 00ff DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:255/255 stat:0x0 Manufacturer Product OHCI Root Hub SerialNumber usb_control_msg: request: 0x6, requesttype: 0xA0 value 0x2900 index 0x0 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0xA0 value 0x2900 index 0x0 length 0x9 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0009 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:9/9 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA0 value 0x0 index 0x0 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a0 0000 0000 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x8 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0001 0000 INFO: WR:portstatus[0] 0x100 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x8 index 0x2 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0002 0000 INFO: WR:portstatus[1] 0x100 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x10 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0010 0001 0000 INFO: WR:portstatus[0] 0x10000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x4 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0001 0000 INFO: WR:portstatus[0] 0x10 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x14 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0001 0000 INFO: WR:portstatus[0] 0x100000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000103 PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 New Device 1 start 0st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. ERROR: CTL:TIMEOUT DEBUG: submit_common_msg: TO status ff DEBUG: RET(ctlr) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x20 usb_new_device: 64 byte descr usb_control_msg: request: 0x3, requesttype: 0x23 value 0x4 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0001 0000 INFO: WR:portstatus[0] 0x10 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x14 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0001 0000 INFO: WR:portstatus[0] 0x100000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000103 PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 set address 2 usb_control_msg: request: 0x5, requesttype: 0x0 value 0x2 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 ERROR: submit_control_message: pipesize for pipe 80000000 is zero USB device not accepting new address (error=80000000) usb_control_msg: request: 0x1, requesttype: 0x23 value 0x1 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0001 0001 0000 INFO: WR:portstatus[0] 0x1 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x2 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0002 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 2 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found Thank you a lot. Best regards -- View this message in context: http://old.nabble.com/ERROR%3A-CTL%3ATIMEOUT---USB-porting-issue-for-UBoot-… Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] building tools/env
by Steve DeLaney 24 Jul '12

24 Jul '12

hi there, I'm attempting to build u-boot 1.1.1 tools/env and the build is failed. Any ideas on best way to enable it in the build. Here's what I did so far first, update tools/Makefile TOOLSUBDIRS = env then top level build make clobber mrproper make octeon_cn3010_evb_hs5_config make all the build in tools/env fails due to missing include files linux/mtd/mtd.h zlib.h add to tools/env/Makefile CPPFLAGS += ../../include and include CPPFLAGS here: fw_printenv : $(SOURCES) $(HEADERS) $(CROSS_COMPILE)gcc -Wall $(CPPFLAGS) -DUSE_HOSTCC $(SOURCES) -o fw_printenv but this leads to build error on definitions of uint32_t, phys_addr_t and erase_info_t Any ideas on preferred way to build tools/env? thanks in advance!

4 3

[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

4 5

[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

5 5

[U-Boot] [PATCH] MIPS: Add initial support for EMMA3SL/LP
by Serge Ziryukin 03 Apr '12

03 Apr '12

This patch adds initial support for EMMA3SL/LP board. Network and USB support will be added as follow up patches. Signed-off-by: Serge Ziryukin <ftrvxmtrx(a)gmail.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/emma3sllp/Makefile | 45 +++++++++ board/emma3sllp/config.mk | 28 ++++++ board/emma3sllp/emma3sllp.c | 39 ++++++++ board/emma3sllp/emma3sllp.h | 51 +++++++++++ board/emma3sllp/lowlevel_init.S | 190 +++++++++++++++++++++++++++++++++++++++ board/emma3sllp/u-boot.lds | 70 ++++++++++++++ doc/README.emma3sllp | 10 ++ include/configs/emma3sllp.h | 131 +++++++++++++++++++++++++++ 11 files changed, 572 insertions(+), 0 deletions(-) create mode 100644 board/emma3sllp/Makefile create mode 100644 board/emma3sllp/config.mk create mode 100644 board/emma3sllp/emma3sllp.c create mode 100644 board/emma3sllp/emma3sllp.h create mode 100644 board/emma3sllp/lowlevel_init.S create mode 100644 board/emma3sllp/u-boot.lds create mode 100644 doc/README.emma3sllp create mode 100644 include/configs/emma3sllp.h diff --git a/MAINTAINERS b/MAINTAINERS index 5cbc845..ec5927d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -841,6 +841,10 @@ Stefan Roese <sr(a)denx.de> vct_xxx MIPS32 4Kc +Serge Ziryukin <ftrvxmtrx(a)gmail.com> + + emma3sllp MIPS32 4KEc + ######################################################################### # Nios-32 Systems: # # # diff --git a/MAKEALL b/MAKEALL index bb09627..75c07ef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -741,6 +741,7 @@ LIST_arm=" \ ######################################################################### LIST_mips4kc=" \ + emma3sllp \ incaip \ qemu_mips \ vct_platinum \ diff --git a/Makefile b/Makefile index 82cbbf4..0bbbbf1 100644 --- a/Makefile +++ b/Makefile @@ -3408,6 +3408,9 @@ vct_platinumavc_onenand_small_config: unconfig fi @$(MKCONFIG) -a vct mips mips vct micronas +emma3sllp_config: unconfig + @$(MKCONFIG) $(@:_config=) mips mips emma3sllp + ######################################################################### ## MIPS32 AU1X00 ######################################################################### diff --git a/board/emma3sllp/Makefile b/board/emma3sllp/Makefile new file mode 100644 index 0000000..aa42b44 --- /dev/null +++ b/board/emma3sllp/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/emma3sllp/config.mk b/board/emma3sllp/config.mk new file mode 100644 index 0000000..d4ff9b5 --- /dev/null +++ b/board/emma3sllp/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2010 +# Serge Ziryukin, ftrvxmtrx(a)gmail.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EMMA3SL/LP +# + +TEXT_BASE = 0xbc000000 diff --git a/board/emma3sllp/emma3sllp.c b/board/emma3sllp/emma3sllp.c new file mode 100644 index 0000000..ff6e12a --- /dev/null +++ b/board/emma3sllp/emma3sllp.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <configs/emma3sllp.h> +#include <asm/io.h> +#include "emma3sllp.h" + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_SDRAM_SIZE; +} + +int checkboard(void) +{ + puts("EMMA3SL/LP\n"); + + return 0; +} diff --git a/board/emma3sllp/emma3sllp.h b/board/emma3sllp/emma3sllp.h new file mode 100644 index 0000000..335f6fd --- /dev/null +++ b/board/emma3sllp/emma3sllp.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EMMA3SLLP_H +#define __EMMA3SLLP_H + +/* host interface */ +#define BHIF_BASE_ADDRESS 0xb0000000 +#define BHIF_ALTERNATE0 0x28 + +/* rom interface */ +#define BROI_BASE_ADDRESS 0xb0000600 +#define BROI_ROM_MODE 0x00 +#define BROI_ROM_IF_MODE 0x08 + +/* memory interface */ +#define MIF_BASE_ADDRESS 0xb0000c00 +#define MIF_CONFIG1 0x04 +#define MIF_INIT 0x08 +#define MIF_REFCNT 0x0c +#define MIF_CONFIG2 0x10 +#define MIF_DLLSTBY 0xf0 +#define MIF_DLLCTRL 0xf4 +#define MIF_DLLOFSTW 0xf8 +#define MIF_DLLOFSTR 0xfc +#define MIF_RSTB 0xe0 +#define MIF_ODTSW 0xe4 +#define MIF_IOLHRSTB 0xe8 +#define MIF_IOLHCTRL 0xec + +#endif /* __EMMA3SLLP_H */ diff --git a/board/emma3sllp/lowlevel_init.S b/board/emma3sllp/lowlevel_init.S new file mode 100644 index 0000000..689e6dc --- /dev/null +++ b/board/emma3sllp/lowlevel_init.S @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include "emma3sllp.h" + +.text +.set noreorder +.set mips32 + +.macro REGWR offset, val + li t1, \val + sw t1, \offset(t0) +.endm + +#define MEM_200US (200 * CPU_CLOCK_RATE / 1000000) + +.global lowlevel_init +lowlevel_init: + + /* =================================== */ + /* enable peripherals */ + /* =================================== */ + li t0, BHIF_BASE_ADDRESS + + /* 17: usb, 18: ethernet, 19: fuart0 */ + REGWR BHIF_ALTERNATE0 0x000e0000 + + /* =================================== */ + /* set flash options */ + /* =================================== */ + li t0, BROI_BASE_ADDRESS + + /* change max size flash rom to 64Mb + to make it start from 0xbc000000 */ + lw t1, BROI_ROM_MODE(t0) + li t2, 0x08 + sub t2, zero, t2 + and t1, t1, t2 + ori t1, t1, 0x04 + sw t1, BROI_ROM_MODE(t0) + + /* enable write (for 4 possible flash chips) */ + lw t1, BROI_ROM_IF_MODE(t0) + ori t1, t1, 0x0f + sw t1, BROI_ROM_IF_MODE(t0) + + /* =================================== */ + /* DDR2 initialization */ + /* =================================== */ + li t0, MIF_BASE_ADDRESS + + /* + set wiring delay + 91-467ps @ 327.68MHz + 110-440ps @ 333.33MHz + */ + REGWR MIF_DLLOFSTW 0x0000e1e1 + REGWR MIF_DLLOFSTR 0x00002424 + + /* 316-350MHz (FSL=6) */ + REGWR MIF_DLLCTRL 0x00000020 + + /* exit from stand-by mode */ + REGWR MIF_DLLSTBY 0x00000000 + + /* clear rst */ + REGWR MIF_IOLHRSTB 0x00000001 + + /* wait until locked */ + li t2, 0x1 +1: + lw t1, MIF_DLLCTRL(t0) + and t1, t2 + bne t1, t2, 1b + nop + + /* wait until fixed */ + li t2, 0x1 +1: + lw t1, MIF_IOLHCTRL(t0) + and t1, t2 + bne t1, t2, 1b + nop + + /* clear rst */ + REGWR MIF_RSTB 0x00000001 + + /* set on-die termination to 75ohm and enable clock */ + REGWR MIF_ODTSW 0x00000101 + + /* 200us */ + li t2, MEM_200US +1: + bne t2, zero, 1b + addi t2, -1 + + /* + column 10 bits (A0 - A9), row 13 bits (A0 - A12) + CAS latency 5, 16-bit bus, 4 banks + */ + REGWR MIF_CONFIG1 0x74ba1b65 + + /* small PCB delay, one CS, 64Mb */ + REGWR MIF_CONFIG2 0x0aa20049 + + /* CKE high */ + REGWR MIF_INIT 0x00000020 + + /* 400ns */ + .rept 16 + nop + .endr + + /* precharge all banks (BA0=0, BA1=0, A10=1) */ + REGWR MIF_INIT 0x10000004 + /* EMRS(2): (BA1=1, BA0=0, Ax=0) */ + REGWR MIF_INIT 0x00020002 + /* EMRS(3): (BA0=1, BA1=1, Ax=0) */ + REGWR MIF_INIT 0x00030002 + /* EMRS(1): enable DLL (BA0=1, BA1=0, Ax=0) */ + REGWR MIF_INIT 0x00010002 + + /* + MRS: reset DLL (A8=1), BL=4 (A1=1) + CL=5 (A4=1, A6=1), WR=5 (A11=1) + */ + REGWR MIF_INIT 0x25480002 + + /* 200us */ + li t2, MEM_200US +1: + bne t2, zero, 1b + addi t2, -1 + + /* precharge all banks (BA0=0, BA1=0, A10=1) */ + REGWR MIF_INIT 0x10000004 + /* refresh */ + REGWR MIF_INIT 0x00000001 + /* refresh */ + REGWR MIF_INIT 0x00000001 + + /* 100ns */ + .rept 4 + nop + .endr + + /* + MRS: clear DLL reset flag (A8=0) + leave other parms as in earlier issued MRS + */ + REGWR MIF_INIT 0x21480002 + + /* + EMRS(1): OCD calibration + driver strength weak (A1=1), Rtt=75ohm (A2=1, A6=0) + */ + REGWR MIF_INIT 0x00590002 + + /* + set refresh interval to (0x50 * 16 * SCLK) + register = (0x50 | REFRESH_ENABLE) + REFRESH_ENABLE = 0x100 + */ + REGWR MIF_REFCNT 0x00000150 + + jr ra + nop diff --git a/board/emma3sllp/u-boot.lds b/board/emma3sllp/u-boot.lds new file mode 100644 index 0000000..73979af --- /dev/null +++ b/board/emma3sllp/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata) } + + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start ) >> 2; + + . = ALIGN(4); + .sbss (NOLOAD) : { *(.sbss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + uboot_end = .; +} diff --git a/doc/README.emma3sllp b/doc/README.emma3sllp new file mode 100644 index 0000000..dfefa9a --- /dev/null +++ b/doc/README.emma3sllp @@ -0,0 +1,10 @@ +EMMA3SL/LP + +generation: 0x02000011 (EMMA3SL/L) +product version: 0x018e +cpu: 4KEc, 288MHz +endianess: big +unified mem clock: 156MHz (SCLK = MCLK/2 = 312/2) +flash: S29GL064N90BFI04 (8Mb, 16bit, bottom boot) +memory: EDE5116AJBG-6E-E (64Mb, 16bit, 667Mbps) +ethernet: KSZ8041NL, RMII diff --git a/include/configs/emma3sllp.h b/include/configs/emma3sllp.h new file mode 100644 index 0000000..599104e --- /dev/null +++ b/include/configs/emma3sllp.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2010 + * Serge Ziryukin, ftrvxmtrx(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/addrspace.h> + +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_MIPS32 1 + +#define CPU_CLOCK_RATE 288000000 + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_TIMESTAMP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BOOTARGS "" +#define CONFIG_EXTRA_ENV_SETTINGS "" +#define CONFIG_BOOTCOMMAND "" +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SAVEENV + +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_FAT + +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BSP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_PORTIO + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + +/* 256Kb */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +/* 64Kb */ +#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_SDRAM_SIZE (64 << 20) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_LOAD_ADDR 0x80400000 +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +/* one flash bank */ +#define PHYS_FLASH_1 0xbc000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/* erase/write timeouts in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +/* env on flash */ +#define CONFIG_ENV_ADDR \ + (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE + +/* cache */ +#define CONFIG_SYS_DCACHE_SIZE (8 << 10) /* 8kB */ +#define CONFIG_SYS_ICACHE_SIZE (8 << 10) /* 8kB */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +/* serial */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_SYS_NS16550_CLK 18432000 +#define CONFIG_SYS_NS16550_COM1 0xb0101000 +#define CONFIG_SYS_NS16550_COM2 0xb0102000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#endif /* __CONFIG_H */ -- 1.7.1

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