February 2010 - U-Boot

[U-Boot] [PATCH 2/2] s5pc1xx: update the README file
by Minkyu Kang 18 Feb '10

18 Feb '10

Because adds support the GPIO Interface, README file is updated. Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- doc/README.s5pc1xx | 18 +++++++++++++++++- 1 files changed, 17 insertions(+), 1 deletions(-) diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx index 5a0fe33..ab1f024 100644 --- a/doc/README.s5pc1xx +++ b/doc/README.s5pc1xx @@ -41,7 +41,23 @@ To check SoC: printf("cpu is s5pc110\n"); gpio - not supported yet. + + struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE; + + /* GPA[0] pin set to irq */ + gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ); + + /* GPA[0] pin set to input */ + gpio_direction_input(&gpio->gpio_a, 0); + + /* GPA[0] pin set to output/high */ + gpio_direction_output(&gpio->gpio_a, 0, 1); + + /* GPA[0] value set to low */ + gpio_set_value(&gpio->gpio_a, 0, 0); + + /* get GPA[0] value */ + value = gpio_get_value(&gpio->gpio_a, 0); Links ===== -- 1.5.4.3

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[U-Boot] ARM pull request
by Tom 17 Feb '10

17 Feb '10

Wolfgang, Please pull from arm/master. Best regards, Tom The following changes since commit 0b692dcb190655c7eb96b6b8003bee163e3b58dd: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-net are available in the git repository at: git://git.denx.de/u-boot-arm master Alessandro Rubini (3): EP93xx: fix syscon_regs definition edb93xx: change calculation un early_udelay.h edb93xx: enable the uart in devicecfg register Daniel Gorsulowski (1): at91: Add esd gmbh OTC570 board support Jens Scharsig (9): add new CONFIG_AT91_LEGACY add c structures for SoC access add a new AT91 GPIO driver convert all at91 files to use at91_gpio driver syntax convert common files to new SoC access update at91sam9263ek board to new SoC access prepare joining at91rm9200 into at91 new at91_emac network driver (NET_MULTI api) new board (eb_cpux9k2) Ladislav Michl (3): NetStar: Disable CONFIG_CMD_JFFS2 NetStar: make crcit utility more readable NetStar: Remove debug junk leaked into eeprom utility Magnus Lilja (1): SPI: Fix 32 bit transfers in mxc_spi.c Matthias Kaehlcke (2): Add support for EDB93xx boards ARM: Add support for EP93xx SoCs Nick Thompson (3): da830evm: Use table driven pin mux configuration Davinci: Add EMIF-A macros for setting chip select parameters DA830 EVM: Enable NAND support on Spectrum Digital EVM Sanjeev Premi (1): OMAP3: Avoid re-write to PRM_CLKSRC_CTRL Scott Ellis (1): Overo GPMC registers Sekhar Nori (1): TI DaVinci: Driver for the davinci SPI controller Tom Rix (1): OMAP3 Move declaration of gpmc_cfg. MAINTAINERS | 15 + MAKEALL | 10 + Makefile | 16 + board/BuS/eb_cpux9k2/Makefile | 50 +++ board/BuS/eb_cpux9k2/config.mk | 1 + board/BuS/eb_cpux9k2/cpux9k2.c | 387 +++++++++++++++++ board/atmel/at91sam9263ek/at91sam9263ek.c | 151 ++++---- board/atmel/at91sam9263ek/led.c | 21 +- board/davinci/da830evm/da830evm.c | 72 +++- board/edb93xx/Makefile | 50 +++ board/edb93xx/config.mk | 33 ++ board/edb93xx/early_udelay.h | 34 ++ board/edb93xx/edb93xx.c | 110 +++++ board/edb93xx/flash_cfg.c | 38 ++ board/edb93xx/pll_cfg.c | 58 +++ board/edb93xx/pll_cfg.h | 72 ++++ board/edb93xx/sdram_cfg.c | 123 ++++++ board/edb93xx/sdram_cfg.h | 144 +++++++ board/esd/otc570/Makefile | 55 +++ board/esd/otc570/config.mk | 1 + board/esd/otc570/otc570.c | 365 ++++++++++++++++ board/esd/otc570/partition.c | 37 ++ board/netstar/crcit.c | 9 +- board/netstar/eeprom.c | 8 +- board/netstar/eeprom_start.S | 166 +-------- board/overo/overo.c | 14 +- board/overo/overo.h | 9 + cpu/arm920t/at91/Makefile | 47 +++ cpu/arm920t/at91/lowlevel_init.S | 164 ++++++++ cpu/arm920t/at91/reset.c | 59 +++ cpu/arm920t/at91/timer.c | 163 ++++++++ cpu/arm920t/cpu.c | 4 + cpu/arm920t/ep93xx/Makefile | 56 +++ cpu/arm920t/ep93xx/cpu.c | 51 +++ cpu/arm920t/ep93xx/led.c | 101 +++++ cpu/arm920t/ep93xx/lowlevel_init.S | 65 +++ cpu/arm920t/ep93xx/speed.c | 110 +++++ cpu/arm920t/ep93xx/timer.c | 168 ++++++++ cpu/arm920t/ep93xx/u-boot.lds | 59 +++ cpu/arm926ejs/at91/at91cap9_devices.c | 128 ++++--- cpu/arm926ejs/at91/at91sam9260_devices.c | 124 +++--- cpu/arm926ejs/at91/at91sam9261_devices.c | 84 +++-- cpu/arm926ejs/at91/at91sam9263_devices.c | 137 ++++--- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 120 +++--- cpu/arm926ejs/at91/at91sam9rl_devices.c | 58 ++-- cpu/arm926ejs/at91/clock.c | 51 ++- cpu/arm926ejs/at91/cpu.c | 4 + cpu/arm926ejs/at91/led.c | 1 + cpu/arm926ejs/at91/lowlevel_init.S | 95 ++--- cpu/arm926ejs/at91/reset.c | 8 +- cpu/arm926ejs/at91/timer.c | 17 +- cpu/arm_cortexa8/omap3/clock.c | 20 +- doc/README.at91-soc | 64 +++ drivers/gpio/Makefile | 1 + drivers/gpio/at91_gpio.c | 214 ++++++++++ drivers/i2c/soft_i2c.c | 11 +- drivers/serial/at91rm9200_usart.c | 8 + drivers/serial/atmel_usart.c | 4 + drivers/spi/Makefile | 1 + drivers/spi/atmel_dataflash_spi.c | 4 + drivers/spi/davinci_spi.c | 223 ++++++++++ drivers/spi/davinci_spi.h | 101 +++++ drivers/spi/mxc_spi.c | 9 + drivers/usb/host/ohci-at91.c | 5 + drivers/video/bus_vcxk.c | 22 +- include/asm-arm/arch-at91/at91_emac.h | 4 +- include/asm-arm/arch-at91/at91_matrix.h | 116 ++++++ include/asm-arm/arch-at91/at91_mc.h | 97 +++++ include/asm-arm/arch-at91/at91_pdc.h | 39 ++ include/asm-arm/arch-at91/at91_pio.h | 111 +++++ include/asm-arm/arch-at91/at91_pit.h | 15 + include/asm-arm/arch-at91/at91_pmc.h | 91 ++++ include/asm-arm/arch-at91/at91_rstc.h | 30 ++- include/asm-arm/arch-at91/at91_spi.h | 21 + include/asm-arm/arch-at91/at91_st.h | 46 ++ include/asm-arm/arch-at91/at91_tc.h | 77 ++++ include/asm-arm/arch-at91/at91_wdt.h | 29 ++ include/asm-arm/arch-at91/at91cap9.h | 8 + include/asm-arm/arch-at91/at91rm9200.h | 135 ++++++ include/asm-arm/arch-at91/at91sam9260.h | 14 + include/asm-arm/arch-at91/at91sam9261.h | 12 +- include/asm-arm/arch-at91/at91sam9263.h | 20 + include/asm-arm/arch-at91/at91sam9_sdramc.h | 13 + include/asm-arm/arch-at91/at91sam9_smc.h | 63 +++ include/asm-arm/arch-at91/at91sam9g45.h | 13 + include/asm-arm/arch-at91/at91sam9rl.h | 12 +- include/asm-arm/arch-at91/gpio.h | 171 +------- include/asm-arm/arch-at91/hardware.h | 2 +- include/asm-arm/arch-at91/io.h | 3 + include/asm-arm/arch-davinci/emif_defs.h | 18 +- include/asm-arm/arch-ep93xx/ep93xx.h | 596 +++++++++++++++++++++++++++ include/asm-arm/arch-omap3/cpu.h | 4 + include/common.h | 3 +- include/configs/afeb9260.h | 3 + include/configs/at91cap9adk.h | 3 + include/configs/at91rm9200dk.h | 2 + include/configs/at91rm9200ek.h | 2 + include/configs/at91sam9260ek.h | 3 + include/configs/at91sam9261ek.h | 3 + include/configs/at91sam9263ek.h | 87 ++-- include/configs/at91sam9m10g45ek.h | 3 + include/configs/at91sam9rlek.h | 3 + include/configs/cmc_pu2.h | 2 + include/configs/cpu9260.h | 3 + include/configs/cpuat91.h | 2 + include/configs/csb637.h | 2 + include/configs/da830evm.h | 21 +- include/configs/devkit8000.h | 1 - include/configs/eb_cpux9k2.h | 415 +++++++++++++++++++ include/configs/edb93xx.h | 270 ++++++++++++ include/configs/kb9202.h | 2 + include/configs/m501sk.h | 2 + include/configs/meesc.h | 3 + include/configs/mp2usb.h | 2 + include/configs/netstar.h | 3 - include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_overo.h | 1 - include/configs/omap3_pandora.h | 1 - include/configs/omap3_sdp3430.h | 1 - include/configs/omap3_zoom1.h | 1 - include/configs/omap3_zoom2.h | 1 - include/configs/otc570.h | 246 +++++++++++ include/configs/pm9261.h | 3 + include/configs/pm9263.h | 3 + include/configs/sbc35_a9g20.h | 3 + include/configs/tny_a9260.h | 3 + include/i2c.h | 5 + tools/Makefile | 3 + tools/logos/esd.bmp | Bin 0 -> 35078 bytes 130 files changed, 6601 insertions(+), 882 deletions(-) create mode 100644 board/BuS/eb_cpux9k2/Makefile create mode 100644 board/BuS/eb_cpux9k2/config.mk create mode 100644 board/BuS/eb_cpux9k2/cpux9k2.c create mode 100644 board/edb93xx/Makefile create mode 100644 board/edb93xx/config.mk create mode 100644 board/edb93xx/early_udelay.h create mode 100644 board/edb93xx/edb93xx.c create mode 100644 board/edb93xx/flash_cfg.c create mode 100644 board/edb93xx/pll_cfg.c create mode 100644 board/edb93xx/pll_cfg.h create mode 100644 board/edb93xx/sdram_cfg.c create mode 100644 board/edb93xx/sdram_cfg.h create mode 100644 board/esd/otc570/Makefile create mode 100644 board/esd/otc570/config.mk create mode 100644 board/esd/otc570/otc570.c create mode 100644 board/esd/otc570/partition.c create mode 100644 cpu/arm920t/at91/Makefile create mode 100644 cpu/arm920t/at91/lowlevel_init.S create mode 100644 cpu/arm920t/at91/reset.c create mode 100644 cpu/arm920t/at91/timer.c create mode 100644 cpu/arm920t/ep93xx/Makefile create mode 100644 cpu/arm920t/ep93xx/cpu.c create mode 100644 cpu/arm920t/ep93xx/led.c create mode 100644 cpu/arm920t/ep93xx/lowlevel_init.S create mode 100644 cpu/arm920t/ep93xx/speed.c create mode 100644 cpu/arm920t/ep93xx/timer.c create mode 100644 cpu/arm920t/ep93xx/u-boot.lds create mode 100644 doc/README.at91-soc create mode 100644 drivers/gpio/at91_gpio.c create mode 100644 drivers/spi/davinci_spi.c create mode 100644 drivers/spi/davinci_spi.h create mode 100644 include/asm-arm/arch-at91/at91_matrix.h create mode 100644 include/asm-arm/arch-at91/at91_mc.h create mode 100644 include/asm-arm/arch-at91/at91_pdc.h create mode 100644 include/asm-arm/arch-at91/at91_st.h create mode 100644 include/asm-arm/arch-at91/at91_tc.h create mode 100644 include/asm-arm/arch-at91/at91rm9200.h create mode 100644 include/asm-arm/arch-ep93xx/ep93xx.h create mode 100644 include/configs/eb_cpux9k2.h create mode 100644 include/configs/edb93xx.h create mode 100644 include/configs/otc570.h create mode 100644 tools/logos/esd.bmp

2 1

[U-Boot] [PATCH ARM] updates the at91 main_clock calculation
by Jens Scharsig 17 Feb '10

17 Feb '10

* updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access * add need register flags Signed-off-by: Jens Scharsig <js_at_ng(a)scharsoft.de> --- cpu/arm926ejs/at91/clock.c | 7 ++++--- include/asm-arm/arch-at91/at91_pmc.h | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 7e03907..f3988fc 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -157,9 +157,10 @@ int at91_clock_init(unsigned long main_clock) */ if (!main_clock) { do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (AT91_SLOW_CLOCK / 16); } #endif main_clk_rate_hz = main_clock; diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 369b5d7..680fe33 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -71,6 +71,9 @@ typedef struct at91_pmc { #define AT91_PMC_PLLBR_USBDIV_2 0x10000000 #define AT91_PMC_PLLBR_USBDIV_4 0x20000000 +#define AT91_PMC_MCFR_MAINRDY 0x00010000 +#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF + #define AT91_PMC_MCKR_CSS_SLOW 0x00000000 #define AT91_PMC_MCKR_CSS_MAIN 0x00000001 #define AT91_PMC_MCKR_CSS_PLLA 0x00000002 -- 1.6.0.2

3 5

[U-Boot] PATCH kup4-boards: minor configuration changes
by Heydeck, Klaus-Jürgen 17 Feb '10

17 Feb '10

also preparation for using hwconfig and device tree support Signed-off-by: Klaus Heydeck <heydeck(a)kieback-peter.de> diff -purN u-boot.git/board/kup/common/kup.c u-boot/board/kup/common/kup.c --- u-boot.git/board/kup/common/kup.c 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/common/kup.c 2010-02-17 13:03:51.000000000 +0100 @@ -24,6 +24,24 @@ #include <common.h> #include <mpc8xx.h> #include "kup.h" +#ifdef CONFIG_KUP4_LOGO + #include "s1d13706.h" +#endif + +#undef DEBUG +#ifdef DEBUG +# define debugk(fmt,args...) printf(fmt ,##args) +#else +# define debugk(fmt,args...) +#endif + +#define PRINTF(fmt,args...) printf(fmt ,##args) + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; + int misc_init_f (void) { @@ -31,7 +49,7 @@ int misc_init_f (void) volatile sysconf8xx_t *siu = &immap->im_siu_conf; while (siu->sc_sipend & 0x20000000) { - /* printf("waiting for 5V VCC\n"); */ + debugk("waiting for 5V VCC\n"); ; } @@ -40,6 +58,14 @@ int misc_init_f (void) immap->im_ioport.iop_papar &= ~(PA_RS485); immap->im_ioport.iop_paodr &= ~(PA_RS485); immap->im_ioport.iop_padir |= (PA_RS485); + + /* IO Reset min 1 msec */ + immap->im_ioport.iop_padat |= (PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_papar &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_paodr &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); + immap->im_ioport.iop_padir |= (PA_RESET_IO_01 | PA_RESET_IO_02); + udelay(1000); + immap->im_ioport.iop_padat &= ~(PA_RESET_IO_01 | PA_RESET_IO_02); return (0); } @@ -70,3 +96,159 @@ void poweron_key (void) else setenv ("key1", "on"); } + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed (void) +{ + return (0); +} +#endif + +unsigned char swapbyte(unsigned char c) +{ + unsigned char result=0; + int i=0; + for(i=0;i<8;++i){ + result=result<<1; + result|=(c&1); + c=c>>1; + } + return result; +} + +#ifdef CONFIG_KUP4_LOGO + +void lcd_logo (bd_t * bd) +{ + FB_INFO_S1D13xxx fb_info; + S1D_INDEX s1dReg; + S1D_VALUE s1dValue; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl; + ushort i; + uchar *fb; + int rs, gs, bs; + int r = 8, g = 8, b = 4; + int r1, g1, b1; + + immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ + immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); + +/*----------------------------------------------------------------------------- */ +/* Initialize the chip and the frame buffer driver. */ +/*----------------------------------------------------------------------------- */ + memctl = &immr->im_memctl; + + /* + * Init ChipSelect #5 (S1D13768) + */ + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; + __asm__ ("eieio"); + + fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); + fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); + + if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) + || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { + printf ("Warning:LCD Controller S1D13706 not found\n"); + setenv ("lcd", "none"); + return; + } + ((S1D_VALUE*)fb_info.RegAddr)[0xA8] = 0x00; + ((S1D_VALUE*)fb_info.RegAddr)[0xA9] = 0x80; + unsigned char s1d1gpio = ((S1D_VALUE*)fb_info.RegAddr)[0xAC]; + /* printf("s1d1gpio:0x%02X\n",s1d1gpio); */ + s1d1gpio &= 0x1E; + s1d1gpio >>= 1; + + /* init controller */ + switch (s1d1gpio){ + + case 0x02: /* STN */ + for (i = 0; i < sizeof (aS1DRegs_stn) / sizeof (aS1DRegs_stn[0]); i++) + { + s1dReg = aS1DRegs_stn[i].Index; + s1dValue = aS1DRegs_stn[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; + break; + case 48000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 64000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; + break; + } + break; + + case 0x00: /* TFT */ + for (i = 0; i < sizeof (aS1DRegs_tft) / sizeof (aS1DRegs_tft[0]); i++) + { + s1dReg = aS1DRegs_tft[i].Index; + s1dValue = aS1DRegs_tft[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 40 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; + break; + } + break; + + case 0x01: /* mono */ + for (i = 0; i < sizeof (aS1DRegs_mono) / sizeof (aS1DRegs_mono[0]); i++) + { + s1dReg = aS1DRegs_mono[i].Index; + s1dValue = aS1DRegs_mono[i].Value; + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = s1dValue; + } + switch (bd->bi_busfreq){ + default: + printf ("KUP4 S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + } + break; + default: + printf("Unknown LCD config!!!\n"); + break; + } + + /* create and set colormap */ + rs = 256 / (r - 1); + gs = 256 / (g - 1); + bs = 256 / (b - 1); + for (i = 0; i < 256; i++) { + r1 = (rs * ((i / (g * b)) % r)) * 255; + g1 = (gs * ((i / b) % g)) * 255; + b1 = (bs * ((i) % b)) * 255; + debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); + S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), + (b1 >> 4)); + } + + /* copy bitmap */ + fb = (uchar *) (fb_info.VmemAddr); + memcpy (fb, (uchar *) CONFIG_KUP4_LOGO, 320 * 240); +} +#endif /* CONFIG_KUP4_LOGO */ diff -purN u-boot.git/board/kup/common/kup.h u-boot/board/kup/common/kup.h --- u-boot.git/board/kup/common/kup.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/common/kup.h 2010-02-17 13:03:51.000000000 +0100 @@ -25,22 +25,35 @@ #define __KUP_H #define PA_8 0x0080 +#define PA_9 0x0040 +#define PA_10 0x0020 #define PA_11 0x0010 #define PA_12 0x0008 #define PB_14 0x00020000 +#define PB_15 0x00010000 +#define PB_16 0x00008000 #define PB_17 0x00004000 #define PC_9 0x0040 #define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 +#define PA_LED_YELLOW PA_8 /* */ +#define PA_RESET_IO_01 PA_9 /* Reset left IO */ +#define PA_RESET_IO_02 PA_10 /* Reset right IO */ +#define PB_PROG_IO_01 PB_15 /* Program left IO */ +#define PB_PROG_IO_02 PB_16 /* Program right IO */ #define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ #define PB_LCD_PWM PB_17 /* PB 17 */ #define PC_SWITCH1 PC_9 /* Reboot switch */ -extern void poweron_key (void); +#define CONFIG_KUP4_LOGO 0x40050000 /* Address of logo bitmap */ -extern void load_sernum_ethaddr(void); +extern void poweron_key (void); +extern unsigned char swapbyte(unsigned char c); +void lcd_logo (bd_t * bd); +extern int read_diag (void); +extern void load_sernum_ethaddr (void); #endif /* __KUP_H */ + diff -purN u-boot.git/board/kup/common/s1d13706.h u-boot/board/kup/common/s1d13706.h --- u-boot.git/board/kup/common/s1d13706.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/kup/common/s1d13706.h 2010-02-17 13:03:51.000000000 +0100 @@ -0,0 +1,237 @@ +/*---------------------------------------------------------------------------- */ +/* */ +/* File generated by S1D13706CFG.EXE */ +/* */ +/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ +/* All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------- */ + +/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ + +#define S1D_DISPLAY_WIDTH 320 +#define S1D_DISPLAY_HEIGHT 240 +#define S1D_DISPLAY_BPP 8 +#define S1D_DISPLAY_SCANLINE_BYTES 320 +#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L +#define S1D_PHYSICAL_VMEM_SIZE 0x14000L +#define S1D_PHYSICAL_REG_ADDR 0x80080000L +#define S1D_PHYSICAL_REG_SIZE 0x100 +#define S1D_DISPLAY_PCLK 6250 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ + ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ + ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ + ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + + +static S1D_REGS aS1DRegs_stn[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x10,0xD0}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xF0}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x80}, /* Vertical Sync Pulse Width Register */ + {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x83}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + +static S1D_REGS aS1DRegs_tft[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x05,0x42}, /* PCLK Config Register */ + {0x10,0x61}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x12,0x30}, /* Horizontal Total Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xFA}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x00}, /* Vertical Sync Pulse Width Register */ + {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x03}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + + + + +/* + MOD Rate = 200Hz (bei 60Hz Framerate) 60 * 3.33 = 240/3.33 = 72 (/2 weil togglen gemeint ist) = 36 = 0x24 + MOD Rate = 400Hz (bei 60Hz Framerate) 60 * 3.33 = 36 (/2 weil togglen gemeint ist) = 18 = 0x12 + MOD Rate 300Hz = 60Hz*5 = 240/5 = 48 (/2 weil togglen gemeint ist) = 24 = 0x18 + + Framerate Powertip-PS320240 : 55..75Hz + + Für MPC859 mit 64/128MHz + +*/ + +static S1D_REGS aS1DRegs_mono[] = +{ + {0x70,0x80}, + {0x04,0x10}, + {0x05,0x30}, + {0x10,0x00}, + {0x11,0x00}, + {0x12,0x30}, + {0x14,0x27}, + {0x16,0x00}, + {0x17,0x00}, + {0x18,0xf0}, + {0x19,0x00}, + {0x1c,0xef}, + {0x1d,0x00}, + {0x1e,0x00}, + {0x1f,0x00}, + {0x20,0x87}, + {0x22,0x00}, + {0x23,0x00}, + {0x24,0x80}, + {0x26,0x01}, + {0x27,0x00}, + {0x70,0x82}, + {0x71,0x00}, + {0x74,0x00}, + {0x75,0x00}, + {0x76,0x00}, + {0x78,0x50}, + {0x79,0x00}, + {0x7c,0x00}, + {0x7d,0x00}, + {0x7e,0x00}, + {0x80,0x50}, + {0x81,0x00}, + {0x84,0x00}, + {0x85,0x00}, + {0x88,0x00}, + {0x89,0x00}, + {0x8c,0x4f}, + {0x8d,0x00}, + {0x90,0xef}, + {0x91,0x00}, + {0xa0,0x00}, + {0xa1,0x00}, + {0xa2,0x00}, + {0xa3,0x00}, + {0xa4,0x00}, + {0xa5,0x00}, + {0xb0,0x11}, + {0xb1,0x08}, + {0xb2,0x01}, + {0xb3,0x00}, + {0xa8,0x01}, + {0xa9,0x80}, + {0xac,0x01}, + {0xad,0x00}, + {0xad,0x80}, + {0x70,0x53}, + {0xb0,0x13}, + {0xb1,0x4e}, + {0xb2,0x01}, + {0xb3,0x00}, +}; diff -purN u-boot.git/board/kup/kup4k/kup4k.c u-boot/board/kup/kup4k/kup4k.c --- u-boot.git/board/kup/kup4k/kup4k.c 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/kup4k/kup4k.c 2010-02-17 13:03:51.000000000 +0100 @@ -23,32 +23,20 @@ */ #include <common.h> +#include <command.h> #include <mpc8xx.h> +#include <hwconfig.h> +#include <i2c.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO - #include "s1d13706.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG -#ifdef DEBUG -# define debugk(fmt,args...) printf(fmt ,##args) -#else -# define debugk(fmt,args...) +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> #endif -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - - -/* ------------------------------------------------------------------------- */ +DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo(bd_t *bd); -#endif +int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* ------------------------------------------------------------------------- */ @@ -60,7 +48,7 @@ const uint sdram_table[] = { * Single Read. (Offset 0 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ + 0x1FF77C47, /* last */ /* * SDRAM Initialization (offset 5 in UPMA RAM) @@ -70,28 +58,28 @@ const uint sdram_table[] = { * sequence, which is executed by a RUN command. * */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ /* * Burst Read. (Offset 8 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, @@ -99,55 +87,87 @@ const uint sdram_table[] = { * Refresh (Offset 30 in UPMA RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, }; /* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ int checkboard (void) { + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - uchar *latch,rev,mod; - - /* - * Init ChipSelect #4 (CAN + HW-Latch) - */ - immap->im_memctl.memc_or4 = 0xFFFF8926; - immap->im_memctl.memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch=(uchar *)0x90000200; - rev = (*latch & 0xF8) >> 3; - mod=(*latch & 0x03); - printf ("Board: KUP4K Rev %d.%d\n",rev,mod); - return (0); + uchar *latch,rev,mod,tmp,pcf,ak_rev,ak_mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + immap->im_memctl.memc_or4 = CONFIG_SYS_OR4; + immap->im_memctl.memc_br4 = CONFIG_SYS_BR4; + __asm__ ("eieio"); + latch = (uchar *)0x90000200; + tmp = swapbyte (*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); + + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (read_diag()) + gd->flags &= ~GD_FLG_SILENT; + + printf ("Board: KUP4K Rev %d.%d AK:",rev,mod); + + /* TI Application report: Before using the IO as an input, + * a high must be written to the IO first + */ + pcf = 0xFF; + i2c_write (0x21, 0, 0 , &pcf, 1); + if (i2c_read (0x21, 0, 0, &pcf, 1)) { + puts ("n/a\n"); + } + else { + ak_rev = (pcf & 0xF8) >> 3; + ak_mod = (pcf & 0x07); + printf ("%d.%d\n",ak_rev,ak_mod); + } + return (0); } /* ------------------------------------------------------------------------- */ + phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; + long int size = 0; + uchar *latch,rev,mod,tmp; - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); + /* + * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision + * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB + */ + immap->im_memctl.memc_or4 = CONFIG_SYS_OR4; + immap->im_memctl.memc_br4 = CONFIG_SYS_BR4; + __asm__ ("eieio"); + latch = (uchar *)0x90000200; + tmp = swapbyte (*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us @@ -158,20 +178,12 @@ phys_size_t initdram (int board_type) memctl->memc_mar = 0x00000088; - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ - -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ - - - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - + if(rev >= 7){ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + } + else{ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + } udelay (200); /* perform SDRAM initializsation sequence */ @@ -200,49 +212,53 @@ phys_size_t initdram (int board_type) memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); -#if 0 /* 3 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; -#else /* 3 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFC000A00; - memctl->memc_br3 = 0x02000081; -#endif - - udelay (10000); - - return (size_b0 + size_b1 + size_b2); + if(rev >= 7){ + char* arguments[3]={"memtest","0x00000000","0x05FFFFFF"}; + char *s; + size = 32 * 3 * 1024 * 1024; + memctl->memc_or1 = CONFIG_SYS_OR1_9COL; + memctl->memc_br1 = CONFIG_SYS_BR1_9COL; + memctl->memc_or2 = CONFIG_SYS_OR2_9COL; + memctl->memc_br2 = CONFIG_SYS_BR2_9COL; + memctl->memc_or3 = CONFIG_SYS_OR3_9COL; + memctl->memc_br3 = CONFIG_SYS_BR3_9COL; + s = getenv ("memtest"); + if(s) + do_mem_mtest(0,0,3,arguments); + } + else{ + char* arguments[3]={"memtest","0x00000000","0x02FFFFFF"}; + char *s; + size = 16 * 3 * 1024 * 1024; + memctl->memc_or1 = CONFIG_SYS_OR1_8COL; + memctl->memc_br1 = CONFIG_SYS_BR1_8COL; + memctl->memc_or2 = CONFIG_SYS_OR2_8COL; + memctl->memc_br2 = CONFIG_SYS_BR2_8COL; + memctl->memc_or3 = CONFIG_SYS_OR3_8COL; + memctl->memc_br3 = CONFIG_SYS_BR3_8COL; + s = getenv ("memtest"); + if(s) + do_mem_mtest(0,0,3,arguments); + } + return (size); } /* ------------------------------------------------------------------------- */ + int misc_init_r (void) { -#ifdef CONFIG_STATUS_LED + DECLARE_GLOBAL_DATA_PTR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#endif -#ifdef CONFIG_KUP4K_LOGO + +#ifdef CONFIG_KUP4_LOGO bd_t *bd = gd->bd; lcd_logo (bd); -#endif /* CONFIG_KUP4K_LOGO */ +#endif #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ immap->im_ioport.iop_padir |= 0x80; @@ -253,152 +269,156 @@ int misc_init_r (void) load_sernum_ethaddr(); setenv("hw","4k"); poweron_key(); +#if 0 + if ((char *p = getenv ("contrast")) != NULL) { + char buffer[64]; + unsigned long contrast = simple_strtoul (p, NULL, 10) * 127 / 100; + sprintf(buffer,"%x",contrast); + char* arguments[4]={"imw","2E","0.0",buffer}; + do_i2c_mw(0,0,4,arguments); + } +#endif return (0); } -#ifdef CONFIG_KUP4K_LOGO - -void lcd_logo (bd_t * bd) +int read_diag (void) { - FB_INFO_S1D13xxx fb_info; - S1D_INDEX s1dReg; - S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl; - ushort i; - uchar *fb; - int rs, gs, bs; - int r = 8, g = 8, b = 4; - int r1, g1, b1; - int n; - char tmp[64]; /* long enough for environment variables */ - int tft = 0; - - immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); - -/*----------------------------------------------------------------------------- */ -/* Initialize the chip and the frame buffer driver. */ -/*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; - - - /* - * Init ChipSelect #5 (S1D13768) - */ - memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ - __asm__ ("eieio"); - - fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); - fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); - - if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { - printf ("Warning:LCD Controller S1D13706 not found\n"); - setenv ("lcd", "none"); - return; - } - - - for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { - s1dReg = aS1DRegs_prelimn[i].Index; - s1dValue = aS1DRegs_prelimn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - - n = getenv_r ("lcd", tmp, sizeof (tmp)); - if (n > 0) { - if (!strcmp ("tft", tmp)) - tft = 1; - else - tft = 0; - } -#if 0 - if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) - tft = 0; - else - tft = 1; -#endif - - debugk ("Port=0x%02x -> TFT=%d\n", tft, - ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); - - /* init controller */ - if (!tft) { - for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { - s1dReg = aS1DRegs_stn[i].Index; - s1dValue = aS1DRegs_stn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_stn[i].Index, - aS1DRegs_stn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = - s1dValue; + #define PC4 0x0800 + #define PC5 0x0400 + int diag; + + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + immr->im_ioport.iop_pcdir &= ~PC4; /* input */ + immr->im_ioport.iop_pcpar &= ~PC4; /* gpio */ + immr->im_ioport.iop_pcdir |= PC5; /* output */ + immr->im_ioport.iop_pcpar &= ~PC4; /* gpio */ + immr->im_ioport.iop_pcdat |= PC5; /* 1 */ + udelay(500); + if(immr->im_ioport.iop_pcdat & PC4){ + immr->im_ioport.iop_pcdat &= ~PC5; /* 0 */ + udelay(500); + if(immr->im_ioport.iop_pcdat & PC4){ + diag=0; } - n = getenv_r ("contrast", tmp, sizeof (tmp)); - ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = - (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; - switch (bd->bi_busfreq) { - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; + else{ + diag=1; } - /* setenv("lcd","stn"); */ - } else { - for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { - s1dReg = aS1DRegs_tft[i].Index; - s1dValue = aS1DRegs_tft[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_tft[i].Index, - aS1DRegs_tft[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - switch (bd->bi_busfreq) { - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; - break; - } - /* setenv("lcd","tft"); */ } - - /* create and set colormap */ - rs = 256 / (r - 1); - gs = 256 / (g - 1); - bs = 256 / (b - 1); - for (i = 0; i < 256; i++) { - r1 = (rs * ((i / (g * b)) % r)) * 255; - g1 = (gs * ((i / b) % g)) * 255; - b1 = (bs * ((i) % b)) * 255; - debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); - S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); + else{ + diag=0; } - - /* copy bitmap */ - fb = (uchar *) (fb_info.VmemAddr); - memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); + immr->im_ioport.iop_pcdir &= ~PC5; /* input */ + return (diag); } -#endif /* CONFIG_KUP4K_LOGO */ + + +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, regname, var, + size); + if (ret < 0) { + printf("ft_blob_update(): " + "cannot set %s/%s property; err: %s\n", + nodename, regname, fdt_strerror (ret)); + } + } else { + printf("ft_blob_update(): " + "cannot find %s node err:%s\n", + nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +int fdt_del_node_name (void *blob, char *nodename) { + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_del_node (blob, nodeoffset); + if (ret < 0) { + printf("%s: cannot delete %s; err: %s\n", + __func__, nodename, fdt_strerror (ret)); + } + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +int fdt_del_prop_name (void *blob, char *nodename, char *propname) { + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_delprop (blob, nodeoffset, propname); + if (ret < 0) { + printf("%s: cannot delete %s %s; err: %s\n", + __func__, nodename, propname, + fdt_strerror (ret)); + } + } else { + printf("%s: cannot find %s node err:%s\n", + __func__, nodename, fdt_strerror (nodeoffset)); + } + return ret; +} + +/* + * update "brg" property in the blob + */ +void ft_blob_update (void *blob, bd_t *bd) { + uchar enetaddr[6]; + ulong brg_data = 0; + + /* BRG */ + brg_data = cpu_to_be32(bd->bi_busfreq); + fdt_set_node_and_value(blob, + "/soc/cpm", "brg-frequency", + &brg_data, sizeof(brg_data)); + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet0", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + + if (hwconfig_arg_cmp("fec", "off")) { + /* no FEC on this plattform, delete DTS nodes */ + fdt_del_node_name (blob, "ethernet1"); + fdt_del_node_name (blob, "mdio1"); + /* also the aliases entries */ + fdt_del_prop_name (blob, "/aliases", "ethernet1"); + fdt_del_prop_name (blob, "/aliases", "mdio1"); + } else { + /* adjust local-mac-address for FEC ethernet */ + if (eth_getenv_enetaddr("eth1addr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet1", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + } +} + +void ft_board_setup(void *blob, bd_t *bd) { + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff -purN u-boot.git/board/kup/kup4k/s1d13706.h u-boot/board/kup/kup4k/s1d13706.h --- u-boot.git/board/kup/kup4k/s1d13706.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/board/kup/kup4k/s1d13706.h 1970-01-01 01:00:00.000000000 +0100 @@ -1,174 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - - -static S1D_REGS aS1DRegs_prelimn[] = -{ - {0x10,0x00}, /* PANEL Type Register */ - {0xA8,0x00}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - -}; - -static S1D_REGS aS1DRegs_stn[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; - -static S1D_REGS aS1DRegs_tft[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x05,0x42}, /* PCLK Config Register */ - {0x10,0x61}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x12,0x30}, /* Horizontal Total Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xFA}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x00}, /* Vertical Sync Pulse Width Register */ - {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x03}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; diff -purN u-boot.git/include/configs/KUP4K.h u-boot/include/configs/KUP4K.h --- u-boot.git/include/configs/KUP4K.h 2010-02-16 09:02:08.000000000 +0100 +++ u-boot/include/configs/KUP4K.h 2010-02-17 13:03:51.000000000 +0100 @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck(a)kieback-peter.de * @@ -42,11 +42,7 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif #define CONFIG_BOARD_TYPES 1 /* support board types */ @@ -56,26 +52,32 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ + "run addhw; mw.b 200000 00 80; diskboot 200000 0:1; bootm 200000\0" \ "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ + "run addhw; mw.b 200000 00 80; diskboot 200000 2:1; bootm 200000\0" \ +"nfs_boot=mw.b 200000 00 80; dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"fat_boot=mw.b 200000 00 80; fatload ide 2:1 200000 st.bin; run addhw;\ + bootm 200000 \0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}${nfs-options}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"addhw=setenv bootargs ${bootargs} console=${console} ${debug} hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ +"nfs-options=,timeo=20,retrans=5\0" \ +"console=ttyS0\0" \ "netdev=eth0\0" \ -"contrast=55\0" \ +"contrast=20\0" \ "silent=1\0" \ +"initrd_high=c00000\0" \ "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ +"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40050000 14000\0" #define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" + "run fat_boot; run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" +#define CONFIG_PREBOOT "setenv preboot; saveenv" #define CONFIG_MISC_INIT_R 1 #define CONFIG_MISC_INIT_F 1 @@ -151,20 +153,8 @@ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII -#if 0 -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#endif -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 -/* POST support */ - -#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) -#endif /* @@ -176,13 +166,18 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NFS +#define CONFIG_CMD_FAT #define CONFIG_CMD_SNTP #ifdef CONFIG_POST #define CONFIG_CMD_DIAG #endif + + + /* * Miscellaneous configurable options */ @@ -197,8 +192,10 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ @@ -416,8 +413,8 @@ /* * FLASH timing: */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ + OR_SCY_5_CLK | OR_EHTR | OR_BI) #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) @@ -475,7 +472,39 @@ /* * MAMR settings for SDRAM */ -#define CONFIG_SYS_MAMR 0x80802114 + +/* 8 column SDRAM */ +#define CONFIG_SYS_MAMR_8COL 0x68802114 +/* 9 column SDRAM */ +#define CONFIG_SYS_MAMR_9COL 0x68904114 + +/* + * Chip Selects +*/ +#define CONFIG_SYS_OR0 +#define CONFIG_SYS_BR0 + +#define CONFIG_SYS_OR1_8COL 0xFF000A00 +#define CONFIG_SYS_BR1_8COL 0x00000081 +#define CONFIG_SYS_OR2_8COL 0xFE000A00 +#define CONFIG_SYS_BR2_8COL 0x01000081 +#define CONFIG_SYS_OR3_8COL 0xFC000A00 +#define CONFIG_SYS_BR3_8COL 0x02000081 + +#define CONFIG_SYS_OR1_9COL 0xFE000A00 +#define CONFIG_SYS_BR1_9COL 0x00000081 +#define CONFIG_SYS_OR2_9COL 0xFE000A00 +#define CONFIG_SYS_BR2_9COL 0x02000081 +#define CONFIG_SYS_OR3_9COL 0xFE000A00 +#define CONFIG_SYS_BR3_9COL 0x04000081 + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ +#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ + + /* * Internal Definitions @@ -487,11 +516,15 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_AUTOBOOT_STOP_STR "." +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_VERSION_VARIABLE 1 + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_HWCONFIG 1 + #endif /* __CONFIG_H */ Amtsgericht Charlottenburg, HRA 9371 Geschäftsführer: Dipl.-Ing. Joachim-Friedrich Laeger, Dr.-Ing. Joachim Horst Laeger Komplementärin: Laeger GmbH Tempelhofer Weg 50 12347 Berlin Amtsgericht Charlottenburg, HRB 6219

2 1

[U-Boot-Users] [PATCH] add explicit bbt creation to commandline
by Harald Welte 17 Feb '10

17 Feb '10

[PATCH] add explicit bbt creation to commandline ("nand createbbt" command) This patch adds user-requested BBT creation. It includes the following changes: - common/cmd_nand.c: move yes/no decision to separate function - do_nand: ask for confirmation for "nand erase" - do_nand: add command "nand createbbt" to erase NAND and create a new BBT Signed-off-by: Werner Almesberger <werner(a)openmoko.org> Signed-off-by: Harald Welte <laforge(a)openmoko.org> --- diff --git a/common/cmd_nand.c b/common/cmd_nand.c index bb46f34..2f41157 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -162,6 +162,17 @@ out: return 0; } +static int yes(void) +{ + char c; + + c = getc(); + if (c != 'y' && c != 'Y') + return 0; + c = getc(); + return c == '\r' || c == '\n'; +} + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i, dev, ret; @@ -231,7 +242,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 && + strcmp(cmd, "createbbt") != 0 ) goto usage; /* the following commands operate on the current device */ @@ -286,13 +298,23 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "are sure of what you are doing!\n" "\nReally scrub this NAND flash? <y/N>\n"); - if (getc() == 'y' && getc() == '\r') { + if (yes()) { opts.scrub = 1; } else { puts("scrub aborted\n"); return -1; } } + else { + if (opts.length == nand->size) { + puts("Really erase everything ? <y/N>\n"); + if (!yes()) { + puts("erase aborted\n"); + return -1; + } + } + } + ret = nand_erase_opts(nand, &opts); printf("%s\n", ret ? "ERROR" : "OK"); @@ -461,6 +483,33 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } + if (strcmp(cmd, "createbbt") == 0) { + struct nand_chip *nand_chip = nand->priv; + nand_erase_options_t opts; + + puts("Create BBT and erase everything ? <y/N>\n"); + if (!yes()) { + puts("createbbt aborted\n"); + return -1; + } + memset(&opts, 0, sizeof(opts)); + opts.length = nand->size; + if (nand_erase_opts(nand, &opts)) { + puts("Erase failed\n"); + return 1; + } + nand_chip->options &= ~NAND_DONT_CREATE_BBT; + puts("Creating BBT. Please wait ..."); + if (nand_default_bbt(nand)) { + puts("\nFailed\n"); + return 1; + } + else { + puts("\n"); + return 0; + } + } + usage: printf("Usage:\n%s\n", cmdtp->usage); return 1; @@ -481,7 +530,8 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n"); + "nand unlock [offset] [size] - unlock section\n" + "nand createbbt - create bad block table\n"); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 27d5988..3fdc25a 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -795,7 +795,8 @@ int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate memory (2bit per block) */ - this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) + this->bbt = kmalloc (len, GFP_KERNEL); if (!this->bbt) { printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); return -ENOMEM; -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

5 16

[U-Boot] [PATCH 0/2] edb93xx: two patches for boot code
by Alessandro Rubini 17 Feb '10

17 Feb '10

While working on a board similar to the EDB9315A, I had to fix two more things as my board doesn't boot without them. I already talked with Matthias Kaehlcke who gave me his ack on those patches. Alessandro Rubini (2): ep93xx leds: remove arrays in data section edb93xx sdram: fix initialization board/edb93xx/sdram_cfg.c | 7 ++++++- cpu/arm920t/ep93xx/led.c | 29 +++++++++-------------------- 2 files changed, 15 insertions(+), 21 deletions(-)

3 9

Re: [U-Boot] newbie mailing list (WAS Re: [U-Boot-Users] test program crashing)
by Wolfgang Denk 17 Feb '10

17 Feb '10

Dear Michael Trimarchi, please note that the old list at SourceForge is dead. Don;t use it any more. In message <4B7B95EB.4030008(a)gandalf.sssup.it> you wrote: > What do you think about a mailing list for newbie? So people can ask > there and someone can help them > in the startup. The welcome message can give them all the info to init: What would that help? Nothing. Guess how many people I refer to documents like http://catb.org/esr/faqs/smart-questions.html or http://www.netmeister.org/news/learn2quote.html do actually _read_ this stuff? The problem was not a newbie issue, but ignorance - not bothering to think a second how anybody could provide help based on zero information. I feel 42 is a perfectly reasonable answer to the question :-) Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Experience is what causes a person to make new mistakes instead of old ones.

2 1

[U-Boot] [PATCH 1/2] s5pc1xx: support the GPIO interface
by Minkyu Kang 17 Feb '10

17 Feb '10

This patch adds support the GPIO interface Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- cpu/arm_cortexa8/s5pc1xx/Makefile | 1 + cpu/arm_cortexa8/s5pc1xx/gpio.c | 143 +++++++++++++++++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/gpio.h | 29 +++++++ 3 files changed, 173 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/gpio.c diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 4f922e6..7290c2f 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -33,6 +33,7 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o +COBJS += gpio.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c new file mode 100644 index 0000000..a97244b --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c @@ -0,0 +1,143 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> + +#define CON_MASK(x) (0xf << ((x) << 2)) +#define CON_SFR(x, v) ((v) << ((x) << 2)) + +#define DAT_MASK(x) (0x1 << (x)) +#define DAT_SET(x) (0x1 << (x)) + +#define PULL_MASK(x) (0x3 << ((x) << 1)) +#define PULL_MODE(x, v) ((v) << ((x) << 1)) + +#define DRV_MASK(x) (0x3 << ((x) << 1)) +#define DRV_SET(x, m) ((m) << ((x) << 1)) +#define RATE_MASK(x) (0x1 << (x + 16)) +#define RATE_SET(x) (0x1 << (x + 16)) + +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg) +{ + unsigned int value; + + value = readl(&bank->con); + value &= ~CON_MASK(gpio); + value |= CON_SFR(gpio, cfg); + writel(value, &bank->con); +} + +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + gpio_cfg_pin(bank, gpio, GPIO_OUTPUT); + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + gpio_cfg_pin(bank, gpio, GPIO_INPUT); +} + +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en) +{ + unsigned int value; + + value = readl(&bank->dat); + value &= ~DAT_MASK(gpio); + if (en) + value |= DAT_SET(gpio); + writel(value, &bank->dat); +} + +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio) +{ + unsigned int value; + + value = readl(&bank->dat); + return !!(value & DAT_MASK(gpio)); +} + +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->pull); + value &= ~PULL_MASK(gpio); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~DRV_MASK(gpio); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(gpio, mode); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode) +{ + unsigned int value; + + value = readl(&bank->drv); + value &= ~RATE_MASK(gpio); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(gpio); + break; + default: + return; + } + + writel(value, &bank->drv); +} diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index afbc7ea..8e4bb86 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -124,6 +124,35 @@ struct s5pc110_gpio { struct s5pc1xx_gpio_bank gpio_h2; struct s5pc1xx_gpio_bank gpio_h3; }; + +/* functions */ +void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg); +void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en); +unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio); +void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); +void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode); #endif +/* Pin configurations */ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +#define GPIO_IRQ 0xf +#define GPIO_FUNC(x) (x) + +/* Pull mode */ +#define GPIO_PULL_NONE 0x0 +#define GPIO_PULL_DOWN 0x1 +#define GPIO_PULL_UP 0x2 + +/* Drive Strength level */ +#define GPIO_DRV_1X 0x0 +#define GPIO_DRV_2X 0x1 +#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_4X 0x3 +#define GPIO_DRV_FAST 0x0 +#define GPIO_DRV_SLOW 0x1 + #endif -- 1.5.4.3

2 1

[U-Boot] The ctrlc() does not work when used from post_hotkeys_pressed()
by Michael Zaidman 16 Feb '10

16 Feb '10

Hello, Working on the POST for mpc834x based board I encountered the following problem: The ctrlc() routine does not work when used from post_hotkeys_pressed(). The value of ctrlc_disabled variable defined as static in the console.c file is lost after code relocation. By adding the ctrlc_disabled to global data gd structure the problem was solved. Here is the code changes: common/console.c | 7 +++---- include/asm-ppc/global_data.h | 3 ++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common/console.c b/common/console.c index dc0d13b..101c308 100644 --- a/common/console.c +++ b/common/console.c @@ -400,11 +400,10 @@ void vprintf(const char *fmt, va_list args) } /* test if ctrl-c was pressed */ -static int ctrlc_disabled = 0; /* see disable_ctrl() */ static int ctrlc_was_pressed = 0; int ctrlc(void) { - if (!ctrlc_disabled && gd->have_console) { + if (!gd->ctrlc_disabled && gd->have_console) { if (tstc()) { switch (getc()) { case 0x03: /* ^C - Control C */ @@ -423,9 +422,9 @@ int ctrlc(void) */ int disable_ctrlc(int disable) { - int prev = ctrlc_disabled; /* save previous state */ + int prev = gd->ctrlc_disabled; /* save previous state */ - ctrlc_disabled = disable; + gd->ctrlc_disabled = disable; return prev; } diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 55e7e20..7b333ef 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -132,7 +132,8 @@ typedef struct global_data { #endif unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ - unsigned long have_console; /* serial_init() was called */ + unsigned char have_console; /* serial_init() was called */ + unsigned char ctrlc_disabled; /* Is the <ctrl C> enabled? */ #if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2) unsigned int dp_alloc_base; unsigned int dp_alloc_top; My questions are: 1) I tested this change for ppc branch only. There are a number of boards belonging to other CPU architectures that also use ctrlc() call from within the post_hotkeys_pressed(). However, I am not sure they use POST at all. I went through the list and found only one such board with CONFIG_POST defined. Does anybody has objection that this change will be expanded to other CPU architectures also? 2) I wondered why the have_console variable which gets true/false values only allocates 4 bytes in memory. So I changed it to 1 byte. Thus, adding ctrlc_disabled of one byte size also did not change the global_data structure size. Any thoughts? Should it be delivered as separate patch?

2 5

[U-Boot] The post_list array order change
by Michael Zaidman 16 Feb '10

16 Feb '10

Hi Detlev, In continuation to my post where I explained necessity of user defined post_progress_status facility (see. http://lists.denx.de/pipermail/u-boot/2010-February/067662.html) I am looking now for the best way of causing the diagnostics output interface test to be run first. In my case it is the diagnostics LEDs test. I would like to ask which one of the possibilities is preferable: add the “diagout” test to the head of the post_list array or override the post_list with proprietary one and make changes in the board specific file. Please comment. Thanks, Michael

3 9

[U-Boot] Booting from NAND on MX51
by Andreas Orfanos 16 Feb '10

16 Feb '10

Hi, I am using mx51 3stack Freescale dev board, and I would like to make it boot u-boot from NAND. Does anyone have any local changes that enable that feature? The u-boot works when is downloaded into RAM from Jtag, but can't get it boot from NAND when I write it there. Do I have to develop nand_spl, early stage0 loader? I have also tried to change the following setting on the standard mx51_3stack config but still cannot get it boot from NAND. #undef CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_SYS_NAND_BOOT 1 Does anyone have u-boot booting from NAND on mx51? Any repository, or a patch that might be available? Regards, Andreas ------------------------------------------------------------------------ - /* * Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> * * (C) Copyright 2009 Freescale Semiconductor, Inc. * * Configuration settings for the MX51-3Stack Freescale board. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #ifndef __CONFIG_H #define __CONFIG_H #include <asm/arch/mx51.h> /* High Level Configuration Options */ #define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ #define CONFIG_SYS_APCS_GNU #define CONFIG_L2_OFF #define CONFIG_MXC 1 #define CONFIG_MX51_3DS 1 /* in a mx51 */ #define CONFIG_FLASH_HEADER 1 #define CONFIG_FLASH_HEADER_OFFSET 0x400 #define CONFIG_FLASH_HEADER_BARKER 0xB1 #undef CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_SYS_NAND_BOOT 1 #define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MMU #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define BOARD_LATE_INIT /* * Disabled for now due to build problems under Debian and a significant * increase in the final file size: 144260 vs. 109536 Bytes. */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_REVISION_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 /* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* * Hardware drivers */ #define CONFIG_MX51_UART 1 #define CONFIG_MX51_UART1 1 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /*********************************************************** * Command definition ***********************************************************/ #include <config_cmd_default.h> #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP /* Enable below configure when supporting nand */ #define CONFIG_CMD_NAND #define CONFIG_MXC_NAND #define CONFIG_CMD_ENV #define CMD_SAVEENV #undef CONFIG_CMD_IMLS #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_NET_MULTI #define CONFIG_CMD_MMC /* * MMC Configs */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC 1 #define CONFIG_GENERIC_MMC #define CONFIG_IMX_MMC #define CONFIG_DOS_PARTITION 1 #define CONFIG_CMD_FAT 1 #endif /* * I2C Configs */ #define CONFIG_CMD_I2C 1 #define CONFIG_HARD_I2C 1 #define CONFIG_I2C_MXC 1 #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ethprime=smc911x\0" \ "uboot_addr=0xa0000000\0" \ "uboot=u-boot.bin\0" \ "kernel=uImage\0" \ "nfsroot=/opt/eldk/arm\0" \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_nfs; " \ "tftpboot ${loadaddr} ${kernel}; bootm\0" \ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ "protect off ${uboot_addr} 0xa003ffff; " \ "erase ${uboot_addr} 0xa003ffff; " \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ "setenv filesize; saveenv\0" /*Support LAN9217*/ #define CONFIG_SMC911X 1 #define CONFIG_SMC911X_16_BIT 1 #define CONFIG_SMC911X_BASE mx51_io_base_addr /* * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A * controller inverted. The controller is capable of detecting and correcting * this, but it needs 4 network packets for that. Which means, at startup, you * will not receive answers to the first 4 packest, unless there have been some * broadcasts on the network, or your board is on a hub. Reducing the ARP * timeout from default 5 seconds to 200ms we speed up the initial TFTP * transfer, should the user wish one, significantly. */ #define CONFIG_ARP_TIMEOUT 200UL /* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "MX51 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 /*---------------------------------------------------------------------- - * Stack sizes * * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ /*---------------------------------------------------------------------- - * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR /* TO1 boards */ /* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) /*---------------------------------------------------------------------- - * FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH /*---------------------------------------------------------------------- - * NAND FLASH driver setup */ #define NAND_MAX_CHIPS 8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */ /* Monitor at beginning of flash */ #define CONFIG_FSL_ENV_IN_NAND /* #define CONFIG_FSL_ENV_IN_NAND */ #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #if defined(CONFIG_FSL_ENV_IN_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x100000 #elif defined(CONFIG_FSL_ENV_IN_MMC) #define CONFIG_ENV_IS_IN_MMC 1 #define CONFIG_ENV_OFFSET (768 * 1024) #else #define CONFIG_ENV_IS_NOWHERE 1 #endif /* * JFFS2 partitions */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nand0" #endif /* __CONFIG_H */

5 11

[U-Boot] (no subject)
by The uknl 16 Feb '10

16 Feb '10

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1 0

[U-Boot] (no subject)
by SHELL INTERNATIONAL LOTTERY 15 Feb '10

15 Feb '10

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1 0

[U-Boot] [PATCH] tsec.c bug: Every key typing in netconsole prints the Eth link mode
by Michael Zaidman 15 Feb '10

15 Feb '10

The problem description: The Ethernet link operation mode printing (such as "Speed: 1000, full duplex") accomplishes every key typing when communicating via netconsole to the mpc834x based board. The string is printed by adjust_link() routine of tsec.c, which in turn is part of the eth_init routine called at every netloop entry. The solution: Do not print the string when compiled with CONFIG_NETCONSOLE and stdin or stdout is set to "nc" Signed-off-by: Michael Zaidman <michael.zaidman(a)gmail.com> --- drivers/net/tsec.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3f74118..87093e6 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -847,10 +847,12 @@ static void adjust_link(struct eth_device *dev) printf("%s: Speed was bad\n", dev->name); break; } - - printf("Speed: %d, %s duplex\n", priv->speed, - (priv->duplexity) ? "full" : "half"); - +#ifdef CONFIG_NETCONSOLE + if ((strcmp(getenv("stdin"),"nc") != 0) && + (strcmp(getenv("stdout"),"nc") != 0)) +#endif + printf("Speed: %d, %s duplex\n", priv->speed, + (priv->duplexity) ? "full" : "half"); } else { printf("%s: No link.\n", dev->name); } -- 1.6.3.3

1 1

[U-Boot] [PATCH 2/4 v4] arm: add support for the suen3 board from keymile
by Heiko Schocher 15 Feb '10

15 Feb '10

This patch adds support for the Keymile suen3 board which is based on the Marvell Kirkwood (88F6281) SoC. As this is a variant of the mgcoge2_arm_p1a board, this board also uses common code stored in board/keymile/km_arm/km_arm.c Signed-off-by: Heiko Schocher <hs(a)denx.de> --- - changes since v1: added comments from Wolfgang Denk: get rid of flash_info_t define in board config (to get this working patch 1/2 is introduced/needed) - changes since v2: added comments from Wolfgang Denk - rearranged if/else in do_spi_toggle() - added I/O accessor functions for bootcounter - changes since v3: added comment Scott Wood - removed nand_init in do_spi_toggle() added comments from Prafulla Wadagaskar - km-arm.h renamed to km_arm.h - reworked eeprom_write_enable() (deleted it) (when reviewing this function, it cropped up, that this pin is connected through a gpio pin, not as in previous version, through the boco (a FPGA)) - moved set_sda(), set_scl(), get_sda(), get_scl() to km_arm.c - split patch in 4 patches (for each board an extra patch) - renamed sdramregs.txt in kwbimage.cfg, also license info added. MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + include/configs/suen3.h | 103 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 108 insertions(+), 0 deletions(-) create mode 100644 include/configs/suen3.h diff --git a/MAINTAINERS b/MAINTAINERS index eda15c8..ab27afc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -411,6 +411,7 @@ Heiko Schocher <hs(a)denx.de> muas3001 MPC8270 municse MPC5200 sc3 PPC405GP + suen3 ARM926EJS (Kirkwood SoC) uc101 MPC5200 diff --git a/MAKEALL b/MAKEALL index 1c18734..7577ea5 100755 --- a/MAKEALL +++ b/MAKEALL @@ -580,6 +580,7 @@ LIST_ARM9=" \ spear310 \ spear320 \ spear600 \ + suen3 \ trab \ VCMA9 \ versatile \ diff --git a/Makefile b/Makefile index 990f932..3ea2b53 100644 --- a/Makefile +++ b/Makefile @@ -3050,6 +3050,9 @@ spear320_config : unconfig spear600_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear +suen3_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/include/configs/suen3.h b/include/configs/suen3.h new file mode 100644 index 0000000..b2730a3 --- /dev/null +++ b/include/configs/suen3.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * for linking errors see + * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html + */ + +#ifndef _CONFIG_SUEN3_H +#define _CONFIG_SUEN3_H + +/* include common defines/options for all arm based Keymile boards */ +#include "km_arm.h" + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKeymile SUEN3" + +#define CONFIG_HOSTNAME suen3 + +/* + * Environment variables configurations + */ +#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ +#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 +#define CONFIG_ENV_EEPROM_IS_ON_I2C 1 +#define CONFIG_SYS_EEPROM_WREN 1 +#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) +#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + +/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_KIRKWOOD_SPI +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */ + +#define FLASH_GPIO_PIN 0x00010000 + +#define MTDIDS_DEFAULT "nand0=orion_nand" +/* test-only: partitioning needs some tuning, this is just for tests */ +#define MTDPARTS_DEFAULT "mtdparts=" \ + "orion_nand:" \ + "-(" CONFIG_KM_UBI_PARTITION_NAME ")" + +#define CONFIG_KM_DEF_ENV_UPDATE \ + "update=" \ + "spi on;sf probe 0;sf erase 0 50000;" \ + "sf write ${u-boot_addr_r} 0 ${filesize};" \ + "spi off\0" + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_DEF_ENV \ + "memsize=0x8000000\0" \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + "rootpath=/opt/eldk/arm\0" \ + "EEprom_ivm=pca9544a:70:9\0" \ + "" + +#endif /* _CONFIG_SUEN3_H */ -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 2

[U-Boot] [PATCH 5/9 V3] convert common files to new SoC access
by Jens Scharsig 14 Feb '10

14 Feb '10

* convert common files in cpu/../at91 and a lot of drivers to use c stucture SoC access * add's a warning to all files, which need update to new SoC access Signed-off-by: Jens Scharsig <js_at_ng(a)scharsoft.de> --- cpu/arm926ejs/at91/at91cap9_devices.c | 4 + cpu/arm926ejs/at91/at91sam9261_devices.c | 4 + cpu/arm926ejs/at91/at91sam9263_devices.c | 33 ++++++-- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 4 + cpu/arm926ejs/at91/at91sam9rl_devices.c | 4 + cpu/arm926ejs/at91/clock.c | 51 +++++++------ cpu/arm926ejs/at91/cpu.c | 4 + cpu/arm926ejs/at91/led.c | 7 ++ cpu/arm926ejs/at91/lowlevel_init.S | 110 +++++++++++++++------------ cpu/arm926ejs/at91/reset.c | 8 +- cpu/arm926ejs/at91/timer.c | 17 +++-- drivers/i2c/soft_i2c.c | 11 ++- drivers/serial/at91rm9200_usart.c | 8 ++ drivers/serial/atmel_usart.c | 4 + drivers/spi/atmel_dataflash_spi.c | 4 + drivers/usb/host/ohci-at91.c | 5 + drivers/video/bus_vcxk.c | 22 +++++- include/i2c.h | 5 + 18 files changed, 209 insertions(+), 96 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index c41e139..0f8086d 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -27,6 +27,10 @@ */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 9112ccb..172845a 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -23,6 +23,10 @@ */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index eb56ebf..05a5ab5 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -27,37 +27,46 @@ */ #include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/arch/at91_pio.h> void at91_serial0_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(A, 26), 1); /* TXD0 */ at91_set_a_periph(AT91_PORTPIN(A, 27), 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); + writel(1 << AT91SAM9263_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(D, 0), 1); /* TXD1 */ at91_set_a_periph(AT91_PORTPIN(D, 1), 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); + writel(1 << AT91SAM9263_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(D, 2), 1); /* TXD2 */ at91_set_a_periph(AT91_PORTPIN(D, 3), 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); + writel(1 << AT91SAM9263_ID_US2, &pmc->pcer); } void at91_serial3_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(C, 30), 0); /* DRXD */ at91_set_a_periph(AT91_PORTPIN(C, 31), 1); /* DTXD */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -82,12 +91,14 @@ void at91_serial_hw_init(void) #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_b_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */ at91_set_b_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */ at91_set_b_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0); + writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_b_periph(AT91_PORTPIN(A, 5), 1); @@ -117,12 +128,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(B, 12), 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PORTPIN(B, 13), 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PORTPIN(B, 14), 0); /* SPI1_SPCK */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1); + writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PORTPIN(B, 15), 1); @@ -190,10 +203,12 @@ void at91_uhp_hw_init(void) #ifdef CONFIG_AT91_CAN void at91_can_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_set_a_periph(AT91_PORTPIN(A, 13), 0); /* CAN_TX */ at91_set_a_periph(AT91_PORTPIN(A, 14), 1); /* CAN_RX */ /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); + writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer); } #endif diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index c3a2102..55b9b5a 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -23,6 +23,10 @@ */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index 9c5624a..946bdc5 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -23,6 +23,10 @@ */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 574f488..7e03907 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -13,9 +13,9 @@ #include <config.h> #include <asm/arch/hardware.h> +#include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> static unsigned long cpu_clk_rate_hz; static unsigned long main_clk_rate_hz; @@ -57,14 +57,14 @@ u32 get_pllb_init(void) static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { - case AT91_PMC_CSS_SLOW: - return AT91_SLOW_CLOCK; - case AT91_PMC_CSS_MAIN: - return main_clk_rate_hz; - case AT91_PMC_CSS_PLLA: - return plla_rate_hz; - case AT91_PMC_CSS_PLLB: - return pllb_rate_hz; + case AT91_PMC_MCKR_CSS_SLOW: + return AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return pllb_rate_hz; } return 0; @@ -146,6 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg) int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; #ifndef AT91_MAIN_CLOCK unsigned tmp; /* @@ -164,7 +165,7 @@ int at91_clock_init(unsigned long main_clock) main_clk_rate_hz = main_clock; /* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); #ifdef CONFIG_USB_ATMEL /* @@ -174,7 +175,7 @@ int at91_clock_init(unsigned long main_clock) * REVISIT: assumes MCK doesn't derive from PLLB! */ at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_USB96M; + AT91_PMC_PLLBR_USBDIV_2; pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); #endif @@ -182,28 +183,32 @@ int at91_clock_init(unsigned long main_clock) * MCK and CPU derive from one of those primary clocks. * For now, assume this parentage won't change. */ - mckr = at91_sys_read(AT91_PMC_MCKR); + mckr = readl(&pmc->mckr); #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* plla divisor by 2 */ plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif - freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = mck_rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* mdiv */ + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #elif defined(CONFIG_AT91SAM9G20) - mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? - freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3 + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #endif cpu_clk_rate_hz = freq; - return 0; + return 0; } diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..993b299 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -22,6 +22,10 @@ */ #include <common.h> +#ifdef CONFIG_AT91_LEGACY +#warning Your board is using legacy SoC access. Please update! +#endif + #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c index be68f59..0a0bb57 100644 --- a/cpu/arm926ejs/at91/led.c +++ b/cpu/arm926ejs/at91/led.c @@ -23,7 +23,14 @@ */ #include <common.h> +/* +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif +*/ #include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S index f11ebc6..869b581 100644 --- a/cpu/arm926ejs/at91/lowlevel_init.S +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -27,15 +27,20 @@ */ #include <config.h> -#include <version.h> #include <asm/arch/hardware.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_wdt.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_matrix.h> #include <asm/arch/at91sam9_sdramc.h> #include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_rstc.h> +#ifdef CONFIG_AT91_LEGACY +#include <asm/arch/at91sam9_matrix.h> +#endif +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#endif _TEXT_BASE: .word TEXT_BASE @@ -75,7 +80,7 @@ POS1: * - Check if the PLL is already initialized * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) ldr r0, [r1] and r0, r0, #3 cmp r0, #0 @@ -85,18 +90,18 @@ POS1: * - Enable the Main Oscillator * --------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r1, =(AT91_ASM_PMC_MOR) + ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS + mov r4, #AT91_PMC_IxR_MOSCS MOSCS_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS + cmp r3, #AT91_PMC_IxR_MOSCS bne MOSCS_Loop /* ---------------------------------------------------------------------------- @@ -105,56 +110,71 @@ MOSCS_Loop: * Setup PLLA * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r1, =(AT91_ASM_PMC_PLLAR) ldr r0, =CONFIG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA + mov r4, #AT91_PMC_IxR_LOCKA MOSCS_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA + cmp r3, #AT91_PMC_IxR_LOCKA bne MOSCS_Loop1 +#ifdef CONFIG_SYS_PLLBR_VAL + ldr r1, =(AT91_ASM_PMC_PLLBR) + ldr r0, =CONFIG_SYS_PLLBR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLB is locked */ + mov r4, #AT91_PMC_IxR_LOCKB +PLLB_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IxR_LOCKB + bne PLLB_Loop +#endif + /* ---------------------------------------------------------------------------- * PMC Init Step 3. * ---------------------------------------------------------------------------- * - Switch on the Main Oscillator * ---------------------------------------------------------------------------- */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ ldr r0, =CONFIG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IxR_MCKRDY MCKRDY_Loop: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IxR_MCKRDY bne MCKRDY_Loop ldr r0, =CONFIG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY + mov r4, #AT91_PMC_IxR_MCKRDY MCKRDY_Loop1: ldr r3, [r2] and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY + cmp r3, #AT91_PMC_IxR_MCKRDY bne MCKRDY_Loop1 - PLL_setup_end: /* ---------------------------------------------------------------------------- * - memory control configuration 2 * ---------------------------------------------------------------------------- */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + + ldr r0, =(AT91_ASM_SDRAMC_TR) + ldr r1, [r0] cmp r1, #0 bne SDRAM_setup_end @@ -183,60 +203,53 @@ SDRAM_setup_end: .ltorg SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) + .word AT91_ASM_WDT_MR .word CONFIG_SYS_WDTC_WDMR_VAL - /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word AT91_ASM_PIOD_PDR .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word AT91_ASM_PIOD_PUDR .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word AT91_ASM_PIOD_ASR .word CONFIG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word AT91_ASM_PIOC_PDR .word CONFIG_SYS_PIOC_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word AT91_ASM_PIOC_PUDR .word CONFIG_SYS_PIOC_PPUDR_VAL #endif - -#if defined(AT91_MATRIX_EBI0CSA) - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL -#else /* AT91_MATRIX_EBICSA */ - .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word AT91_ASM_MATRIX_CSA0 .word CONFIG_SYS_MATRIX_EBICSA_VAL -#endif /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word AT91_ASM_SMC_MODE0 .word CONFIG_SYS_SMC0_MODE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word AT91_ASM_SMC_CYCLE0 .word CONFIG_SYS_SMC0_CYCLE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word AT91_ASM_SMC_PULSE0 .word CONFIG_SYS_SMC0_PULSE0_VAL - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word AT91_ASM_SMC_SETUP0 .word CONFIG_SYS_SMC0_SETUP0_VAL SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word AT91_ASM_SDRAMC_CR .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word AT91_ASM_SDRAMC_MDR .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL2 @@ -254,26 +267,25 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL8 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 .word AT91_SDRAM_BASE .word CONFIG_SYS_SDRAM_VAL12 /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word AT91_ASM_MATRIX_MCFG .word 0x1FF #endif - SMRDATA2: .word 0 diff --git a/cpu/arm926ejs/at91/reset.c b/cpu/arm926ejs/at91/reset.c index f963e14..1b67e77 100644 --- a/cpu/arm926ejs/at91/reset.c +++ b/cpu/arm926ejs/at91/reset.c @@ -32,10 +32,12 @@ */ void reset_cpu(ulong ignored) { + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; + /* this is the way Linux does it */ - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | - AT91_RSTC_PROCRST | - AT91_RSTC_PERRST); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | AT91_RSTC_CR_PERRST, + &rstc->cr); while (1); /* Never reached */ diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c index 7352b5c..d21eebf 100644 --- a/cpu/arm926ejs/at91/timer.c +++ b/cpu/arm926ejs/at91/timer.c @@ -35,8 +35,6 @@ * setting the 20 bit counter period to its maximum (0xfffff). */ #define TIMER_LOAD_VAL 0xfffff -#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR) -#define READ_TIMER at91_sys_read(AT91_PIT_PIIR) static ulong timestamp; static ulong lastinc; @@ -61,14 +59,16 @@ static inline unsigned long long usec_to_tick(unsigned long long usec) /* nothing really to do with interrupts, just starts up a counter. */ int timer_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; /* * Enable PITC Clock * The clock is already enabled for system controller in boot */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + writel(1 << AT91_ID_SYS, &pmc->pcer); /* Enable PITC */ - at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN); + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); reset_timer_masked(); @@ -82,7 +82,9 @@ int timer_init(void) */ unsigned long long get_ticks(void) { - ulong now = READ_TIMER; + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + ulong now = readl(&pit->piir); if (now >= lastinc) /* normal mode (non roll) */ /* move stamp forward with absolut diff ticks */ @@ -96,7 +98,10 @@ unsigned long long get_ticks(void) void reset_timer_masked(void) { /* reset time */ - lastinc = READ_TIMER; /* capture current incrementer value time */ + at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE; + + /* capture current incrementer value time */ + lastinc = readl(&pit->piir); timestamp = 0; /* start "advancing" time stamp from 0 */ } diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 9a48783..e0cf1e1 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -30,14 +30,15 @@ #include <ioports.h> #include <asm/io.h> #endif -#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ +#if defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263) #include <asm/io.h> #include <asm/arch/hardware.h> -#endif -#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ -#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#ifdef CONFIG_AT91_LEGACY #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#endif #endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> diff --git a/drivers/serial/at91rm9200_usart.c b/drivers/serial/at91rm9200_usart.c index 858bde9..05ebbc3 100644 --- a/drivers/serial/at91rm9200_usart.c +++ b/drivers/serial/at91rm9200_usart.c @@ -30,8 +30,16 @@ */ #include <common.h> + +#ifndef CONFIG_AT91_LEGACY #include <asm/io.h> #include <asm/arch/hardware.h> +#define CONFIG_AT91_LEGACY +#include <asm/arch-at91rm9200/AT91RM9200.h> +#warning Please update to use C structur SoC access ! +#else +#include <asm/arch/AT91RM9200.h> +#endif DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f50552a..cad3412 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -16,6 +16,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <watchdog.h> #include <asm/io.h> diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 3a648e6..4a5c4aa 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -20,6 +20,10 @@ */ #include <common.h> +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif #include <asm/arch/hardware.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 226859a..29f3ba1 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -25,6 +25,11 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) +#ifndef CONFIG_AT91_LEGACY +#define CONFIG_AT91_LEGACY +#warning Please update to use C structur SoC access ! +#endif + #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c index 7726bb3..67a59a7 100644 --- a/drivers/video/bus_vcxk.c +++ b/drivers/video/bus_vcxk.c @@ -31,9 +31,29 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #ifdef CONFIG_AT91RM9200 #include <asm/arch/hardware.h> + #include <asm/arch/at91_pio.h> + #ifndef VCBITMASK #define VCBITMASK(bitno) (0x0001 << (bitno % 16)) #endif +#ifndef CONFIG_AT91_LEGACY +at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; +#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ + do { \ + writel(PIN, &pio->PORT.per); \ + writel(PIN, &pio->PORT.DDR); \ + writel(PIN, &pio->PORT.mddr); \ + if (!I0O1) \ + writel(PIN, &pio->PORT.puer); \ + } while (0); + +#define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); +#define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); + +#define VCXK_ACKNOWLEDGE \ + (!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \ + CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) +#else #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ ((AT91PS_PIO) PORT)->PIO_PER = PIN; \ ((AT91PS_PIO) PORT)->DDR = PIN; \ @@ -46,7 +66,7 @@ vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE)); #define VCXK_ACKNOWLEDGE \ (!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\ PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN)) - +#endif #elif defined(CONFIG_MCF52x2) #include <asm/m5282.h> #ifndef VCBITMASK diff --git a/include/i2c.h b/include/i2c.h index b754769..31088b6 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -74,6 +74,11 @@ # define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); # elif defined(CONFIG_8xx) # define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + +# elif (defined(CONFIG_AT91RM9200) || \ + defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ + defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; # else # define I2C_SOFT_DECLARATIONS # endif

3 8

[U-Boot] Instant Online Loan Grant
by Private Loans & Money Lender 14 Feb '10

14 Feb '10

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1 0

[U-Boot] [PATCH ARM 3/3 v3] change s3c24x0 register struct members to lower case
by Kevin Morfitt 13 Feb '10

13 Feb '10

Changes the names of the s3c24x0 register struct members from upper-case to lower-case. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- v2 changes - re-number to be 3/3 v3 changes - re-based to modified patch 2/3 checkpatch.pl reports no errors. MAKEALL ARM9 reports no new warnings or errors. board/mpl/vcma9/vcma9.c | 42 ++-- board/mpl/vcma9/vcma9.h | 20 +- board/samsung/smdk2400/smdk2400.c | 29 +- board/samsung/smdk2410/smdk2410.c | 38 ++- board/sbc2410x/sbc2410x.c | 46 ++-- board/trab/auto_update.c | 1 + board/trab/cmd_trab.c | 36 ++- board/trab/rs485.c | 44 ++- board/trab/trab.c | 71 ++-- board/trab/trab_fkt.c | 159 +++++---- board/trab/tsc2000.c | 38 +- board/trab/tsc2000.h | 112 ++++--- board/trab/vfd.c | 89 +++--- cpu/arm920t/s3c24x0/interrupts.c | 3 +- cpu/arm920t/s3c24x0/speed.c | 8 +- cpu/arm920t/s3c24x0/timer.c | 18 +- cpu/arm920t/s3c24x0/usb.c | 11 +- cpu/arm920t/s3c24x0/usb_ohci.c | 15 +- drivers/i2c/s3c24x0_i2c.c | 102 +++--- drivers/mtd/nand/s3c2410_nand.c | 24 +- drivers/rtc/s3c24x0_rtc.c | 52 ++-- drivers/serial/serial_s3c24x0.c | 26 +- include/asm-arm/arch-s3c24x0/s3c24x0.h | 578 ++++++++++++++++---------------- 23 files changed, 819 insertions(+), 743 deletions(-) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index afaa568..5464798 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -30,6 +30,7 @@ #include <asm/arch/s3c24x0_cpu.h> #include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> #include "vcma9.h" #include "../common/common_util.h" @@ -78,43 +79,44 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x002AAAAA; - gpio->GPBUP = 0x000002BF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x000037F7; - gpio->GPFCON = 0x00000000; - gpio->GPFUP = 0x00000000; - gpio->GPGCON = 0xFFEAFF5A; - gpio->GPGUP = 0x0000F0DC; - gpio->GPHCON = 0x0028AAAA; - gpio->GPHUP = 0x00000656; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); /* setup correct IRQ modes for NIC */ /* rising edge mode */ - gpio->EXTINT2 = (gpio->EXTINT2 & ~(7 << 8)) | (4 << 8); + writel((readl(&gpio->extint2) & ~(7 << 8)) | (4 << 8), &gpio->extint2); /* select USB port 2 to be host or device (fix to host for now) */ - gpio->MISCCR |= 0x08; + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); /* init serial */ gd->baudrate = CONFIG_BAUDRATE; diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 51dc050..2992b72 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -41,14 +41,14 @@ inline void nf_conf(u16 conf) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCONF = conf; + writel(conf, &nand->nfconf); } inline void nf_cmd(u8 cmd) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCMD = cmd; + writel(cmd, &nand->nfcmd); } inline void nf_cmd_w(u8 cmd) @@ -61,7 +61,7 @@ inline void nf_addr(u8 addr) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFADDR = addr; + writel(addr, &nand->nfaddr); } inline void nf_set_ce(enum nfce_state s) @@ -70,10 +70,10 @@ inline void nf_set_ce(enum nfce_state s) switch (s) { case nfce_low: - nand->NFCONF &= ~(1 << 11); + writel(readl(&nand->nfconf) & ~(1 << 11), &nand->nfconf); break; case nfce_high: - nand->NFCONF |= (1 << 11); + writel(readl(&nand->nfconf) | (1 << 11), &nand->nfconf); break; } } @@ -82,7 +82,7 @@ inline void nf_wait_rb(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - while (!(nand->NFSTAT & (1 << 0))) + while (!(readl(&nand->nfstat) & (1 << 0))) /* Wait */; } @@ -90,28 +90,28 @@ inline void nf_write(u8 data) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFDATA = data; + writel(data, &nand->nfdata); } inline u8 nf_read(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - return (nand->NFDATA); + return readl(&nand->nfdata); } inline void nf_init_ecc(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCONF |= (1 << 12); + writel(readl(&nand->nfconf) | (1 << 12), &nand->nfconf); } inline u32 nf_read_ecc(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - return (nand->NFECC); + return readl(&nand->nfecc); } #endif diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index c2ce2ca..74ca08b 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,30 +48,30 @@ int board_init(void) /* memory and cpu-speed are setup before relocation */ /* change the clock to be 50 MHz 1:1:1 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - gpio->PECON = 0x0; - gpio->PEUP = 0x0; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); + writel(0x0, &gpio->pecon); + writel(0x0, &gpio->peup); #ifdef CONFIG_HWFLOW /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0xa22; + writel(0xa22, &gpio->pfcon); /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->PFUP = 0x35; + writel(0x35, &gpio->pfup); #else /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0x22; + writel(0x22, &gpio->pfcon); /* Disable pull-up on Rx and Tx pins */ - gpio->PFUP = 0x5; + writel(0x5, &gpio->pfup); #endif /* CONFIG_HWFLOW */ - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr); /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index e3a4490..7b64408 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -72,36 +73,37 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044555; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FFBA; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x002AFAAA; - gpio->GPHUP = 0x000007FF; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044555, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FFBA, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x002AFAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 52007a7..ae959bc 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -31,6 +31,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand.h> @@ -80,40 +81,41 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044556; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FF3A; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x0016FAAA; - gpio->GPHUP = 0x000007FF; - - gpio->EXTINT0 = 0x22222222; - gpio->EXTINT1 = 0x22222222; - gpio->EXTINT2 = 0x22222222; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044556, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FF3A, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x0016FAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); + + writel(0x22222222, &gpio->extint0); + writel(0x22222222, &gpio->extint1); + writel(0x22222222, &gpio->extint2); /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 4f30c23..27507ec 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -31,6 +31,7 @@ #include <i2c.h> #include <flash.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "trab.h" diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index 2c31d50..5d686fe 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -26,6 +26,7 @@ #include <common.h> #include <command.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <rtc.h> #include <i2c.h> #include "tsc2000.h" @@ -604,28 +605,33 @@ static int adc_read(unsigned int channel) adc_init(); - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; } - result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -642,8 +648,10 @@ static void adc_init(void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon); /* * Wait some time to avoid problem with very first call of @@ -664,10 +672,10 @@ static void led_set(unsigned int state) switch (state) { case 0: /* turn LED off */ - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); break; case 1: /* turn LED on */ - gpio->PADAT &= ~(1 << 12); + writel(readl(&gpio->padat) & ~(1 << 12), &gpio->padat); break; default: break; @@ -693,8 +701,8 @@ static void led_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPA12 as output and set to High -> LED off */ - gpio->PACON &= ~(1 << 12); - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->pacon) & ~(1 << 12), &gpio->pacon); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); } static void sdelay(unsigned long seconds) diff --git a/board/trab/rs485.c b/board/trab/rs485.c index 79f8cc4..794b197 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "rs485.h" static void rs485_setbrg(void); @@ -51,16 +52,16 @@ static void rs485_setbrg(void) reg = (33000000 / (16 * 38400)) - 1; /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - uart->UCON = 0x245; - uart->UBRDIV = reg; + writel(0x245, &uart->ucon); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) ; @@ -70,16 +71,21 @@ static void rs485_cfgio(void) { struct s3c24x0_gpio *const gpio = s3c24x0_get_base_gpio(); - gpio->PFCON &= ~(0x3 << 2); - gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) & ~(0x3 << 2), &gpio->pfcon); + /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 2), &gpio->pfcon); - gpio->PFCON &= ~(0x3 << 6); - gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) &= ~(0x3 << 6), &gpio->pfcon); + /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 6), &gpio->pfcon); - gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ - gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ + /* disable pullup on GPF1 */ + writel(readl(&gpio->pfup) | (1 << 1), &gpio->pfup); + /* disable pullup on GPF3 */ + writel(readl(&gpio->pfup) | (1 << 3), &gpio->pfup); - gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ + /* set GPA11 (RS485_DE) to output */ + writel(readl(&gpio->pacon) & ~(1 << 11), &gpio->pacon); } /* @@ -104,10 +110,10 @@ int rs485_getc(void) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - while (!(uart->UTRSTAT & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */; - return uart->URXH & 0xff; + return readl(&uart->urxh) & 0xff; } /* @@ -117,10 +123,10 @@ void rs485_putc(const char c) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - while (!(uart->UTRSTAT & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */; - uart->UTXH = c; + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -134,7 +140,7 @@ int rs485_tstc(void) { struct s3c24x0_uart *const uart = s3c24x0_get_base_uart(UART_NR); - return uart->UTRSTAT & 0x1; + return readl(&uart->utrstat) & 0x1; } void rs485_puts(const char *s) @@ -171,9 +177,9 @@ static void set_rs485de(unsigned char rs485de_state) /* This is on PORT A bit 11 */ if (rs485de_state) - gpio->PADAT |= (1 << 11); + writel(readl(&gpio->padat) | (1 << 11), &gpio->padat); else - gpio->PADAT &= ~(1 << 11); + writel(readl(&gpio->padat) & ~(1 << 11), &gpio->padat); } void trab_rs485_enable_tx(void) diff --git a/board/trab/trab.c b/board/trab/trab.c index f0b320e..16d29dd 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <malloc.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <command.h> #include "trab.h" @@ -74,38 +75,38 @@ int board_init() #ifdef CONFIG_TRAB_50MHZ /* change the clock to be 50 MHz 1:1:1 */ /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); #else /* change the clock to be 133 MHz 1:2:4 */ /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->MPLLCON = 0x7d041; - clk_power->CLKDIVN = 3; + writel(0x7d041, &clk_power->mpllcon); + writel(3, &clk_power->clkdivn); #endif /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->PFCON = (2 << 0) | (2 << 2) | (2 << 4) | - (2 << 6) | (2 << 8) | (2 << 10); + writel((2 << 0) | (2 << 2) | (2 << 4) | (2 << 6) | (2 << 8) | (2 << 10), + &gpio->pfcon); #ifdef CONFIG_HWFLOW /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | - (1 << 3) | (1 << 4) | (1 << 5); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5), + &gpio->pfup); #else /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), &gpio->pfup); #endif - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr); /* suppress flicker of the VFDs */ - gpio->MISCCR = 0x40; - gpio->PFCON |= (2 << 12); + writel(0x40, gpio->misccr); + writel(readl(&gpio->pfcon) | (2 << 12), &gpio->pfcon); gd->bd->bi_arch_number = MACH_TYPE_TRAB; @@ -113,8 +114,8 @@ int board_init() gd->bd->bi_boot_params = 0x0c000100; /* Make sure both buzzers are turned off */ - gpio->PDCON |= 0x5400; - gpio->PDDAT &= ~0xE0; + writel(readl(&gpio->pdcon) | 0x5400, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0xE0, &gpio->pddat); #ifdef CONFIG_VFD vfd_init_clocks(); @@ -131,7 +132,7 @@ int board_init() #ifdef CONFIG_DRIVER_S3C24X0_I2C /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; + writel((readl(&gpio->pgcon) & 0x003c00) | 0x003c00, &gpio->pgcon); #endif /* CONFIG_DRIVER_S3C24X0_I2C */ return 0; @@ -328,14 +329,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); } static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); } static void spi_init(void) @@ -345,23 +346,23 @@ static void spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon); CLR_CS_TOUCH(); /* Baudrate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon); /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); wait_transmit_done(); } @@ -369,7 +370,7 @@ static void wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; } @@ -384,13 +385,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg, command |= (page << 11); command |= (reg << 5); - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writel((data & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writel(data & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done(); CLR_CS_TOUCH(); diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 760db67..38603d7 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -27,6 +27,7 @@ #include <exports.h> #include <timestamp.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "rs485.h" @@ -376,28 +377,33 @@ static int adc_read(unsigned int channel) padc = s3c2400_get_base_adc(); channel &= 0x7; - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; } - result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -414,8 +420,10 @@ static void adc_init(void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon); /* * Wait some time to avoid problem with very first call of @@ -456,10 +464,10 @@ int do_power_switch(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPE7 as input */ - gpio->PECON &= ~(0x3 << (2 * 7)); + writel(readl(&gpio->pecon) & ~(0x3 << (2 * 7)), &gpio->pecon); /* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; + result = ((readl(&gpio->pedat) & (1 << 7)) == (1 << 7)) ? 0 : 1; print_identifier(); printf("%d\n", result); @@ -522,20 +530,20 @@ int do_vfd_id(void) /* try to red vfd board id from the value defined by pull-ups */ - pcup_old = gpio->PCUP; - pccon_old = gpio->PCCON; + pcup_old = readl(&gpio->pcup); + pccon_old = readl(&gpio->pccon); /* activate GPC0...GPC3 pull-ups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon); udelay(10); /* allow signals to settle */ /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F; - gpio->PCCON = pccon_old; - gpio->PCUP = pcup_old; + writel(pccon_old, &gpio->pccon); + writel(pcup_old, &gpio->pcup); /* print vfd_board_id to console */ print_identifier(); @@ -557,40 +565,42 @@ int do_buzzer(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* set divider for timer 2 */ - timers->TCFG1 &= ~0xF00; - timers->TCFG1 |= 0x300; + writel(readl(&timers->tcfg1) & ~0xF00, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x300, &timers->tcfg1); /* set frequency */ counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].TCNTB = counter; - timers->ch[2].TCMPB = counter / 2; + writel(counter, &timers->ch[2].tcntb); + writel(counter / 2, &timers->ch[2].tcmpb); if (strcmp(argv[2], "on") == 0) { debug("%s: frequency: %d\n", __FUNCTION__, BUZZER_FREQ); /* configure pin GPD7 as TOUT2 */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x8000; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x8000, &gpio->pdcon); /* start */ - timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & - ~INVERT2; - timers->TCON = (timers->TCON | START2) & ~UPDATE2; + writel((readl(&timers->tcon) | UPDATE2 | RELOAD2) & ~INVERT2, + &timers->tcon); + writel((readl(&timers->tcon) | START2) & ~UPDATE2, + &timers->tcon); return 0; } else if (strcmp(argv[2], "off") == 0) { /* stop */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon); /* configure GPD7 as output and set to low */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x4000; - gpio->PDDAT &= ~0x80; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x4000, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0x80, &gpio->pddat); return 0; } @@ -603,12 +613,12 @@ int do_led(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PC14 and PC15 as output */ - gpio->PCCON &= ~(0xF << 28); - gpio->PCCON |= (0x5 << 28); + writel(readl(&gpio->pccon) & ~(0xF << 28), &gpio->pccon); + writel(readl(&gpio->pccon) | (0x5 << 28), &gpio->pccon); /* configure PD0 and PD4 as output */ - gpio->PDCON &= ~((0x3 << 8) | 0x3); - gpio->PDCON |= ((0x1 << 8) | 0x1); + writel(readl(&gpio->pdcon) & ~((0x3 << 8) | 0x3), &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 8) | 0x1), &gpio->pdcon); switch (simple_strtoul(argv[2], NULL, 10)) { case 0: @@ -616,27 +626,27 @@ int do_led(char **argv) break; case 2: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 14); + writel(readl(&gpio->pcdat) | (1 << 14), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 14); + writel(readl(&gpio->pcdat) & ~(1 << 14), &gpio->pcdat); return 0; case 3: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 15); + writel(readl(&gpio->pcdat) | (1 << 15), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 15); + writel(readl(&gpio->pcdat) & ~(1 << 15), &gpio->pcdat); return 0; case 4: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 0); + writel(readl(&gpio->pddat) | (1 << 0), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 0); + writel(readl(&gpio->pddat) & ~(1 << 0), &gpio->pddat); return 0; case 5: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 4); + writel(readl(&gpio->pddat) | (1 << 4), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 4); + writel(readl(&gpio->pddat) & ~(1 << 4), &gpio->pddat); return 0; default: break; @@ -650,22 +660,24 @@ int do_full_bridge(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PD5 and PD6 as output */ - gpio->PDCON &= ~((0x3 << 5 * 2) | (0x3 << 6 * 2)); - gpio->PDCON |= ((0x1 << 5 * 2) | (0x1 << 6 * 2)); + writel(readl(&gpio->pdcon) & ~((0x3 << 5 * 2) | (0x3 << 6 * 2)), + &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 5 * 2) | (0x1 << 6 * 2)), + &gpio->pdcon); if (strcmp(argv[2], "+") == 0) { - gpio->PDDAT |= (1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) | (1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "-") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "off") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT &= ~(1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) & ~(1 << 6), &gpio->pddat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -755,15 +767,15 @@ int do_motor(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* Configure I/O port */ - gpio->PGCON &= ~(0x3 << 0); - gpio->PGCON |= (0x1 << 0); + writel(readl(&gpio->pgcon) & ~(0x3 << 0), &gpio->pgcon); + writel(readl(&gpio->pgcon) | (0x1 << 0), &gpio->pgcon); if (strcmp(argv[2], "on") == 0) { - gpio->PGDAT &= ~(1 << 0); + writel(readl(&gpio->pgdat) & ~(1 << 0), &gpio->pgdat); return 0; } if (strcmp(argv[2], "off") == 0) { - gpio->PGDAT |= (1 << 0); + writel(readl(&gpio->pgdat) | (1 << 0), &gpio->pgdat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -783,36 +795,39 @@ int do_pwm(char **argv) if (strcmp(argv[2], "on") == 0) { /* configure pin GPD8 as TOUT3 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x2 << 8*2); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x2 << 8 * 2), &gpio->pdcon); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* set divider for timer 3 */ - timers->TCFG1 &= ~(0xf << 12); - timers->TCFG1 |= (0x3 << 12); + writel(readl(&timers->tcfg1) & ~(0xF << 12), &timers->tcfg1); + writel(readl(&timers->tcfg1) | (0x3 << 12), &timers->tcfg1); /* set frequency */ counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].TCNTB = counter; - timers->ch[3].TCMPB = counter / 2; + writel(counter, &timers->ch[3].tcntb); + writel(counter / 2, &timers->ch[3].tcmpb); /* start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); return 0; } if (strcmp(argv[2], "off") == 0) { /* stop timer */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon); /* configure pin GPD8 as output and set to 0 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x1 << 8*2); - gpio->PDDAT &= ~(1 << 8); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x1 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pddat) & ~(1 << 8), &gpio->pdcon); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index 2855825..c07b4df 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -50,23 +50,23 @@ void tsc2000_spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon); CLR_CS_TOUCH(); /* Baud-rate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon); /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); } @@ -74,7 +74,7 @@ void spi_wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; } @@ -85,13 +85,13 @@ void tsc2000_write(unsigned short reg, unsigned short data) SET_CS_TOUCH(); command = reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writeb((data & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writeb(data & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); CLR_CS_TOUCH(); @@ -105,19 +105,19 @@ unsigned short tsc2000_read(unsigned short reg) SET_CS_TOUCH(); command = 0x8000 | reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - data = spi->ch[0].SPRDAT; - spi->ch[0].SPTDAT = 0xFF; + data = readl(&spi->ch[0].sprdat); + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); CLR_CS_TOUCH(); - return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); + return (readl(&spi->ch[0].sprdat) & 0x0FF) | (data << 8); } void tsc2000_set_mux(unsigned int channel) diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h index db4b408..3719c2e 100644 --- a/board/trab/tsc2000.h +++ b/board/trab/tsc2000.h @@ -29,45 +29,75 @@ #define _TSC2000_H_ /* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) - -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) +#define CON_MUX0 (writel((readl(&gpio->pccon) & 0x0FFFFFCFF) | \ + 0x00000100, &gpio->pccon)) +#define CLR_MUX0 (writel(readl(&gpio->pcdat) & 0x0FFEF, \ + &gpio->pcdat)) +#define SET_MUX0 (writel(readl(&gpio->pcdat) | 0x00010, \ + &gpio->pcdat)) + +#define CON_MUX1 (writel((readl(&gpio->pccon) & 0x0FFFFF3FF) | \ + 0x00000400, &gpio->pccon)) +#define CLR_MUX1 (writel(readl(&gpio->pcdat) & 0x0FFDF, \ + &gpio->pcdat)) +#define SET_MUX1 (writel(readl(&gpio->pcdat) | 0x00020, \ + &gpio->pcdat)) + +#define CON_MUX1_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFFCFFF) | \ + 0x00001000, &gpio->pccon)) +#define CLR_MUX1_ENABLE (writel(readl(&gpio->pcdat) | 0x00040, \ + &gpio->pcdat)) +#define SET_MUX1_ENABLE (writel(readl(&gpio->pcdat) & 0x0FFBF, \ + &gpio->pcdat)) + +#define CON_MUX2_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFF3FFF) | \ + 0x00004000, &gpio->pccon)) +#define CLR_MUX2_ENABLE (writel(readl(&gpio->pcdat) | 0x00080, \ + &gpio->pcdat)) +#define SET_MUX2_ENABLE (writel(readl(&gpio->pcdat) & 0x0FF7F, \ + &gpio->pcdat)) + +#define CON_MUX3_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFCFFFF) | \ + 0x00010000, &gpio->pccon)) +#define CLR_MUX3_ENABLE (writel(readl(&gpio->pcdat) | 0x00100, \ + &gpio->pcdat)) +#define SET_MUX3_ENABLE (writel(readl(&gpio->pcdat) & 0x0FEFF, \ + &gpio->pcdat)) + +#define CON_MUX4_ENABLE (writel((readl(&gpio->pccon) & 0x0FFF3FFFF) | \ + 0x00040000, &gpio->pccon)) +#define CLR_MUX4_ENABLE (writel(readl(&gpio->pcdat) | 0x00200, \ + &gpio->pcdat)) +#define SET_MUX4_ENABLE (writel(readl(&gpio->pcdat) & 0x0FDFF, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_0 (writel((readl(&gpio->pccon) & 0x0FFCFFFFF) | \ + 0x00100000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) & 0x0FBFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) | 0x00400, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_1 (writel((readl(&gpio->pccon) & 0x0FF3FFFFF) | \ + 0x00400000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) & 0x0F7FF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) | 0x00800, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_2 (writel((readl(&gpio->pccon) & 0x0FCFFFFFF) | \ + 0x01000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) & 0x0EFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) | 0x01000, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_3 (writel((readl(&gpio->pccon) & 0x0F3FFFFFF) | \ + 0x04000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) & 0x0DFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) | 0x02000, \ + &gpio->pcdat)) /* TSC2000 register definition */ #define TSC2000_REG_X ((0 << 11) | (0 << 5)) @@ -130,14 +160,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); } static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); } #endif /* _TSC2000_H_ */ diff --git a/board/trab/vfd.c b/board/trab/vfd.c index cc7f9d3..ad5b8c2 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -38,6 +38,7 @@ #include <linux/types.h> #include <stdio_dev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -414,15 +415,15 @@ int vfd_init_clocks(void) * defined by pull-ups */ /* activate GPC0...GPC3 pullups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon); /* allow signals to settle */ /* udelay isn't working yet at this point! */ for (i = 0; i < 10000; i++) __asm__("NOP"); /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F; VFD_DISABLE; /* activate blank for the vfd */ @@ -434,39 +435,41 @@ int vfd_init_clocks(void) /* Enable 500 Hz timer for fill level sensor to operate * properly */ /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->PDCON &= ~0x30000; - gpio->PDCON |= 0x20000; - gpio->PDUP |= (1 << 8); + writel(readl(&gpio->pdcon) & ~0x30000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x20000, &gpio->pdcon); + writel(readl(&gpio->pdup) | (1 << 8), &gpio->pdup); /* Configure the prescaler */ - timers->TCFG0 &= ~0xff00; - timers->TCFG0 |= 0x0f00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* Select MUX input (divider) for timer3 (1/16) */ - timers->TCFG1 &= ~0xf000; - timers->TCFG1 |= 0x3000; + writel(readl(&timers->tcfg1) & ~0xF000, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x3000, &timers->tcfg1); /* Enable autoreload and set the counter and compare * registers to values for the 500 Hz clock * (for a given prescaler (15) and divider (16)): * counter = (66000000 / 500) >> 9; */ - timers->ch[3].TCNTB = 0x101; - timers->ch[3].TCMPB = 0x101 / 2; + writel(0x101, &timers->ch[3].tcntb); + writel(0x101 / 2, &timers->ch[3].tcmpb); /* Start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); } #endif /* If old board revision, then use vm-signal as cpld-clock */ - lcd->LCDCON2 = 0x00FFC000; - lcd->LCDCON3 = 0x0007FF00; - lcd->LCDCON4 = 0x00000000; - lcd->LCDCON5 = 0x00000400; - lcd->LCDCON1 = 0x00000B75; + writel(0x00FFC000, &lcd->lcdcon2); + writel(0x0007FF00, &lcd->lcdcon3); + writel(0x00000000, &lcd->lcdcon4); + writel(0x00000400, &lcd->lcdcon5); + writel(0x00000B75, &lcd->lcdcon1); /* VM (GPD1) is used as clock for the CPLD */ - gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; + writel((readl(&gpio->pdcon) & 0xFFFFFFF3) | 0x00000008, &gpio->pdcon); return 0; } @@ -536,46 +539,46 @@ int drv_vfd_init(void) * see manual S3C2400 */ /* Stopp LCD-Controller */ - lcd->LCDCON1 = 0x00000000; + writel(0x00000000, &lcd->lcdcon1); /* frame buffer startadr */ - lcd->LCDSADDR1 = gd->fb_base >> 1; + writel(gd->fb_base >> 1, &lcd->lcdsaddr1); /* frame buffer endadr */ - lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->LCDSADDR3 = ((256 / 4)); - lcd->LCDCON2 = 0x000DC000; + writel((gd->fb_base + FRAME_BUF_SIZE) >> 1, &lcd->lcdsaddr2); + writel(256 / 4, &lcd->lcdsaddr3); + writel(0x000DC000, &lcd->lcdcon2); if (gd->vfd_type == VFD_TYPE_MN11236) - lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ + writel(37 << 14, &lcd->lcdcon2); /* MN11236: 38 lines */ else - lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ - lcd->LCDCON3 = 0x0051000A; - lcd->LCDCON4 = 0x00000001; + writel(55 << 14, &lcd->lcdcon2); /* T119C: 56 lines */ + writel(0x0051000A, &lcd->lcdcon3); + writel(0x00000001, &lcd->lcdcon4); if (gd->vfd_type && vfd_inv_data) - lcd->LCDCON5 = 0x000004C0; + writel(0x000004C0, &lcd->lcdcon5); else - lcd->LCDCON5 = 0x00000440; + writel(0x00000440, &lcd->lcdcon5); /* Port pins as LCD output */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00) | 0x000000AA; - gpio->PDCON = (gpio->PDCON & 0xFFFFFF03) | 0x000000A8; + writel((readl(&gpio->pccon) & 0xFFFFFF00) | 0x000000AA, &gpio->pccon); + writel((readl(&gpio->pdcon) & 0xFFFFFF03) | 0x000000A8, &gpio->pdcon); /* Synchronize VFD enable with LCD controller to avoid flicker */ /* Start LCD-Controller */ - lcd->LCDCON1 = 0x00000B75; - while ((lcd->LCDCON5 & 0x180000) != 0x100000) + writel(0x00000B75, &lcd->lcdcon1); + while ((readl(&lcd->lcdcon5) & 0x180000) != 0x100000) /* Wait for end of VSYNC */; /* Wait for next HSYNC */ - while ((lcd->LCDCON5 & 0x060000) != 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) == 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) == 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) != 0x000000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x000000) ; if (gd->vfd_type) VFD_ENABLE; - debug("LCDSADDR1: %lX\n", lcd->LCDSADDR1); - debug("LCDSADDR2: %lX\n", lcd->LCDSADDR2); - debug("LCDSADDR3: %lX\n", lcd->LCDSADDR3); + debug("LCDSADDR1: %lX\n", readl(&lcd->lcdsaddr1)); + debug("LCDSADDR2: %lX\n", readl(&lcd->lcdsaddr2)); + debug("LCDSADDR3: %lX\n", readl(&lcd->lcdsaddr3)); return 0; } @@ -589,8 +592,8 @@ void disable_vfd(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); VFD_DISABLE; - gpio->PDCON &= ~0xC; - gpio->PDUP &= ~0x2; + writel(readl(&gpio->pdcon) & ~0xC, &gpio->pdcon); + writel(readl(&gpio->pdup) & ~0x2, &gpio->pdup); } /************************************************************************/ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 879fda6..5d7b05e 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -33,10 +33,11 @@ #include <asm/arch/s3c24x0_cpu.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> void do_irq (struct pt_regs *pt_regs) { struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt(); - u_int32_t intpnd = readl(&irq->INTPND); + u_int32_t intpnd = readl(&irq->intpnd); } diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index b13283a..58e8865 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s; if (pllreg == MPLL) - r = readl(&clk_power->MPLLCON); + r = readl(&clk_power->mpllcon); else if (pllreg == UPLL) - r = readl(&clk_power->UPLLCON); + r = readl(&clk_power->upllcon); else hang(); @@ -78,7 +78,7 @@ ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); + return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); } /* return PCLK frequency */ @@ -86,7 +86,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); + return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); } /* return UCLK frequency */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 7d47354..9fcfec2 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - return readl(&timers->TCNTO4) & 0xffff; + return readl(&timers->tcnto4) & 0xffff; } static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->TCFG0); + writel(0x0f00, &timers->tcfg0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val; - writel(timer_load_val, &timers->TCNTB4); + writel(timer_load_val, &timers->tcntb4); /* auto load, manual update of Timer 4 */ - tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->TCON); + tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; + writel(tmr, &timers->tcon); /* auto load, start Timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->TCON); + writel(tmr, &timers->tcon); timestamp = 0; return (0); @@ -206,13 +206,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ - writel(0x0000, &watchdog->WTCON); + writel(0x0000, &watchdog->wtcon); /* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->WTCNT); + writel(0x0001, &watchdog->wtcnt); /* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->WTCON); + writel(0x0021, &watchdog->wtcon); while (1) /* loop forever and wait for reset to happen */; diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index e468ed0..2033965 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,15 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON); + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR); + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); return 0; } @@ -55,14 +56,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64..4799610 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,14 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - clk_power->CLKCON |= (1 << 4); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1710,8 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; } @@ -1722,7 +1724,8 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; } #ifdef DEBUG @@ -1748,7 +1751,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index e6c0083..4e43344 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -58,10 +58,10 @@ static int get_i2c_sda(void) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - return (readl(&gpio->GPEDAT) & 0x8000) >> 15; + return (readl(&gpio->gpedat) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (readl(&gpio->PGDAT) & 0x0020) >> 5; + return (readl(&gpio->pgdat) & 0x0020) >> 5; #endif } @@ -70,10 +70,10 @@ static void set_i2c_scl(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); + writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 - writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); + writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } @@ -83,26 +83,26 @@ static int wait_for_xfer(void) int i; i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { udelay(100); i--; } - return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } static int is_ack(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); } static void read_write_byte(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); + writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } void i2c_init(int speed, int slaveadd) @@ -115,30 +115,30 @@ void i2c_init(int speed, int slaveadd) /* wait for some time to give previous transfer a chance to finish */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || get_i2c_sda() == 0) { + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || get_i2c_sda() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = readl(&gpio->GPECON); + ulong old_gpecon = readl(&gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = readl(&gpio->PGCON); + ulong old_gpecon = readl(&gpio->pgcon); #endif /* bus still busy probably by (most) previously interrupted transfer */ #ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, - &gpio->GPECON); + writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, + &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, - &gpio->PGCON); + writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, + &gpio->pgcon); #endif /* toggle I2CSCL until bus idle */ @@ -157,10 +157,10 @@ void i2c_init(int speed, int slaveadd) /* restore pin functions */ #ifdef CONFIG_S3C2410 - writel(old_gpecon, &gpio->GPECON); + writel(old_gpecon, &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - writel(old_gpecon, &gpio->PGCON); + writel(old_gpecon, &gpio->pgcon); #endif } @@ -176,13 +176,13 @@ void i2c_init(int speed, int slaveadd) /* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->IICSTAT); - writel(slaveadd, &i2c->IICADD); + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } @@ -211,47 +211,47 @@ int i2c_transfer(unsigned char cmd_type, /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) + if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT; - writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); result = I2C_OK; switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } } else { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } @@ -261,42 +261,42 @@ int i2c_transfer(unsigned char cmd_type, result = wait_for_xfer(); /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break; case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer(); if (is_ack()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); result = wait_for_xfer(); i++; } - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->IICSTAT); + I2C_START_STOP, &i2c->iicstat); read_write_byte(); result = wait_for_xfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) - & ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) + & ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -304,11 +304,11 @@ int i2c_transfer(unsigned char cmd_type, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer(); if (is_ack()) { @@ -316,11 +316,11 @@ int i2c_transfer(unsigned char cmd_type, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) & - ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) & + ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -329,7 +329,7 @@ int i2c_transfer(unsigned char cmd_type, } /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index a27d47e..ccc771f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, + &nand->nfconf); else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, + &nand->nfconf); } if (cmd != NAND_CMD_NONE) @@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "dev_ready\n"); - return readl(&nand->NFSTAT) & 0x01; + return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC @@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); - ecc_code[0] = readb(&nand->NFECC); - ecc_code[1] = readb(&nand->NFECC + 1); - ecc_code[2] = readb(&nand->NFECC + 2); + ecc_code[0] = readb(&nand->nfecc); + ecc_code[1] = readb(&nand->nfecc + 1); + ecc_code[2] = readb(&nand->nfecc + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand) debugX(1, "board_nand_init()\n"); - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); /* initialize hardware */ twrph0 = 3; @@ -141,10 +141,10 @@ int board_nand_init(struct nand_chip *nand) cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + writel(cfg, &nand_reg->nfconf); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata; nand->select_chip = NULL; diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 04de5ca..7f02f05 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a) switch (a) { case RTC_ENABLE: - writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); break; case RTC_DISABLE: - writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); break; } } @@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp) /* read RTC registers */ do { - sec = readb(&rtc->BCDSEC); - min = readb(&rtc->BCDMIN); - hour = readb(&rtc->BCDHOUR); - mday = readb(&rtc->BCDDATE); - wday = readb(&rtc->BCDDAY); - mon = readb(&rtc->BCDMON); - year = readb(&rtc->BCDYEAR); - } while (sec != readb(&rtc->BCDSEC)); + sec = readb(&rtc->bcdsec); + min = readb(&rtc->bcdmin); + hour = readb(&rtc->bcdhour); + mday = readb(&rtc->bcddate); + wday = readb(&rtc->bcdday); + mon = readb(&rtc->bcdmon); + year = readb(&rtc->bcdyear); + } while (sec != readb(&rtc->bcdsec)); /* read ALARM registers */ - a_sec = readb(&rtc->ALMSEC); - a_min = readb(&rtc->ALMMIN); - a_hour = readb(&rtc->ALMHOUR); - a_date = readb(&rtc->ALMDATE); - a_mon = readb(&rtc->ALMMON); - a_year = readb(&rtc->ALMYEAR); - a_armed = readb(&rtc->RTCALM); + a_sec = readb(&rtc->almsec); + a_min = readb(&rtc->almmin); + a_hour = readb(&rtc->almhour); + a_date = readb(&rtc->almdate); + a_mon = readb(&rtc->almmon); + a_year = readb(&rtc->almyear); + a_armed = readb(&rtc->rtcalm); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp) SetRTC_Access(RTC_ENABLE); /* write RTC registers */ - writeb(sec, &rtc->BCDSEC); - writeb(min, &rtc->BCDMIN); - writeb(hour, &rtc->BCDHOUR); - writeb(mday, &rtc->BCDDATE); - writeb(wday, &rtc->BCDDAY); - writeb(mon, &rtc->BCDMON); - writeb(year, &rtc->BCDYEAR); + writeb(sec, &rtc->bcdsec); + writeb(min, &rtc->bcdmin); + writeb(hour, &rtc->bcdhour); + writeb(mday, &rtc->bcddate); + writeb(wday, &rtc->bcdday); + writeb(mon, &rtc->bcdmon); + writeb(year, &rtc->bcdyear); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -163,8 +163,8 @@ void rtc_reset(void) { struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); - writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); + writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); + writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); } #endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 5dd4dd8..a613229 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -100,7 +100,7 @@ void _serial_setbrg(const int dev_index) /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - writel(reg, &uart->UBRDIV); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) /* Delay */ ; } @@ -130,26 +130,26 @@ static int serial_init_dev(const int dev_index) #endif /* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->UFCON); - writel(0x0, &uart->UMCON); + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ULCON); + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - writel(0x245, &uart->UCON); + writel(0x245, &uart->ucon); #ifdef CONFIG_HWFLOW - writel(0x1, &uart->UMCON); /* RTS up */ + writel(0x1, &uart->umcon); /* RTS up */ #endif /* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->UMCON); + writel(0x10, &uart->umcon); #endif _serial_setbrg(dev_index); @@ -175,10 +175,10 @@ int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - while (!(readl(&uart->UTRSTAT) & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */ ; - return readb(&uart->URXH) & 0xff; + return readb(&uart->urxh) & 0xff; } #if defined(CONFIG_SERIAL_MULTI) @@ -236,15 +236,15 @@ void _serial_putc(const char c, const int dev_index) return; #endif - while (!(readl(&uart->UTRSTAT) & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ; #ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + while (hwflow && !(readl(&uart->umstat) & 0x1)) /* Wait for CTS up */ ; #endif - writeb(c, &uart->UTXH); + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -271,7 +271,7 @@ int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - return readl(&uart->UTRSTAT) & 0x1; + return readl(&uart->utrstat) & 0x1; } #if defined(CONFIG_SERIAL_MULTI) diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h index 15f53dd..3481dd6 100644 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -33,12 +33,12 @@ /* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - u32 BWSCON; - u32 BANKCON[8]; - u32 REFRESH; - u32 BANKSIZE; - u32 MRSRB6; - u32 MRSRB7; + u32 bwscon; + u32 bankcon[8]; + u32 refresh; + u32 banksize; + u32 mrsrb6; + u32 mrsrb7; }; @@ -72,34 +72,34 @@ struct s3c24x0_usb_host { /* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - u32 SRCPND; - u32 INTMOD; - u32 INTMSK; - u32 PRIORITY; - u32 INTPND; - u32 INTOFFSET; + u32 srcpnd; + u32 intmod; + u32 intmsk; + u32 priority; + u32 intpnd; + u32 intoffset; #ifdef CONFIG_S3C2410 - u32 SUBSRCPND; - u32 INTSUBMSK; + u32 subsrcpnd; + u32 intsubmsk; #endif }; /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - u32 DISRC; + u32 disrc; #ifdef CONFIG_S3C2410 - u32 DISRCC; + u32 disrcc; #endif - u32 DIDST; + u32 didst; #ifdef CONFIG_S3C2410 - u32 DIDSTC; + u32 didstc; #endif - u32 DCON; - u32 DSTAT; - u32 DCSRC; - u32 DCDST; - u32 DMASKTRIG; + u32 dcon; + u32 dstat; + u32 dcsrc; + u32 dcdst; + u32 dmasktrig; #ifdef CONFIG_S3C2400 u32 res[1]; #endif @@ -116,90 +116,90 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - u32 LOCKTIME; - u32 MPLLCON; - u32 UPLLCON; - u32 CLKCON; - u32 CLKSLOW; - u32 CLKDIVN; + u32 locktime; + u32 mpllcon; + u32 upllcon; + u32 clkcon; + u32 clkslow; + u32 clkdivn; }; /* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - u32 LCDCON1; - u32 LCDCON2; - u32 LCDCON3; - u32 LCDCON4; - u32 LCDCON5; - u32 LCDSADDR1; - u32 LCDSADDR2; - u32 LCDSADDR3; - u32 REDLUT; - u32 GREENLUT; - u32 BLUELUT; + u32 lcdcon1; + u32 lcdcon2; + u32 lcdcon3; + u32 lcdcon4; + u32 lcdcon5; + u32 lcdsaddr1; + u32 lcdsaddr2; + u32 lcdsaddr3; + u32 redlut; + u32 greenlut; + u32 bluelut; u32 res[8]; - u32 DITHMODE; - u32 TPAL; + u32 dithmode; + u32 tpal; #ifdef CONFIG_S3C2410 - u32 LCDINTPND; - u32 LCDSRCPND; - u32 LCDINTMSK; - u32 LPCSEL; + u32 lcdintpnd; + u32 lcdsrcpnd; + u32 lcdintmsk; + u32 lpcsel; #endif }; /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - u32 NFCONF; - u32 NFCMD; - u32 NFADDR; - u32 NFDATA; - u32 NFSTAT; - u32 NFECC; + u32 nfconf; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfstat; + u32 nfecc; }; /* UART (see manual chapter 11) */ struct s3c24x0_uart { - u32 ULCON; - u32 UCON; - u32 UFCON; - u32 UMCON; - u32 UTRSTAT; - u32 UERSTAT; - u32 UFSTAT; - u32 UMSTAT; + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 utrstat; + u32 uerstat; + u32 ufstat; + u32 umstat; #ifdef __BIG_ENDIAN u8 res1[3]; - u8 UTXH; + u8 utxh; u8 res2[3]; - u8 URXH; + u8 urxh; #else /* Little Endian */ - u8 UTXH; + u8 utxh; u8 res1[3]; - u8 URXH; + u8 urxh; u8 res2[3]; #endif - u32 UBRDIV; + u32 ubrdiv; }; /* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - u32 TCNTB; - u32 TCMPB; - u32 TCNTO; + u32 tcntb; + u32 tcmpb; + u32 tcnto; }; struct s3c24x0_timers { - u32 TCFG0; - u32 TCFG1; - u32 TCON; + u32 tcfg0; + u32 tcfg1; + u32 tcon; struct s3c24x0_timer ch[4]; - u32 TCNTB4; - u32 TCNTO4; + u32 tcntb4; + u32 tcnto4; }; @@ -207,9 +207,9 @@ struct s3c24x0_timers { struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN u8 res[3]; - u8 EP_FIFO_REG; + u8 ep_fifo_reg; #else /* little endian */ - u8 EP_FIFO_REG; + u8 ep_fifo_reg; u8 res[3]; #endif }; @@ -217,29 +217,29 @@ struct s3c24x0_usb_dev_fifos { struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res2[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res3[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res4[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res5[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res6[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; #else /* little endian */ - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res1[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res2[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res3[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res4[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res5[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; u8 res6[3]; #endif }; @@ -247,69 +247,69 @@ struct s3c24x0_usb_dev_dmas { struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res2[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res3[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res4[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res5[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res6[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res7[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res8[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res9[3]; - u8 INDEX_REG; + u8 index_reg; u8 res10[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res11[3]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res12[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res13[7]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res14[3]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res15[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res16[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; #else /* little endian */ - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res1[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res2[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res3[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res4[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res5[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res6[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res7[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res8[3]; - u8 INDEX_REG; + u8 index_reg; u8 res9[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res10[7]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res11[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res12[3]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res13[7]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res14[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res15[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; @@ -319,18 +319,18 @@ struct s3c24x0_usb_device { /* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - u32 WTCON; - u32 WTDAT; - u32 WTCNT; + u32 wtcon; + u32 wtdat; + u32 wtcnt; }; /* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - u32 IICCON; - u32 IICSTAT; - u32 IICADD; - u32 IICDS; + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; }; @@ -338,25 +338,25 @@ struct s3c24x0_i2c { struct s3c24x0_i2s { #ifdef __BIG_ENDIAN u16 res1; - u16 IISCON; + u16 iiscon; u16 res2; - u16 IISMOD; + u16 iismod; u16 res3; - u16 IISPSR; + u16 iispsr; u16 res4; - u16 IISFCON; + u16 iisfcon; u16 res5; - u16 IISFIFO; + u16 iisfifo; #else /* little endian */ - u16 IISCON; + u16 iiscon; u16 res1; - u16 IISMOD; + u16 iismod; u16 res2; - u16 IISPSR; + u16 iispsr; u16 res3; - u16 IISFCON; + u16 iisfcon; u16 res4; - u16 IISFIFO; + u16 iisfifo; u16 res5; #endif }; @@ -365,87 +365,87 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - u32 PACON; - u32 PADAT; + u32 pacon; + u32 padat; - u32 PBCON; - u32 PBDAT; - u32 PBUP; + u32 pbcon; + u32 pbdat; + u32 pbup; - u32 PCCON; - u32 PCDAT; - u32 PCUP; + u32 pccon; + u32 pcdat; + u32 pcup; - u32 PDCON; - u32 PDDAT; - u32 PDUP; + u32 pdcon; + u32 pddat; + u32 pdup; - u32 PECON; - u32 PEDAT; - u32 PEUP; + u32 pecon; + u32 pedat; + u32 peup; - u32 PFCON; - u32 PFDAT; - u32 PFUP; + u32 pfcon; + u32 pfdat; + u32 pfup; - u32 PGCON; - u32 PGDAT; - u32 PGUP; + u32 pgcon; + u32 pgdat; + u32 pgup; - u32 OPENCR; + u32 opencr; - u32 MISCCR; - u32 EXTINT; + u32 misccr; + u32 extint; #endif #ifdef CONFIG_S3C2410 - u32 GPACON; - u32 GPADAT; + u32 gpacon; + u32 gpadat; u32 res1[2]; - u32 GPBCON; - u32 GPBDAT; - u32 GPBUP; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; u32 res2; - u32 GPCCON; - u32 GPCDAT; - u32 GPCUP; + u32 gpccon; + u32 gpcdat; + u32 gpcup; u32 res3; - u32 GPDCON; - u32 GPDDAT; - u32 GPDUP; + u32 gpdcon; + u32 gpddat; + u32 gpdup; u32 res4; - u32 GPECON; - u32 GPEDAT; - u32 GPEUP; + u32 gpecon; + u32 gpedat; + u32 gpeup; u32 res5; - u32 GPFCON; - u32 GPFDAT; - u32 GPFUP; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; u32 res6; - u32 GPGCON; - u32 GPGDAT; - u32 GPGUP; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; u32 res7; - u32 GPHCON; - u32 GPHDAT; - u32 GPHUP; + u32 gphcon; + u32 gphdat; + u32 gphup; u32 res8; - u32 MISCCR; - u32 DCLKCON; - u32 EXTINT0; - u32 EXTINT1; - u32 EXTINT2; - u32 EINTFLT0; - u32 EINTFLT1; - u32 EINTFLT2; - u32 EINTFLT3; - u32 EINTMASK; - u32 EINTPEND; - u32 GSTATUS0; - u32 GSTATUS1; - u32 GSTATUS2; - u32 GSTATUS3; - u32 GSTATUS4; + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; #endif }; @@ -454,74 +454,74 @@ struct s3c24x0_gpio { struct s3c24x0_rtc { #ifdef __BIG_ENDIAN u8 res1[67]; - u8 RTCCON; + u8 rtccon; u8 res2[3]; - u8 TICNT; + u8 ticnt; u8 res3[11]; - u8 RTCALM; + u8 rtcalm; u8 res4[3]; - u8 ALMSEC; + u8 almsec; u8 res5[3]; - u8 ALMMIN; + u8 almmin; u8 res6[3]; - u8 ALMHOUR; + u8 almhour; u8 res7[3]; - u8 ALMDATE; + u8 almdate; u8 res8[3]; - u8 ALMMON; + u8 almmon; u8 res9[3]; - u8 ALMYEAR; + u8 almyear; u8 res10[3]; - u8 RTCRST; + u8 rtcrst; u8 res11[3]; - u8 BCDSEC; + u8 bcdsec; u8 res12[3]; - u8 BCDMIN; + u8 bcdmin; u8 res13[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res14[3]; - u8 BCDDATE; + u8 bcddate; u8 res15[3]; - u8 BCDDAY; + u8 bcdday; u8 res16[3]; - u8 BCDMON; + u8 bcdmon; u8 res17[3]; - u8 BCDYEAR; + u8 bcdyear; #else /* little endian */ u8 res0[64]; - u8 RTCCON; + u8 rtccon; u8 res1[3]; - u8 TICNT; + u8 ticnt; u8 res2[11]; - u8 RTCALM; + u8 rtcalm; u8 res3[3]; - u8 ALMSEC; + u8 almsec; u8 res4[3]; - u8 ALMMIN; + u8 almmin; u8 res5[3]; - u8 ALMHOUR; + u8 almhour; u8 res6[3]; - u8 ALMDATE; + u8 almdate; u8 res7[3]; - u8 ALMMON; + u8 almmon; u8 res8[3]; - u8 ALMYEAR; + u8 almyear; u8 res9[3]; - u8 RTCRST; + u8 rtcrst; u8 res10[3]; - u8 BCDSEC; + u8 bcdsec; u8 res11[3]; - u8 BCDMIN; + u8 bcdmin; u8 res12[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res13[3]; - u8 BCDDATE; + u8 bcddate; u8 res14[3]; - u8 BCDDAY; + u8 bcdday; u8 res15[3]; - u8 BCDMON; + u8 bcdmon; u8 res16[3]; - u8 BCDYEAR; + u8 bcdyear; u8 res17[3]; #endif }; @@ -529,34 +529,34 @@ struct s3c24x0_rtc { /* ADC (see manual chapter 16) */ struct s3c2400_adc { - u32 ADCCON; - u32 ADCDAT; + u32 adccon; + u32 adcdat; }; /* ADC (see manual chapter 16) */ struct s3c2410_adc { - u32 ADCCON; - u32 ADCTSC; - u32 ADCDLY; - u32 ADCDAT0; - u32 ADCDAT1; + u32 adccon; + u32 adctsc; + u32 adcdly; + u32 adcdat0; + u32 adcdat1; }; /* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - u8 SPCON; + u8 spcon; u8 res1[3]; - u8 SPSTA; + u8 spsta; u8 res2[3]; - u8 SPPIN; + u8 sppin; u8 res3[3]; - u8 SPPRE; + u8 sppre; u8 res4[3]; - u8 SPTDAT; + u8 sptdat; u8 res5[3]; - u8 SPRDAT; + u8 sprdat; u8 res6[3]; u8 res7[16]; }; @@ -570,53 +570,53 @@ struct s3c24x0_spi { struct s3c2400_mmc { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 MMCON; + u8 mmcon; u8 res2[3]; - u8 MMCRR; + u8 mmcrr; u8 res3[3]; - u8 MMFCON; + u8 mmfcon; u8 res4[3]; - u8 MMSTA; + u8 mmsta; u16 res5; - u16 MMFSTA; + u16 mmfsta; u8 res6[3]; - u8 MMPRE; + u8 mmpre; u16 res7; - u16 MMLEN; + u16 mmlen; u8 res8[3]; - u8 MMCR7; - u32 MMRSP[4]; + u8 mmcr7; + u32 mmrsp[4]; u8 res9[3]; - u8 MMCMD0; - u32 MMCMD1; + u8 mmcmd0; + u32 mmcmd1; u16 res10; - u16 MMCR16; + u16 mmcr16; u8 res11[3]; - u8 MMDAT; + u8 mmdat; #else - u8 MMCON; + u8 mmcon; u8 res1[3]; - u8 MMCRR; + u8 mmcrr; u8 res2[3]; - u8 MMFCON; + u8 mmfcon; u8 res3[3]; - u8 MMSTA; + u8 mmsta; u8 res4[3]; - u16 MMFSTA; + u16 mmfsta; u16 res5; - u8 MMPRE; + u8 mmpre; u8 res6[3]; - u16 MMLEN; + u16 mmlen; u16 res7; - u8 MMCR7; + u8 mmcr7; u8 res8[3]; - u32 MMRSP[4]; - u8 MMCMD0; + u32 mmrsp[4]; + u8 mmcmd0; u8 res9[3]; - u32 MMCMD1; - u16 MMCR16; + u32 mmcmd1; + u16 mmcr16; u16 res10; - u8 MMDAT; + u8 mmdat; u8 res11[3]; #endif }; @@ -624,29 +624,29 @@ struct s3c2400_mmc { /* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - u32 SDICON; - u32 SDIPRE; - u32 SDICARG; - u32 SDICCON; - u32 SDICSTA; - u32 SDIRSP0; - u32 SDIRSP1; - u32 SDIRSP2; - u32 SDIRSP3; - u32 SDIDTIMER; - u32 SDIBSIZE; - u32 SDIDCON; - u32 SDIDCNT; - u32 SDIDSTA; - u32 SDIFSTA; + u32 sdicon; + u32 sdipre; + u32 sdicarg; + u32 sdiccon; + u32 sdicsta; + u32 sdirsp0; + u32 sdirsp1; + u32 sdirsp2; + u32 sdirsp3; + u32 sdidtimer; + u32 sdibsize; + u32 sdidcon; + u32 sdidcnt; + u32 sdidsta; + u32 sdifsta; #ifdef __BIG_ENDIAN u8 res[3]; - u8 SDIDAT; + u8 sdidat; #else - u8 SDIDAT; + u8 sdidat; u8 res[3]; #endif - u32 SDIIMSK; + u32 sdiimsk; }; #endif /*__S3C24X0_H__*/ -- 1.6.6

4 6

[U-Boot] VIDEOBOOT Patch for Linux 2.6?
by Patrick Simmons 13 Feb '10

13 Feb '10

Hi guys, I'm trying to get an x86 ATI card working on SPARC, and I think SciTechSoft's SNAP Videoboot is my best bet. Unfortunately, the patch doesn't seem to be available from SciTechSoft (which has been acquired) anymore, and you guys are the only ones who seem to have anything resembling that code available for download. So, I was wondering if any of you have a patch I can take and patch some 2.6 kernel with to boot my graphics card from. I'm trying to use radeonfb, so VIDEOBOOT would be perfect for me ... I just can't find it anywhere! If the easiest way for me to do this is to run U-Boot on a SunBlade 2500, that's fine, but my understanding is that U-Boot is primarily for embedded systems. So ... anyone have the videoboot-2.6x patch lying around? Pretty please? Please CC me as I am not on the list. Thanks, --Patrick Simmons

1 0

[U-Boot] [PATCH 1/9 V3] add new CONFIG_AT91_LEGACY
by Jens Scharsig 13 Feb '10

13 Feb '10

* add's the new temporary CONFIG_AT91_LEGACY to all board configs * This will need for backward compatiblity, while change the SoC access to c structures. If CONFIG_AT91_LEGACY is defined, the deprecated SoC is used. * please see README.at91-soc for details Signed-off-by: Jens Scharsig <js_at_ng(a)scharsoft.de> --- doc/README.at91-soc | 42 ++++++++++++++++++++++++++++++++++++ include/configs/afeb9260.h | 2 + include/configs/at91cap9adk.h | 2 + include/configs/at91rm9200dk.h | 2 + include/configs/at91rm9200ek.h | 2 + include/configs/at91sam9260ek.h | 2 + include/configs/at91sam9261ek.h | 2 + include/configs/at91sam9263ek.h | 2 + include/configs/at91sam9m10g45ek.h | 2 + include/configs/at91sam9rlek.h | 2 + include/configs/cmc_pu2.h | 2 + include/configs/cpu9260.h | 2 + include/configs/cpuat91.h | 2 + include/configs/csb637.h | 2 + include/configs/kb9202.h | 2 + include/configs/m501sk.h | 2 + include/configs/meesc.h | 2 + include/configs/mp2usb.h | 2 + include/configs/pm9261.h | 2 + include/configs/pm9263.h | 2 + include/configs/sbc35_a9g20.h | 2 + include/configs/tny_a9260.h | 2 + 22 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 doc/README.at91-soc diff --git a/doc/README.at91-soc b/doc/README.at91-soc new file mode 100644 index 0000000..063016e --- /dev/null +++ b/doc/README.at91-soc @@ -0,0 +1,42 @@ + New C structure AT91 SoC access +================================= + +The gool +-------- + +Currently the at91 arch uses hundreds of address defines and special +at91_xxxx_write/read functions to access the SOC. +The u-boot project prefer the better to readable access via c stuctures, +which describe the SoC peripherie. + +e.g. old + + *AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + *AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + + at91_sys_write(AT91_RSTC_CR, + AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + +e.g new + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | + AT91_RSTC_CR_PERRST, &rstc->cr); + +The Way +------- + +1. add's the new temporary CONFIG_AT91_LEGACY to all board configs + that not converted to new SoC access +2. add new structures for SoC access +3. Convert arch, driver and boards file zu new SoC +4. remove legacy code, if all boards and drives are ready + diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 58b8c8c..3b69de8 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 322718f..4c2782a 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 590c69a..bc61677 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -25,6 +25,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index b4f075e..f5206b1 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ /* * from 18.432 MHz crystal diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 0509011..a620d57 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index fbf7389..832b1cd 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 571351c..1d82a15 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 06184e7..50b118f 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 6fad75d..8db296a 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index be478b2..16ae03e 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -25,6 +25,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 4ef8566..e967e7c 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -31,6 +31,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #define CONFIG_DISPLAY_CPUINFO 1 #define AT91_MAIN_CLOCK 18432000 diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 8746f70..9f0ac03 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #ifdef CONFIG_CPUAT91_RAM #define CONFIG_SKIP_LOWLEVEL_INIT 1 #define CONFIG_SKIP_RELOCATE_UBOOT 1 diff --git a/include/configs/csb637.h b/include/configs/csb637.h index f4fd808..90269a7 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */ #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 7dd81e6..24fd1ef 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -29,6 +29,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */ #define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index 5c06642..17469e5 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -27,6 +27,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MAIN_CLOCK 179712000 diff --git a/include/configs/meesc.h b/include/configs/meesc.h index ab5cbca..253a53d 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -31,6 +31,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* Common stuff */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_MEESC 1 /* Board is esd MEESC */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 0c2ee60..c66f8ea 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */ #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 399d15f..26a2fad 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9261" diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0af1280..e55098c 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + /* ARM asynchronous clock */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index f4b3477..7bdc729 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -26,6 +26,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM) #define CONFIG_SBC35_A9G20 #endif diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 4ad081b..21475f8 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -30,6 +30,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_AT91_LEGACY + #if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM) #define CONFIG_TNY_A9260 #elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)

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[U-Boot] howto flash ubi rootfs image into nand flash with u-boot?
by Dieter Kiermaier 12 Feb '10

12 Feb '10

Hi everybody, I wonder how I can flash a ubi rootfs image into my NAND flash by using u-boot to do this? The doc inside u-boot doesn't show me some readme and also google doesn't have some interesting links for me. The online help of the ubi commands is "a bit crypted " - at least for me and the denx online manual has no entries about ubi commands :( Please can someone point me into the right direction? Thank you very much and have fun, Dieter

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[U-Boot] BBT support to UBOOT question
by Steven Zedeck 12 Feb '10

12 Feb '10

Hi all, I'm not really sure as to the protocol for asking this question. So I'll go right ahead. I've seen code on the web written by open moko that tries to address the issue of adding BBT creation to the uboot nand command. I looked at the latest released uboot (2009.11.1) and I don't see the "createbbt" support in the common/cmd_nand.c file I'm not sure what that means? Does it mean there is an issue with it or does it not mean some uboot criteria? Again, hope I'm asking this correctly. Does this functionality exist elsewhere within Uboot? I'd rather not reinvent the wheel, plus the fact that I don't know the details about nand devices as yet. I was hoping that support to create/generate the Nand BBT in Uboot existed. Any info would be greatly appreciated. thanks in advance, Steve -- View this message in context: http://old.nabble.com/BBT-support-to-UBOOT-question-tp27565331p27565331.html Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Please pull u-boot-ti/master
by s-paulraj＠ti.com 12 Feb '10

12 Feb '10

The following changes since commit 2f8f29f5f6f86b7c467a98508d02a28df735d1ee: Sandeep Paulraj (1): Merge branch 'master' of git://git.denx.de/u-boot-ti are available in the git repository at: git://git.denx.de/u-boot-ti.git master Nick Thompson (2): Davinci: Add EMIF-A macros for setting chip select parameters DA830 EVM: Enable NAND support on Spectrum Digital EVM Sanjeev Premi (1): OMAP3: Avoid re-write to PRM_CLKSRC_CTRL board/davinci/da830evm/da830evm.c | 37 ++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/clock.c | 20 +++++++++++++--- include/asm-arm/arch-davinci/emif_defs.h | 18 +++++++++++++- include/configs/da830evm.h | 21 +++++++++++++---- 4 files changed, 86 insertions(+), 10 deletions(-)

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[U-Boot] [PATCH v2 2/3] S5PC100: Function to configure the SROMC registers.
by Naveen Krishna Ch 12 Feb '10

12 Feb '10

From: Naveen Krishna CH <chnaveen(a)chnaveen.localdomain> Nand Flash, Ethernet, other features might need to configure the SROMC registers accordingly. The config_sromc() functions helps with this. Signed-off-by: Naveen Krishna Ch <ch.naveen(a)samsung.com> --- Changes since V1: 1. Funtion config_sromc() is renamed to s5pc1xx_config_sromc(). Comments from Minkyu Kang are fixed cpu/arm_cortexa8/s5pc1xx/Makefile | 1 + cpu/arm_cortexa8/s5pc1xx/sromc.c | 54 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/smc.h | 3 ++ 3 files changed, 58 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile index 4f922e6..0a6a9b4 100644 --- a/cpu/arm_cortexa8/s5pc1xx/Makefile +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -34,6 +34,7 @@ SOBJS += reset.o COBJS += clock.o COBJS += cpu_info.o COBJS += timer.o +COBJS += sromc.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c new file mode 100644 index 0000000..1d6e738 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/smc.h> + +/* + * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM Bank 0 to 5 + * smc_bw_conf - SMC Band witdh reg configuration value + * smc_bc_conf - SMC Bank Control reg configuration value + */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) +{ + u32 tmp; +#if defined(CONFIG_S5PC100) + struct s5pc1xx_smc *const srom = + (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; +#elif defined(CONFIG_S5PC110) + struct s5pc1xx_smc *const srom = + (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; +#endif + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= smc_bw_conf; + srom->bw = tmp; + + /* Configure SMC_BC register */ + srom->bc[srom_bank] = smc_bc_conf; +} diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h index 2a1ee07..a280dc1 100644 --- a/include/asm-arm/arch-s5pc1xx/smc.h +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -51,4 +51,7 @@ struct s5pc1xx_smc { }; #endif /* __ASSEMBLY__ */ +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); + #endif /* __ASM_ARCH_SMC_H_ */ -- 1.6.6

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[U-Boot] [PATCH V2 1/3] S5PC100: Memory SubSystem Header file, register description(SROMC).
by Naveen Krishna Ch 12 Feb '10

12 Feb '10

From: Naveen Krishna CH <chnaveen(a)chnaveen.localdomain> Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand, NAND Flash, DDRs. mem.h is a common place for the register description of Memory subsystem of S5PC100. Note: Only SROM related registers are descibed now. Signed-off-by: Naveen Krishna Ch <ch.naveen(a)samsung.com> --- Changes since V1: 1. The header file is renamed to smc.h from mem.h 2. The Macros are renamed according to TRM. Comments from Minkyu kang are fixed. Note: Some of the defined macros are not used now. They are added to facilitiate simple cofiguration of SMC registers. include/asm-arm/arch-s5pc1xx/smc.h | 54 ++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h diff --git a/include/asm-arm/arch-s5pc1xx/smc.h b/include/asm-arm/arch-s5pc1xx/smc.h new file mode 100644 index 0000000..2a1ee07 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/smc.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for Memory subsystem + * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX. + * + * Only SROMC is defined as of now + */ + +#ifndef __ASM_ARCH_SMC_H_ +#define __ASM_ARCH_SMC_H_ + +#define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SMC_BC_TACS 0x0 /* 0clk address set-up */ +#define SMC_BC_TCOS 0x4 /* 4clk chip selection set-up */ +#define SMC_BC_TACC 0xe /* 14clk access cycle */ +#define SMC_BC_TCOH 0x1 /* 1clk chip selection hold */ +#define SMC_BC_TAH 0x4 /* 4clk address holding time */ +#define SMC_BC_TACP 0x6 /* 6clk page mode access cycle */ +#define SMC_BC_PMC 0x0 /* normal(1data)page mode configuration */ + +#define SMC_BC_CON ((SMC_BC_TACS<<28)|(SMC_BC_TCOS<<24)| \ + (SMC_BC_TACC<<16)|(SMC_BC_TCOH<<12)| \ + (SMC_BC_TAH<<8)|(SMC_BC_TACP<<4)|(SMC_BC_PMC)) + +#ifndef __ASSEMBLY__ +struct s5pc1xx_smc { + unsigned int bw; + unsigned int bc[6]; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_SMC_H_ */ -- 1.6.6

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