February 2010 - U-Boot

[U-Boot] Can't start Linux if U-Boot built with CONFIG_WATCHDOG
by Matthew Lear 26 Aug '15

26 Aug '15

Hello all, I've added watchdog support based on U-Boot (git) for the m68k coldfire mcf54455evb platform. I've fed the patch to the maintainer to help in development. However, I am unable to start my m68k w/MMU coldfire Linux kernel from U-Boot if U-Boot is built with CONFIG_WATCHDOG regardless if the watchdog_enable(), watchdog_reset() and watchdog_disable() functions touch hardware or not. I initially thought this was a problem with enabling the watchdog somehow (ie when Linux started, some hw configuration in the device was getting upset or corrupted etc resulting in the failure), but when I commented out the code from the above functions that actually accesses the hw (ie to enable, kick and disable the watchdog timer hw block), Linux is still unable to start. In fact, I don't think Linux actually gets started! That's the problem. If I rebuild the same U-Boot code base with CONFIG_WATCHDOG undefined, Linux can start just fine. As far as I can tell, there are no functional differences in building U-Boot with or without CONFIG_WATCHDOG enabled when the functions above are stubs and do absolutely nothing at all. If I build U-Boot with debug, what I see is as follows: ## Transferring control to Linux (at address 40020000) ... BIV ...and then the board is dead. I occasionally see something like the following from U-Boot: *** Unexpected exception *** Vector Number: 4 Format: 04 Fault Status: 0 PC: 4fdbfdc8 SR: 00002700 SP: 4fd72a64 D0: 00000004 D1: 000003f9 D2: 4fdb4202 D3: 004fa3da D4: 00000000 D5: 4fdc7c8c D6: 122c0034 D7: 4fd82f76 A0: 4033cb98 A1: 4025aa39 A2: 40020000 A3: 4fdbfdc8 A4: 00000000 A5: 4fdc5800 A6: 4fd72afb *** Please Reset Board! *** The 'BIV' is relevant because in my 2.6.29 kernel src arch/m68k/include/asm/bootinfo_mm.h, BOOTINFOV_MAGIC is defined to be 0x4249561A which is BIV^Z. This ascii text is located in the kernel image header info: >From arch/m68k/coldfire/head.S: .section ".text.head","ax" ENTRY(_stext) bras 1f /* Jump over bootinfo version numbers */ .long BOOTINFOV_MAGIC .long 0 And from U-Boot itself: -> md ${loadaddr} 40010000: 27051956 97342d7d 4a54afd5 00300000 '..V.4-}JT...0.. 40010010: 40020000 40020000 8a006fc1 050c0200 @...@.....o..... 40010020: 4c696e75 78204b65 726e656c 20496d61 Linux Kernel Ima 40010030: 67650000 00000000 00000000 00000000 ge.............. 40010040: 60084249 561a0000 00004ef9 40304000 `.BIV.....N.@0@. I suspect that the failure of starting Linux is caused by some mismatch in data structures (or versions there of) shared/copied between Linux and U-Boot and that this data has somehow changed when U-Boot is built with CONFIG_WATCHDOG #defined. However, I can't find any evidence of this in the U-Boot code base. The bras instruction above must be key and I suspect that this is the area causing the problem. Can anybody offer any advice / explanation of what exactly could be going on and why? I wouldn't have expected that defining CONFIG_WATCHDOG would change anything as fundamental as this. Apologies for the cross-post (U-Boot and m68k kernel dev) but I hope to get opinions/feedback/help from both communities. Any assistance very much appreciated indeed. Many thanks, -- Matt

2 1

[U-Boot] [PATCH] fsl: Fix compiler warnings from gcc-4.4 in sys_eeprom code
by Kumar Gala 30 Aug '13

30 Aug '13

sys_eeprom.c: In function 'do_mac': sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules sys_eeprom.c: In function 'mac_read_from_eeprom': sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/common/sys_eeprom.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index ae5304a..3e1e332 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -78,12 +78,14 @@ static int has_been_read = 0; #ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif #ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ -#define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) +#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \ + (e.id[2] == 'I') || (e.id[3] == 'D')) #endif /** -- 1.6.0.6

2 1

[U-Boot-Users] minimum bdi config to read flash on 85xx
by robert lazarski 28 May '13

28 May '13

Hi all, On our custom 8548 board, we can't read our flash correctly. We have one 1Gb bank of spansion S29GL01GP flash and we get: atum>mdh 0xf8000000 0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 The big problem we have now: is this a hardware issue or a bdi config issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone help us track our flash issues down to be hardware, config file, or some combination? The hardware guys think the board is fine. We've been deep into the manuals of both the 8548 and the bdi and can't find anything wrong. Here's the config, thanks for any help! ;bdiGDB configuration file for ATUM 8548 ;--------------------------------------------------- ; [INIT] ; ; ; use the following two lines for STARTUP HALT WSPR 63 0xffff0000 ;IVPR to boot core WSPR 415 0x0000f000 ;IVOR15 : Debug exception ; ; ;================= setup for flash programming =============== ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0xe0000C10 0x80f0001d ;LAWAR0 : DDR 1GB WM32 0xe0000C28 0xf8000000 ;LAWBAR1 : @0xf8000000 WM32 0xe0000C30 0x8040001a ;LAWAR1 : Local Bus 128MB for S29GL01GP ; ; Setup Flash chip select WM32 0xe0005000 0xf8001001 ;BR0 WM32 0xe0005004 0xf8000E65 ;OR0 ; CS0_BNDS WM32 0xe0002000 0x0000000f ; DDR CS0 ; CS0_CONFIG WM32 0xe0002080 0x80000102 ; TIMING_CFG_0 WM32 0xe0002104 0x00260802 ; TIMING_CFG_1 WM32 0xe0002108 0x38355322 ; TIMING_CFG_2 WM32 0xe000210C 0x039048c7 ; DDR_SDRAM_MODE WM32 0xe0002118 0x00000432 ; DDR_SDRAM_INTERVAL WM32 0xe0002124 0x05150100 ; DDR_SDRAM_CFG2 WM32 0xe0002114 0x24000000 ; DDR_SDRAM_CLK_CNTL WM32 0xe0002130 0x03000000 DELAY 200 ; enable the memory interface ; DDR_SDRAM_CFG ; enable the memory interface WM32 0xe0002110 0xc3000000 ;================= end flash programming ===================== ; [TARGET] CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;STARTUP STOP 5000 ;let U-boot code setup the system STARTUP HALT ;halt core while HRESET is asserted BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms [REGS] FILE $reg8548.def [HOST] IP 10.101.43.10 FILE vmlinux.8548 FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP e500.bin PROMPT atum> [FLASH] CHIPTYPE MIRRORX16 ;S29GL01GP CHIPSIZE 0x8000000 ;The size of one flash chip in bytes - 1Gb BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE u-boot.bin FORMAT BIN 0xF8000000 ERASE 0xF8000000 ;erase sector 0 [REGS] FILE $reg8548.def

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[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

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[U-Boot] ERROR: CTL:TIMEOUT - USB porting issue for UBoot on S3C2450
by dongdaking 23 Nov '12

23 Nov '12

Hi, I am porting UBoot on S3C2450 and has an USB issue. Here is an error message: ERROR: CTL:TIMEOUT USB device not responding, giving up (status=20) 2 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found The problem seems submit_common_msg couldn't get description of USB flash memory device Could I have help? Please tell me if you had this issue before. Thank you for your helping Here is a log data usb start (Re)start USB... USB: INFO: aligned ghcca c3e4f900 DEBUG: USB HC reset_hc usb-smdk2450: ctrl = 0x9F ; DEBUG: OHCI controller usb-smdk2450 state DEBUG: control: 0x0000008f HCFS=operational IE PLE CBSR=3 DEBUG: cmdstatus: 0x00000000 SOC=0 DEBUG: intrstatus: 0x00000044 RHSC SF DEBUG: intrenable: 0x00000053 RHSC UE WDH SO DEBUG: hcca frame #0000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS scanning bus for devices... New Device 0 start 0st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 start 1st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 start 2st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 INFO: Root-Hub: adr: 0 cmd(8): 00000680 0100 0000 0040 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:64/64 stat:0x0 set address 1 usb_control_msg: request: 0x5, requesttype: 0x0 value 0x1 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000500 0001 0000 0000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x12 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/18 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0100 0000 0012 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:18/18 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x200 index 0x0 length 0x8 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/8 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0008 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:8/8 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x200 index 0x0 length 0x19 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/25 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0200 0000 0019 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:25/25 stat:0x0 get_conf_no 0 Result 25, wLength 25 if 0, ep 0 ##EP epmaxpacketin[1] = 2 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0 value 0x1 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000900 0001 0000 0000 INFO: WR:status 0x10000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 new device strings: Mfr=0, Product=1, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x300 index 0x0 length 0xFF INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0300 0000 00ff DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:255/255 stat:0x0 USB device number 1 default language ID 0x409 usb_control_msg: request: 0x6, requesttype: 0x80 value 0x301 index 0x409 length 0xFF INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/255 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000680 0301 0409 00ff DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:255/255 stat:0x0 Manufacturer Product OHCI Root Hub SerialNumber usb_control_msg: request: 0x6, requesttype: 0xA0 value 0x2900 index 0x0 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x6, requesttype: 0xA0 value 0x2900 index 0x0 length 0x9 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/9 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000006a0 2900 0000 0009 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:9/9 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA0 value 0x0 index 0x0 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a0 0000 0000 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x8 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0001 0000 INFO: WR:portstatus[0] 0x100 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x8 index 0x2 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0008 0002 0000 INFO: WR:portstatus[1] 0x100 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00010101 CSC PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x10 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0010 0001 0000 INFO: WR:portstatus[0] 0x10000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x3, requesttype: 0x23 value 0x4 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0001 0000 INFO: WR:portstatus[0] 0x10 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x14 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0001 0000 INFO: WR:portstatus[0] 0x100000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000103 PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 New Device 1 start 0st usb_new_device usb_control_msg: request: 0x6, requesttype: 0x80 value 0x100 index 0x0 length 0x40 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: SUB URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x80000000 DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. DEBUG: % DEBUG: hc_interrupt: returning.. ERROR: hc_interrupt: returning.. ERROR: CTL:TIMEOUT DEBUG: submit_common_msg: TO status ff DEBUG: RET(ctlr) URB:[ 0] dev: 0,ep: 0-I,type:CTRL,len:0/64 stat:0x20 usb_new_device: 64 byte descr usb_control_msg: request: 0x3, requesttype: 0x23 value 0x4 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000323 0004 0001 0000 INFO: WR:portstatus[0] 0x10 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x1 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0001 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00100103 PRSC PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 usb_control_msg: request: 0x1, requesttype: 0x23 value 0x14 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0014 0001 0000 INFO: WR:portstatus[0] 0x100000 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000103 PPS PES CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 set address 2 usb_control_msg: request: 0x5, requesttype: 0x0 value 0x2 index 0x0 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 0,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 ERROR: submit_control_message: pipesize for pipe 80000000 is zero USB device not accepting new address (error=80000000) usb_control_msg: request: 0x1, requesttype: 0x23 value 0x1 index 0x1 length 0x0 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 00000123 0001 0001 0000 INFO: WR:portstatus[0] 0x1 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-O,type:CTRL,len:0/0 stat:0x0 usb_control_msg: request: 0x0, requesttype: 0xA3 value 0x0 index 0x2 length 0x4 INFO: submit_control_msg DEBUG: SUB URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 DEBUG: SUB(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:0/4 stat:0x80000000 INFO: Root-Hub: adr: 1 cmd(8): 000000a3 0000 0002 0004 DEBUG: roothub.a: 02001202 POTPGT=2 NOCP NPS NDP=2 DEBUG: roothub.b: 00000000 PPCM=0000 DR=0000 DEBUG: roothub.status: 00000000 DEBUG: roothub.portstatus [0] = 0x00000101 PPS CCS DEBUG: roothub.portstatus [1] = 0x00000100 PPS DEBUG: RET(rh) URB:[ 0] dev: 1,ep: 0-I,type:CTRL,len:4/4 stat:0x0 2 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found Thank you a lot. Best regards -- View this message in context: http://old.nabble.com/ERROR%3A-CTL%3ATIMEOUT---USB-porting-issue-for-UBoot-… Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot-Users] U boot modification...
by Kiran Jammula 23 May '12

23 May '12

Hi, I am using U boot for my project. I need to configure the console while booting by prompting the user from target board LCD and Keypad. So please let me know which file of the U-boot I have to modify to achieve this. Kiran _________________________________________________________________ Special offer for NRIs! http://creative.mediaturf.net/creatives/citibankrca/rca_msntagofline.htm Get a zero balance account for next 20 years. From Citibank

4 5

[U-Boot-Users] Ethernet loopback command
by Thomas Schäfer 17 Apr '12

17 Apr '12

Hi, The patch attached provides a command called 'ethloop' which allows to perform loopback testing on the current eth device. To achieve this, a new ethernet packet type (PROT_TEST, 0x0808, AFAIK this is not used otherwise) is introduced in net/net.c. The patch is against SF CVS from 20050307. The functions EthLoopStart, EthLoopSend and EthLoopHandler generate a simple ethernet frame with NetOurEther as destination address and packet type PROT_TEST. The looped back package is compared with the original one and a message is displayed. It is necessary to set the ethernet line into loopback mode either by programming the PHY or using a loopback plug. I've tested this on our PPC405 custom board, but it should also work on all other systems because packet generation is independent of the underlying ethernet hardware. Example usage: => mii w 0 0 7100 <-- sets PHY into loopback mode => ethloop Using ppc_405x_eth0 device Got ethernet loopback frame, len=64 loopback test successfully completed => mii w 0 0 8000 <-- PHY reset after test is completed Maybe this is also useful for others.. Best regards, Thomas Schäfer ____________________________________ Kontron Modular Computers GmbH Konrad-Zuse-Str. 9 66115 Saarbrücken Tel.: + 49 (0)681 / 95916 - 203 Fax: + 49 (0)681 / 95916 - 100 E-mail: thomas.schaefer(a)kontron.com

5 5

[U-Boot] U-boot running on DDR fails to detect the CFI compliant flash
by prakash bedge 15 Feb '12

15 Feb '12

Hi Stefan, In October 09 month, I had asked whether U-boot supports M29W128GH, a CFI compilant chip and I got a yes reply. Please refer below URL for reference. http://www.mail-archive.com/u-boot@lists.denx.de/msg24531.html. So I have used Uboot for my PPC440 based board. When I flashed U-boot on flash and then run the Uboot in DDR then U-boot running on DDR fails to detect CFI chip M29W128GH (16M x 8 mode). flash_detect_cfi function gives error that flash not found. I have added debug statements for temporary debug purpose. Please see the below error I am getting. The CFI query address looks different in below code and not as per ST make M29W128GH specs. PCIMW. static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; debug ("1__flash detect cfi\n"); /* We do not yet know what kind of commandset to use, so we issue the reset command in both Intel and AMD variants, in the hope that AMD flash roms ignore the Intel command. */ flash_write_cmd (info, 0, 0, AMD_CMD_RESET); flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); debug ("2__flash detect cfi\n"); for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); debug ("3__flash detect cfi\n"); if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); /* UART Output */ U-Boot 2009.08 (Jan 15 2010 - 16:44:40) DRAM: Meminfo.ptrCDBs: 0xc00174e0 512 MB (ECC is ON, 400 MHz, CL 7) Top of RAM usable for U-Boot at: 20000000 Reserving 174k for U-Boot at: 1ffd4000 Reserving 1040k for malloc() at: 1fed0000 Reserving 128 Bytes for Board Info at: 1fecff80 Reserving 64 Bytes for Global Data at: 1fecff40 Stack Pointer at: 1fecff28 New Stack Pointer is: 1fecff28 after watchdog reset after watchdog reset 2 after memcpy befor relocate addr_sp = 1fecff28, id = 1fecff40, addr = 1ffd4000 Now running in RAM - U-Boot at: 1ffd4000 FLASH: flash detect cfi 1__flash detect cfi fwc addr ff000000 cmd f0 f0 8bit x 8 bit Entering into First Write First Write is done fwc addr ff000000 cmd ff ff 8bit x 8 bit Entering into First Write First Write is done 2__flash detect cfi fwc addr ff000055 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 fwc addr ff000555 cmd 98 98 8bit x 8 bit Entering into First Write First Write is done 3__flash detect cfi is= cmd 51(Q) addr ff000010 is= ff 51 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 5151 1__flash detect cfi fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000000 cmd ff 00ff 16bit x 16 bit 2__flash detect cfi fwc addr ff0000aa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 fwc addr ff000aaa cmd 98 0098 16bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000020 is= ffff 0051 1__flash detect cfi fwc addr ff000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr ff000000 cmd ff ffffffff 32bit x 8 bit 2__flash detect cfi fwc addr ff000154 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 fwc addr ff001554 cmd 98 98989898 32bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 51515151 1__flash detect cfi fwc addr ff000000 cmd f0 00f000f0 32bit x 16 bit fwc addr ff000000 cmd ff 00ff00ff 32bit x 16 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 fwc addr ff001554 cmd 98 00980098 32bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00510051 1__flash detect cfi fwc addr ff000000 cmd f0 000000f0 32bit x 32 bit fwc addr ff000000 cmd ff 000000ff 32bit x 32 bit 2__flash detect cfi fwc addr ff000154 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 fwc addr ff001554 cmd 98 00000098 32bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000040 is= ffffffff 00000051 1__flash detect cfi fwrite addr ff000000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit fwrite addr ff000000 cmd ff ffffffffffffffff 64 bit x 8 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 fwrite addr ff002aa8 cmd 98 9898989898989898 64 bit x 8 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 5151515151515151 1__flash detect cfi fwrite addr ff000000 cmd f0 00f000f000f000f0 64 bit x 16 bit fwrite addr ff000000 cmd ff 00ff00ff00ff00ff 64 bit x 16 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 fwrite addr ff002aa8 cmd 98 0098009800980098 64 bit x 16 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0051005100510051 1__flash detect cfi fwrite addr ff000000 cmd f0 000000f0000000f0 64 bit x 32 bit fwrite addr ff000000 cmd ff 000000ff000000ff 64 bit x 32 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 fwrite addr ff002aa8 cmd 98 0000009800000098 64 bit x 32 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000005100000051 1__flash detect cfi fwrite addr ff000000 cmd f0 00000000000000f0 64 bit x 64 bit fwrite addr ff000000 cmd ff 00000000000000ff 64 bit x 64 bit 2__flash detect cfi fwrite addr ff0002a8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 fwrite addr ff002aa8 cmd 98 0000000000000098 64 bit x 64 bit 3__flash detect cfi is= cmd 51(Q) addr ff000080 is= ffffffffffffffff 0000000000000051 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFFFC0000 to 0xFFFE8AFF flash_protect ON: from 0xFFFA0000 to 0xFFFBFFFF *** failed *** ### ERROR ### Please RESET the board ### What should be the cause. It would be really helpful if someone who have face this kind of issues can give some inputs. TIA. Regards, Prakash

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[U-Boot] [RFC] CDC Ethernet support + USB Gadget in U-boot
by Remy Bohmer 19 Jan '12

19 Jan '12

Hello All, We (Thomas Smits and I) have been working on CDC Ethernet support in U-boot. We ported the Linux Gadget and CDC Ethernet driver to U-boot and added support for the Atmel AT91SAM9261-EK kit. Support for other cores can be added easily. Although it is still work in progress, it is already working stable. I also have a patch for adding RNDIS support on top of this series, but that is not finished/stable yet. The series is quite huge, and still in development, so I decided to not post this series inline. I made the tree public via the U-boot-usb tree, 'cdc' branch ( http://git.denx.de/?p=u-boot/u-boot-usb.git;a=shortlog;h=refs/heads/cdc) I would like to stabilise this code in a separate branch until it is mature enough for mainline integration, I will keep this branch always ahead mainline. So, any comments on this code are welcome! But, even more welcome are patches on top of it to make it even better and add more board support for it. Kind Regards, Remy

2 1

[U-Boot] Uboot for Mips
by Rahanesh 13 Sep '11

13 Sep '11

Hi All, I am currently working on MIPS board. I have a 32MB RAM. The address that is shown in uboot when i type bdinfo if 0x80000000 and size is 0x1000000(16MB). I want to increase the size to 32 MB as board has 32 MB RAM. Interesting Finding: When i write any data to 0x80000000 the same data is being written into 0x81000000. Same for all address in the range (data in 0x80000000 - 0x80ffffff is same as 0x81000000 - 0x81ffffff ). It seems that there is a dual mapping . What might be the reason? Please help -- View this message in context: http://www.nabble.com/Uboot-for-Mips-tp24366921p24366921.html Sent from the Uboot - Users mailing list archive at Nabble.com.

2 1

[U-Boot] Atmel AT91 USB DFU and USB device port driver
by Krishna Pattabiraman 12 Feb '11

12 Feb '11

Hi All, I am currently developing a USB DFU feature for at91sam9263 board. I have to develop the driver for USB device port. I looked the uboot-usb git cdc branch it has a at91_udc.c driver it doesnt contain the udc_* api implementations. I found a earlier post where it was discussed. http://www.mail-archive.com/u-boot@lists.denx.de/msg08709.html Can any point give me a pointer to implement it or the implementations if exist. Bye, Krishna.

3 4

[U-Boot] [PATCH] Clarify applicable licensing terms in COPYING file.
by Wolfgang Denk 09 Jan '11

09 Jan '11

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- COPYING | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/COPYING b/COPYING index f616ab9..9930863 100644 --- a/COPYING +++ b/COPYING @@ -1,4 +1,11 @@ - NOTE! This copyright does *not* cover the so-called "standalone" + U-Boot is free software. It is copyrighted by Wolfgang Denk and +many others who contributed code (see the actual source code for +details). You can redistribute U-Boot and/or modify it under the +terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 of the License (see text +below), or (at your option) any later version. + + NOTE! This license does *not* cover the so-called "standalone" applications that use U-Boot services by means of the jump table provided by U-Boot exactly for this purpose - this is merely considered normal use of U-Boot, and does *not* fall under the -- 1.6.2.5

2 5

[U-Boot] [PATCH] ppc4xx: Generic architecture for xilinx ppc405(v3)
by Ricardo Ribalda Delgado 24 Dec '10

24 Dec '10

As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)uam.es> --- v2 Includes changes propossed by Stefan Roese -Remove unneeded init.S -PPC404 ->PPC405 v3 rebased to ppc4xx/master CREDITS | 1 + MAINTAINERS | 1 + Makefile | 16 ++ board/xilinx/ppc405-generic/.gitignore | 1 + board/xilinx/ppc405-generic/Makefile | 60 ++++++++ board/xilinx/ppc405-generic/config.mk | 25 ++++ board/xilinx/ppc405-generic/u-boot-ram.lds | 134 ++++++++++++++++++ board/xilinx/ppc405-generic/u-boot-rom.lds | 144 ++++++++++++++++++++ .../xilinx/ppc405-generic/xilinx_ppc405_generic.c | 59 ++++++++ board/xilinx/ppc405-generic/xparameters.h | 36 +++++ cpu/ppc4xx/start.S | 3 +- include/configs/xilinx-ppc405-generic.h | 58 ++++++++ include/configs/xilinx-ppc405.h | 126 +++++++++++++++++ 13 files changed, 663 insertions(+), 1 deletions(-) create mode 100644 board/xilinx/ppc405-generic/.gitignore create mode 100644 board/xilinx/ppc405-generic/Makefile create mode 100644 board/xilinx/ppc405-generic/config.mk create mode 100644 board/xilinx/ppc405-generic/u-boot-ram.lds create mode 100644 board/xilinx/ppc405-generic/u-boot-rom.lds create mode 100644 board/xilinx/ppc405-generic/xilinx_ppc405_generic.c create mode 100644 board/xilinx/ppc405-generic/xparameters.h create mode 100644 include/configs/xilinx-ppc405-generic.h create mode 100644 include/configs/xilinx-ppc405.h diff --git a/CREDITS b/CREDITS index 3767322..9ddf0d2 100644 --- a/CREDITS +++ b/CREDITS @@ -407,6 +407,7 @@ N: Ricardo Ribalda Delgado E: ricardo.ribalda(a)uam.es D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval D: Virtex ppc440 generic architecture +D: Virtex ppc405 generic architecture W: http://www.ii.uam.es/~rribalda N: Stefan Roese diff --git a/MAINTAINERS b/MAINTAINERS index 60cb6a6..a5d1038 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -320,6 +320,7 @@ Ricardo Ribalda <ricardo.ribalda(a)uam.es> ml507 PPC440x5 v5fx30teval PPC440x5 xilinx-pp440-generic PPC440x5 + xilinx-pp405-generic PPC405 Stefan Roese <sr(a)denx.de> diff --git a/Makefile b/Makefile index fceb8a2..66922eb 100644 --- a/Makefile +++ b/Makefile @@ -1518,6 +1518,22 @@ sycamore_config: unconfig WUH405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd +xilinx-ppc405-generic_flash_config: unconfig + @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic + @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\ + > $(obj)board/xilinx/ppc405-generic/config.tmp + @echo "TEXT_BASE := 0xFE360000" \ + >> $(obj)board/xilinx/ppc405-generic/config.tmp + @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx + +xilinx-ppc405-generic_config: unconfig + @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic + @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\ + > $(obj)board/xilinx/ppc405-generic/config.tmp + @echo "TEXT_BASE := 0x04000000" \ + >> $(obj)board/xilinx/ppc405-generic/config.tmp + @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx + xilinx-ppc440-generic_flash_config: unconfig @mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\ diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore new file mode 100644 index 0000000..b644f59 --- /dev/null +++ b/board/xilinx/ppc405-generic/.gitignore @@ -0,0 +1 @@ +config.tmp diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile new file mode 100644 index 0000000..b56bb49 --- /dev/null +++ b/board/xilinx/ppc405-generic/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +endif + +INCS := +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ppc405-generic/config.mk b/board/xilinx/ppc405-generic/config.mk new file mode 100644 index 0000000..6d76755 --- /dev/null +++ b/board/xilinx/ppc405-generic/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp diff --git a/board/xilinx/ppc405-generic/u-boot-ram.lds b/board/xilinx/ppc405-generic/u-boot-ram.lds new file mode 100644 index 0000000..0004d61 --- /dev/null +++ b/board/xilinx/ppc405-generic/u-boot-ram.lds @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ppc405-generic/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds new file mode 100644 index 0000000..d2bac9f --- /dev/null +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start) + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c new file mode 100644 index 0000000..9bd1770 --- /dev/null +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +ulong __get_PCI_freq(void) +{ + return 0; +} + +ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC405 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 0000000..e8e8ced --- /dev/null +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 31902a0..882ef21 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -918,7 +918,8 @@ _start: ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l mtdccr r4 -#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) +#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ + && !defined (CONFIG_XILINX_405) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ diff --git a/include/configs/xilinx-ppc405-generic.h b/include/configs/xilinx-ppc405-generic.h new file mode 100644 index 0000000..5036c62 --- /dev/null +++ b/include/configs/xilinx-ppc405-generic.h @@ -0,0 +1,58 @@ +/* + * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt <schardt(a)team-ctech.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_GEN_H +#define __CONFIG_GEN_H + +#include "../board/xilinx/ppc405-generic/xparameters.h" + +/* sdram */ +#define CONFIG_SYS_SDRAM_SIZE_MB 256 + +/* environment */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_SYS_ENV_OFFSET 0x3F0000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET) +#define CONFIG_ENV_OVERWRITE 1 + +/*Misc*/ +#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CONFIG_SYS_FLASH_SIZE (32*1024*1024) +#define CONFIG_SYS_MAX_FLASH_SECT 71 +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define MTDIDS_DEFAULT "nor0=ppc405-flash" +#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)" + +#include <configs/xilinx-ppc405.h> +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc405.h b/include/configs/xilinx-ppc405.h new file mode 100644 index 0000000..7458470 --- /dev/null +++ b/include/configs/xilinx-ppc405.h @@ -0,0 +1,126 @@ +/* + * + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda(a)uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * (C) Copyright 2008 + * Georg Schardt <schardt(a)team-ctech.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* cpu parameter */ +#define CONFIG_4xx 1 +#define CONFIG_405 1 +#define CONFIG_XILINX_405 1 + +/* memory map */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* u-boot commands configuration */ +#include <config_cmd_default.h> + +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + /* Initial Memory map for Linux */ +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_CACHELINE_SHIFT 2 + +/* stack */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ +#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_FLASH_CF 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_PROTECTION + +/* serial communication */ +#ifdef XPAR_UARTLITE_0_BASEADDR +#define CONFIG_XILINX_UARTLITE +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } +#else +#ifdef XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR +#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 } +#endif +#endif + +/* cmd config */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +#endif -- 1.5.6.5

4 5

[U-Boot] [STATUS] v2009.08-rc3 is out
by Wolfgang Denk 22 Dec '10

22 Dec '10

Hi everybody... v2009.08-rc3 has just been released. Please help testing, and submit fixes to the remaining problems. Things still missing should be submitted ASAP. * Many boards now throw the (expected) #warning Ethernet driver is deprecated. Please update to use CONFIG_NET_MULTI messages. * ARM, MIPS and PowerPC: mostly compile clean; there are a few issues (mostly harmless) - responsibles have been notified Comments and fixes welcome. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de 'What shall we do?' said Twoflower. 'Panic?' said Rincewind hope- fully. He always held that panic was the best means of survival; back in the olden days, his theory went, people faced with hungry sabre- toothed tigers could be divided very simply in those who panicked and those who stood there saying 'What a magnificent brute!' or 'Here, pussy.' - Terry Pratchett, _The Light Fantastic_

5 10

[U-Boot] [PATCH] Remove duplicate #defines in atngw100.h and mimc200.h
by Semih Hazar 28 Nov '10

28 Nov '10

Two configuration include files had duplicate CONFIG_DOS_PARTITION definitions with the same value. This patch does not effect anything, just trims unnecessary text. Signed-off-by: Semih Hazar <semih.hazar(a)indefia.com> --- include/configs/atngw100.h | 2 -- include/configs/mimc200.h | 2 -- 2 files changed, 0 insertions(+), 4 deletions(-) diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 4ed5514..5066448 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -101,8 +101,6 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_GATEWAY -#define CONFIG_DOS_PARTITION 1 - /* * Command line configuration. */ diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 8ff2f8a..b2cb206 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -104,8 +104,6 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_GATEWAY -#define CONFIG_DOS_PARTITION 1 - /* * Command line configuration. */ -- 1.5.4.3

2 1

[U-Boot] Hanging in kmalloc of nand_scan_tail() function
by J.Hwan.Kim 15 Nov '10

15 Nov '10

Hi, everyone I'm using U-boot 2009-03. U-boot hangs in nand_init() function. I found the routine kmalloc in nand_scan_tail() cause U-boot reset. int nand_scan_tail(struct mtd_info *mtd) { int i; struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_OWN_BUFFERS)) { chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); } if (!chip->buffers) return -ENOMEM; ........ U-boot displays message as follows : NAND: data abort pc : [<31f902b4>]\0x09 lr : [<31fa084c>] sp : 31f5bee0 ip : 00000076\0x09 fp : 00000000 r10: 00001188 r9 : 00020000\0x09 r8 : 31f5bfdc r7 : 00000001 r6 : 00000000\0x09 r5 : 31fa42b8 r4 : 31fa4364 r3 : 31fa052c r2 : 00000064\0x09 r1 : 00000063 r0 : ffffffff Flags: NzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Where the malloc function is defined? Why the kmalloc() hangs the u-boot? Is there any configuation definition needed? Thanks in advance. Regards, J.Hwan Kim

4 10

[U-Boot] Is the Numonyx's M29W128 fully supported in U-Boot?
by txema lopez 28 Oct '10

28 Oct '10

Hi all, We have a MPC5200B custom board and we are evaluating the Numonyx M29W128 Flash as a second source for the Spansion's S29GL128. I've checked the top of the tree version of the U-Boot (u-boot.git) CFI driver and the Numonyx Flash is not detected. This is the U-Boot debug output: FLASH: flash detect cfi fwc addr fe000000 cmd f0 f0 8bit x 8 bit fwc addr fe000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fe000010 is= 0 51 fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5100 5151 fwc addr fe000000 cmd f0 00f0 16bit x 16 bit fwc addr fe0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr fe000020 is= 6d69 0051 fwc addr fe000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr fe000154 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 51515151 fwc addr fe000000 cmd f0 00f000f0 32bit x 16 bit fwc addr fe000154 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 00510051 fwc addr fe000000 cmd f0 000000f0 32bit x 32 bit fwc addr fe000154 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 00000051 fwrite addr fe000000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit fwrite addr fe0002a8 cmd 98 9898989898989898 64 bit x 8 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 5151515151515151 fwrite addr fe000000 cmd f0 00f000f000f000f0 64 bit x 16 bit fwrite addr fe0002a8 cmd 98 0098009800980098 64 bit x 16 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0051005100510051 fwrite addr fe000000 cmd f0 000000f0000000f0 64 bit x 32 bit fwrite addr fe0002a8 cmd 98 0000009800000098 64 bit x 32 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0000005100000051 fwrite addr fe000000 cmd f0 00000000000000f0 64 bit x 64 bit fwrite addr fe0002a8 cmd 98 0000000000000098 64 bit x 64 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0000000000000051 not found ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB This is the debug output for the Spansion Flash that works fine. FLASH: flash detect cfi fwc addr fe000000 cmd f0 f0 8bit x 8 bit fwc addr fe000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fe000010 is= 0 51 fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5151 5151 is= cmd 52(R) addr fe000022 is= 5252 5252 is= cmd 59(Y) addr fe000024 is= 5959 5959 ushort addr is at fe000050 info->portwidth = 2 addr[0] = 0x2 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 1 port 16 bits chip 8 bits ushort addr is at fe000026 info->portwidth = 2 addr[0] = 0x2 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fe000020 : 51 51 52 52 59 59 02 02 00 00 40 40 00 00 00 00 QQRRYY....@@.... fe000030 : 00 00 00 00 00 00 27 27 36 36 00 00 00 00 06 06 ......''66...... fe000040 : 06 06 09 09 13 13 03 03 05 05 03 03 02 02 18 18 ................ fe000050 : 02 02 00 00 06 06 00 00 01 01 7f 7f 00 00 00 00 ................ fe000060 : 02 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fe000070 : 00 00 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ................ fe000080 : 50 50 52 52 49 49 31 31 33 33 14 14 02 02 01 01 PPRRII1133...... fe000090 : 00 00 08 08 00 00 00 00 02 02 b5 b5 c5 c5 04 04 ................ manufacturer is 2 size_ratio 1 port 16 bits chip 8 bits found 1 erase regions long addr is at fe00005a info->portwidth = 2 addr[0] = 0x7f addr[1] = 0x7f addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x2 addr[7] = 0x2 erase_region_count = 128 erase_region_size = 131072 ushort addr is at fe000054 info->portwidth = 2 addr[0] = 0x6 addr[1] = 0x6 addr[2] = 0x0 addr[3] = 0x0 retval = 0x6 So the problem seems to be that the Numonyx Flash do not put the CFI query information in the odd bytes as you can see here: fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5100 5151 I've checked the U-Boot mainling list and I've found only something about a M29W128 bug but in a coldfire architecture. So I think the Numonyx Flash has been tested in some boards but I don't knwon if there is full support in U-Boot for it. If not, is there a patch available or in process? Any clue will be welcomed. TIA,

3 5

[U-Boot] [PATCH] cmd_elf: CONFIG_ELF_SIMPLE_LOAD: load ELFs according to PHDRs
by Mike Frysinger 06 Oct '10

06 Oct '10

The current ELF loading function does a lot of work above and beyond a simple "loading". It ignores the real load addresses and loads things into their virtual (runtime) address. This is undesirable when we just want it to load an ELF and let the ELF do the actual C runtime init. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_elf.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 3ebb6d9..7b82749 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -276,6 +276,32 @@ int valid_elf_image (unsigned long addr) * A very simple elf loader, assumes the image is valid, returns the * entry point address. * ====================================================================== */ +#ifdef CONFIG_ELF_SIMPLE_LOAD +unsigned long load_elf_image (unsigned long addr) +{ + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + unsigned long entry; + size_t i; + + ehdr = (Elf32_Ehdr *) addr; + phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); + + entry = ehdr->e_entry; + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *) phdr->p_paddr; + void *src = (void *) addr + phdr->p_offset; + printf ("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + memcpy (dst, src, phdr->p_filesz); + ++phdr; + } + + return entry; +} +#else unsigned long load_elf_image (unsigned long addr) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ @@ -327,6 +353,7 @@ unsigned long load_elf_image (unsigned long addr) return ehdr->e_entry; } +#endif /* ====================================================================== */ U_BOOT_CMD( -- 1.6.0.3

2 5

[U-Boot-Users] how to u-boot in LPC2468 board using uClinux
by anand 28 Sep '10

28 Sep '10

do any one have u-boot.bin file for LPC2468 i downloaded u-boot-1.1.6 but i din't get the u-boot prombt in the terminal window its gets struck in the starting display itself anyone pls help thanks in advance

3 2

[U-Boot-Users] [PATCH, resend] Support dynamic/patched NAND ENV offset
by Harald Welte 18 Sep '10

18 Sep '10

Hi! I've first sent this on Feb 17, 2007. Unfortunately no reply was received. I think this is a quite useful feature, since a compile time offset into the NAND flash for the environment just doesn't work well with bad blocks ;) This is the current version of the patch. I'd love to see it included. Thanks! --- This patch adds support for CFG_ENV_OFFSET_PATCHED and CFG_ENV_OFFSET_OOB. Both try to solve the problem of fixing the environment location in NAND flash at compile time, which doesn't work well if the NAND flash has a bad block at exactly that location. CFG_ENV_OFFSET_PATCHED puts the environment in a global variable. You can then use the linker script to put that variable to a fixed location in the u-boot image. Then you can use bianry patching during the production flash process. The idea of CFG_ENV_OFFSET_OOB is to store the environment offset in the NAND OOB data of block 0. We can do this in case the vendor makes a guarantee that block 0 never is a factory-default bad block. Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/common/Makefile =================================================================== --- u-boot.orig/common/Makefile +++ u-boot/common/Makefile @@ -55,6 +55,7 @@ COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o +COBJS-y += cmd_dynenv.o COBJS-y += cmd_eeprom.o COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o Index: u-boot/common/cmd_dynenv.c =================================================================== --- /dev/null +++ u-boot/common/cmd_dynenv.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2006-2007 OpenMoko, Inc. + * Author: Harald Welte <laforge(a)openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <environment.h> +#include <nand.h> +#include <asm/errno.h> +#include "cmd_nand.h" + +#if defined(CFG_ENV_OFFSET_OOB) + +int do_dynenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct mtd_info *mtd = &nand_info[0]; + int ret, size = 8; + uint8_t *buf; + + char *cmd = argv[1]; + + buf = malloc(mtd->oobsize); + if (!buf) + return -ENOMEM; + + ret = mtd->read_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + if (!strcmp(cmd, "get")) { + + if (buf[0] == 'E' && buf[1] == 'N' && + buf[2] == 'V' && buf[3] == '0') + printf("0x%08x\n", *((u_int32_t *) &buf[4])); + else + printf("No dynamic environment marker in OOB block 0\n"); + + } else if (!strcmp(cmd, "set")) { + unsigned long addr, dummy; + + if (argc < 3) + goto usage; + + buf[0] = 'E'; + buf[1] = 'N'; + buf[2] = 'V'; + buf[3] = '0'; + + if (arg_off_size(argc-2, argv+2, mtd, &addr, &dummy) < 0) { + printf("Offset or partition name expected\n"); + goto fail; + } + if (!ret) { + uint8_t tmp[4]; + int i; + + memcpy(&tmp, &addr, 4); + for (i = 0; i != 4; i++) + if (tmp[i] & ~buf[i+4]) { + printf("ERROR: erase OOB block to " + "write this value\n"); + goto fail; + } + } + memcpy(buf+4, &addr, 4); + + printf("%02x %02x %02x %02x - %02x %02x %02x %02x\n", + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + ret = mtd->write_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + if (!ret) + CFG_ENV_OFFSET = addr; + } else + goto usage; + + free(buf); + return ret; + +usage: + printf("Usage:\n%s\n", cmdtp->usage); +fail: + free(buf); + return 1; +} + +U_BOOT_CMD(dynenv, 3, 1, do_dynenv, + "dynenv - dynamically placed (NAND) environment\n", + "dynenv set off - set enviromnent offset\n" + "dynenv get - get environment offset\n"); + +#endif /* CFG_ENV_OFFSET_OOB */ Index: u-boot/common/env_nand.c =================================================================== --- u-boot.orig/common/env_nand.c +++ u-boot/common/env_nand.c @@ -292,6 +292,33 @@ int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1, *tmp_env2; +#if defined(CFG_ENV_OFFSET_OOB) + struct mtd_info *mtd = &nand_info[0]; + struct nand_chip *this = mtd->priv; + int buf_len; + uint8_t *buf; + + buf_len = (1 << this->bbt_erase_shift); + buf_len += (buf_len >> this->page_shift) * mtd->oobsize; + buf = malloc(buf_len); + if (!buf) + return; + + nand_read_raw(mtd, buf, 0, mtd->oobblock, mtd->oobsize); + if (buf[mtd->oobblock + 8 + 0] == 'E' && + buf[mtd->oobblock + 8 + 1] == 'N' && + buf[mtd->oobblock + 8 + 2] == 'V' && + buf[mtd->oobblock + 8 + 3] == '0') { + CFG_ENV_OFFSET = *((unsigned long *) &buf[mtd->oobblock + 8 + 4]); + /* fall through to the normal environment reading code below */ + free(buf); + puts("Found Environment offset in OOB..\n"); + } else { + free(buf); + return use_default(); + } +#endif + total = CFG_ENV_SIZE; tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); Index: u-boot/common/environment.c =================================================================== --- u-boot.orig/common/environment.c +++ u-boot/common/environment.c @@ -29,6 +29,12 @@ #undef __ASSEMBLY__ #include <environment.h> +#if defined(CFG_ENV_OFFSET_PATCHED) +unsigned long env_offset = CFG_ENV_OFFSET_PATCHED; +#elif defined(CFG_ENV_OFFSET_OOB) +unsigned long env_offset = CFG_ENV_OFFSET_OOB; +#endif + /* * Handle HOSTS that have prepended * crap on symbol names, not TARGETS. Index: u-boot/include/environment.h =================================================================== --- u-boot.orig/include/environment.h +++ u-boot/include/environment.h @@ -70,6 +70,10 @@ #endif /* CFG_ENV_IS_IN_FLASH */ #if defined(CFG_ENV_IS_IN_NAND) +#if defined(CFG_ENV_OFFSET_PATCHED) || defined(CFG_ENV_OFFSET_OOB) +extern unsigned long env_offset; +#define CFG_ENV_OFFSET env_offset +#else # ifndef CFG_ENV_OFFSET # error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND" # endif @@ -82,6 +86,7 @@ # ifdef CFG_ENV_IS_EMBEDDED # define ENV_IS_EMBEDDED 1 # endif +#endif /* CFG_ENV_NAND_PATCHED */ #endif /* CFG_ENV_IS_IN_NAND */ #ifdef USE_HOSTCC Index: u-boot/common/cmd_nand.h =================================================================== --- /dev/null +++ u-boot/common/cmd_nand.h @@ -0,0 +1,33 @@ +/* + * cmd_nand.h - Convenience functions + * + * (C) Copyright 2006-2007 OpenMoko, Inc. + * Author: Werner Almesberger <werner(a)openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef CMD_NAND_H +#define CMD_NAND_H + +#include <nand.h> + + +/* common/cmd_nand.c */ +int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, + ulong *size); + +#endif /* CMD_NAND_H */ Index: u-boot/common/cmd_nand.c =================================================================== --- u-boot.orig/common/cmd_nand.c +++ u-boot/common/cmd_nand.c @@ -90,7 +90,7 @@ return (*p != '\0' && *endptr == '\0') ? 1 : 0; } -static int +int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size) { int idx = nand_curr_device; -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

7 98

[U-Boot] [PATCH] Support for Calao USB A9263 board based on AT91SAM9263 CPU
by Thomas Petazzoni 20 Aug '10

20 Aug '10

The Calao USB A9263 board is a board manufactured and sold by Calao Systems <http://www.calao-systems.com>. Its components are very similar to the AT91SAM9263EK board, so its configuration is based on the configuration of this board. There are however some differences: different clocks, no LCD, etc. Signed-off-by: Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/calao/usb-a9263/Makefile | 58 ++++++++++++ board/calao/usb-a9263/config.mk | 24 +++++ board/calao/usb-a9263/partition.c | 38 ++++++++ board/calao/usb-a9263/usb-a9263.c | 185 +++++++++++++++++++++++++++++++++++++ include/configs/usb-a9263.h | 183 ++++++++++++++++++++++++++++++++++++ 8 files changed, 496 insertions(+), 0 deletions(-) create mode 100644 board/calao/usb-a9263/Makefile create mode 100644 board/calao/usb-a9263/config.mk create mode 100644 board/calao/usb-a9263/partition.c create mode 100644 board/calao/usb-a9263/usb-a9263.c create mode 100644 include/configs/usb-a9263.h diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d..03f990c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -667,6 +667,10 @@ Peter Pearse <peter.pearse(a)arm.com> versatile ARM926EJ-S versatile ARM926EJ-S +Thomas Petazzoni <thomas.petazzoni(a)free-electrons.com> + + usb-a9263 ARM926EJS (AT91SAM9263 SoC) + Dave Peverley <dpeverley(a)mpc-data.co.uk> omap730p2 ARM926EJS diff --git a/MAKEALL b/MAKEALL index ab1bb6f..99ce563 100755 --- a/MAKEALL +++ b/MAKEALL @@ -657,6 +657,7 @@ LIST_at91=" \ SBC35_A9G20 \ TNY_A9260 \ TNY_A9G20 \ + usb9263 \ " ######################################################################### diff --git a/Makefile b/Makefile index ed6156f..d5b7f76 100644 --- a/Makefile +++ b/Makefile @@ -2874,6 +2874,9 @@ TNY_A9260_config : unconfig @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h @$(MKCONFIG) -a tny_a9260 arm arm926ejs tny_a9260 calao at91 +usb_a9263_config : unconfig + $(MKCONFIG) -a usb-a9263 arm arm926ejs usb-a9263 calao at91 + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/calao/usb-a9263/Makefile b/board/calao/usb-a9263/Makefile new file mode 100644 index 0000000..ec79872 --- /dev/null +++ b/board/calao/usb-a9263/Makefile @@ -0,0 +1,58 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop(a)leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# (C) Copyright 2009 +# Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += usb-a9263.o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/usb-a9263/config.mk b/board/calao/usb-a9263/config.mk new file mode 100644 index 0000000..2724a7d --- /dev/null +++ b/board/calao/usb-a9263/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2009 +# Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x23f00000 diff --git a/board/calao/usb-a9263/partition.c b/board/calao/usb-a9263/partition.c new file mode 100644 index 0000000..614ef0d --- /dev/null +++ b/board/calao/usb-a9263/partition.c @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2008-2009 + * Ulf Samuelsson <ulf(a)atmel.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/board/calao/usb-a9263/usb-a9263.c b/board/calao/usb-a9263/usb-a9263.c new file mode 100644 index 0000000..ca66f01 --- /dev/null +++ b/board/calao/usb-a9263/usb-a9263.c @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2007-2009 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/sizes.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/at91sam9263_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void usb_a9263_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOCDE); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void usb_a9263_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUDR); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PC25), + pin_to_controller(AT91_PIN_PC0) + PIO_PUER); + writel(pin_to_mask(AT91_PIN_PE25) | + pin_to_mask(AT91_PIN_PE26), + pin_to_controller(AT91_PIN_PE0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of USB-A9263-Board */ + gd->bd->bi_arch_number = MACH_TYPE_USB_A9263; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + usb_a9263_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */ + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + usb_a9263_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size((long*) PHYS_SDRAM, + PHYS_SDRAM_SIZE); + if (gd->bd->bi_dram[0].size != PHYS_SDRAM_SIZE) + return -1; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/include/configs/usb-a9263.h b/include/configs/usb-a9263.h new file mode 100644 index 0000000..aa398aa --- /dev/null +++ b/include/configs/usb-a9263.h @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2007-2009 + * Stelian Pop <stelian.pop(a)leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Thomas Petazzoni, Free Electrons, <thomas.petazzoni(a)free-electrons.com> + * + * Configuration settings for the Calao USB-A9263 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/at91sam9263.h> + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_CALAO_USB_A9263 1 /* on an Calao USB A 9263 Board */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#undef CONFIG_LCD + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 8000000 +#define DATAFLASH_TCSS (0x1c << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* no NOR flash */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91SAM9263_UHP_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0) +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_BOOTCOMMAND "nboot 21000000 0" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:2m(kernel)ro,-(root) "\ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, \ + 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- 1.6.3.3

2 1

[U-Boot] [PATCH v2] AT91: Add SD/MMC controller support
by Albin Tonnerre 26 May '10

26 May '10

This patch allows to use the atmel_mci SD/MMC driver on the at91 architecture. It contains: - initialization code for the MCI controller for all the supported AT91. It allows the use of only one controller even if a SoC has two controllers (anyway there's no support for it in atmel_mci as of now) - the necessary get_mci_clk_rate function - definition of MMCI_BASE for use in atmel_mci - the cpu_mmc_init function. As of now this is not used, but will be required when atmel_mci is ported to the new generic mmc API. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- Changes since v1 (http://lists.denx.de/pipermail/u-boot/2009-September/059665.html): - Fix the MCI controller ID in the init code for CAP9, SAM9263 and SAM9G45 - Move AT91_BASE_MCI* define to soc header - define AT91_BASE_MCI{0,1} instead of AT91_BASE_MCI for boards which have 2 controllers - rework the way MMCI_BASE is defined accordingly Note: I am fully aware that MMCI0_BASE and MMCI1_BASE should be defined, instead of MMCI_BASE. However, I'd rather wait until the patch that switches atmel_mci to the generic mmc API is accepted, as it will be easier to do it then. cpu/arm926ejs/at91/at91cap9_devices.c | 37 ++++++++++++++++++ cpu/arm926ejs/at91/at91sam9260_devices.c | 27 +++++++++++++ cpu/arm926ejs/at91/at91sam9261_devices.c | 18 +++++++++ cpu/arm926ejs/at91/at91sam9263_devices.c | 55 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 55 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9rl_devices.c | 22 +++++++++++ cpu/arm926ejs/at91/cpu.c | 7 +++ include/asm-arm/arch-at91/at91_common.h | 2 + include/asm-arm/arch-at91/at91cap9.h | 3 + include/asm-arm/arch-at91/at91sam9260.h | 2 + include/asm-arm/arch-at91/at91sam9261.h | 1 + include/asm-arm/arch-at91/at91sam9263.h | 3 + include/asm-arm/arch-at91/at91sam9g45.h | 3 + include/asm-arm/arch-at91/at91sam9rl.h | 1 + include/asm-arm/arch-at91/clk.h | 5 ++ include/asm-arm/arch-at91/memory-map.h | 6 +++ 16 files changed, 247 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..53a58a9 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -79,6 +79,43 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA16, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA17, 1); + at91_set_A_periph(AT91_PIN_PA18, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + at91_set_A_periph(AT91_PIN_PA21, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index f86cb99..ea22030 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -75,6 +75,33 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA8, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_A_periph(AT91_PIN_PA7, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..7ee573c 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -75,6 +75,24 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_MCI); + at91_set_B_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA6, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..6a89fab 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -79,6 +79,61 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA21, 1); + at91_set_B_periph(AT91_PIN_PA22, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA23, 1); + at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_B_periph(AT91_PIN_PA25, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..c4db5f4 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -75,6 +75,61 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..41ae4a8 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -75,6 +75,28 @@ void at91_serial_hw_init(void) #endif } +/* + * The AT91SAM9RL64 is said to have 2 slots, but the datasheet doesn't + * seem to mention to what pins the second slot is assigned + */ +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..f96b715 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -52,3 +52,10 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_GENERIC_MMC +int cpu_mmc_init(bd_t *bis) +{ + atmel_mci_init(bis); +} +#endif /* GENERIC_MMC */ diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h index 01840ee..01fcdd6 100644 --- a/include/asm-arm/arch-at91/at91_common.h +++ b/include/asm-arm/arch-at91/at91_common.h @@ -32,6 +32,8 @@ void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); void at91_serial3_hw_init(void); +void at91_mci0_hw_init(unsigned long mask); +void at91_mci1_hw_init(unsigned long mask); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index b128ac5..2ad3280 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -109,6 +109,9 @@ #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 +#define AT91_BASE_MCI0 AT91CAP9_BASE_MCI0 +#define AT91_BASE_MCI1 AT91CAP9_BASE_MCI1 + /* * SCKCR flags */ diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 73975f4..b92f0ee 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -105,6 +105,8 @@ #define AT91_USART4 AT91SAM9260_BASE_US4 #define AT91_USART5 AT91SAM9260_BASE_US5 +#define AT91_BASE_MCI0 AT91SAM9260_BASE_MCI + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index b303e07..11fdc3e 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -88,6 +88,7 @@ #define AT91_USART1 AT91SAM9261_BASE_US1 #define AT91_USART2 AT91SAM9261_BASE_US2 +#define AT91_BASE_MCI0 AT91SAM9261_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 966a683..6bf124b 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -108,6 +108,9 @@ #define AT91_SMC AT91_SMC0 #define AT91_SDRAMC AT91_SDRAMC0 +#define AT91_BASE_MCI0 AT91SAM9263_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9263_BASE_MCI1 + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index 0feed9c..16deadc 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -114,6 +114,9 @@ #define AT91_USART2 AT91SAM9G45_BASE_US2 #define AT91_USART3 AT91SAM9G45_BASE_US3 +#define AT91_BASE_MCI0 AT91SAM9G45_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9G45_BASE_MCI1 + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 4dd8037..f0da7a2 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -99,6 +99,7 @@ #define AT91_USART2 AT91SAM9RL_BASE_US2 #define AT91_USART3 AT91SAM9RL_BASE_US3 +#define AT91_BASE_MCI0 AT91SAM9RL_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index f642dd9..457e6c9 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index f605f37..445d128 100644 --- a/include/asm-arm/arch-at91/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h @@ -32,4 +32,10 @@ #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) #define SPI0_BASE AT91_BASE_SPI +#ifndef (CONFIG_AT91_MCI1) +# define MMCI_BASE AT91_BASE_MCI0 +#else +# define MMCI_BASE AT91_BASE_MCI1 +#endif + #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ -- 1.6.3.3

5 10

[U-Boot] Fwd: TI:OMAP: [PATCH 5/7] Add DSS driver for OMAP3
by Khasim Syed Mohammed 13 May '10

13 May '10

On Sun, Jan 24, 2010 at 5:48 AM, Tom <Tom.Rix(a)windriver.com> wrote: > Khasim Syed Mohammed wrote: >> >> From cf8fa28973de7609d27146730d9e019b7c919b51 Mon Sep 17 00:00:00 2001 >> From: Syed Mohammed Khasim <khasim(a)ti.com> >> Date: Tue, 12 Jan 2010 23:57:28 +0530 >> Subject: [PATCH] Add DSS driver for OMAP3 >> >> Supports dynamic panel configuration >> Supports dynamic tv standard selection >> Adds support for DSS register access through generic APIs >> >> Incorporated DSS register access using structures. >> >> Previous discussions are here >> http://www.mail-archive.com/u-boot@lists.denx.de/msg27150.html >> >> Signed-off-by: Syed Mohammed Khasim <khasim(a)ti.com> >> --- >> drivers/video/Makefile | 1 + >> drivers/video/omap3_dss.c | 130 ++++++++++++++++++++++++++++ >> include/asm-arm/arch-omap3/dss.h | 173 >> ++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 304 insertions(+), 0 deletions(-) >> create mode 100644 drivers/video/omap3_dss.c >> create mode 100644 include/asm-arm/arch-omap3/dss.h >> >> diff --git a/drivers/video/Makefile b/drivers/video/Makefile >> index bb6b5a0..cb15dc2 100644 >> --- a/drivers/video/Makefile >> +++ b/drivers/video/Makefile >> @@ -37,6 +37,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o >> COBJS-$(CONFIG_VIDEO_SM501) += sm501.o >> COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o >> COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o >> +COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o > > Alphabetical order Sure > >> COBJS-y += videomodes.o >> >> COBJS := $(COBJS-y) >> diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c >> new file mode 100644 >> index 0000000..69c705a >> --- /dev/null >> +++ b/drivers/video/omap3_dss.c >> @@ -0,0 +1,130 @@ >> +/* >> + * (C) Copyright 2010 >> + * Texas Instruments, <www.ti.com> >> + * Syed Mohammed Khasim <khasim(a)ti.com> >> + * >> + * Referred to Linux DSS driver files for OMAP3 >> + * >> + * See file CREDITS for list of people who contributed to this >> + * project. >> + * >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation's version 2 of >> + * the License. > > This needs an - or later - > http://www.denx.de/wiki/U-Boot/Patches > Similar problem below. > >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * > > <snip> Sure > >> + * You should have received a copy of the GNU General Public License >> + * along with this program; if not, write to the Free Software >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, >> + * MA 02111-1307 USA >> + */ >> + > > >> +#include <common.h> >> new file mode 100644 >> index 0000000..e5e3b0d >> --- /dev/null >> +++ b/include/asm-arm/arch-omap3/dss.h >> @@ -0,0 +1,173 @@ >> +/* >> + * (C) Copyright 2010 >> + * Texas Instruments, <www.ti.com> >> + * Syed Mohammed Khasim <khasim(a)ti.com> >> + * >> + * Referred to Linux DSS driver files for OMAP3 >> + * >> + * See file CREDITS for list of people who contributed to this >> + * project. >> + * >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation's version 2 of >> + * the License. > > Similar license > - or later - Sure > >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License >> + * along with this program; if not, write to the Free Software >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, >> + * MA 02111-1307 USA >> + */ >> + >> +#ifndef DSS_H >> +#define DSS_H >> + >> +/* >> + * DSS Base Registers >> + */ >> +#define OMAP3_DSS_BASE 0x48050040 >> +#define OMAP3_DISPC_BASE 0x48050440 >> +#define OMAP3_VENC_BASE 0x48050C00 >> + >> +/* DSS Registers */ >> +struct dss_regs { >> + u32 control; /* 0x40 */ > > Add a comment to explain why base starts at 0x40 > could also be handled with changing code > OMAP3_DSS_BASE 0x48050000 > struct dss_regs { > u8 reserved_1[0x40]; > .. may be,.. let me try. > >> + u32 sdi_control; /* 0x44 */ >> + u32 pll_control; /* 0x48 */ >> +}; >> + >> +/* DISPC Registers */ >> +struct dispc_regs { > > similar ok > >> + u32 control; /* 0x40 */ > > Tom Thanks for very detailed review. Mainly Licensing. Regards, Khasim

4 3

[U-Boot] [PATCH 01/17] SPARC: added unaligned definitions, patch supplied by Magnus Sjalander.
by Daniel Hellstrom 06 May '10

06 May '10

Signed-off-by: Daniel Hellstrom <daniel(a)gaisler.com> --- include/asm-sparc/unaligned.h | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) create mode 100644 include/asm-sparc/unaligned.h diff --git a/include/asm-sparc/unaligned.h b/include/asm-sparc/unaligned.h new file mode 100644 index 0000000..4e604c1 --- /dev/null +++ b/include/asm-sparc/unaligned.h @@ -0,0 +1,17 @@ +#ifndef _ASM_SPARC_UNALIGNED_H +#define _ASM_SPARC_UNALIGNED_H + +#ifdef __KERNEL__ + +/* + * The SPARC can not do unaligned accesses, it must be split into multiple + * byte accesses. The SPARC is in big endian mode. + */ +#include <linux/unaligned/be_byteshift.h> +#include <linux/unaligned/generic.h> + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#endif /* __KERNEL__ */ +#endif /* _ASM_SPARC_UNALIGNED_H */ -- 1.5.4

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[U-Boot] [PATCH] Add Yaffs2 image writing support.
by Li Wenhao 10 Apr '10

10 Apr '10

Signed-off-by: Li Wenhao <liwenhao.g(a)gmail.com> --- common/cmd_nand.c | 21 +++++++++++++++++++++ 1 files changed, 21 insertions(+), 0 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 075a8af..38c6480 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -390,6 +390,27 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ret = nand->read_oob(nand, off, &ops); else ret = nand->write_oob(nand, off, &ops); + } else if (!strcmp(s, ".yaffs2") && !read) { + mtd_oob_ops_t ops = { + .mode = MTD_OOB_AUTO, + .len = 2048, /* page size */ + .ooblen = 64, /* spare size */ + }; + + ulong page = 0; + ulong block_size = ops.len + ops.ooblen; + while (page * block_size < size) { + ops.datbuf = addr + page * block_size; + ops.oobbuf = ops.datbuf + ops.len; + + ret = nand->write_oob(nand, + off + page * ops.len, + &ops); + + if (ret) break; + + page++; + } } else { printf("Unknown nand command suffix '%s'.\n", s); return 1; -- 1.6.3.3

4 4