December 2010 - U-Boot

[U-Boot] [PATCH v3] ftgmac100: support of gigabit eth ftgmac100
by Macpaul Lin 09 Jan '11

09 Jan '11

Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Coding Style cleanup - Makefile Order sorted - Volatile statement eliminated - Error handling added - Autonegotiation timeout value rechecked - Link speed detection code is reduced - Logic of autonegotiation and Link speed update reorganized - Redundent registers offset table cleared - The explaination of sub configuration of this driver has moved into README Changes for v3: - Coding Style clean up about - 2 continue blank line - incorrect multi-line comment style - useless else statement and return value statement - make multi-line statement into single line which doesn't exceed 80 chars - brance with multi-line statement (comments included before one line code) README | 12 + drivers/net/Makefile | 1 + drivers/net/ftgmac100.c | 570 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ftgmac100.h | 255 +++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 839 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ftgmac100.c create mode 100644 drivers/net/ftgmac100.h diff --git a/README b/README index 68f5fb0..d7a23cd 100644 --- a/README +++ b/README @@ -861,6 +861,18 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_FTGMAC100 + Support for Faraday's FTGMAC100 Gigabit SoC Ethernet + + CONFIG_FTGMAC100_EGIGA + Define this to use GE link update with gigabit PHY. + Define this if FTGMAC100 is connected to gigabit PHY. + If your system has 10/100 PHY only, it might not occur + wrong behavior. Because PHY usually return timeout or + useless data when polling gigabit status and gigabit + control registers. This behavior won't affect the + correctnessof 10/100 link speed update. + CONFIG_SMC911X Support for SMSC's LAN911x and LAN921x chips diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b605eea..fd9d0b4 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c new file mode 100644 index 0000000..dc7a80e --- /dev/null +++ b/drivers/net/ftgmac100.c @@ -0,0 +1,570 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> +#include <linux/mii.h> + +#include "ftgmac100.h" + +#define ETH_ZLEN 60 + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* RBSR - hw default init value is also 0x640 */ +#define RBSR_DEFAULT_VALUE 0x640 + +/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ +#define PKTBUFSTX 4 /* must be power of 2 */ + +struct ftgmac100_data { + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; + int tx_index; + int rx_index; + int phy_addr; +}; + +/* + * struct mii_bus functions + */ +static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, + int regnum) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIRD; + + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { + int data; + + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); + } + + mdelay(10); + } + + debug("mdio read timed out\n"); + return -1; +} + +static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, + int regnum, u16 value) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int data; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIWR; + + data = FTGMAC100_PHYDATA_MIIWDATA(value); + + writel(data, &ftgmac100->phydata); + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { + debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ + "phy_addr: %x\n", phy_addr); + return 0; + } + + mdelay(1); + } + + debug("mdio write timed out\n"); + return -1; +} + +int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value) +{ + *value = ftgmac100_mdiobus_read(dev , addr, reg); + + if (*value == -1) + return -1; + + return 0; +} + +int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value) +{ + if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + return -1; + + return 0; +} + +static int ftgmac100_phy_reset(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + + ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv); + + printf("%s: Starting autonegotiation...\n", dev->name); + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (status & BMSR_ANEGCOMPLETE) + break; + mdelay(1); + } + + if (status & BMSR_ANEGCOMPLETE) { + printf("%s: Autonegotiation complete\n", dev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->name, status); + return 0; + } + + return 1; +} + +static int ftgmac100_phy_init(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + + int phy_addr; + u16 phy_id, status, adv, lpa, stat_ge; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + + ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id); + + /* + * When it is unable to found PHY, + * the interface usually return 0xffff or 0x0000 + */ + if (phy_id != 0xffff && phy_id != 0x0) { + printf("%s: found PHY at 0x%02x\n", + dev->name, phy_addr); + priv->phy_addr = phy_addr; + break; + } + } + + if (phy_id == 0xffff || phy_id == 0x0) { + printf("%s: no PHY present\n", dev->name); + return 0; + } + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + ftgmac100_phy_reset(dev); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", dev->name); + return 0; + } + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); + + speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) + ? 1 : 0); + + duplex = ((stat_ge & LPA_1000FULL) + ? 1 : 0); + + if (speed) { /* Speed is 1000 */ + printf("%s: link up, 1000bps %s-duplex\n", + dev->name, duplex ? "full" : "half"); + return 0; + } +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv); + ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa); + + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + + printf("%s: link up, %sMbps %s-duplex\n", + dev->name, speed ? "100" : "10", duplex ? "full" : "half"); + + return 1; +} + +static int ftgmac100_update_link_speed(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + + unsigned short stat_fe; + unsigned short stat_ge; + unsigned int maccr; + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge); +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe); + + if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ + return 0; + + /* read MAC control register and clear related bits */ + maccr = readl(&ftgmac100->maccr) & + ~(FTGMAC100_MACCR_GIGA_MODE | + FTGMAC100_MACCR_FAST_MODE | + FTGMAC100_MACCR_FULLDUP); + +#ifdef CONFIG_FTGMAC100_EGIGA + if (stat_ge & LPA_1000FULL) { + /* set gmac for 1000BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_ge & LPA_1000HALF) { + /* set gmac for 1000BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE; + } +#endif + + if (stat_fe & BMSR_100FULL) { + /* set MII for 100BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_10FULL) { + /* set MII for 10BaseT and Full Duplex */ + maccr |= FTGMAC100_MACCR_FULLDUP; + } + + if (stat_fe & BMSR_100HALF) { + /* set MII for 100BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE; + } + + if (stat_fe & BMSR_10HALF) { + /* set MII for 10BaseT and Half Duplex */ + /* we have already clear these bits, do nothing */ + ; + } + + /* update MII config into maccr */ + writel(maccr, &ftgmac100->maccr); + + return 1; +} + +/* + * Reset MAC + */ +static void ftgmac100_reset(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + + while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftgmac100_set_mac(struct eth_device *dev, + const unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + writel(maddr, &ftgmac100->mac_madr); + writel(laddr, &ftgmac100->mac_ladr); +} + +static void ftgmac100_set_mac_from_env(struct eth_device *dev) +{ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + ftgmac100_set_mac(dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftgmac100_halt(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(0, &ftgmac100->maccr); +} + +static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *txdes = priv->txdes; + struct ftgmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug("%s()\n", __func__); + + ftgmac100_reset(dev); + + /* set the ethernet address */ + ftgmac100_set_mac_from_env(dev); + + /* disable all interrupts */ + writel(0, &ftgmac100->ier); + + /* initialize descriptors */ + priv->tx_index = 0; + priv->rx_index = 0; + + txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + for (i = 0; i < PKTBUFSTX; i++) { + /* TXBUF_BADR */ + txdes[i].txdes3 = 0; + txdes[i].txdes1 = 0; + } + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + } + + /* transmit ring */ + writel((unsigned int)txdes, &ftgmac100->txr_badr); + + /* receive ring */ + writel((unsigned int)rxdes, &ftgmac100->rxr_badr); + + /* poll receive descriptor automatically */ + writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); + + /* config receive buffer size register */ + writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + + /* enable transmitter, receiver */ + maccr = FTGMAC100_MACCR_TXMAC_EN | + FTGMAC100_MACCR_RXMAC_EN | + FTGMAC100_MACCR_TXDMA_EN | + FTGMAC100_MACCR_RXDMA_EN | + FTGMAC100_MACCR_CRC_APD | + FTGMAC100_MACCR_FULLDUP | + FTGMAC100_MACCR_RX_RUNT | + FTGMAC100_MACCR_RX_BROADPKT; + + writel(maccr, &ftgmac100->maccr); + + if (!ftgmac100_phy_init(dev)) { + if (!ftgmac100_update_link_speed(dev)) + return -1; + } + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftgmac100_recv(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) + return -1; + + if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | + FTGMAC100_RXDES0_CRC_ERR | + FTGMAC100_RXDES0_FTL | + FTGMAC100_RXDES0_RUNT | + FTGMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + NetReceive((void *)curr_des->rxdes3, rxlen); + + /* release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftgmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + int start; + + if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + debug("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */ + + /* only one descriptor on TXBUF */ + curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | + FTGMAC100_TXDES0_LTS | + FTGMAC100_TXDES0_TXBUF_SIZE(length) | + FTGMAC100_TXDES0_TXDMA_OWN ; + + /* start transmit */ + writel(1, &ftgmac100->txpd); + + /* wait for transfer to succeed */ + start = get_timer(0); + while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + if (get_timer(0) >= 5) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + + priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; + + return 0; +} + +int ftgmac100_initialize(bd_t *bd) +{ + struct eth_device *dev; + struct ftgmac100_data *priv; + + dev = malloc(sizeof *dev); + if (!dev) { + printf("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + priv = memalign(16, sizeof(struct ftgmac100_data)); + if (!priv) { + printf("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(*priv)); + + sprintf(dev->name, "FTGMAC100"); + dev->iobase = CONFIG_FTGMAC100_BASE; + dev->init = ftgmac100_init; + dev->halt = ftgmac100_halt; + dev->send = ftgmac100_send; + dev->recv = ftgmac100_recv; + dev->priv = priv; + + eth_register(dev); + + return 1; + +free_dev: + free(dev); +out: + return 0; +} diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h new file mode 100644 index 0000000..46b7369 --- /dev/null +++ b/drivers/net/ftgmac100.h @@ -0,0 +1,255 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2010 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTGMAC100_H +#define __FTGMAC100_H + +/* The registers offset table of ftgmac100 */ +struct ftgmac100 { + unsigned int isr; /* 0x00 */ + unsigned int ier; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int hptxpd; /* 0x28 */ + unsigned int hptxpd_badr; /* 0x2c */ + unsigned int itc; /* 0x30 */ + unsigned int aptc; /* 0x34 */ + unsigned int dblac; /* 0x38 */ + unsigned int dmafifos; /* 0x3c */ + unsigned int revr; /* 0x40 */ + unsigned int fear; /* 0x44 */ + unsigned int tpafcr; /* 0x48 */ + unsigned int rbsr; /* 0x4c */ + unsigned int maccr; /* 0x50 */ + unsigned int macsr; /* 0x54 */ + unsigned int tm; /* 0x58 */ + unsigned int resv1; /* 0x5c */ /* not defined in spec */ + unsigned int phycr; /* 0x60 */ + unsigned int phydata; /* 0x64 */ + unsigned int fcr; /* 0x68 */ + unsigned int bpr; /* 0x6c */ + unsigned int wolcr; /* 0x70 */ + unsigned int wolsr; /* 0x74 */ + unsigned int wfcrc; /* 0x78 */ + unsigned int resv2; /* 0x7c */ /* not defined in spec */ + unsigned int wfbm1; /* 0x80 */ + unsigned int wfbm2; /* 0x84 */ + unsigned int wfbm3; /* 0x88 */ + unsigned int wfbm4; /* 0x8c */ + unsigned int nptxr_ptr; /* 0x90 */ + unsigned int hptxr_ptr; /* 0x94 */ + unsigned int rxr_ptr; /* 0x98 */ + unsigned int resv3; /* 0x9c */ /* not defined in spec */ + unsigned int tx; /* 0xa0 */ + unsigned int tx_mcol_scol; /* 0xa4 */ + unsigned int tx_ecol_fail; /* 0xa8 */ + unsigned int tx_lcol_und; /* 0xac */ + unsigned int rx; /* 0xb0 */ + unsigned int rx_bc; /* 0xb4 */ + unsigned int rx_mc; /* 0xb8 */ + unsigned int rx_pf_aep; /* 0xbc */ + unsigned int rx_runt; /* 0xc0 */ + unsigned int rx_crcer_ftl; /* 0xc4 */ + unsigned int rx_col_lost; /* 0xc8 */ +}; + +/* + * Interrupt status register & interrupt enable register + */ +#define FTGMAC100_INT_RPKT_BUF (1 << 0) +#define FTGMAC100_INT_RPKT_FIFO (1 << 1) +#define FTGMAC100_INT_NO_RXBUF (1 << 2) +#define FTGMAC100_INT_RPKT_LOST (1 << 3) +#define FTGMAC100_INT_XPKT_ETH (1 << 4) +#define FTGMAC100_INT_XPKT_FIFO (1 << 5) +#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) +#define FTGMAC100_INT_XPKT_LOST (1 << 7) +#define FTGMAC100_INT_AHB_ERR (1 << 8) +#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) + +/* + * Interrupt timer control register + */ +#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) +#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) +#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) + +/* + * Automatic polling timer control register + */ +#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * DMA burst length and arbitration control register + */ +#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) +#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) +#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) +#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) +#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) + +/* + * DMA FIFO status register + */ +#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) +#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) +#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) +#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) + +/* + * Receive buffer size register + */ +#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) + +/* + * MAC control register + */ +#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) +#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) +#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) +#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) +#define FTGMAC100_MACCR_RM_VLAN (1 << 4) +#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) +#define FTGMAC100_MACCR_LOOP_EN (1 << 6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) +#define FTGMAC100_MACCR_FULLDUP (1 << 8) +#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) +#define FTGMAC100_MACCR_CRC_APD (1 << 10) +#define FTGMAC100_MACCR_RX_RUNT (1 << 12) +#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) +#define FTGMAC100_MACCR_RX_ALL (1 << 14) +#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) +#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_FAST_MODE (1 << 19) +#define FTGMAC100_MACCR_SW_RST (1 << 31) + +/* + * PHY control register + */ +#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f +#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) +#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTGMAC100_PHYCR_MIIRD (1 << 26) +#define FTGMAC100_PHYCR_MIIWR (1 << 27) + +/* + * PHY data register + */ +#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) +#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftgmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* not used by HW */ + unsigned int txdes3; /* TXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) +#define FTGMAC100_TXDES0_EDOTR (1 << 15) +#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_TXDES0_LTS (1 << 28) +#define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) +#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) +#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) +#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) +#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) +#define FTGMAC100_TXDES1_LLC (1 << 22) +#define FTGMAC100_TXDES1_TX2FIC (1 << 30) +#define FTGMAC100_TXDES1_TXIC (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftgmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* not used by HW */ + unsigned int rxdes3; /* RXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) +#define FTGMAC100_RXDES0_EDORR (1 << 15) +#define FTGMAC100_RXDES0_MULTICAST (1 << 16) +#define FTGMAC100_RXDES0_BROADCAST (1 << 17) +#define FTGMAC100_RXDES0_RX_ERR (1 << 18) +#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_RXDES0_FTL (1 << 20) +#define FTGMAC100_RXDES0_RUNT (1 << 21) +#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) +#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) +#define FTGMAC100_RXDES0_LRS (1 << 28) +#define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) + +#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff +#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) +#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) +#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) +#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) +#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) +#define FTGMAC100_RXDES1_LLC (1 << 22) +#define FTGMAC100_RXDES1_DF (1 << 23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) + +#endif /* __FTGMAC100_H */ diff --git a/include/netdev.h b/include/netdev.h index 7f66419..1a542e8 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -61,6 +61,7 @@ int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); +int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -- 1.7.3.2

2 1

[U-Boot] [PATCH 01/15] powerpc/fsl-pci: Add generic code to setup PCIe controllers
by Kumar Gala 09 Jan '11

09 Jan '11

Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/fsl_pci.h | 10 +++ board/freescale/p1022ds/p1022ds.c | 67 +------------------ drivers/pci/fsl_pci_init.c | 127 ++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+), 65 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 5cbe139..15ab50d 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -22,6 +22,8 @@ #define __FSL_PCI_H_ #include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <pci.h> int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -172,6 +174,9 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info); +int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ @@ -220,6 +225,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; \ FT_FSL_PCIE4_SETUP; +#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP #elif defined(CONFIG_MPC85xx) #define FSL_PCI_COMPAT "fsl,mpc8540-pci" #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" @@ -229,6 +235,10 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, FT_FSL_PCIE1_SETUP; \ FT_FSL_PCIE2_SETUP; \ FT_FSL_PCIE3_SETUP; +#define FT_FSL_PCIE_SETUP \ + FT_FSL_PCIE1_SETUP; \ + FT_FSL_PCIE2_SETUP; \ + FT_FSL_PCIE3_SETUP; #elif defined(CONFIG_MPC86xx) #define FSL_PCI_COMPAT "fsl,mpc8610-pci" #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..fc62a00 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -200,7 +200,7 @@ static u8 serdes_dev_slot[][SATA2 + 1] = { * Returns the name of the slot to which the PCIe or SATA controller is * connected */ -const char *serdes_slot_name(enum srds_prtcl device) +const char *board_serdes_name(enum srds_prtcl device) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); @@ -215,73 +215,10 @@ const char *serdes_slot_name(enum srds_prtcl device) return "Nothing"; } -static void configure_pcie(struct fsl_pci_info *info, - struct pci_controller *hose, - const char *connected) -{ - static int bus_number = 0; - int is_endpoint; - - set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); - set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); - is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); - bus_number = fsl_pci_init_port(info, hose, bus_number); -} - -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - #ifdef CONFIG_PCI void pci_init_board(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pci_info pci_info; - u32 devdisr = in_be32(&gur->devdisr); - -#ifdef CONFIG_PCIE1 - if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - SET_STD_PCIE_INFO(pci_info, 1); - configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - SET_STD_PCIE_INFO(pci_info, 2); - configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - SET_STD_PCIE_INFO(pci_info, 3); - configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ -#endif + fsl_pcie_init_board(0); } #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 71ab02b..64c0198 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -18,6 +18,8 @@ */ #include <common.h> +#include <malloc.h> +#include <asm/fsl_serdes.h> DECLARE_GLOBAL_DATA_PTR; @@ -513,6 +515,131 @@ void fsl_pci_config_unlock(struct pci_controller *hose) } } +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \ + defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4) +int fsl_configure_pcie(struct fsl_pci_info *info, + struct pci_controller *hose, + const char *connected, int busno) +{ + int is_endpoint; + + set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); + set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); + printf("PCIE%u: connected to %s as %s (base addr %lx)\n", + info->pci_num, connected, + is_endpoint ? "Endpoint" : "Root Complex", info->regs); + return fsl_pci_init_port(info, hose, busno); +} + +#if defined(CONFIG_FSL_CORENET) + #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC85xx) + #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE + #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#elif defined(CONFIG_MPC86xx) + #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1 + #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2 + #define _DEVDISR_PCIE3 0 + #define _DEVDISR_PCIE4 0 + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) +#else +#error "No defines for DEVDISR_PCIE" +#endif + +/* Implement a dummy function for those platforms w/o SERDES */ +static const char *__board_serdes_name(enum srds_prtcl device) +{ + return NULL; +} + +__attribute__((weak, alias("__board_serdes_name"))) const char * +board_serdes_name(enum srds_prtcl device); + +static u32 devdisr_mask[] = { + _DEVDISR_PCIE1, + _DEVDISR_PCIE2, + _DEVDISR_PCIE3, + _DEVDISR_PCIE4, +}; + +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + struct pci_controller *hose; + int num = dev - PCIE1; + + hose = calloc(1, sizeof(struct pci_controller)); + if (!hose) + return busno; + + if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) { + busno = fsl_configure_pcie(pci_info, hose, + board_serdes_name(dev), busno); + } else { + printf("PCIE%d: disabled\n", num + 1); + } + + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + struct fsl_pci_info pci_info; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + u32 devdisr = in_be32(&gur->devdisr); + +#ifdef CONFIG_PCIE1 + SET_STD_PCIE_INFO(pci_info, 1); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + SET_STD_PCIE_INFO(pci_info, 2); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + SET_STD_PCIE_INFO(pci_info, 3); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */ +#endif + +#ifdef CONFIG_PCIE4 + SET_STD_PCIE_INFO(pci_info, 4); + busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info); +#else + setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */ +#endif + + return busno; +} +#else +int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, + struct fsl_pci_info *pci_info) +{ + return busno; +} + +int fsl_pcie_init_board(int busno) +{ + return busno; +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP #include <libfdt.h> #include <fdt_support.h> -- 1.6.0.6

3 37

[U-Boot] [PATCH] fsl_pci: Update PCIe boot ouput
by Peter Tyser 09 Jan '11

09 Jan '11

This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- This applies to Kumar's u-boot-85xx.git 'dev' branch. arch/powerpc/include/asm/fsl_pci.h | 2 +- drivers/pci/fsl_pci_init.c | 38 ++++++++++++++++++----------------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 15ab50d..0a98bde 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -27,7 +27,6 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); @@ -172,6 +171,7 @@ struct fsl_pci_info { int pci_num; }; +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info); int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 64c0198..fa23992 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -217,8 +217,10 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) +void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) { + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr; + u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data; u16 temp16; u32 temp32; int enabled, r, inbound = 0; @@ -235,10 +237,6 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) u64 out_hi = 0, out_lo = -1ULL; u32 pcicsrbar, pcicsrbar_sz; -#ifdef DEBUG - int neg_link_w; -#endif - pci_setup_indirect(hose, cfg_addr, cfg_data); /* Handle setup of outbound windows first */ @@ -354,20 +352,20 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) #endif if (!enabled) { - debug("....PCIE link error. Skipping scan." - "LTSSM=0x%02x\n", ltssm); + /* Let the user know there's no PCIe link */ + printf("no link, regs @ 0x%lx\n", pci_info->regs); hose->last_busno = hose->first_busno; return; } out_be32(&pci->pme_msg_det, 0xffffffff); out_be32(&pci->pme_msg_int_en, 0xffffffff); -#ifdef DEBUG + + /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); - neg_link_w = (temp16 & 0x3f0 ) >> 4; - printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", - ltssm, neg_link_w); -#endif + printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, + pci_info->regs); + hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); } @@ -476,7 +474,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, hose->region_count = r - hose->regions; hose->first_busno = busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + fsl_pci_init(hose, pci_info); if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); @@ -485,7 +483,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? - "E" : "", pci_info->pci_num, + "e" : "", pci_info->pci_num, hose->first_busno, hose->last_busno); return(hose->last_busno + 1); @@ -525,10 +523,14 @@ int fsl_configure_pcie(struct fsl_pci_info *info, set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); + is_endpoint = fsl_setup_hose(hose, info->regs); - printf("PCIE%u: connected to %s as %s (base addr %lx)\n", - info->pci_num, connected, - is_endpoint ? "Endpoint" : "Root Complex", info->regs); + printf("PCIe%u: %s", info->pci_num, + is_endpoint ? "Endpoint" : "Root Complex"); + if (connected) + printf(" of %s", connected); + puts(", "); + return fsl_pci_init_port(info, hose, busno); } @@ -585,7 +587,7 @@ int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, busno = fsl_configure_pcie(pci_info, hose, board_serdes_name(dev), busno); } else { - printf("PCIE%d: disabled\n", num + 1); + printf("PCIe%d: disabled\n", num + 1); } return busno; -- 1.7.0.4

3 2

[U-Boot] [PATCH] MAINTAINERS: sort Blackfin entries
by Mike Frysinger 09 Jan '11

09 Jan '11

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- MAINTAINERS | 49 ++++++++++++++++++++++--------------------------- 1 files changed, 22 insertions(+), 27 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ba83f71..553930a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1033,6 +1033,7 @@ Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> BF518F-EZBRD BF518 BF526-EZBRD BF526 + BF527-AD7160-EVAL BF527 BF527-EZKIT BF527 BF527-EZKIT-V2 BF527 BF527-SDP BF527 @@ -1044,52 +1045,46 @@ Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> BF548-EZKIT BF548 BF561-EZKIT BF561 - BF527-AD7160-EVAL BF527 +Brent Kandetzki <brentk(a)teleco.com> -Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> + IP04 BF532 - CM-BF527 BF527 - CM-BF533 BF533 - CM-BF537E BF537 - CM-BF537U BF537 - CM-BF548 BF548 - CM-BF561 BF561 - TCM-BF518 BF518 - TCM-BF537 BF537 +Peter Meerwald <devel(a)bct-electronic.com> -Martin Strubel <strubel(a)section5.ch> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> + bct-brettl2 BF536 - BF537-minotaur BF537 - BF537-srv1 BF537 +I-SYST Micromodule <support(a)i-syst.com> + + IBF-DSP561 BF561 Wojtek Skulski <skulski(a)pas.rochester.edu> Wojtek Skulski <info(a)skutek.com> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> Benjamin Matthews <mben12(a)gmail.com> BlackStamp BF533 BlackVME BF561 -I-SYST Micromodule <support(a)i-syst.com> -Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> +Martin Strubel <strubel(a)section5.ch> - IBF-DSP561 BF561 + BF537-minotaur BF537 + BF537-srv1 BF537 + +Bluetechnix Tinyboards <bluetechnix(a)blackfin.uclinux.org> + + CM-BF527 BF527 + CM-BF533 BF533 + CM-BF537E BF537 + CM-BF537U BF537 + CM-BF548 BF548 + CM-BF561 BF561 + TCM-BF518 BF518 + TCM-BF537 BF537 Valentin Yakovenkov <yakovenkov(a)niistt.ru> Anton Shurpin <shurpin.aa(a)niistt.ru> BF561-ACVILON BF561 -Brent Kandetzki <brentk(a)teleco.com> - - IP04 BF532 - -Peter Meerwald <devel(a)bct-electronic.com> - - bct-brettl2 BF536 - ######################################################################### # End of MAINTAINERS list # ######################################################################### -- 1.7.3.4

2 1

[U-Boot] [PATCH] miiphy: convert to linux/mii.h
by Mike Frysinger 09 Jan '11

09 Jan '11

The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- note: i tried to build test this, but it's currently pretty hard considering many boards are broken already. when i wrote it against v2010.09, things seemed to be ok then. some tree greps don't find anything for me to update either. arch/arm/cpu/arm920t/at91rm9200/lxt972.c | 14 ++-- arch/arm/cpu/arm926ejs/davinci/lxt972.c | 14 ++-- arch/arm/cpu/ixp/npe/miiphy.c | 16 +++--- arch/arm/cpu/ixp/npe/npe.c | 8 +- arch/powerpc/cpu/mpc8xx/fec.c | 4 +- arch/powerpc/cpu/ppc4xx/miiphy.c | 72 ++++++++++++------------ board/Marvell/rd6281a/rd6281a.c | 4 +- board/actux1/actux1.c | 4 +- board/csb272/csb272.c | 6 +- board/csb472/csb472.c | 6 +- board/evb64260/eth.c | 16 +++--- board/freescale/mpc8260ads/mpc8260ads.c | 12 ++-- board/freescale/mpc8560ads/mpc8560ads.c | 6 +- board/manroland/uc100/uc100.c | 4 +- board/netphone/netphone.c | 8 +- board/netta/netta.c | 8 +- board/netta2/netta2.c | 8 +- board/prodrive/p3mx/mv_eth.c | 30 +++++----- board/sbc8560/sbc8560.c | 6 +- board/stx/stxgp3/stxgp3.c | 6 +- board/stx/stxssa/stxssa.c | 6 +- board/stx/stxxtc/stxxtc.c | 6 +- board/tqc/tqm8xx/tqm8xx.c | 6 +- common/cmd_mii.c | 29 +++++----- common/miiphyutil.c | 50 ++++++++-------- drivers/net/4xx_enet.c | 10 ++-- drivers/net/altera_tse.c | 14 ++-- drivers/net/altera_tse.h | 2 - drivers/net/davinci_emac.c | 16 +++--- drivers/net/designware.c | 54 +++++++++--------- drivers/net/eepro100.c | 2 +- drivers/net/fec_mxc.c | 20 +++--- drivers/net/fsl_mcdmafec.c | 2 +- drivers/net/inca-ip_sw.c | 6 +- drivers/net/mcffec.c | 2 +- drivers/net/mcfmii.c | 14 ++-- drivers/net/ns7520_eth.c | 36 ++++++------ drivers/net/ns9750_eth.c | 51 ++++++++--------- drivers/net/phy/mv88e61xx.c | 2 +- drivers/net/smc911x.c | 12 ++-- drivers/net/tsec.c | 50 ++++++++-------- drivers/qe/uec_phy.c | 68 +++++++++++----------- drivers/qe/uec_phy.h | 18 ------ include/miiphy.h | 89 +++--------------------------- include/tsec.h | 2 - 45 files changed, 361 insertions(+), 458 deletions(-) diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c index 260d393..f02cfdd 100644 --- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c +++ b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c @@ -52,8 +52,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); + at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1); + at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -170,18 +170,18 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_BMCR_RST_NEG; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) + value |= BMCR_ANRESTART; + if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); - if (!(value & PHY_BMSR_AUTN_COMP)) + at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value); + if (!(value & BMSR_ANEGCOMPLETE)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c index ce3e41c..733d413 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c +++ b/arch/arm/cpu/arm926ejs/davinci/lxt972.c @@ -39,9 +39,9 @@ int lxt972_is_phy_connected(int phy_addr) { u_int16_t id1, id2; - if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &id1)) + if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1)) return(0); - if (!davinci_eth_phy_read(phy_addr, PHY_PHYIDR2, &id2)) + if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2)) return(0); if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) @@ -105,19 +105,19 @@ int lxt972_auto_negotiate(int phy_addr) { u_int16_t tmp; - if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_BMCR_RST_NEG; - davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); + tmp |= BMCR_ANRESTART; + davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) return(0); - if (!(tmp & PHY_BMSR_AUTN_COMP)) + if (!(tmp & BMSR_ANEGCOMPLETE)) return(0); return (lxt972_get_link_speed(phy_addr)); diff --git a/arch/arm/cpu/ixp/npe/miiphy.c b/arch/arm/cpu/ixp/npe/miiphy.c index 4b0201a..a04779a 100644 --- a/arch/arm/cpu/ixp/npe/miiphy.c +++ b/arch/arm/cpu/ixp/npe/miiphy.c @@ -85,16 +85,16 @@ int phy_setup_aneg (char *devname, unsigned char addr) unsigned short ctl, adv; /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, MII_BMCR, &ctl); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, ctl); return 0; } diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c index 2e68689..857bcad 100644 --- a/arch/arm/cpu/ixp/npe/npe.c +++ b/arch/arm/cpu/ixp/npe/npe.c @@ -359,15 +359,15 @@ static int npe_init(struct eth_device *dev, bd_t * bis) debug("%s: 1\n", __FUNCTION__); - miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, &reg_short); + miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -378,7 +378,7 @@ static int npe_init(struct eth_device *dev, bd_t * bis) if ((i++ % 1000) == 0) { putc ('.'); - miiphy_read (dev->name, p_npe->phy_no, PHY_BMSR, &reg_short); + miiphy_read (dev->name, p_npe->phy_no, MII_BMSR, &reg_short); } udelay (1000); /* 1 ms */ } diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index d4abeb1..a2d2bd6 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -888,14 +888,14 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + MII_PHYSID1)) << 16; #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 3b28122..206c476 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -89,60 +89,60 @@ int phy_setup_aneg (char *devname, unsigned char addr) u16 exsr = 0x0000; #endif - miiphy_read (devname, addr, PHY_BMSR, &bmsr); + miiphy_read (devname, addr, MII_BMSR, &bmsr); #if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); + if (bmsr & BMSR_ESTATEN) + miiphy_read (devname, addr, MII_ESTATUS, &exsr); - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { + if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { /* 1000BASE-X */ u16 anar = 0x0000; - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; + if (exsr & ESTATUS_1000XF) + anar |= ADVERTISE_1000XFULL); - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; + if (exsr & ESTATUS_1000XH) + anar |= ADVERTISE_1000XHALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); } else #endif { u16 anar, btcr; - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); + miiphy_read (devname, addr, MII_ADVERTISE, &anar); + anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | + LPA_100HALF | LPA_10FULL | LPA_10HALF); - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); + miiphy_read (devname, addr, MII_CTRL1000, &btcr); btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; + if (bmsr & BMSR_100BASE4) + anar |= LPA_100BASE4; - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; + if (bmsr & BMSR_100FULL) + anar |= LPA_100FULL; - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; + if (bmsr & BMSR_100HALF) + anar |= LPA_100HALF; - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; + if (bmsr & BMSR_10FULL) + anar |= LPA_10FULL; - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; + if (bmsr & BMSR_10HALF) + anar |= LPA_10HALF; - miiphy_write (devname, addr, PHY_ANAR, anar); + miiphy_write (devname, addr, MII_ADVERTISE, anar); #if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) + if (exsr & ESTATUS_1000_TFULL) btcr |= PHY_1000BTCR_1000FD; - if (exsr & PHY_EXSR_1000TH) + if (exsr & ESTATUS_1000_THALF) btcr |= PHY_1000BTCR_1000HD; - miiphy_write (devname, addr, PHY_1000BTCR, btcr); + miiphy_write (devname, addr, MII_CTRL1000, btcr); #endif } @@ -152,21 +152,21 @@ int phy_setup_aneg (char *devname, unsigned char addr) */ u16 adv; - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | + LPA_10FULL | LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, MII_BMCR, &bmcr); + bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, bmcr); return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index e69e035..ecdea82 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -139,11 +139,11 @@ void mv_phy_88e1116_init(char *name) miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); /* reset the phy */ - if (miiphy_read (name, devadr, PHY_BMCR, &reg) != 0) { + if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) { printf("Err..(%s) PHY status read failed\n", __FUNCTION__); return; } - if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { + if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) { printf("Err..(%s) PHY reset failed\n", __FUNCTION__); return; } diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 399be23..e73aff8 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -140,8 +140,8 @@ void reset_phy (void) /* initialize the PHY */ miiphy_reset ("NPE0", CONFIG_PHY_ADDR); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1); - miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); id2 &= 0xFFF0; /* mask out revision bits */ diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index e248aa7..8b36127 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -176,11 +176,11 @@ int last_stage_init(void) miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); return 0; /* success */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 25709f2..eac4408 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -144,11 +144,11 @@ int last_stage_init(void) miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR); /* AUTO neg */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); /* LEDs */ - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08); return 0; /* success */ } diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index a96e655..352505a 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -422,24 +422,24 @@ gt6426x_dump_mii(bd_t *bis, unsigned short phy) static void check_phy_state(struct eth_dev_s *p) { - int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR); + int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR); int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); - if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) { - int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) & - miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR); + if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) { + int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) & + miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA); int want; - if (nego & PHY_ANLPAR_TXFD) { + if (nego & LPA_100FULL) { want = 0x3; printf("MII: 100Base-TX, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_TX) { + } else if (nego & LPA_100HALF) { want = 0x1; printf("MII: 100Base-TX, Half Duplex\n"); - } else if (nego & PHY_ANLPAR_10FD) { + } else if (nego & LPA_10FULL) { want = 0x2; printf("MII: 10Base-T, Full Duplex\n"); - } else if (nego & PHY_ANLPAR_10) { + } else if (nego & LPA_10HALF) { want = 0x0; printf("MII: 10Base-T, Half Duplex\n"); } else { diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index be55626..8f617ca 100644 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c @@ -243,8 +243,8 @@ void reset_phy (void) * Enable autonegotiation. */ bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #else /* * Ethernet PHY is configured (by means of configuration pins) @@ -254,13 +254,13 @@ void reset_phy (void) */ /* Advertise all capabilities */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1); /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR, 0x0000); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000); - bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ #endif /* CONFIG_MII */ } diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..2ae0459 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -239,10 +239,10 @@ void reset_phy (void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ } diff --git a/board/manroland/uc100/uc100.c b/board/manroland/uc100/uc100.c index bdee4de..959b2ad 100644 --- a/board/manroland/uc100/uc100.c +++ b/board/manroland/uc100/uc100.c @@ -261,10 +261,10 @@ int misc_init_r (void) mii_init(); /* disable auto-negotiation, 100mbit, full-duplex */ - fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100); + fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100); /* set LED's to Link, Transmit, Receive */ - fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122); + fec8xx_miiphy_write(NULL, 0, MII_NWAYTEST, 0x4122); return 0; } diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index ce5f051..7fea71b 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -488,13 +488,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/netta/netta.c b/board/netta/netta.c index 5c935f4..d15dc9b 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -436,13 +436,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index 3b0191d..ff713d9 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -486,13 +486,13 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v); + fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, - PHY_BMCR_RESET | PHY_BMCR_AUTON); + fec8xx_miiphy_write(NULL, phyno, MII_BMCR, + BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index 567ae99..fac7633 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -586,16 +586,16 @@ static int mv64460_eth_real_open (struct eth_device *dev) } #endif /* defined(CONFIG_PHY_RESET) */ - miiphy_read (dev->name, reg, PHY_BMSR, &reg_short); + miiphy_read (dev->name, reg, MII_BMSR, &reg_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -608,7 +608,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) putc ('.'); } udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, &reg_short); + miiphy_read (dev->name, reg, MII_BMSR, &reg_short); } puts (" done\n"); @@ -2241,20 +2241,20 @@ int phy_setup_aneg (char *devname, unsigned char addr) unsigned short ctl, adv; /* Setup standard advertise */ - miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10); - miiphy_write (devname, addr, PHY_ANAR, adv); + miiphy_read (devname, addr, MII_ADVERTISE, &adv); + adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF); + miiphy_write (devname, addr, MII_ADVERTISE, adv); - miiphy_read (devname, addr, PHY_1000BTCR, &adv); + miiphy_read (devname, addr, MII_CTRL1000, &adv); adv |= (0x0300); - miiphy_write (devname, addr, PHY_1000BTCR, adv); + miiphy_write (devname, addr, MII_CTRL1000, adv); /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &ctl); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, ctl); + miiphy_read (devname, addr, MII_BMCR, &ctl); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + miiphy_write (devname, addr, MII_BMCR, ctl); return 0; } diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..7bf8179 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -228,10 +228,10 @@ void reset_phy (void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ } diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..1ed340e 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -242,10 +242,10 @@ reset_phy(void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ #endif } diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..6cd28a3 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -241,10 +241,10 @@ reset_phy(void) miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ - bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028); - bb_miiphy_write(NULL, 0x02, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + bb_miiphy_write(NULL, 0x02, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); #endif /* CONFIG_MII */ #endif } diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c index 6693a70..4afbbf5 100644 --- a/board/stx/stxxtc/stxxtc.c +++ b/board/stx/stxxtc/stxxtc.c @@ -481,12 +481,12 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC", phyno, PHY_PHYIDR1, &v); + miiphy_read("FEC", phyno, MII_PHYSID1, &v); if (v == 0xFFFF) continue; - miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_POWD); + miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN); udelay(10000); - miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); udelay(10000); } } diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 940cc8f..6576e02 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -722,15 +722,15 @@ int last_stage_init(void) return 0; for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC", phy[i], PHY_BMCR, &reg); + ret = miiphy_read("FEC", phy[i], MII_BMCR, &reg); if (ret) { printf("Cannot read BMCR on PHY %d\n", phy[i]); return 0; } /* Auto-negotiation off, hard set full duplex, 100Mbps */ ret = miiphy_write("FEC", phy[i], - PHY_BMCR, (reg | PHY_BMCR_100MB | - PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON); + MII_BMCR, (reg | BMCR_SPEED100 | + BMCR_FULLDPLX) & ~BMCR_ANENABLE); if (ret) { printf("Cannot write BMCR on PHY %d\n", phy[i]); return 0; diff --git a/common/cmd_mii.c b/common/cmd_mii.c index 3fb0795..23b723e 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -35,12 +35,12 @@ typedef struct _MII_reg_desc_t { } MII_reg_desc_t; static const MII_reg_desc_t reg_0_5_desc_tbl[] = { - { 0, "PHY control register" }, - { 1, "PHY status register" }, - { 2, "PHY ID 1 register" }, - { 3, "PHY ID 2 register" }, - { 4, "Autonegotiation advertisement register" }, - { 5, "Autonegotiation partner abilities register" }, + { MII_BMCR, "PHY control register" }, + { MII_BMSR, "PHY status register" }, + { MII_PHYSID1, "PHY ID 1 register" }, + { MII_PHYSID2, "PHY ID 2 register" }, + { MII_ADVERTISE, "Autonegotiation advertisement register" }, + { MII_LPA, "Autonegotiation partner abilities register" }, }; typedef struct _MII_field_desc_t { @@ -212,20 +212,19 @@ static int special_field( const MII_field_desc_t *pdesc, ushort regval) { - if ((regno == 0) && (pdesc->lo == 6)) { - ushort speed_bits = regval & PHY_BMCR_SPEED_MASK; + if ((regno == MII_BMCR) && (pdesc->lo == 6)) { + ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100); printf("%2u,%2u = b%u%u speed selection = %s Mbps", 6, 13, (regval >> 6) & 1, (regval >> 13) & 1, - speed_bits == PHY_BMCR_1000_MBPS ? "1000" : - speed_bits == PHY_BMCR_100_MBPS ? "100" : - speed_bits == PHY_BMCR_10_MBPS ? "10" : - "???"); + speed_bits == BMCR_SPEED1000 ? "1000" : + speed_bits == BMCR_SPEED100 ? "100" : + "10"); return 1; } - else if ((regno == 0) && (pdesc->lo == 8)) { + else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { printf("%2u = %5u duplex = %s", pdesc->lo, (regval >> pdesc->lo) & 1, @@ -233,7 +232,7 @@ static int special_field( return 1; } - else if ((regno == 4) && (pdesc->lo == 0)) { + else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; printf("%2u-%2u = %5u selector = %s", pdesc->hi, pdesc->lo, sel_bits, @@ -245,7 +244,7 @@ static int special_field( return 1; } - else if ((regno == 5) && (pdesc->lo == 0)) { + else if ((regno == MII_LPA) && (pdesc->lo == 0)) { ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; printf("%2u-%2u = %u selector = %s", pdesc->hi, pdesc->lo, sel_bits, diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 9cf845f..e282096 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -253,20 +253,20 @@ int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, unsigned int reg = 0; unsigned short tmp; - if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { + if (miiphy_read (devname, addr, MII_PHYSID2, &tmp) != 0) { debug ("PHY ID register 2 read failed\n"); return (-1); } reg = tmp; - debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); + debug ("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg); if (reg == 0xFFFF) { /* No physical device present at this address */ return (-1); } - if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { + if (miiphy_read (devname, addr, MII_PHYSID1, &tmp) != 0) { debug ("PHY ID register 1 read failed\n"); return (-1); } @@ -290,11 +290,11 @@ int miiphy_reset(const char *devname, unsigned char addr) unsigned short reg; int timeout = 500; - if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) { + if (miiphy_read (devname, addr, MII_BMCR, &reg) != 0) { debug ("PHY status read failed\n"); return (-1); } - if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) { + if (miiphy_write (devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { debug ("PHY reset failed\n"); return (-1); } @@ -308,7 +308,7 @@ int miiphy_reset(const char *devname, unsigned char addr) */ reg = 0x8000; while (((reg & 0x8000) != 0) && timeout--) { - if (miiphy_read(devname, addr, PHY_BMCR, &reg) != 0) { + if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { debug("PHY status read failed\n"); return -1; } @@ -345,7 +345,7 @@ int miiphy_speed(const char *devname, unsigned char addr) * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. */ /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { + if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) { printf ("PHY 1000BT status"); goto miiphy_read_failed; } @@ -356,21 +356,21 @@ int miiphy_speed(const char *devname, unsigned char addr) #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { + if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) { printf ("PHY speed"); goto miiphy_read_failed; } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if (bmcr & BMCR_ANENABLE) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { printf ("PHY AN speed"); goto miiphy_read_failed; } - return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET; + return (anlpar & LPA_100) ? _100BASET : _10BASET; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET; + return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET; miiphy_read_failed: printf (" read failed, assuming 10BASE-T\n"); @@ -391,7 +391,7 @@ int miiphy_duplex(const char *devname, unsigned char addr) /* Check for 1000BASE-X. */ if (miiphy_is_1000base_x (devname, addr)) { /* 1000BASE-X */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { printf ("1000BASE-X PHY AN duplex"); goto miiphy_read_failed; } @@ -400,7 +400,7 @@ int miiphy_duplex(const char *devname, unsigned char addr) * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. */ /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { + if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) { printf ("PHY 1000BT status"); goto miiphy_read_failed; } @@ -414,22 +414,22 @@ int miiphy_duplex(const char *devname, unsigned char addr) #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { + if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) { puts ("PHY duplex"); goto miiphy_read_failed; } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if (bmcr & BMCR_ANENABLE) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { + if (miiphy_read (devname, addr, MII_LPA, &anlpar)) { puts ("PHY AN duplex"); goto miiphy_read_failed; } - return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ? + return (anlpar & (LPA_10FULL | LPA_100FULL)) ? FULL : HALF; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF; + return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; miiphy_read_failed: printf (" read failed, assuming half duplex\n"); @@ -446,12 +446,12 @@ int miiphy_is_1000base_x(const char *devname, unsigned char addr) #if defined(CONFIG_PHY_GIGE) u16 exsr; - if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) { + if (miiphy_read (devname, addr, MII_ESTATUS, &exsr)) { printf ("PHY extended status read failed, assuming no " "1000BASE-X\n"); return 0; } - return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)); + return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)); #else return 0; #endif @@ -467,14 +467,14 @@ int miiphy_link(const char *devname, unsigned char addr) unsigned short reg; /* dummy read; needed to latch some phys */ - (void)miiphy_read (devname, addr, PHY_BMSR, &reg); - if (miiphy_read (devname, addr, PHY_BMSR, &reg)) { - puts ("PHY_BMSR read failed, assuming no link\n"); + (void)miiphy_read (devname, addr, MII_BMSR, &reg); + if (miiphy_read (devname, addr, MII_BMSR, &reg)) { + puts ("MII_BMSR read failed, assuming no link\n"); return (0); } /* Determine if a link is active */ - if ((reg & PHY_BMSR_LS) != 0) { + if ((reg & BMSR_LSTATUS) != 0) { return (1); } else { return (0); diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 45ff4f3..b1763b1 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -1185,16 +1185,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif /* defined(CONFIG_PHY_RESET) */ - miiphy_read (dev->name, reg, PHY_BMSR, &reg_short); + miiphy_read (dev->name, reg, MII_BMSR, &reg_short); /* * Wait if PHY is capable of autonegotiation and autonegotiation is not complete */ - if ((reg_short & PHY_BMSR_AUTN_ABLE) - && !(reg_short & PHY_BMSR_AUTN_COMP)) { + if ((reg_short & BMSR_ANEGCAPABLE) + && !(reg_short & BMSR_ANEGCOMPLETE)) { puts ("Waiting for PHY auto negotiation to complete"); i = 0; - while (!(reg_short & PHY_BMSR_AUTN_COMP)) { + while (!(reg_short & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -1207,7 +1207,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) putc ('.'); } udelay (1000); /* 1 ms */ - miiphy_read (dev->name, reg, PHY_BMSR, &reg_short); + miiphy_read (dev->name, reg, MII_BMSR, &reg_short); } puts (" done\n"); udelay (500000); /* another 500 ms (results in faster booting) */ diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index d45aab1..54a944b 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -475,12 +475,12 @@ static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) */ mii_reg = tse_mdio_read(priv, MIIM_STATUS); - if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) - && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE) + && !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -643,13 +643,13 @@ static struct phy_info phy_info_generic = { "Unknown/Generic PHY", 32, (struct phy_cmd[]){ /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]){ /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, {miim_end,} }, (struct phy_cmd[]){ /* shutdown */ diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h index c1cb79e..8880bfc 100644 --- a/drivers/net/altera_tse.h +++ b/drivers/net/altera_tse.h @@ -41,8 +41,6 @@ #define MIIM_STATUS 0x1 #define MIIM_STATUS_AN_DONE 0x00000020 #define MIIM_STATUS_LINK 0x0004 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_AUTN_COMP 0x0020 #define MIIM_PHYIR1 0x2 #define MIIM_PHYIR2 0x3 diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index 43a3d79..56cd2aa 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -236,7 +236,7 @@ static int gen_is_phy_connected(int phy_addr) { u_int16_t dummy; - return(davinci_eth_phy_read(phy_addr, PHY_PHYIDR1, &dummy)); + return(davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy)); } static int gen_get_link_speed(int phy_addr) @@ -280,19 +280,19 @@ static int gen_auto_negotiate(int phy_addr) { u_int16_t tmp; - if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) return(0); /* Restart Auto_negotiation */ - tmp |= PHY_BMCR_AUTON; - davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp); + tmp |= BMCR_ANENABLE; + davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); /*check AutoNegotiate complete */ udelay (10000); - if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)) + if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) return(0); - if (!(tmp & PHY_BMSR_AUTN_COMP)) + if (!(tmp & BMSR_ANEGCOMPLETE)) return(0); return(gen_get_link_speed(phy_addr)); @@ -694,14 +694,14 @@ int davinci_emac_initialize(void) return(0); /* Get PHY ID and initialize phy_ops for a detected PHY */ - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR1, &tmp)) { + if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID1, &tmp)) { active_phy_addr = 0xff; return(0); } phy_id = (tmp << 16) & 0xffff0000; - if (!davinci_eth_phy_read(active_phy_addr, PHY_PHYIDR2, &tmp)) { + if (!davinci_eth_phy_read(active_phy_addr, MII_PHYSID2, &tmp)) { active_phy_addr = 0xff; return(0); } diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 2f923f2..3f5eeb7 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -318,19 +318,19 @@ static int find_phy(struct eth_device *dev) u16 ctrl, oldctrl; do { - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - oldctrl = ctrl & PHY_BMCR_AUTON; + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + oldctrl = ctrl & BMCR_ANENABLE; - ctrl ^= PHY_BMCR_AUTON; - eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - ctrl &= PHY_BMCR_AUTON; + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + ctrl &= BMCR_ANENABLE; if (ctrl == oldctrl) { phy_addr++; } else { - ctrl ^= PHY_BMCR_AUTON; - eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + ctrl ^= BMCR_ANENABLE; + eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); return phy_addr; } @@ -347,10 +347,10 @@ static int dw_reset_phy(struct eth_device *dev) int timeout = CONFIG_PHYRESET_TIMEOUT; u32 phy_addr = priv->address; - eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); do { - eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); - if (!(ctrl & PHY_BMCR_RESET)) + eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); + if (!(ctrl & BMCR_RESET)) break; udelay(1000); } while (timeout--); @@ -386,33 +386,33 @@ static int configure_phy(struct eth_device *dev) return -1; #if defined(CONFIG_DW_AUTONEG) - bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ - PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; + bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \ + BMCR_FULLDPLX | BMCR_SPEED1000; #else - bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; #if defined(CONFIG_DW_SPEED10M) - bmcr &= ~PHY_BMCR_100MB; + bmcr &= ~BMCR_SPEED100; #endif #if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~PHY_BMCR_DPLX; + bmcr &= ~BMCR_FULLDPLX; #endif #endif - if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) return -1; /* Read the phy status register and populate priv structure */ #if defined(CONFIG_DW_AUTONEG) timeout = CONFIG_AUTONEG_TIMEOUT; do { - eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); - if (bmsr & PHY_BMSR_AUTN_COMP) + eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); + if (bmsr & BMSR_ANEGCOMPLETE) break; udelay(1000); } while (timeout--); - eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); - eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); + eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { priv->speed = SPEED_1000M; @@ -421,28 +421,28 @@ static int configure_phy(struct eth_device *dev) else priv->duplex = HALF_DUPLEX; } else { - if (anlpar & PHY_ANLPAR_100) + if (anlpar & LPA_100) priv->speed = SPEED_100M; else priv->speed = SPEED_10M; - if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + if (anlpar & (LPA_10FULL | LPA_100FULL)) priv->duplex = FULL_DUPLEX; else priv->duplex = HALF_DUPLEX; } #else - if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) return -1; - if (ctrl & PHY_BMCR_DPLX) + if (ctrl & BMCR_FULLDPLX) priv->duplex = FULL_DUPLEX; else priv->duplex = HALF_DUPLEX; - if (ctrl & PHY_BMCR_1000_MBPS) + if (ctrl & BMCR_SPEED1000) priv->speed = SPEED_1000M; - else if (ctrl & PHY_BMCR_100_MBPS) + else if (ctrl & BMCR_SPEED100) priv->speed = SPEED_100M; else priv->speed = SPEED_10M; diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index ae0e0d4..86709a7 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -335,7 +335,7 @@ static struct eth_device* verify_phyaddr (const char *devname, } /* read id2 register */ - if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { + if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) { printf("%s: mii read timeout!\n", devname); return NULL; } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0d0f392..c438962 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -163,20 +163,20 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Reset PHY, then delay 300ns */ #ifdef CONFIG_MX27 - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF); #endif - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, - PHY_BMCR_RESET); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + BMCR_RESET); udelay(1000); /* * Set the auto-negotiation advertisement register bits */ - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR, - PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3); - miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR, - PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE, + LPA_100FULL | LPA_100HALF | LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); + miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); return 0; } @@ -197,12 +197,12 @@ static int miiphy_wait_aneg(struct eth_device *dev) } if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR, - PHY_BMSR, &status)) { + MII_BMSR, &status)) { printf("%s: Autonegotiation failed. status: 0x%04x\n", dev->name, status); return -1; } - } while (!(status & PHY_BMSR_LS)); + } while (!(status & BMSR_LSTATUS)); return 0; } diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 35a6dfb..5330dbc 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -200,7 +200,7 @@ static int fec_send(struct eth_device *dev, volatile void *packet, int length) cbd_t *pTbd, *pUsedTbd; u16 phyStatus; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); /* process all the consumed TBDs */ while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) { diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c index 492f5ce..bd3360c 100644 --- a/drivers/net/inca-ip_sw.c +++ b/drivers/net/inca-ip_sw.c @@ -756,7 +756,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (6 << 16)); /* PHY_ANER */ + (6 << 16)); /* MII_EXPANSION */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); } while (phyReg6 & (1 << 31)); @@ -769,7 +769,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (4 << 16)); /* PHY_ANAR */ + (4 << 16)); /* MII_ADVERTISE */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); } while (phyReg4 & (1 << 31)); @@ -782,7 +782,7 @@ static int inca_amdix(void) (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ - (5 << 16)); /* PHY_ANLPAR */ + (5 << 16)); /* MII_LPA */ do { SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); } while (phyReg5 & (1 << 31)); diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 64be5de..a08ff27 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -141,7 +141,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length) int j, rc; u16 phyStatus; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus); /* section 16.9.23.3 * Wait for ready diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 401182d..f959c00 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -171,7 +171,7 @@ int mii_discover_phy(struct eth_device *dev) for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); + phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type\n", phytype, pass); #endif @@ -180,7 +180,7 @@ int mii_discover_phy(struct eth_device *dev) phyaddr = phyno; phytype <<= 16; phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + mii_send(mk_mii_read(phyno, MII_PHYSID2)); #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d\n", phyno, pass); @@ -256,18 +256,18 @@ void __mii_init(void) status = 0; i++; /* Read PHY control register */ - miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status); + miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); /* If phy set to autonegotiate, wait for autonegotiation done, * if phy is not autonegotiating, just wait for link up. */ - if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS); + if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) { + linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS); } else { - linkgood = PHY_BMSR_LS; + linkgood = BMSR_LSTATUS; } /* Read PHY status register */ - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status); + miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); if ((status & linkgood) == linkgood) break; diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c index bfa651b..de82b04 100644 --- a/drivers/net/ns7520_eth.c +++ b/drivers/net/ns7520_eth.c @@ -387,8 +387,8 @@ static int ns7520_eth_reset(void) ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); /* reset PHY */ - ns7520_mii_write(PHY_BMCR, PHY_BMCR_RESET); - ns7520_mii_write(PHY_BMCR, 0); + ns7520_mii_write(MII_BMCR, BMCR_RESET); + ns7520_mii_write(MII_BMCR, 0); udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ @@ -438,23 +438,23 @@ static void ns7520_link_auto_negotiate(void) /* run auto-negotation */ /* define what we are capable of */ - ns7520_mii_write(PHY_ANAR, - PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | + ns7520_mii_write(MII_ADVERTISE, + LPA_100FULL | + LPA_100HALF | + LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns7520_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + ns7520_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); /* wait for completion */ ulStartJiffies = get_timer(0); while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { - uiStatus = ns7520_mii_read(PHY_BMSR); + uiStatus = ns7520_mii_read(MII_BMSR); if ((uiStatus & - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) == + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) { /* lucky we are, auto-negotiation succeeded */ ns7520_link_print_changed(); ns7520_link_update_egcr(); @@ -515,13 +515,13 @@ static void ns7520_link_print_changed(void) DEBUG_FN(DEBUG_LINK); - uiControl = ns7520_mii_read(PHY_BMCR); + uiControl = ns7520_mii_read(MII_BMCR); - if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - /* PHY_BMSR_LS is only set on autonegotiation */ - uiStatus = ns7520_mii_read(PHY_BMSR); + if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) { + /* BMSR_LSTATUS is only set on autonegotiation */ + uiStatus = ns7520_mii_read(MII_BMSR); - if (!(uiStatus & PHY_BMSR_LS)) { + if (!(uiStatus & BMSR_LSTATUS)) { printk(KERN_WARNING NS7520_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -582,12 +582,12 @@ static char ns7520_mii_identify_phy(void) DEBUG_FN(DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_PHYIDR1); + phyDetected = (PhyType) uiID1 = ns7520_mii_read(MII_PHYSID1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns7520_mii_read(PHY_PHYIDR2); + uiID2 = ns7520_mii_read(MII_PHYSID2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/ns9750_eth.c b/drivers/net/ns9750_eth.c index d4901b4..9899563 100644 --- a/drivers/net/ns9750_eth.c +++ b/drivers/net/ns9750_eth.c @@ -399,8 +399,8 @@ static int ns9750_eth_reset (void) ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); /* reset PHY */ - ns9750_mii_write(PHY_BMCR, PHY_BMCR_RESET); - ns9750_mii_write(PHY_BMCR, 0); + ns9750_mii_write(MII_BMCR, BMCR_RESET); + ns9750_mii_write(MII_BMCR, 0); /* @TODO check time */ udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But @@ -455,26 +455,25 @@ static void ns9750_link_force (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read(PHY_BMCR); - uiControl &= ~(PHY_BMCR_SPEED_MASK | - PHY_BMCR_AUTON | PHY_BMCR_DPLX); + uiControl = ns9750_mii_read(MII_BMCR); + uiControl &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | + BMCR_ANENABLE | BMCR_FULLDPLX); uiLastLinkStatus = 0; if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == FS_EEPROM_AUTONEG_SPEED_100) { - uiControl |= PHY_BMCR_100MB; + uiControl |= BMCR_SPEED100; uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; - } else - uiControl |= PHY_BMCR_10_MBPS; + } if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == FS_EEPROM_AUTONEG_DUPLEX_FULL) { - uiControl |= PHY_BMCR_DPLX; + uiControl |= BMCR_FULLDPLX; uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; } - ns9750_mii_write(PHY_BMCR, uiControl); + ns9750_mii_write(MII_BMCR, uiControl); ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -495,23 +494,23 @@ static void ns9750_link_auto_negotiate (void) /* run auto-negotation */ /* define what we are capable of */ - ns9750_mii_write(PHY_ANAR, - PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | - PHY_ANLPAR_10 | + ns9750_mii_write(MII_ADVERTISE, + LPA_100FULL | + LPA_100HALF | + LPA_10FULL | + LPA_10HALF | PHY_ANLPAR_PSB_802_3); /* start auto-negotiation */ - ns9750_mii_write(PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + ns9750_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); /* wait for completion */ ulStartJiffies = get_ticks (); while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { - uiStatus = ns9750_mii_read(PHY_BMSR); + uiStatus = ns9750_mii_read(MII_BMSR); if ((uiStatus & - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) == - (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)) { + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) == + (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) { /* lucky we are, auto-negotiation succeeded */ ns9750_link_print_changed (); ns9750_link_update_egcr (); @@ -569,13 +568,13 @@ static void ns9750_link_print_changed (void) DEBUG_FN (DEBUG_LINK); - uiControl = ns9750_mii_read(PHY_BMCR); + uiControl = ns9750_mii_read(MII_BMCR); - if ((uiControl & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) { - /* PHY_BMSR_LS is only set on autonegotiation */ - uiStatus = ns9750_mii_read(PHY_BMSR); + if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) { + /* BMSR_LSTATUS is only set on autonegotiation */ + uiStatus = ns9750_mii_read(MII_BMSR); - if (!(uiStatus & PHY_BMSR_LS)) { + if (!(uiStatus & BMSR_LSTATUS)) { printk (KERN_WARNING NS9750_DRIVER_NAME ": link down\n"); /* @TODO Linux: carrier_off */ @@ -634,12 +633,12 @@ static char ns9750_mii_identify_phy (void) DEBUG_FN (DEBUG_MII); - phyDetected = (PhyType) uiID1 = ns9750_mii_read(PHY_PHYIDR1); + phyDetected = (PhyType) uiID1 = ns9750_mii_read(MII_PHYSID1); switch (phyDetected) { case PHY_LXT971A: szName = "LXT971A"; - uiID2 = ns9750_mii_read(PHY_PHYIDR2); + uiID2 = ns9750_mii_read(MII_PHYSID2); nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; cRes = 1; break; diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 2d1de02..483a920 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -354,7 +354,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) printf("Invalid cpu port config, using default port5\n"); } - RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, &reg); switch (reg &= 0xfff0) { case 0x1610: idstr = "88E6161"; diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 3da4c35..aeafeba 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -103,11 +103,11 @@ static void smc911x_phy_configure(struct eth_device *dev) smc911x_phy_reset(dev); - smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_RESET); + smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_RESET); mdelay(1); - smc911x_miiphy_write(dev, 1, PHY_ANAR, 0x01e1); - smc911x_miiphy_write(dev, 1, PHY_BMCR, PHY_BMCR_AUTON | - PHY_BMCR_RST_NEG); + smc911x_miiphy_write(dev, 1, MII_ADVERTISE, 0x01e1); + smc911x_miiphy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | + BMCR_ANRESTART); timeout = 5000; do { @@ -115,9 +115,9 @@ static void smc911x_phy_configure(struct eth_device *dev) if ((timeout--) == 0) goto err_out; - if (smc911x_miiphy_read(dev, 1, PHY_BMSR, &status) != 0) + if (smc911x_miiphy_read(dev, 1, MII_BMSR, &status) != 0) goto err_out; - } while (!(status & PHY_BMSR_LS)); + } while (!(status & BMSR_LSTATUS)); printf(DRIVERNAME ": phy initialized\n"); diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 77908d1..9c8fe62 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -377,11 +377,11 @@ static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -427,17 +427,17 @@ static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) { /* We're using autonegotiation */ - if (mii_reg & PHY_BMSR_AUTN_ABLE) { + if (mii_reg & BMSR_ANEGCAPABLE) { uint lpa = 0; uint gblpa = 0; /* Check for gigabit capability */ - if (mii_reg & PHY_BMSR_EXT) { + if (mii_reg & BMSR_ERCAP) { /* We want a list of states supported by * both PHYs in the link */ - gblpa = read_phy_reg(priv, PHY_1000BTSR); - gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2; + gblpa = read_phy_reg(priv, MII_STAT1000); + gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2; } /* Set the baseline so we only have to set them @@ -457,29 +457,29 @@ static uint mii_parse_link(uint mii_reg, struct tsec_private *priv) return 0; } - lpa = read_phy_reg(priv, PHY_ANAR); - lpa &= read_phy_reg(priv, PHY_ANLPAR); + lpa = read_phy_reg(priv, MII_ADVERTISE); + lpa &= read_phy_reg(priv, MII_LPA); - if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) { + if (lpa & (LPA_100FULL | LPA_100HALF)) { priv->speed = 100; - if (lpa & PHY_ANLPAR_TXFD) + if (lpa & LPA_100FULL) priv->duplexity = 1; - } else if (lpa & PHY_ANLPAR_10FD) + } else if (lpa & LPA_10FULL) priv->duplexity = 1; } else { - uint bmcr = read_phy_reg(priv, PHY_BMCR); + uint bmcr = read_phy_reg(priv, MII_BMCR); priv->speed = 10; priv->duplexity = 0; - if (bmcr & PHY_BMCR_DPLX) + if (bmcr & BMCR_FULLDPLX) priv->duplexity = 1; - if (bmcr & PHY_BMCR_1000_MBPS) + if (bmcr & BMCR_SPEED1000) priv->speed = 1000; - else if (bmcr & PHY_BMCR_100_MBPS) + else if (bmcr & BMCR_SPEED100) priv->speed = 100; } @@ -1645,14 +1645,14 @@ static struct phy_info phy_info_ksz804 = { "Micrel KSZ804 PHY", 4, (struct phy_cmd[]) { /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, - {PHY_BMSR, miim_read, &mii_parse_link}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ @@ -1666,14 +1666,14 @@ static struct phy_info phy_info_generic = { "Unknown/Generic PHY", 32, (struct phy_cmd[]) { /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]) { /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, - {PHY_BMSR, miim_read, &mii_parse_link}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, &mii_parse_link}, {miim_end,} }, (struct phy_cmd[]) { /* shutdown */ diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 35f2368..465a497 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -242,7 +242,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info) advertise = mii_info->advertising; /* Setup standard advertisement */ - adv = phy_read (mii_info, PHY_ANAR); + adv = phy_read (mii_info, MII_ADVERTISE); adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); if (advertise & ADVERTISED_10baseT_Half) adv |= ADVERTISE_10HALF; @@ -252,7 +252,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info) adv |= ADVERTISE_100HALF; if (advertise & ADVERTISED_100baseT_Full) adv |= ADVERTISE_100FULL; - phy_write (mii_info, PHY_ANAR, adv); + phy_write (mii_info, MII_ADVERTISE, adv); } static void genmii_setup_forced (struct uec_mii_info *mii_info) @@ -260,24 +260,24 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info) u16 ctrl; u32 features = mii_info->phyinfo->features; - ctrl = phy_read (mii_info, PHY_BMCR); + ctrl = phy_read (mii_info, MII_BMCR); - ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS | - PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON); - ctrl |= PHY_BMCR_RESET; + ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | + BMCR_SPEED1000 | BMCR_ANENABLE); + ctrl |= BMCR_RESET; switch (mii_info->speed) { case SPEED_1000: if (features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)) { - ctrl |= PHY_BMCR_1000_MBPS; + ctrl |= BMCR_SPEED1000; break; } mii_info->speed = SPEED_100; case SPEED_100: if (features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)) { - ctrl |= PHY_BMCR_100_MBPS; + ctrl |= BMCR_SPEED100; break; } mii_info->speed = SPEED_10; @@ -290,7 +290,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info) break; } - phy_write (mii_info, PHY_BMCR, ctrl); + phy_write (mii_info, MII_BMCR, ctrl); } /* Enable and Restart Autonegotiation */ @@ -298,9 +298,9 @@ static void genmii_restart_aneg (struct uec_mii_info *mii_info) { u16 ctl; - ctl = phy_read (mii_info, PHY_BMCR); - ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - phy_write (mii_info, PHY_BMCR, ctl); + ctl = phy_read (mii_info, MII_BMCR); + ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); + phy_write (mii_info, MII_BMCR, ctl); } static int gbit_config_aneg (struct uec_mii_info *mii_info) @@ -335,7 +335,7 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info) /* The Marvell PHY has an errata which requires * that certain registers get written in order * to restart autonegotiation */ - phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET); + phy_write (mii_info, MII_BMCR, BMCR_RESET); phy_write (mii_info, 0x1d, 0x1f); phy_write (mii_info, 0x1e, 0x200c); @@ -373,18 +373,18 @@ static int genmii_update_link (struct uec_mii_info *mii_info) u16 status; /* Status is read once to clear old link state */ - phy_read (mii_info, PHY_BMSR); + phy_read (mii_info, MII_BMSR); /* * Wait if the link is up, and autonegotiation is in progress * (ie - we're capable and it's not done) */ - status = phy_read(mii_info, PHY_BMSR); - if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE) - && !(status & PHY_BMSR_AUTN_COMP)) { + status = phy_read(mii_info, MII_BMSR); + if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) + && !(status & BMSR_ANEGCOMPLETE)) { int i = 0; - while (!(status & PHY_BMSR_AUTN_COMP)) { + while (!(status & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -395,11 +395,11 @@ static int genmii_update_link (struct uec_mii_info *mii_info) i++; udelay(1000); /* 1 ms */ - status = phy_read(mii_info, PHY_BMSR); + status = phy_read(mii_info, MII_BMSR); } mii_info->link = 1; } else { - if (status & PHY_BMSR_LS) + if (status & BMSR_LSTATUS) mii_info->link = 1; else mii_info->link = 0; @@ -429,13 +429,13 @@ static int genmii_read_status (struct uec_mii_info *mii_info) else mii_info->duplex = DUPLEX_HALF; } else { - status = phy_read(mii_info, PHY_ANLPAR); + status = phy_read(mii_info, MII_LPA); - if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + if (status & (LPA_10FULL | LPA_100FULL)) mii_info->duplex = DUPLEX_FULL; else mii_info->duplex = DUPLEX_HALF; - if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + if (status & (LPA_100FULL | LPA_100HALF)) mii_info->speed = SPEED_100; else mii_info->speed = SPEED_10; @@ -463,8 +463,8 @@ static int bcm_init(struct uec_mii_info *mii_info) /* Wait for aneg to complete. */ do - val = phy_read(mii_info, PHY_BMSR); - while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); + val = phy_read(mii_info, MII_BMSR); + while (--cnt && !(val & BMSR_ANEGCOMPLETE)); /* Set RDX clk delay. */ phy_write(mii_info, 0x18, 0x7 | (7 << 12)); @@ -511,7 +511,7 @@ static int marvell_init(struct uec_mii_info *mii_info) temp |= MII_M1111_HWCFG_MODE_RGMII; phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); - phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET); + phy_write(mii_info, MII_BMCR, BMCR_RESET); } return 0; @@ -582,11 +582,11 @@ static int marvell_config_intr (struct uec_mii_info *mii_info) static int dm9161_init (struct uec_mii_info *mii_info) { /* Reset the PHY */ - phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) | - PHY_BMCR_RESET); + phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) | + BMCR_RESET); /* PHY and MAC connect */ - phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) & - ~PHY_BMCR_ISO); + phy_write (mii_info, MII_BMCR, phy_read (mii_info, MII_BMCR) & + ~BMCR_ISOLATE); phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); @@ -825,11 +825,11 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info) struct phy_info *theInfo = NULL; /* Grab the bits from PHYIR1, and put them in the upper half */ - phy_reg = phy_read (mii_info, PHY_PHYIDR1); + phy_reg = phy_read (mii_info, MII_PHYSID1); phy_ID = (phy_reg & 0xffff) << 16; /* Grab the bits from PHYIR2, and put them in the lower half */ - phy_reg = phy_read (mii_info, PHY_PHYIDR2); + phy_reg = phy_read (mii_info, MII_PHYSID2); phy_ID |= (phy_reg & 0xffff); /* loop through all the known PHY types, and find one that */ @@ -900,8 +900,8 @@ void marvell_phy_interface_mode (struct eth_device *dev, /* handle 88e1111 rev.B2 erratum 5.6 */ if (mii_info->autoneg) { - status = phy_read (mii_info, PHY_BMCR); - phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON); + status = phy_read (mii_info, MII_BMCR); + phy_write (mii_info, MII_BMCR, status | BMCR_ANENABLE); } /* now the B2 will correctly report autoneg completion status */ } diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index 7ac1ff9..929d9bd 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -169,24 +169,6 @@ #define ADVERTISED_BNC (1 << 11) #define ADVERTISED_10000baseT_Full (1 << 12) -/* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - /* Taken from mii_if_info and sungem_phy.h */ struct uec_mii_info { /* Information about the PHY type */ diff --git a/include/miiphy.h b/include/miiphy.h index 2f7d915..42dc127 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -34,6 +34,7 @@ #ifndef _miiphy_h_ #define _miiphy_h_ +#include <linux/mii.h> #include <net.h> int miiphy_read (const char *devname, unsigned char addr, unsigned char reg, @@ -100,89 +101,17 @@ int bb_miiphy_write (const char *devname, unsigned char addr, #define FULL 44 /* phy register offsets */ -#define PHY_BMCR 0x00 -#define PHY_BMSR 0x01 -#define PHY_PHYIDR1 0x02 -#define PHY_PHYIDR2 0x03 -#define PHY_ANAR 0x04 -#define PHY_ANLPAR 0x05 -#define PHY_ANER 0x06 -#define PHY_ANNPTR 0x07 -#define PHY_ANLPNP 0x08 -#define PHY_1000BTCR 0x09 -#define PHY_1000BTSR 0x0A -#define PHY_EXSR 0x0F -#define PHY_PHYSTS 0x10 -#define PHY_MIPSCR 0x11 -#define PHY_MIPGSR 0x12 -#define PHY_DCR 0x13 -#define PHY_FCSCR 0x14 -#define PHY_RECR 0x15 -#define PHY_PCSR 0x16 -#define PHY_LBR 0x17 -#define PHY_10BTSCR 0x18 -#define PHY_PHYCTRL 0x19 - -/* PHY BMCR */ -#define PHY_BMCR_RESET 0x8000 -#define PHY_BMCR_LOOP 0x4000 -#define PHY_BMCR_100MB 0x2000 -#define PHY_BMCR_AUTON 0x1000 -#define PHY_BMCR_POWD 0x0800 -#define PHY_BMCR_ISO 0x0400 -#define PHY_BMCR_RST_NEG 0x0200 -#define PHY_BMCR_DPLX 0x0100 -#define PHY_BMCR_COL_TST 0x0080 - -#define PHY_BMCR_SPEED_MASK 0x2040 -#define PHY_BMCR_1000_MBPS 0x0040 -#define PHY_BMCR_100_MBPS 0x2000 -#define PHY_BMCR_10_MBPS 0x0000 - -/* phy BMSR */ -#define PHY_BMSR_100T4 0x8000 -#define PHY_BMSR_100TXF 0x4000 -#define PHY_BMSR_100TXH 0x2000 -#define PHY_BMSR_10TF 0x1000 -#define PHY_BMSR_10TH 0x0800 -#define PHY_BMSR_EXT_STAT 0x0100 -#define PHY_BMSR_PRE_SUP 0x0040 -#define PHY_BMSR_AUTN_COMP 0x0020 -#define PHY_BMSR_RF 0x0010 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_LS 0x0004 -#define PHY_BMSR_JD 0x0002 -#define PHY_BMSR_EXT 0x0001 - -/*phy ANLPAR */ -#define PHY_ANLPAR_NP 0x8000 -#define PHY_ANLPAR_ACK 0x4000 -#define PHY_ANLPAR_RF 0x2000 -#define PHY_ANLPAR_ASYMP 0x0800 -#define PHY_ANLPAR_PAUSE 0x0400 -#define PHY_ANLPAR_T4 0x0200 -#define PHY_ANLPAR_TXFD 0x0100 -#define PHY_ANLPAR_TX 0x0080 -#define PHY_ANLPAR_10FD 0x0040 -#define PHY_ANLPAR_10 0x0020 -#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */ -/* phy ANLPAR 1000BASE-X */ -#define PHY_X_ANLPAR_NP 0x8000 -#define PHY_X_ANLPAR_ACK 0x4000 -#define PHY_X_ANLPAR_RF_MASK 0x3000 -#define PHY_X_ANLPAR_PAUSE_MASK 0x0180 -#define PHY_X_ANLPAR_HD 0x0040 -#define PHY_X_ANLPAR_FD 0x0020 - -#define PHY_ANLPAR_PSB_MASK 0x001f +#define MII_MIPSCR 0x11 + +/* MII_LPA */ #define PHY_ANLPAR_PSB_802_3 0x0001 #define PHY_ANLPAR_PSB_802_9 0x0002 -/* phy 1000BTCR */ +/* MII_CTRL1000 masks */ #define PHY_1000BTCR_1000FD 0x0200 #define PHY_1000BTCR_1000HD 0x0100 -/* phy 1000BTSR */ +/* MII_STAT1000 masks */ #define PHY_1000BTSR_MSCF 0x8000 #define PHY_1000BTSR_MSCR 0x4000 #define PHY_1000BTSR_LRS 0x2000 @@ -191,9 +120,7 @@ int bb_miiphy_write (const char *devname, unsigned char addr, #define PHY_1000BTSR_1000HD 0x0400 /* phy EXSR */ -#define PHY_EXSR_1000XF 0x8000 -#define PHY_EXSR_1000XH 0x4000 -#define PHY_EXSR_1000TF 0x2000 -#define PHY_EXSR_1000TH 0x1000 +#define ESTATUS_1000XF 0x8000 +#define ESTATUS_1000XH 0x4000 #endif diff --git a/include/tsec.h b/include/tsec.h index 1e90365..d56ec2c 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,6 @@ #define MIIM_STATUS 0x1 #define MIIM_STATUS_AN_DONE 0x00000020 #define MIIM_STATUS_LINK 0x0004 -#define PHY_BMSR_AUTN_ABLE 0x0008 -#define PHY_BMSR_AUTN_COMP 0x0020 #define MIIM_PHYIR1 0x2 #define MIIM_PHYIR2 0x3 -- 1.7.3.4

2 1

[U-Boot] [PATCH] cmd editing: mark erase/tab seqs constant
by Mike Frysinger 09 Jan '11

09 Jan '11

These strings are only read, so no need to have them be writable. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/main.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/common/main.c b/common/main.c index d97ccd7..fa7c49d 100644 --- a/common/main.c +++ b/common/main.c @@ -71,8 +71,8 @@ static int abortboot(int); char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); -static char erase_seq[] = "\b \b"; /* erase sequence */ -static char tab_seq[] = " "; /* used to expand TABs */ +static const char erase_seq[] = "\b \b"; /* erase sequence */ +static const char tab_seq[] = " "; /* used to expand TABs */ #ifdef CONFIG_BOOT_RETRY_TIME static uint64_t endtime = 0; /* must be set, default is instant timeout */ -- 1.7.3.4

2 1

[U-Boot] [PATCH] cmd_mem: localize state variables
by Mike Frysinger 09 Jan '11

09 Jan '11

These "last" variables aren't used outside of this file, so add static. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_mem.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index f7a442a..f03233c 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -48,9 +48,9 @@ static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. * Memory modify remembered values are different from display memory. */ -uint dp_last_addr, dp_last_size; -uint dp_last_length = 0x40; -uint mm_last_addr, mm_last_size; +static uint dp_last_addr, dp_last_size; +static uint dp_last_length = 0x40; +static uint mm_last_addr, mm_last_size; static ulong base_address = 0; -- 1.7.3.4

2 1

[U-Boot] [PATCH] config_cmd_defaults.h: new header for common u-boot command defaults
by Mike Frysinger 09 Jan '11

09 Jan '11

We have config_defaults.h which are random configuration settings that everyone gets by default. We also have config_cmd_default.h which is a recommended list of defaults but boards have to opt into. Now we have config_cmd_defaults.h which is a list of defaults that everyone gets and has to actively opt out of. For now, we populate it with the bootm command which previously was unable to be disabled. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/Makefile | 2 +- include/config_cmd_defaults.h | 14 ++++++++++++++ mkconfig | 1 + 3 files changed, 16 insertions(+), 1 deletions(-) create mode 100644 include/config_cmd_defaults.h diff --git a/common/Makefile b/common/Makefile index abea91c..048df0c 100644 --- a/common/Makefile +++ b/common/Makefile @@ -41,7 +41,7 @@ COBJS-y += xyzModem.o # core command COBJS-y += cmd_boot.o -COBJS-y += cmd_bootm.o +COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o COBJS-y += cmd_help.o COBJS-y += cmd_nvedit.o COBJS-y += cmd_version.o diff --git a/include/config_cmd_defaults.h b/include/config_cmd_defaults.h new file mode 100644 index 0000000..9283daa --- /dev/null +++ b/include/config_cmd_defaults.h @@ -0,0 +1,14 @@ +/* + * config_cmd_defaults.h - sane defaults for everyone + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _CONFIG_CMD_DEFAULTS_H_ +#define _CONFIG_CMD_DEFAULTS_H_ + +#define CONFIG_CMD_BOOTM 1 + +#endif diff --git a/mkconfig b/mkconfig index 2fda1d4..db69336 100755 --- a/mkconfig +++ b/mkconfig @@ -155,6 +155,7 @@ done cat << EOF >> config.h #define CONFIG_BOARDDIR board/$BOARDDIR +#include <config_cmd_defaults.h> #include <config_defaults.h> #include <configs/${CONFIG_NAME}.h> #include <asm/config.h> -- 1.7.3.4

2 3

[U-Boot] [PATCH] Clarify applicable licensing terms in COPYING file.
by Wolfgang Denk 09 Jan '11

09 Jan '11

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- COPYING | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/COPYING b/COPYING index f616ab9..9930863 100644 --- a/COPYING +++ b/COPYING @@ -1,4 +1,11 @@ - NOTE! This copyright does *not* cover the so-called "standalone" + U-Boot is free software. It is copyrighted by Wolfgang Denk and +many others who contributed code (see the actual source code for +details). You can redistribute U-Boot and/or modify it under the +terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 of the License (see text +below), or (at your option) any later version. + + NOTE! This license does *not* cover the so-called "standalone" applications that use U-Boot services by means of the jump table provided by U-Boot exactly for this purpose - this is merely considered normal use of U-Boot, and does *not* fall under the -- 1.6.2.5

2 5

[U-Boot] [RFC PATCH 1/2] hashtable: drop all non-reentrant versions
by Mike Frysinger 09 Jan '11

09 Jan '11

The non-reentrant versions of the hashtable functions operate on a single shared hashtable. So if two different people try using these funcs for two different purposes, they'll cause problems for the other. Avoid this by converting all existing hashtable consumers over to the reentrant versions and then punting the non-reentrant ones. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_nvedit.c | 18 +++++++++--------- common/env_common.c | 6 ++++-- common/env_dataflash.c | 2 +- common/env_eeprom.c | 2 +- common/env_flash.c | 4 ++-- common/env_mmc.c | 2 +- common/env_nand.c | 4 ++-- common/env_nvram.c | 2 +- common/env_onenand.c | 2 +- common/env_sf.c | 4 ++-- include/environment.h | 8 ++++++++ include/search.h | 18 +----------------- lib/hashtable.c | 40 ++-------------------------------------- 13 files changed, 35 insertions(+), 77 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index dcc93c1..d8d314e 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -111,7 +111,7 @@ static int env_print(char *name) e.key = name; e.data = NULL; - ep = hsearch (e, FIND); + hsearch_r(e, FIND, &ep, &env_htab); if (ep == NULL) return 0; len = printf ("%s=%s\n", ep->key, ep->data); @@ -119,7 +119,7 @@ static int env_print(char *name) } /* print whole list */ - len = hexport('\n', &res, 0); + len = hexport_r(&env_htab, '\n', &res, 0); if (len > 0) { puts(res); @@ -184,7 +184,7 @@ int _do_env_set (int flag, int argc, char * const argv[]) */ e.key = name; e.data = NULL; - ep = hsearch (e, FIND); + hsearch_r(e, FIND, &ep, &env_htab); /* Check for console redirection */ if (strcmp(name,"stdin") == 0) { @@ -267,7 +267,7 @@ int _do_env_set (int flag, int argc, char * const argv[]) /* Delete only ? */ if ((argc < 3) || argv[2] == NULL) { - int rc = hdelete(name); + int rc = hdelete_r(name, &env_htab); return !rc; } @@ -293,7 +293,7 @@ int _do_env_set (int flag, int argc, char * const argv[]) e.key = name; e.data = value; - ep = hsearch(e, ENTER); + hsearch_r(e, ENTER, &ep, &env_htab); free(value); if (!ep) { printf("## Error inserting \"%s\" variable, errno=%d\n", @@ -456,7 +456,7 @@ char *getenv (char *name) e.key = name; e.data = NULL; - ep = hsearch (e, FIND); + hsearch_r(e, FIND, &ep, &env_htab); return (ep ? ep->data : NULL); } @@ -651,7 +651,7 @@ static int do_env_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv } if (sep) { /* export as text file */ - len = hexport(sep, &addr, size); + len = hexport_r(&env_htab, sep, &addr, size); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); @@ -670,7 +670,7 @@ static int do_env_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv else /* export as raw binary data */ res = addr; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); @@ -790,7 +790,7 @@ static int do_env_import(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg addr = (char *)ep->data; } - if (himport(addr, size, sep, del ? 0 : H_NOCLEAR) == 0) { + if (himport_r(&env_htab, addr, size, sep, del ? 0 : H_NOCLEAR) == 0) { error("Environment import failed: errno = %d\n", errno); return 1; } diff --git a/common/env_common.c b/common/env_common.c index a276efc..ae710e5 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -129,6 +129,8 @@ uchar default_environment[] = { "\0" }; +struct hsearch_data env_htab; + static uchar env_get_char_init (int index) { uchar c; @@ -187,7 +189,7 @@ void set_default_env(const char *s) puts("Using default environment\n\n"); } - if (himport((char *)default_environment, + if (himport_r(&env_htab, (char *)default_environment, sizeof(default_environment), '\0', 0) == 0) { error("Environment import failed: errno = %d\n", errno); } @@ -213,7 +215,7 @@ int env_import(const char *buf, int check) } } - if (himport((char *)ep->data, ENV_SIZE, '\0', 0)) { + if (himport_r(&env_htab, (char *)ep->data, ENV_SIZE, '\0', 0)) { gd->flags |= GD_FLG_ENV_READY; return 1; } diff --git a/common/env_dataflash.c b/common/env_dataflash.c index 270f2b3..1d57079 100644 --- a/common/env_dataflash.c +++ b/common/env_dataflash.c @@ -68,7 +68,7 @@ int saveenv(void) char *res; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_eeprom.c b/common/env_eeprom.c index 792b44f..0a179ad 100644 --- a/common/env_eeprom.c +++ b/common/env_eeprom.c @@ -143,7 +143,7 @@ int saveenv(void) BUG_ON(env_ptr != NULL); res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_flash.c b/common/env_flash.c index 54c0bfe..456f2e8 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -155,7 +155,7 @@ int saveenv(void) } res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); goto done; @@ -289,7 +289,7 @@ int saveenv(void) goto done; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); goto done; diff --git a/common/env_mmc.c b/common/env_mmc.c index 7c9392c..71dcc4c 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -107,7 +107,7 @@ int saveenv(void) return 1; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_nand.c b/common/env_nand.c index 4e8307a..6f5fac3 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -199,7 +199,7 @@ int saveenv(void) return 1; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; @@ -256,7 +256,7 @@ int saveenv(void) return 1; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_nvram.c b/common/env_nvram.c index 6e90f2b..544ce47 100644 --- a/common/env_nvram.c +++ b/common/env_nvram.c @@ -94,7 +94,7 @@ int saveenv(void) int rcode = 0; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_onenand.c b/common/env_onenand.c index 02cb535..5e04a06 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -109,7 +109,7 @@ int saveenv(void) }; res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; diff --git a/common/env_sf.c b/common/env_sf.c index 47c6a70..41cc00a 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -92,7 +92,7 @@ int saveenv(void) } res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; @@ -308,7 +308,7 @@ int saveenv(void) } res = (char *)&env_new.data; - len = hexport('\0', &res, ENV_SIZE); + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); goto done; diff --git a/include/environment.h b/include/environment.h index bedbc54..082b3e1 100644 --- a/include/environment.h +++ b/include/environment.h @@ -149,6 +149,12 @@ typedef struct environment_s { unsigned char data[ENV_SIZE]; /* Environment data */ } env_t; +#ifndef DO_DEPS_ONLY + +#include <search.h> + +extern struct hsearch_data env_htab; + /* Function that returns a character from the environment */ unsigned char env_get_char (int); @@ -165,4 +171,6 @@ void set_default_env(const char *s); /* Import from binary representation into hash table */ int env_import(const char *buf, int check); +#endif + #endif /* _ENVIRONMENT_H_ */ diff --git a/include/search.h b/include/search.h index fccc757..81ced7f 100644 --- a/include/search.h +++ b/include/search.h @@ -32,15 +32,6 @@ #define __set_errno(val) do { errno = val; } while (0) -/* - * Prototype structure for a linked-list data structure. - * This is the type used by the `insque' and `remque' functions. - */ - -/* For use with hsearch(3). */ -typedef int (*__compar_fn_t) (__const void *, __const void *); -typedef __compar_fn_t comparison_fn_t; - /* Action which shall be performed in the call the hsearch. */ typedef enum { FIND, @@ -69,11 +60,9 @@ struct hsearch_data { }; /* Create a new hashing table which will at most contain NEL elements. */ -extern int hcreate(size_t __nel); extern int hcreate_r(size_t __nel, struct hsearch_data *__htab); /* Destroy current internal hashing table. */ -extern void hdestroy(void); extern void hdestroy_r(struct hsearch_data *__htab); /* @@ -82,25 +71,20 @@ extern void hdestroy_r(struct hsearch_data *__htab); * NULL. If ACTION is `ENTER' replace existing data (if any) with * ITEM.data. * */ -extern ENTRY *hsearch(ENTRY __item, ACTION __action); extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval, struct hsearch_data *__htab); /* Search and delete entry matching ITEM.key in internal hash table. */ -extern int hdelete(const char *__key); extern int hdelete_r(const char *__key, struct hsearch_data *__htab); -extern ssize_t hexport(const char __sep, char **__resp, size_t __size); extern ssize_t hexport_r(struct hsearch_data *__htab, const char __sep, char **__resp, size_t __size); -extern int himport(const char *__env, size_t __size, const char __sep, - int __flag); extern int himport_r(struct hsearch_data *__htab, const char *__env, size_t __size, const char __sep, int __flag); -/* Flags for himport() / himport_r() */ +/* Flags for himport_r() */ #define H_NOCLEAR 1 /* do not clear hash table before importing */ #endif /* search.h */ diff --git a/lib/hashtable.c b/lib/hashtable.c index 7ac3ddd..b47f3b6 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -60,11 +60,6 @@ */ /* - * The non-reentrant version use a global space for storing the hash table. - */ -static struct hsearch_data htab; - -/* * The reentrant version has no static variables to maintain the state. * Instead the interface of all functions is extended to take an argument * which describes the current status. @@ -97,11 +92,6 @@ static int isprime(unsigned int number) return number % div != 0; } -int hcreate(size_t nel) -{ - return hcreate_r(nel, &htab); -} - /* * Before using the hash table we must allocate memory for it. * Test for an existing table are done. We allocate one element @@ -110,6 +100,7 @@ int hcreate(size_t nel) * The contents of the table is zeroed, especially the field used * becomes zero. */ + int hcreate_r(size_t nel, struct hsearch_data *htab) { /* Test for correct arguments. */ @@ -143,15 +134,12 @@ int hcreate_r(size_t nel, struct hsearch_data *htab) /* * hdestroy() */ -void hdestroy(void) -{ - hdestroy_r(&htab); -} /* * After using the hash table it has to be destroyed. The used memory can * be freed and the local static variable can be marked as not used. */ + void hdestroy_r(struct hsearch_data *htab) { int i; @@ -214,15 +202,6 @@ void hdestroy_r(struct hsearch_data *htab) * example for functions like hdelete(). */ -ENTRY *hsearch(ENTRY item, ACTION action) -{ - ENTRY *result; - - (void) hsearch_r(item, action, &result, &htab); - - return result; -} - int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, struct hsearch_data *htab) { @@ -369,11 +348,6 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, * do that. */ -int hdelete(const char *key) -{ - return hdelete_r(key, &htab); -} - int hdelete_r(const char *key, struct hsearch_data *htab) { ENTRY e, *ep; @@ -442,11 +416,6 @@ int hdelete_r(const char *key, struct hsearch_data *htab) * bytes in the string will be '\0'-padded. */ -ssize_t hexport(const char sep, char **resp, size_t size) -{ - return hexport_r(&htab, sep, resp, size); -} - static int cmpkey(const void *p1, const void *p2) { ENTRY *e1 = *(ENTRY **) p1; @@ -605,11 +574,6 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, * '\0' and '\n' have really been tested. */ -int himport(const char *env, size_t size, const char sep, int flag) -{ - return himport_r(&htab, env, size, sep, flag); -} - int himport_r(struct hsearch_data *htab, const char *env, size_t size, const char sep, int flag) { -- 1.7.3.3

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