December 2010 - U-Boot

[U-Boot] Atmel AT91 USB DFU and USB device port driver
by Krishna Pattabiraman 12 Feb '11

12 Feb '11

Hi All, I am currently developing a USB DFU feature for at91sam9263 board. I have to develop the driver for USB device port. I looked the uboot-usb git cdc branch it has a at91_udc.c driver it doesnt contain the udc_* api implementations. I found a earlier post where it was discussed. http://www.mail-archive.com/u-boot@lists.denx.de/msg08709.html Can any point give me a pointer to implement it or the implementations if exist. Bye, Krishna.

3 4

[U-Boot] [PATCH] Fix to make U-Boot work with more USB sticks
by Simon Glass 11 Feb '11

11 Feb '11

I am sending this to the list looking for comments. Testing has been confined to just a few USB sticks - no USB hard drives, USB card readers, etc. But there are reports on the mailing list of problems with U-Boot's detection of USB mass storage devices. We have had a lot of problems with different USB sticks, specifically the faster bulk storage devices. Two of these sticks have a problem where they do not respond to a USB descriptor submission within the allowed U-Boot timeout. This seems to only happen when a REQUEST SENSE is submitted immediately after a TEST UNIT READY fails. There is also some oddness with reset, where some devices need more than one reset. This appears to be due to faulty reset code in U-Boot. USB sticks where this this problem has been noticed are: ID 13fe:3800 Kingston Technology Company Inc. ID 0930:6545 Toshiba Corp. Kingston DataTraveler 2.0 Stick (4GB) / PNY Attache 4GB Stick This problem has been reproduced on the Tegra 20 Seaboard, but it is TBD whether it happens on other ARM platforms with HS USB also. This patch: 1. Increases the USB descriptor submission timeout to 3 seconds since the original 1 second timeout seems arbitrary 2. Replaces the delay-based reset logic with logic which waits until it sees the reset is successful, rather than blindly continuing 3. Resets and retries a USB mass storage device after it fails once, in case even 3 seconds is not enough BUG=chromiumos-6780 TEST=tried with four different USB sticks, including two which previously failed Change-Id: I5bd8891bff67a74b758e349f2a3b3575806eed59 Signed-off-by: Simon Glass <sjg(a)chromium.org> --- common/usb.c | 176 ++++++++++++++++++++++++++++++++++++------- common/usb_storage.c | 55 +++++++++++--- drivers/usb/host/ehci-hcd.c | 20 ++++- include/usb.h | 11 +++ 4 files changed, 217 insertions(+), 45 deletions(-) diff --git a/common/usb.c b/common/usb.c index 9896f46..3265d5d 100644 --- a/common/usb.c +++ b/common/usb.c @@ -222,10 +222,14 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout) { + int err; + if (len < 0) return -1; dev->status = USB_ST_NOT_PROC; /*not yet processed */ - submit_bulk_msg(dev, pipe, data, len); + err = submit_bulk_msg(dev, pipe, data, len); + if (err < 0) + return err; while (timeout--) { if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) break; @@ -758,6 +762,39 @@ struct usb_device *usb_alloc_new_device(void) return &usb_dev[dev_index - 1]; } +/* find a device's parent hub, and reset this device's port on that hub */ + +int usb_reset_device_on_hub(struct usb_device *dev) +{ + struct usb_device *parent = dev->parent; + unsigned short portstatus; + int port = -1; + int err; + + /* find the port number we're at */ + if (parent) { + int j; + + for (j = 0; j < parent->maxchild; j++) { + if (parent->children[j] == dev) { + port = j; + break; + } + } + if (port < 0) { + printf("usb_new_device:cannot locate device's port.\n"); + return 1; + } + + err = hub_port_reset(dev->parent, port, &portstatus); + if (err < 0) { + printf("\n Couldn't reset port %i\n", port); + return 1; + } + } + return 0; +} + /* * Free the newly created device node. * Called in error cases where configuring a newly attached @@ -941,6 +978,14 @@ int usb_new_device(struct usb_device *dev) return 0; } +/* reset and restart a device that is misbehaving */ + +int usb_restart_device(struct usb_device *dev) +{ + usb_reset_device_on_hub(dev); /* ignore return value */ + return usb_new_device(dev); +} + /* build device Tree */ void usb_scan_devices(void) { @@ -1069,45 +1114,123 @@ static inline char *portspeed(int portstatus) return "12 Mb/s"; } -static int hub_port_reset(struct usb_device *dev, int port, - unsigned short *portstat) +/* brought this in from kernel 2.6.36 as it is a problem area. Some USB +sticks do not operate properly with the previous reset code */ +#define PORT_RESET_TRIES 5 +#define SET_ADDRESS_TRIES 2 +#define GET_DESCRIPTOR_TRIES 2 +#define SET_CONFIG_TRIES (2 * (use_both_schemes + 1)) +#define USE_NEW_SCHEME(i) ((i) / 2 == old_scheme_first) + +#define HUB_ROOT_RESET_TIME 50 /* times are in msec */ +#define HUB_SHORT_RESET_TIME 10 +#define HUB_LONG_RESET_TIME 200 +#define HUB_RESET_TIMEOUT 500 + +#define ENOTCONN 107 + +static int hub_port_wait_reset(struct usb_device *dev, int port, + unsigned int delay, unsigned short *portstatus_ret) { - int tries; + int delay_time, ret; struct usb_port_status portsts; unsigned short portstatus, portchange; - USB_HUB_PRINTF("hub_port_reset: resetting port %d...\n", port); - for (tries = 0; tries < MAX_TRIES; tries++) { - - usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); - wait_ms(200); + for (delay_time = 0; + delay_time < HUB_RESET_TIMEOUT; + delay_time += delay) { + /* wait to give the device a chance to reset */ + wait_ms(delay); - if (usb_get_port_status(dev, port + 1, &portsts) < 0) { + /* read and decode port status */ + ret = usb_get_port_status(dev, port + 1, &portsts); + if (ret < 0) { USB_HUB_PRINTF("get_port_status failed status %lX\n", dev->status); - return -1; + return ret; } portstatus = le16_to_cpu(portsts.wPortStatus); portchange = le16_to_cpu(portsts.wPortChange); - USB_HUB_PRINTF("portstatus %x, change %x, %s\n", - portstatus, portchange, - portspeed(portstatus)); + /* Device went away? */ + if (!(portstatus & USB_PORT_STAT_CONNECTION)) + return -ENOTCONN; - USB_HUB_PRINTF("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \ - " USB_PORT_STAT_ENABLE %d\n", - (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0, - (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, - (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); + /* bomb out completely if the connection bounced */ + if ((portchange & USB_PORT_STAT_C_CONNECTION)) + return -ENOTCONN; - if ((portchange & USB_PORT_STAT_C_CONNECTION) || - !(portstatus & USB_PORT_STAT_CONNECTION)) - return -1; + /* if we`ve finished resetting, then break out of the loop */ + if (!(portstatus & USB_PORT_STAT_RESET) && + (portstatus & USB_PORT_STAT_ENABLE)) { + *portstatus_ret = portstatus; + return 0; + } - if (portstatus & USB_PORT_STAT_ENABLE) - break; + /* switch to the long delay after two short delay failures */ + if (delay_time >= 2 * HUB_SHORT_RESET_TIME) + delay = HUB_LONG_RESET_TIME; + + USB_HUB_PRINTF( + "port %d not reset yet, waiting %dms\n", + port, delay); + } + + return -1; +} + + +static int hub_port_reset(struct usb_device *dev, int port, + unsigned short *portstat) +{ + int tries, status; + unsigned delay = HUB_SHORT_RESET_TIME; + int oldspeed = dev->speed; + + /* root hub ports have a slightly longer reset period + * (from USB 2.0 spec, section 7.1.7.5) + */ + if (!dev->parent) { + delay = HUB_ROOT_RESET_TIME; + } - wait_ms(200); + /* Some low speed devices have problems with the quick delay, so */ + /* be a bit pessimistic with those devices. RHbug #23670 */ + if (oldspeed == USB_SPEED_LOW) + delay = HUB_LONG_RESET_TIME; + + USB_HUB_PRINTF("hub_port_reset: resetting port %d...\n", port); + for (tries = 0; tries < MAX_TRIES; tries++) { + + status = usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET); + if (status) + USB_HUB_PRINTF("cannot reset port %d (err = %d)\n", + port, status); + else { + status = hub_port_wait_reset(dev, port, delay, + portstat); + if (status && status != -ENOTCONN) + USB_HUB_PRINTF("port_wait_reset: err = %d\n", + status); + } + + /* return on disconnect or reset */ + switch (status) { + case 0: + /* TRSTRCY = 10 ms; plus some extra */ + wait_ms(10 + 40); + /* FALL THROUGH */ + case -1: + /* we have finished trying to reset, so return */ + usb_clear_port_feature(dev, + port + 1, USB_PORT_FEAT_C_RESET); + return 0; + } + + USB_HUB_PRINTF ( + "port %d not enabled, trying reset again...\n", + port); + delay = HUB_LONG_RESET_TIME; } if (tries == MAX_TRIES) { @@ -1116,9 +1239,6 @@ static int hub_port_reset(struct usb_device *dev, int port, USB_HUB_PRINTF("Maybe the USB cable is bad?\n"); return -1; } - - usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET); - *portstat = portstatus; return 0; } diff --git a/common/usb_storage.c b/common/usb_storage.c index 76949b8..0fb9c1b 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -158,9 +158,10 @@ struct us_data { static struct us_data usb_stor[USB_MAX_STOR_DEV]; +/* start our error numbers after the USB ones */ #define USB_STOR_TRANSPORT_GOOD 0 -#define USB_STOR_TRANSPORT_FAILED -1 -#define USB_STOR_TRANSPORT_ERROR -2 +#define USB_STOR_TRANSPORT_FAILED (USB_ENEXTFREE) +#define USB_STOR_TRANSPORT_ERROR (USB_ENEXTFREE-1) int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); @@ -213,6 +214,7 @@ int usb_stor_scan(int mode) { unsigned char i; struct usb_device *dev; + int result; /* GJ */ memset(usb_stor_buf, 0, sizeof(usb_stor_buf)); @@ -244,8 +246,21 @@ int usb_stor_scan(int mode) /* ok, it is a storage devices * get info and fill it in */ - if (usb_stor_get_info(dev, &usb_stor[usb_max_devs], - &usb_dev_desc[usb_max_devs]) == 1) + result = usb_stor_get_info(dev, &usb_stor[usb_max_devs], + &usb_dev_desc[usb_max_devs]); + if (result == USB_EDEVCRITICAL) { + /* + * Something there, but failed badly. + * Retry one more time. This happens + * sometimes with some USB sticks, + * e.g. Patriot Rage ID 13fe:3800 + */ + printf ("."); + usb_restart_device(dev); /* ignore return value */ + result = usb_stor_get_info(dev, &usb_stor[usb_max_devs], + &usb_dev_desc[usb_max_devs]); + } + if (result == 1) usb_max_devs++; } /* if storage device */ @@ -690,10 +705,13 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) goto st; } if (result < 0) { - USB_STOR_PRINTF("usb_bulk_msg error status %ld\n", + USB_STOR_PRINTF("usb_bulk_msg error status %#lx\n", us->pusb_dev->status); usb_stor_BBB_reset(us); - return USB_STOR_TRANSPORT_FAILED; + + /* if we got a critical device error, report it specially */ + return result == USB_EDEVCRITICAL ? result + : USB_STOR_TRANSPORT_FAILED; } #ifdef BBB_XPORT_TRACE for (index = 0; index < data_actlen; index++) @@ -900,6 +918,7 @@ static int usb_inquiry(ccb *srb, struct us_data *ss) static int usb_request_sense(ccb *srb, struct us_data *ss) { + int result; char *ptr; ptr = (char *)srb->pdata; @@ -909,7 +928,12 @@ static int usb_request_sense(ccb *srb, struct us_data *ss) srb->datalen = 18; srb->pdata = &srb->sense_buf[0]; srb->cmdlen = 12; - ss->transport(srb, ss); + result = ss->transport(srb, ss); + if (result < 0) { + if (result != USB_EDEVCRITICAL) + USB_STOR_PRINTF("Request Sense failed\n"); + return result; + } USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); @@ -920,6 +944,7 @@ static int usb_request_sense(ccb *srb, struct us_data *ss) static int usb_test_unit_ready(ccb *srb, struct us_data *ss) { int retries = 10; + int result; do { memset(&srb->cmd[0], 0, 12); @@ -928,7 +953,9 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss) srb->cmdlen = 12; if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) return 0; - usb_request_sense(srb, ss); + result = usb_request_sense(srb, ss); + if (result == USB_EDEVCRITICAL) + return result; wait_ms(100); } while (retries--); @@ -1314,6 +1341,7 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, unsigned long cap[2]; unsigned long *capacity, *blksz; ccb *pccb = &usb_ccb; + int result; /* for some reasons a couple of devices would not survive this reset */ if ( @@ -1372,11 +1400,14 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, #endif /* CONFIG_USB_BIN_FIXUP */ USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n", usb_stor_buf[2], usb_stor_buf[3]); - if (usb_test_unit_ready(pccb, ss)) { + result = usb_test_unit_ready(pccb, ss); + if (result) { + if (result == USB_EDEVCRITICAL) + return result; printf("Device NOT ready\n" - " Request Sense returned %02X %02X %02X\n", - pccb->sense_buf[2], pccb->sense_buf[12], - pccb->sense_buf[13]); + " Request Sense returned %02X %02X %02X\n", + pccb->sense_buf[2], pccb->sense_buf[12], + pccb->sense_buf[13]); if (dev_desc->removable == 1) { dev_desc->type = perq; return 1; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 13cd84a..1143cd6 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -330,6 +330,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, uint32_t c, toggle; uint32_t cmd; int ret = 0; + int result = USB_EFAIL; #ifdef CONFIG_USB_EHCI_DATA_ALIGN /* In case ehci host requires alignment for buffers */ @@ -342,8 +343,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, if (!align_buf) return -1; if ((int)align_buf & (CONFIG_USB_EHCI_DATA_ALIGN - 1)) - buffer = (void *)((int)align_buf + - CONFIG_USB_EHCI_DATA_ALIGN - + buffer = (void *)((int)align_buf + + CONFIG_USB_EHCI_DATA_ALIGN - ((int)align_buf & (CONFIG_USB_EHCI_DATA_ALIGN - 1))); else buffer = align_buf; @@ -475,7 +476,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, goto fail; } - /* Wait for TDs to be processed. */ + /* + * Wait for TDs to be processed. We wait 3s since some USB + * sticks can take a long time immediately after system reset + */ ts = get_timer(0); vtd = td; do { @@ -484,7 +488,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, token = hc32_to_cpu(vtd->qt_token); if (!(token & 0x80)) break; - } while (get_timer(ts) < CONFIG_SYS_HZ); + } while (get_timer(ts) < CONFIG_SYS_HZ * 3); /* Disable async schedule. */ cmd = ehci_readl(&hcor->or_usbcmd); @@ -497,6 +501,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, printf("EHCI fail timeout STD_ASS reset\n"); goto fail; } + /* check that the TD processing happened */ + if (token & 0x80) { + printf("EHCI timed out on TD - token=%#x\n", token); + result = USB_EDEVCRITICAL; + goto fail; + } qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); @@ -559,7 +569,7 @@ fail: td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); } ehci_free(qh, sizeof(*qh)); - return -1; + return result; } static inline int min3(int a, int b, int c) diff --git a/include/usb.h b/include/usb.h index afd65e3..91aa441 100644 --- a/include/usb.h +++ b/include/usb.h @@ -42,6 +42,16 @@ #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ +/* + * Errors we can report, e.g. return USB_EDEVCRITICAL + * Use -ve numbers to fit in with usb_storage + * U-Boot needs some unified numbers + */ +#define USB_EOK 0 /* ok, no error */ +#define USB_EFAIL -1 /* general failure(!) */ +#define USB_EDEVCRITICAL -2 /* must reset device on hub */ +#define USB_ENEXTFREE -3 /* next free error number */ + /* device request (setup) */ struct devrequest { unsigned char requesttype; @@ -198,6 +208,7 @@ int usb_get_class_descriptor(struct usb_device *dev, int ifnum, int usb_clear_halt(struct usb_device *dev, int pipe); int usb_string(struct usb_device *dev, int index, char *buf, size_t size); int usb_set_interface(struct usb_device *dev, int interface, int alternate); +int usb_restart_device(struct usb_device *dev); /* big endian -> little endian conversion */ /* some CPUs are already little endian e.g. the ARM920T */ -- 1.7.3.1

3 11

[U-Boot] [PATCH] BLOCK: Fixup iMX51 ATA driver
by Marek Vasut 01 Feb '11

01 Feb '11

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- NOTE: Wolfgang, is this what you meant ? If so, I'll merge this with the old driver and send a v2 patch. Otherwise, can you point me in a right direction? NOTE2: I haven't tested this, I'll do so in the evening. drivers/block/mxc_ata.c | 131 +++++++++++++++++++++++++--------------------- 1 files changed, 71 insertions(+), 60 deletions(-) diff --git a/drivers/block/mxc_ata.c b/drivers/block/mxc_ata.c index 6f19e6f..e65cfa7 100644 --- a/drivers/block/mxc_ata.c +++ b/drivers/block/mxc_ata.c @@ -37,49 +37,53 @@ #include <asm/arch/clock.h> /* MXC ATA register offsets */ -enum { - MXC_ATA_TIME_OFF = 0x00, - MXC_ATA_TIME_ON = 0x01, - MXC_ATA_TIME_1 = 0x02, - MXC_ATA_TIME_2W = 0x03, - MXC_ATA_TIME_2R = 0x04, - MXC_ATA_TIME_AX = 0x05, - MXC_ATA_TIME_PIO_RDX = 0x06, - MXC_ATA_TIME_4 = 0x07, - MXC_ATA_TIME_9 = 0x08, - MXC_ATA_TIME_M = 0x09, - MXC_ATA_TIME_JN = 0x0a, - MXC_ATA_TIME_D = 0x0b, - MXC_ATA_TIME_K = 0x0c, - MXC_ATA_TIME_ACK = 0x0d, - MXC_ATA_TIME_ENV = 0x0e, - MXC_ATA_TIME_UDMA_RDX = 0x0f, - MXC_ATA_TIME_ZAH = 0x10, - MXC_ATA_TIME_MLIX = 0x11, - MXC_ATA_TIME_DVH = 0x12, - MXC_ATA_TIME_DZFS = 0x13, - MXC_ATA_TIME_DVS = 0x14, - MXC_ATA_TIME_CVH = 0x15, - MXC_ATA_TIME_SS = 0x16, - MXC_ATA_TIME_CYC = 0x17, - MXC_ATA_FIFO_DATA_16 = 0x1c, - MXC_ATA_FIFO_DATA_32 = 0x18, - MXC_ATA_FIFO_FILL = 0x20, - MXC_ATA_ATA_CONTROL = 0x24, - MXC_ATA_INTERRUPT_PENDING = 0x28, - MXC_ATA_INTERRUPT_ENABLE = 0x2c, - MXC_ATA_INTERRUPT_CLEAR = 0x30, - MXC_ATA_FIFO_ALARM = 0x34, - MXC_ATA_DRIVE_DATA = 0xa0, - MXC_ATA_DRIVE_FEATURES = 0xa4, - MXC_ATA_DRIVE_SECTOR_COUNT = 0xa8, - MXC_ATA_DRIVE_SECTOR_NUM = 0xac, - MXC_ATA_DRIVE_CYL_LOW = 0xb0, - MXC_ATA_DRIVE_CYL_HIGH = 0xb4, - MXC_ATA_DRIVE_DEV_HEAD = 0xb8, - MXC_ATA_COMMAND = 0xbc, - MXC_ATA_STATUS = 0xbc, - MXC_ATA_ALT_STATUS = 0xd8, +struct mxc_ata_config_regs { + u8 time_off; /* 0x00 */ + u8 time_on; + u8 time_1; + u8 time_2w; + u8 time_2r; + u8 time_ax; + u8 time_pio_rdx; + u8 time_4; + u8 time_9; + u8 time_m; + u8 time_jn; + u8 time_d; + u8 time_k; + u8 time_ack; + u8 time_env; + u8 time_udma_rdx; + u8 time_zah; /* 0x10 */ + u8 time_mlix; + u8 time_dvh; + u8 time_dzfs; + u8 time_dvs; + u8 time_cvh; + u8 time_ss; + u8 time_cyc; + u32 hole; + u32 fifo_data_16; + u32 fifo_data_32; + u32 fifo_fill; + u32 ata_control; + u32 interrupt_pending; + u32 interrupt_enable; + u32 interrupt_clear; + u32 fifo_alarm; +}; + +struct mxc_data_hdd_regs { + u32 drive_data; /* 0xa0 */ + u32 drive_features; + u32 drive_sector_count; + u32 drive_sector_num; + u32 drive_cyl_low; + u32 drive_cyl_high; + u32 drive_dev_head; + u32 command; + u32 status; + u32 alt_status; }; /* PIO timing table */ @@ -93,47 +97,54 @@ uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; -#define REG_TO_OFFSET(reg) ((reg & 0x3) * 8) +#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) static void set_ata_bus_timing(unsigned char mode) { uint32_t val; uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + if (mode >= NR_PIO_SPECS) return; /* Write TIME_OFF/ON/1/2W */ - val = (3 << REG_TO_OFFSET(MXC_ATA_TIME_OFF)) | - (3 << REG_TO_OFFSET(MXC_ATA_TIME_ON)) | - (((pio_t1[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_1)) | - (((pio_t2_8[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_2W)); - writel(val, MXC_ATA_TIME_OFF + CONFIG_SYS_ATA_BASE_ADDR); + val = (3 << REG2OFF(&ata_cfg_regs->time_off)) | + (3 << REG2OFF(&ata_cfg_regs->time_on)) | + (((pio_t1[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_1)) | + (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2w)); + writeb(val, &ata_cfg_regs->time_off); /* Write TIME_2R/AX/RDX/4 */ - val = (((pio_t2_8[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_2R)) | - (((pio_tA[mode] + T) / T + 2) << REG_TO_OFFSET(MXC_ATA_TIME_AX)) | - (1 << REG_TO_OFFSET(MXC_ATA_TIME_PIO_RDX)) | - (((pio_t4[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_4)); - writel(val, MXC_ATA_TIME_2R + CONFIG_SYS_ATA_BASE_ADDR); + val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2r)) | + (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_cfg_regs->time_ax)) | + (1 << REG2OFF(&ata_cfg_regs->time_pio_rdx)) | + (((pio_t4[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_4)); + writel(val, &ata_cfg_regs->time_2r); /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ - val = (((pio_t9[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_9)); - writel(val, MXC_ATA_TIME_9 + CONFIG_SYS_ATA_BASE_ADDR); + val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_9)); + writel(val, &ata_cfg_regs->time_9); } int ide_preinit(void) { - uint32_t ata_control = CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_ATA_CONTROL; + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; /* 46.3.3.4 @ FSL iMX51 manual */ - writel(0x80, ata_control); /* FIFO normal op., drive reset */ - writel(0xc0, ata_control); /* FIFO normal op., drive not reset */ + /* FIFO normal op., drive reset */ + writel(0x80, ata_cfg_regs->ata_control); + /* FIFO normal op., drive not reset */ + writel(0xc0, ata_cfg_regs->ata_control); /* Configure the PIO timing */ set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); /* 46.3.3.4 @ FSL iMX51 manual */ - writel(0x41, ata_control); /* Drive not reset, IORDY handshake */ + /* Drive not reset, IORDY handshake */ + writel(0x41, ata_cfg_regs->ata_control); return 0; } -- 1.7.2.3

2 2

[U-Boot] U-Boot v2010.12 released - Merge Window OPEN
by Wolfgang Denk 28 Jan '11

28 Jan '11

Hello all, U-Boot v2010.12 has been released and is available from the git repository and the FTP server. The "next" branch has been pulled into mainline ("master" branch) and has been removed afterward. ******************** ******************** ** ** ** BIG FAT NOTE ** ** ** ******************** ******************** The release contains, among many other things, 3 major groups of changes: 1) New implementation for internal handling of environment variables. In addition to the traditional commands "setenv", "printenv" and "saveenv" there is now a new "env" command with a number opf subcommands that offer many new features. Please see the commit message of commit ea882baf for details: http://git.denx.de/?p=3Du-boot.git;a=3Dcommit;h=3Dea882baf 2) ARM cache support. This greatly accelerates U-Boot on many ARM systems, especially functions like uncompressing images or loading images form external storage are now much faster, sometimes by a factor > 10. For details please see these commits: 7e4a9e6 ARM (ARM11): add data cache support, test on Qong board 95c6f6d ARM V7 (OMAP): add data cache support, test on Beagle board c3330e9 ARM (ARM926ejs): add data cache support, tested on magnesium and tx25 board http://git.denx.de/?p=u-boot.git;a=commit;h=7e4a9e6 http://git.denx.de/?p=u-boot.git;a=commit;h=95c6f6d http://git.denx.de/?p=u-boot.git;a=commit;h=c3330e9 3) ARM relocation support (ELF relocation) This allows to efficiently use the same U-Boot binary image on systems with different RAM sizes, and brings the implementation much more in line with the code used for example on Power Architecture systems (eventually allowing to merge into common code). This seems especially interesting now that ARM is getting Device Tree support as well. Please note that not all ARM boards have been adapted to this new code yet, which requires testing on the actual hardware, so this is a task for the respective board maintainers or other users. ***************************************************************** * Currently, >100 ARM boards are *broken* and *do not compile*. * ***************************************************************** Board maintainers or othe rinterested parties are requested to adapt their boards to the new code in the timeframe of the upcoming release v2010.03; all boards that have not been converted by then, i. e. that are still broken then, are considered unmaintained and without interest to the community and will be removed. --- end of big fat note --- The Merge Window for the next release (v2011.03) is open until Sat Jan 15, 2011, 23:59:59 CET = 24 days remaining. The next release v2011.03 is scheduled for March 13, 2011. See http://www.denx.de/wiki/U-Boot/ReleaseCycle for details, including guestimates for the next releases after that. A little statistics [1] - changes since release v2020.09: Processed 859 csets from 111 developers 29 employers found A total of 75649 lines added, 90937 removed (delta -15288) Developers with the most changesets Wolfgang Denk 90 (10.5%) Mike Frysinger 58 (6.8%) Stefan Roese 41 (4.8%) Marek Vasut 41 (4.8%) Heiko Schocher 39 (4.5%) Peter Tyser 36 (4.2%) Stefano Babic 32 (3.7%) Andreas Bießmann 22 (2.6%) Kumar Gala 21 (2.4%) Steve Sakoman 21 (2.4%) ... Developers with the most changed lines Wolfgang Denk 32621 (23.4%) Mike Frysinger 24015 (17.2%) Marek Vasut 11055 (7.9%) Stefano Babic 10994 (7.9%) Stefan Roese 4722 (3.4%) Heiko Schocher 4668 (3.3%) Remy Bohmer 4425 (3.2%) Peter Tyser 4069 (2.9%) Reinhard Meyer 2539 (1.8%) Dirk Eibach 1544 (1.1%) ... Developers with the most lines removed Wolfgang Denk 23946 (26.3%) Mike Frysinger 13431 (14.8%) Marek Vasut 6370 (7.0%) Peter Tyser 3131 (3.4%) Stefan Roese 962 (1.1%) Prafulla Wadaskar 645 (0.7%) Timur Tabi 635 (0.7%) Andreas Bießmann 471 (0.5%) Mikhail Kshevetskiy 411 (0.5%) Kumar Gala 248 (0.3%) ... Developers with the most signoffs (total 206) Kumar Gala 51 (24.8%) Sandeep Paulraj 45 (21.8%) Ben Warren 14 (6.8%) Wolfgang Denk 13 (6.3%) Mike Frysinger 12 (5.8%) Peter Tyser 11 (5.3%) Kim Phillips 11 (5.3%) Stefan Roese 10 (4.9%) Anatolij Gustschin 6 (2.9%) Kyungmin Park 4 (1.9%) ... Developers with the most reviews (total 4) Ben Gardiner 3 (75.0%) Sudhakar Rajashekhara 1 (25.0%) Developers with the most test credits (total 55) Steve Sakoman 10 (18.2%) Heiko Schocher 10 (18.2%) Ben Gardiner 9 (16.4%) Stefano Babic 8 (14.5%) Wolfgang Denk 3 (5.5%) Reinhard Meyer 3 (5.5%) Sandeep Paulraj 2 (3.6%) Thomas Chou 2 (3.6%) Sudhakar Rajashekhara 1 (1.8%) Peter Tyser 1 (1.8%) ... Developers who gave the most tested-by credits (total 55) Wolfgang Denk 10 (18.2%) Scott Wood 5 (9.1%) Dirk Behme 5 (9.1%) Steve Sakoman 4 (7.3%) Jerry Huang 4 (7.3%) Sukumar Ghorai 4 (7.3%) Nick Thompson 3 (5.5%) Enric Balletbo i Serra 3 (5.5%) John Rigby 2 (3.6%) Kumar Gala 2 (3.6%) ... Developers with the most report credits (total 4) Vivi Li 2 (50.0%) Dan Lykowski 1 (25.0%) Peter Maydell 1 (25.0%) Developers who gave the most report credits (total 4) Mike Frysinger 2 (50.0%) Wolfgang Denk 1 (25.0%) Steve Sakoman 1 (25.0%) Top changeset contributors by employer DENX Software Engineering 210 (24.4%) (Unknown) 207 (24.1%) Freescale 83 (9.7%) Analog Devices 59 (6.9%) Extreme Engineering Solutions 46 (5.4%) Texas Instruments 26 (3.0%) Graeme Russ 20 (2.3%) Sakoman Inc. 20 (2.3%) Nobuhiro Iwamatsu 17 (2.0%) EmCraft Systems 14 (1.6%) ... Top lines changed by employer DENX Software Engineering 56393 (40.4%) Analog Devices 30593 (21.9%) (Unknown) 29056 (20.8%) Extreme Engineering Solutions 5551 (4.0%) Freescale 4445 (3.2%) Oce Technologies 4425 (3.2%) Guntermann & Drunck 1544 (1.1%) EmCraft Systems 1467 (1.1%) Marvell 1443 (1.0%) Liebherr 1090 (0.8%) ... Employers with the most signoffs (total 206) Freescale 65 (31.6%) Texas Instruments 46 (22.3%) DENX Software Engineering 32 (15.5%) (Unknown) 32 (15.5%) Analog Devices 13 (6.3%) Extreme Engineering Solutions 11 (5.3%) Samsung 6 (2.9%) Gaisler Research 1 (0.5%) [1] See http://www.denx.de/wiki/U-Boot/UbootStat_2010_12 for full statistics, and http://www.denx.de/wiki/UBoot/ReleaseCycle for links to statistics for earlier releases. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Prediction is very difficult, especially of the future. - Niels Bohr

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[U-Boot] [PATCH] mpq101: initial support for Mercury Computer Systems MPQ101 board
by Alex Dubov 27 Jan '11

27 Jan '11

Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548 processor, 512MB of hardwired DDR2 RAM and 128MB of hardwired NAND flash memory. USB controller is available, but not presently enabled. Additional board information is available at: http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.as… Signed-off-by: Alex Dubov <oakad(a)yahoo.com> --- board/mercury/mpq101/Makefile | 53 ++++++ board/mercury/mpq101/config.mk | 7 + board/mercury/mpq101/law.c | 54 ++++++ board/mercury/mpq101/mpq101.c | 167 ++++++++++++++++++ board/mercury/mpq101/tlb.c | 82 +++++++++ boards.cfg | 1 + include/configs/mpq101.h | 381 ++++++++++++++++++++++++++++++++++++++++ 7 files changed, 745 insertions(+), 0 deletions(-) create mode 100644 board/mercury/mpq101/Makefile create mode 100644 board/mercury/mpq101/config.mk create mode 100644 board/mercury/mpq101/law.c create mode 100644 board/mercury/mpq101/mpq101.c create mode 100644 board/mercury/mpq101/tlb.c create mode 100644 include/configs/mpq101.h diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile new file mode 100644 index 0000000..58bc1b3 --- /dev/null +++ b/board/mercury/mpq101/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk new file mode 100644 index 0000000..1870680 --- /dev/null +++ b/board/mercury/mpq101/config.mk @@ -0,0 +1,7 @@ +# +# mpq101 board +# + +# Make room for environment at the beginning of flash sector +CONFIG_SYS_TEXT_BASE = 0xfffc0800 +LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR) diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c new file mode 100644 index 0000000..bc89bc5 --- /dev/null +++ b/board/mercury/mpq101/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x1fff_ffff DDR SYS_SDRAM_SIZE + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1, + LAW_TRGT_IF_DDR_1), +#ifdef CONFIG_SYS_RIO_MEM_PHYS + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c new file mode 100644 index 0000000..18fb88e --- /dev/null +++ b/board/mercury/mpq101/mpq101.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2010 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> + +void local_bus_init(void); +void sdram_init(void); + +unsigned long get_clock_freq(void) +{ + return 33000000; +} + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + puts ("Board: Mercury Computer Systems, Inc. MPQ-101 "); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) "); +#endif + putc ('\n'); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */ + + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ + return 0; +} + +phys_size_t +initdram (int board_type) +{ + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + phys_size_t dram_size = 0; + const char *p_mode = getenv("perf_mode"); + + puts("Initializing...."); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + + if (p_mode && !strcmp("performance", p_mode)) { + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_PERF; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_PERF; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_PERF; + } else { + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + } + + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; + + asm("sync;isync"); + udelay(500); + + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + asm("sync; isync"); + udelay(500); + + dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20)); + + puts(" DDR: "); + + return dram_size << 20; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ +} + +void +pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* PCI is disabled */ + out_be32(&gur->devdisr, in_be32(&gur->devdisr) + | MPC85xx_DEVDISR_PCI1 + | MPC85xx_DEVDISR_PCI2 + | MPC85xx_DEVDISR_PCIE); +} + + +#if defined(CONFIG_OF_BOARD_SETUP) + +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +#endif diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c new file mode 100644 index 0000000..1f1c5b1 --- /dev/null +++ b/board/mercury/mpq101/tlb.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 256M Non-cacheable, guarded + * 0xf0000000 256M LBC (FLASH included) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, + CONFIG_SYS_LBC_OPTION_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 1: 1M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_SYS_RIO_MEM_PHYS + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 08e531e..a0baa4f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -189,6 +189,7 @@ TQM834x powerpc mpc83xx tqm834x tqc sbc8349 powerpc mpc83xx sbc8349 - - sbc8349 caddy2 powerpc mpc83xx vme8349 esd - vme8349:CADDY2 vme8349 powerpc mpc83xx vme8349 esd - vme8349 +mpq101 powerpc mpc85xx mpq101 mercury - mpq101 PM854 powerpc mpc85xx pm854 PM856 powerpc mpc85xx pm856 P1022DS powerpc mpc85xx p1022ds freescale diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h new file mode 100644 index 0000000..7f8c5c5 --- /dev/null +++ b/include/configs/mpq101.h @@ -0,0 +1,381 @@ +/* + * Copyright 2010 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Merury Computers MPQ101 board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + +//#define DEBUG 5 +//#define CMD_MEM_DEBUG 1 + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_MPQ101 1 /* MPQ101 board specific */ + +#define CONFIG_RIO + +#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE 1 /* toggle L2 cache */ +#define CONFIG_BTB 1 /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + + +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0ffffffc + +#define CONFIG_PANIC_HANG + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define +#define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_SPD_EEPROM +#undef CONFIG_DDR_SPD +#undef CONFIG_DDR_DLL + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1 /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* Fixed 512MB DDR2 parameters */ +#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 +#define CONFIG_SYS_DDR_TIMING_3 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432 +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322 +#define CONFIG_SYS_DDR_TIMING_2 0x03984cce +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca +#define CONFIG_SYS_DDR_MODE_1 0x00400442 +#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x08200100 +#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100 +#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 +#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2 0x04400000 + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * One bank, 128M, using the CFI driver. + */ + +#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +/* 0xf8001801 */ +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_32 | BR_V) + +/* 0xf8006ff7 */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 | OR_GPCM_TRLX \ + | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM + +//#define CONFIG_SYS_BR0_PRELIM 0xff001801 +//#define CONFIG_SYS_BR1_PRELIM 0xf0001001 + +//#define CONFIG_SYS_OR0_PRELIM 0xff006e65 +//#define CONFIG_SYS_OR1_PRELIM 0xff006e65 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +/* + * Local Bus + */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 +#define CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LBC_OPTION_BASE +#define CONFIG_SYS_LBC_CACHE_SIZE 64 +#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf4000000 +#define CONFIG_SYS_LBC_NONCACHE_SIZE 64 + +#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +//#define CONFIG_SYS_64BIT_VSPRINTF 1 +//#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_RIO_MEM_PHYS 0xfc0000000ull +#else +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#endif +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0x10 +#define TSEC2_PHY_ADDR 0x11 +#define TSEC3_PHY_ADDR 0x12 +#define TSEC4_PHY_ADDR 0x13 + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_USE_PPCENV 1 +#define ENV_IS_EMBEDDED 1 +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ +#define CONFIG_ENV_SIZE 0x800 +#define CONFIG_ENV_ADDR 0xfffc0000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NFS +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_JFFS2 + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#endif /* __CONFIG_H */ -- 1.7.3.2

3 31

[U-Boot] [PATCH 0/8 v2] Add support to tpl boot and p1021mds board
by Haiying.Wang＠freescale.com 26 Jan '11

26 Jan '11

This is the second version of patchset to add support of TPL(Tertiary Program Loader) and P1021MDS board. Compared with the previous version, patch #3 is splitted into two patches and incorporates the comments from Wolfgang and Mike. Patch#4 has changes based on 2010.12-rc2 release. The other patches remain unchanged. [PATCH 1/8] powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not defined [PATCH 2/8] 8xxx/ddr: add support to only compute the ddr sdram size [PATCH 3/8 v2] Introduce the Tertiary Program loader [PATCH 4/8 v2] powerpc/85xx: add TPL_BOOT support [PATCH 5/8 v2] P1021MDS: add P1021MDS board support [PATCH 6/8] powerpc/p1021: add more P1021 defines. [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash [PATCH 8/8] p1021mds: add QE and UEC support

5 19

[U-Boot] [PATCH] Switch from archive libraries to partial linking
by Sebastien Carlier 26 Jan '11

26 Jan '11

13 78

[U-Boot] [PATCH 2/2] arm: a320evb: fixes for relocation support
by ratbert.chuang＠gmail.com 24 Jan '11

24 Jan '11

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> - add CONFIG_SYS_SDRAM_BASE and CONFIG_SYS_INIT_SP_ADDR - do not update gd->bd in dram_init() because bd is unavailable then Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- board/faraday/a320evb/a320evb.c | 3 +-- include/configs/a320evb.h | 10 +++++++--- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index 85b11b9..b9343e4 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -46,8 +46,7 @@ int dram_init(void) actual_size = get_ram_size((void *)sdram_base, expected_size); - gd->bd->bi_dram[0].start = sdram_base; - gd->bd->bi_dram[0].size = actual_size; + gd->ram_size = actual_size; if (expected_size != actual_size) printf("Warning: Only %lu of %lu MiB SDRAM is working\n", diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index 0284d40..97bf8b9 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -138,15 +138,19 @@ #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + /* * Load address and memory test area should agree with * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. */ -#define CONFIG_SYS_LOAD_ADDR 0x12000000 +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000) /* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x13F00000 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000) #define CONFIG_SYS_TEXT_BASE 0 -- 1.6.3.3

3 2

[U-Boot] [PATCH 1/2] arm: a320 timer: move static data to global_data struct
by ratbert.chuang＠gmail.com 24 Jan '11

24 Jan '11

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> timer.c used static data and are called before relocation. Move all static variables into global_data structure. Also cleanup timer.c from unused stubs and make it truly use 64 bit tick values. Based on Reinhard Meyer <u-boot(a)emk-elektronik.de>'s patch 5dca710a3d7703e41da0e9894f2d71f9e25bea6b Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- arch/arm/cpu/arm920t/a320/timer.c | 137 ++++++++++++++---------------------- arch/arm/include/asm/global_data.h | 5 ++ board/faraday/a320evb/config.mk | 35 --------- include/configs/a320evb.h | 2 + 4 files changed, 59 insertions(+), 120 deletions(-) delete mode 100644 board/faraday/a320evb/config.mk diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c index d2e316f..ac48328 100644 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ b/arch/arm/cpu/arm920t/a320/timer.c @@ -18,10 +18,13 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/arch/ftpmu010.h> #include <asm/arch/fttmr010.h> +DECLARE_GLOBAL_DATA_PTR; + static ulong timestamp; static ulong lastdec; @@ -31,6 +34,22 @@ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; #define TIMER_CLOCK 32768 #define TIMER_LOAD_VAL 0xffffffff +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_CLOCK); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_CLOCK; + do_div(usec, 1000000); + + return TIMER_LOAD_VAL - usec; +} + int timer_init(void) { unsigned int oscc; @@ -76,115 +95,63 @@ int timer_init(void) cr |= FTTMR010_TM3_ENABLE; writel(cr, &tmr->cr); - /* init the timestamp and lastdec value */ - reset_timer_masked(); + gd->tbu = gd->tbl = 0; return 0; } /* - * timer without interrupts - */ - -/* - * reset time + * Get the current 64 bit timer tick count */ -void reset_timer_masked(void) +unsigned long long get_ticks(void) { - /* capure current decrementer value time */ - lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - debug("%s(): lastdec = %lx\n", __func__, lastdec); -} + ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); -void reset_timer(void) -{ debug("%s()\n", __func__); - reset_timer_masked(); -} -/* - * return timer ticks - */ -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); - - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp fordward with absoulte diff ticks - */ - timestamp += lastdec - now; - } else { - /* - * we have overflow of the count down timer - * - * nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll and - * cause problems. - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - - lastdec = now; - - debug("%s() returns %lx\n", __func__, timestamp); - - return timestamp; -} - -/* - * return difference between timer ticks and base - */ -ulong get_timer(ulong base) -{ - debug("%s(%lx)\n", __func__, base); - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - debug("%s(%lx)\n", __func__, t); - timestamp = t; + /* increment tbu if tbl has rolled over */ + if (now < gd->tbl) + gd->tbu++; + gd->tbl = now; + return (((unsigned long long)gd->tbu) << 32) | gd->tbl; } /* delay x useconds AND preserve advance timestamp value */ void __udelay(unsigned long usec) { - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&tmr->timer3_counter); - - debug("%s(%lu)\n", __func__, usec); - while (tmo > 0) { - now = readl(&tmr->timer3_counter); - if (now > last) /* count down timer overflow */ - tmo -= TIMER_LOAD_VAL + last - now; - else - tmo -= last - now; - last = now; - } + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + ; } /* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. + * reset_timer() and get_timer(base) are a pair of functions that are used by + * some timeout/sleep mechanisms in u-boot. + * + * reset_timer() marks the current time as epoch and + * get_timer(base) works relative to that epoch. + * + * The time is used in CONFIG_SYS_HZ units! */ -unsigned long long get_ticks(void) +void reset_timer(void) { debug("%s()\n", __func__); - return get_timer(0); + gd->timer_reset_value = get_ticks(); +} + +ulong get_timer(ulong base) +{ + debug("%s(%lx)\n", __func__, base); + return tick_to_time(get_ticks() - gd->timer_reset_value) - base; } /* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. + * Return the number of timer ticks per second. */ ulong get_tbclk(void) { diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index ada3fbb..04c1564 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -61,6 +61,11 @@ typedef struct global_data { unsigned long tbu; unsigned long long timer_reset_value; #endif +#ifdef CONFIG_FTTMR010_BASE + unsigned long tbl; + unsigned long tbu; + unsigned long long timer_reset_value; +#endif unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ unsigned long mon_len; /* monitor len */ diff --git a/board/faraday/a320evb/config.mk b/board/faraday/a320evb/config.mk deleted file mode 100644 index b751d0d..0000000 --- a/board/faraday/a320evb/config.mk +++ /dev/null @@ -1,35 +0,0 @@ -# -# (C) Copyright 2009 Faraday Technology -# Po-Yu Chuang <ratbert(a)faraday-tech.com> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus -# -# see http://www.faraday-tech.com/ for more information - -# A320 has 1 bank of 64 MB DRAM -# -# 1000'0000 to 1400'0000 -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# -# we load ourself to 13f8'0000 -# -# download area is 1200'0000 - -CONFIG_SYS_TEXT_BASE = 0x13f80000 diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h index f67cf06..0284d40 100644 --- a/include/configs/a320evb.h +++ b/include/configs/a320evb.h @@ -148,6 +148,8 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x13F00000 +#define CONFIG_SYS_TEXT_BASE 0 + /*----------------------------------------------------------------------- * Static memory controller configuration */ -- 1.6.3.3

5 7

[U-Boot] [PATCH 4/8 v2] powerpc/85xx: add TPL_BOOT support
by Haiying.Wang＠freescale.com 24 Jan '11

24 Jan '11

From: Haiying Wang <Haiying.Wang(a)freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- Splitted from TPL patch to only address 85xx changes arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 34 ++++++++++- arch/powerpc/cpu/mpc85xx/start.S | 12 ++-- arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++++++++++++++++++++++++++++++ 3 files changed, 137 insertions(+), 8 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index 8fb27ab..decedca 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -40,7 +40,8 @@ void cpu_init_f(void) #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined #endif -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) \ + && !defined(CONFIG_TPL_BOOT) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; char *l2srbar; int i; @@ -60,4 +61,33 @@ void cpu_init_f(void) for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) l2srbar[i] = 0; #endif +#ifdef CONFIG_TPL_BOOT + init_used_tlb_cams(); +#endif +} + +#ifdef CONFIG_TPL_BOOT +/* + * Because the primary cpu's info is enough for the 2nd stage, we define the + * cpu number to 1 so as to keep code size for 2nd stage binary as small as + * possible. + */ +int cpu_numcores() +{ + return 1; +} + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk(void) +{ +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else + return (gd->bus_clk + 4UL)/8UL; +#endif } +#endif /* CONFIG_TPL_BOOT */ diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 945c1b8..12b0ebb 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -58,12 +58,12 @@ GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_TPL_BOOT) GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) -#endif +#endif /* !CONFIG_TPL_BOOT || !CONFIG_NAND_SPL*/ GOT_ENTRY(__init_end) GOT_ENTRY(_end) @@ -435,7 +435,7 @@ _start_cont: /* NOTREACHED - board_init_f() does not return */ -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_TPL_BOOT) . = EXC_OFF_SYS_RESET .globl _start_of_vectors _start_of_vectors: @@ -877,7 +877,7 @@ in32: in32r: lwbrx r3,r0,r3 blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !CONFIG_NAND_SPL && !CONFIG_TPL_BOOT */ /*------------------------------------------------------------------------------*/ @@ -1067,7 +1067,7 @@ clear_bss: mr r4,r10 /* Destination Address */ bl board_init_r -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_TPL_BOOT) /* * Copy exception vector code to low memory * @@ -1207,4 +1207,4 @@ setup_ivors: #include "fixed_ivor.S" blr -#endif /* !CONFIG_NAND_SPL */ +#endif /* !CONFIG_NAND_SPL && !CONFIG_TPL_BOOT */ diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds new file mode 100644 index 0000000..1c17acf --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds @@ -0,0 +1,99 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .text : + { + *(.text*) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + KEEP(*(.got)) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) - 0x1000 : + { + start.o KEEP(*(.bootpg)) + } :text = 0xffff + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss*) + *(.bss*) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} -- 1.7.3.1.50.g1e633

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