December 2010 - U-Boot

[U-Boot] the mips cache code question ?
by Scott Nicholas 02 Dec '10

02 Dec '10

hello, On Wed, Dec 1, 2010 at 10:27 AM, Andrew Dyer <amdyer(a)gmail.com> wrote: > On Dec 1, 2010 12:26 AM, "奥刘" <happyoach(a)gmail.com> wrote: > >> In the file .\cpu\mips\cache.s , i found some code confounded . >> >> line 152 to line 156 : >> >> cache_op Index_Store_Tag_I t0 >> PTR_ADDU t0, a2 >> bne t0, t1, 1b >> /* fill once, so data field parity is correct */ >> PTR_LI t0, INDEX_BASE >> >> the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this >> instruction will be implement every branch cycle. >> >> Is it right ? Then the cache operation logic seems wrong . It would seem. a NOP is needed in this case. seem every branch is incorrect. a disassembly would be best way to confirm. assembler might insert it for us. > > From a quick glance I think the code is OK. I would suggest > disassembling the executable code to make sure of what the assembler > did. > > The answer depends on what mode the assembler is in. For MIPS > assembler there is a 'reorder mode' where the assembler will fill in > the branch delay slot for you or place a nop if necessary, and the > next instruction in the source is really the one after the delay slot, > or there is noreorder mode where the next instruction after the branch > is what is put in the delay slot. > > Normally the assembler runs in reorder mode, and you use a '.set > reorder' and '.set noreorder' to switch between them. Noreorder mode > is commonly used in code that requires precise control of where > instructions get executed (cache & tlb handling) the file does specify noreorder! This is interesting, and of course I will be looking at a disassembly of my u-boot later, it is not available to me now. Tho, the cache's work, and have seen nothing that makes it seem otherwise.. -- Scott

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[U-Boot] [rft 16] : mental health counselors - 283, 184 records 7, 206 emails
by Gay mccallum 01 Dec '10

01 Dec '10

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[U-Boot] [rft 15] : business marketing database
by charm 01 Dec '10

01 Dec '10

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[U-Boot] [PATCH] mpc512x: aria: cleanup board config file
by Anatolij Gustschin 01 Dec '10

01 Dec '10

CONFIG_FSL_DIU_LOGO_BMP has been removed while refactoring MPC8610 and MPC5121 DIU code, so remove it. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- include/configs/aria.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/aria.h b/include/configs/aria.h index b3ca8d2..3a60de0 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -49,7 +49,6 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ -#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 -- 1.7.1

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[U-Boot] [PATCH 0/7] Address partial linking issues
by Wolfgang Denk 01 Dec '10

01 Dec '10

The switch from archive libraries to partial linking has introduced a number of problems, that are non-trivial to solve. For example, it is no longer possible to include individual object files in the linker script as we did before for example in the case of boards with embedded environment to fill up the gap caused by the need to align the environment on flash erase block boundaries. The best (but unfortunately not easiest) approach to address this problem is probably to enable -ffunction-sections (and -ffunction-sections) so we can again (and even in much finer granularity) place certain code where we want it. When doing this step, it seems only consequent to also add --gc-sections which has the added benefit of reducing the memory footprint of the U-Boot image (both in flash and in RAM). Unfortunately, this requires changes to a lot of linker scripts. The following patch series prepares the groung a bit, then enables --gc-sections, -ffunction-sections and -ffunction-sections for the Power Archtiecture, and then starts to make all PowerPC boards build again, beginning with 4xx. As it turns out, this process uncovers a number of (so far undetected) bugs that have creapt in, which I try to fix as well. To Stefan Roese: Stefan, I need your help fixing the kilauea_nand and haleakala_nand board configurations; currently these fail with a "undefined reference to `initdram'" error. It appears that in the past these included the code from cpu/ppc4xx/denali_spd_ddr2.c, but I doubt that was correct? Comments and.or help converting the remaining processors welcome. Note: these patches are also available in the "gc-sections" branch of the u-boot-testing repository. Overview: ========= [PATCH 1/7] common/Makefile: don't include env_embedded.o into libcommon common/Makefile | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) [PATCH 2/7] cpu/ppc4xx/Makefile: build only needed object files arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 4 --- arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 3 -- arch/powerpc/cpu/ppc4xx/Makefile | 25 ++++++++------------- 3 files changed, 10 insertions(+), 22 deletions(-) [PATCH 3/7] arch/powerpc/config.mk: make CONFIG_SYS_LDSCRIPT settings work arch/powerpc/config.mk | 7 +++++++ arch/powerpc/cpu/ppc4xx/config.mk | 6 +++++- 2 files changed, 12 insertions(+), 1 deletions(-) [PATCH 4/7] PPChameleonEVB and CATcenter need a custom linker script board/dave/PPChameleonEVB/u-boot.lds | 128 ++++++++++++++++++++++++++++++++++ include/configs/CATcenter.h | 1 + include/configs/PPChameleonEVB.h | 1 + 3 files changed, 130 insertions(+), 0 deletions(-) create mode 100644 board/dave/PPChameleonEVB/u-boot.lds [PATCH 5/7] ERIC: drop unsupported board configuration CREDITS | 4 - MAINTAINERS | 2 - board/eric/Makefile | 51 --- board/eric/eric.c | 203 --------- board/eric/eric.h | 44 -- board/eric/flash.c | 1131 ------------------------------------------------ board/eric/init.S | 359 --------------- boards.cfg | 1 - doc/README.scrapyard | 3 +- include/configs/ERIC.h | 369 ---------------- 10 files changed, 2 insertions(+), 2165 deletions(-) delete mode 100644 board/eric/Makefile delete mode 100644 board/eric/eric.c delete mode 100644 board/eric/eric.h delete mode 100644 board/eric/flash.c delete mode 100644 board/eric/init.S delete mode 100644 include/configs/ERIC.h [PATCH 6/7] POWERPC: enable --gc-sections and -ffunction-sections -fdata-sections arch/powerpc/config.mk | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) [PATCH 7/7] 4xx: Cleanup for partial linking and --gc-sections arch/powerpc/cpu/ppc4xx/Makefile | 2 +- arch/powerpc/cpu/ppc4xx/u-boot.lds | 53 +++++-------------------- board/amcc/bamboo/Makefile | 6 ++- board/amcc/bamboo/u-boot-nand.lds | 50 +++++------------------ board/amcc/bluestone/Makefile | 6 ++- board/amcc/canyonlands/Makefile | 6 ++- board/amcc/canyonlands/u-boot-nand.lds | 48 ++++------------------ board/amcc/sequoia/Makefile | 6 ++- board/amcc/sequoia/u-boot-nand.lds | 48 ++++------------------ board/amcc/sequoia/u-boot-ram.lds | 50 +++++------------------ board/amirix/ap1000/Makefile | 4 +- board/amirix/ap1000/u-boot.lds | 67 +++++-------------------------- board/cray/L1/L1.c | 6 --- board/esd/dasa_sim/u-boot.lds | 57 ++++++--------------------- board/esd/du440/Makefile | 6 ++- board/esd/pmc440/Makefile | 6 ++- board/gdsys/intip/Makefile | 6 ++- board/korat/Makefile | 6 ++- board/lwmon5/Makefile | 6 ++- board/ml2/u-boot.lds | 69 ++++--------------------------- board/netstal/hcu5/Makefile | 4 +- board/sbc405/sbc405.c | 7 --- board/t3corp/Makefile | 6 ++- include/configs/AP1000.h | 8 ++++ include/configs/CANBT.h | 2 +- include/configs/CPCI2DP.h | 2 +- include/configs/DP405.h | 1 + include/configs/ML2.h | 9 ++++ include/configs/sc3.h | 2 +- 29 files changed, 147 insertions(+), 402 deletions(-) Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de I used to be indecisive, now I'm not sure.

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[U-Boot] [PATCH 7/8] powerpc/85xx: do not initialize QE if QE's firmware is in nand flash
by Haiying.Wang＠freescale.com 01 Dec '10

01 Dec '10

From: Haiying Wang <Haiying.Wang(a)freescale.com> For some board which doesn't have NOR flash and the QE's firmware(ucode) is saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will call it later after nand is initialized. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4b8faa5..eb34378 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -369,7 +369,7 @@ int cpu_init_r(void) enable_cpc(); -#ifdef CONFIG_QE +#if defined(CONFIG_QE) && !defined(CONFIG_SYS_QE_FW_IN_NAND) uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ qe_init(qe_base); qe_reset(); -- 1.7.3.1.50.g1e633

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[U-Boot] at91rm9200ek NOR booting is broken
by Andreas Bießmann 01 Dec '10

01 Dec '10

Dear Albert Aribaud, as mentioned in another thread here is the description of broken at91rm9200ek NOR booting. I use the patchset posted in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/89974 on top of v2010.12-rc2 tag. I configure the code for 'at91rm9200ek_config' and build that with a homebrew 4.5.1 toolchain with 2.20.1 binutils (I think the toolchain does not matter). The same board configured with 'at91rm9200ek_ram_config' do work with an JTAG. The JTAG configuration is copied from u-boot (just to mention the SDRAM and clock initialisation is sane). regards Andreas Bießmann

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[U-Boot] [PATCH 8/8] p1021mds: add QE and UEC support
by Haiying.Wang＠freescale.com 01 Dec '10

01 Dec '10

From: Haiying Wang <Haiying.Wang(a)freescale.com> P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. P1021MDS has to load the microcode from NAND flash, this patch defines misc_init_r() for loading ucode and initializing qe. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++ arch/powerpc/include/asm/immap_85xx.h | 13 +++++ board/freescale/p1021mds/p1021mds.c | 82 +++++++++++++++++++++++++++++++++ drivers/qe/uec.c | 38 +++++++++++++++ include/configs/P1021MDS.h | 47 +++++++++++++++++++ 5 files changed, 184 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index dd4c6b3..6f1aa7b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo) #endif #ifdef CONFIG_QE +#ifdef CONFIG_P1021 + sysInfo->freqQE = sysInfo->freqSystemBus; +#else qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#endif #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9eb106c..1e4dae9 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1924,6 +1924,19 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 +#define MPC85xx_PMUXCR_QE0 0x00008000 +#define MPC85xx_PMUXCR_QE1 0x00004000 +#define MPC85xx_PMUXCR_QE2 0x00002000 +#define MPC85xx_PMUXCR_QE3 0x00001000 +#define MPC85xx_PMUXCR_QE4 0x00000800 +#define MPC85xx_PMUXCR_QE5 0x00000400 +#define MPC85xx_PMUXCR_QE6 0x00000200 +#define MPC85xx_PMUXCR_QE7 0x00000100 +#define MPC85xx_PMUXCR_QE8 0x00000080 +#define MPC85xx_PMUXCR_QE9 0x00000040 +#define MPC85xx_PMUXCR_QE10 0x00000020 +#define MPC85xx_PMUXCR_QE11 0x00000010 +#define MPC85xx_PMUXCR_QE12 0x00000008 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ u8 res6[8]; u32 devdisr; /* Device disable control */ diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c index 5d981e2..7d71bd7 100644 --- a/board/freescale/p1021mds/p1021mds.c +++ b/board/freescale/p1021mds/p1021mds.c @@ -37,6 +37,54 @@ #include <tsec.h> #include <netdev.h> +#ifdef CONFIG_QE +#ifdef CONFIG_SYS_QE_FW_IN_NAND +#include <nand.h> +#include <asm/errno.h> +#endif +extern void qe_init(uint qe_base); +extern void qe_reset(void); +#endif + +#ifdef CONFIG_QE +const qe_iop_conf_t qe_iop_conf_tab[] = { + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + int board_early_init_f(void) { @@ -98,6 +146,14 @@ int board_eth_init(bd_t *bis) tsec_eth_init(bis, tsec_info, num); +#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); + + uec_standard_init(bis); +#endif + return pci_eth_init(bis); } #endif @@ -119,6 +175,10 @@ void ft_board_setup(void *blob, bd_t *bd) ft_pci_board_setup(blob); +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif } #endif ; @@ -130,3 +190,25 @@ void board_lmb_reserve(struct lmb *lmb) cpu_mp_lmb_reserve(lmb); } #endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r() +{ +#if defined(CONFIG_QE) && defined(CONFIG_SYS_QE_FW_LENGTH) + int ret; + size_t fw_length = CONFIG_SYS_QE_FW_LENGTH; + + /* load QE firmware from NAND flash to DDR first */ + ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FW_IN_NAND, + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); + + if (ret && ret == -EUCLEAN) { + printf ("NAND read for QE firmware at offset %x failed %d\n", + (loff_t)CONFIG_SYS_QE_FW_IN_NAND, ret); + } + + qe_init(CONFIG_SYS_IMMR + 0x00080000); + qe_reset(); +#endif +} +#endif diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 282ab23..1a31873 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -30,6 +30,9 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#ifdef CONFIG_P1021 +#define BCSR11_ENET_MICRST 0x20 +#endif /* Default UTBIPAR SMI address */ #ifndef CONFIG_UTBIPAR_INIT_TBIPA @@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); +#ifdef CONFIG_P1021 + /* + * QE12 is muxed with LBCTL, it needs to be released for enabling + * LBCTL signal for LBC usage. + */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + /* Adjust the interface according to speed */ adjust_link(dev); } @@ -1198,10 +1217,24 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; +#ifdef CONFIG_P1021 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { +#ifdef CONFIG_P1021 + /* reset micrel phy for each UEC */ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); + udelay(200); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR11_ENET_MICRST); + + /* QE9 and QE12 need to be set for enabling QE MII managment signals */ + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + err = init_phy(dev); if (err) { printf("%s: Cannot initialize PHY, aborting.\n", @@ -1228,6 +1261,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); +#ifdef CONFIG_P1021 + /* QE12 needs to be released for enabling LBCTL signal*/ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); +#endif + if (err || i <= 0) printf("warning: %s: timeout on PHY link\n", dev->name); diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h index 2e3d893..8331f46 100644 --- a/include/configs/P1021MDS.h +++ b/include/configs/P1021MDS.h @@ -414,6 +414,50 @@ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */ +#define CONFIG_QE + +#ifdef CONFIG_QE +/* QE microcode/firmware address */ +#define CONFIG_SYS_QE_FW_IN_NAND 0x1f00000 +#define CONFIG_SYS_QE_FW_ADDR 0x10000000 +#define CONFIG_SYS_QE_FW_LENGTH 0x10000 + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) + +#define CONFIG_UEC_ETH +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define CONFIG_HAS_ETH0 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ +#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH1 */ + +#define CONFIG_UEC_ETH5 /* GETH5 */ +#define CONFIG_HAS_ETH1 + +#ifdef CONFIG_UEC_ETH5 +#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ +#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ +#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ +#define CONFIG_SYS_UEC5_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 +#endif /* CONFIG_UEC_ETH2 */ + +#endif /* CONFIG_QE */ + /* * I2C2 EEPROM */ @@ -458,6 +502,8 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #endif +#define CONFIG_E1000 + #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ @@ -491,6 +537,7 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ #define CONFIG_MMC #ifdef CONFIG_MMC -- 1.7.3.1.50.g1e633

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[U-Boot] [PATCH] powerpc/85xx: Enable HWCONFIG on MPC8572DS
by Kumar Gala 01 Dec '10

01 Dec '10

We need HWCONFIG to allow configuration of DDR params Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/configs/MPC8572DS.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2e40237..0abb8a6 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -242,6 +242,7 @@ #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT -- 1.7.2.3

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[U-Boot] [PATCH v3 3/7] [REPOST] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
by Prafulla Wadaskar 01 Dec '10

01 Dec '10

Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Please Ignore earlier patch, below bufix is added to this patch Change log v3: Fixed: Read-modify-Write a mfg register as per configuration ANDed with MASK value before ORing for each configuration drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mfp.h | 97 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mfp.c create mode 100644 include/mfp.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 398024c..f6903d5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MFP) += mfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mfp.c b/drivers/gpio/mfp.c new file mode 100644 index 0000000..f26af97 --- /dev/null +++ b/drivers/gpio/mfp.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com>, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#define MFPR_BASE ARMD1_MFPR_BASE; +#else +#error Unsupported SoC... +#endif + +/* + * mfp_config + * + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin + * configuration registers to configure each GPIO/Function pin on the + * SoC. + * + * This function reads the array of values for + * MFPR_X registers and programms them into respective + * Multi-Function Pin registers. + * It supports - Alternate Function Selection programming. + * + * Whereas, + * The Configureation value is constructed using ARMD_MFP() + * array consists of 32bit values as- + * Bits 31-16 : Mfp instance number (i.e. MFPR no. to be programmed) + * Bits 15-13 : PULL_UP/PULL_DOWN selection + * Bits 11:10 : Pin Driver strength + * Bits 6-4 : Edge detection configuration + * Bits 2-0 : Alternate Function Selection + * + * For more details please refer respective Product Software Manual + */ +void mfp_config(u32 *mfp_cfgs) +{ + u32 *p_mfpr = NULL; + u32 val, cfg_val, mfpr_no; + + do { + cfg_val = *mfp_cfgs++; + /* exit if End of configuration table detected */ + if (cfg_val == MFP_EOC) + break; + /* abstract mfpr tobe programmed from configuration value */ + mfpr_no = (cfg_val & MFP_PINNO_MASK) >> 16; + BUG_ON(mfpr_no >= MFP_PIN_MAX); + + /* the offset address are divided in three regions and not + * consecutive, this corrects the same (Ref: Specs: A1.1) */ + p_mfpr = (u32 *)MFPR_BASE; + if ( mfpr_no < 37) + p_mfpr += (0x004c / 4) + mfpr_no; + else if ( mfpr_no >= 56) + p_mfpr += (0x00e0 / 4) + (mfpr_no - 56); + else + p_mfpr += (mfpr_no - 37); + /*p_mfpr contains address of register to be programmed */ + + /* Read-modify-Write a mfg register as per configuration */ + val = readl(p_mfpr); + if (cfg_val & MFP_CFG_AF) { + /* Abstract and program Afternate-Func Selection */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_AF_MASK; + } if (cfg_val & MFP_CFG_EDGE) { + /* Abstract and program Edge configuration */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_LPM_EDGE_MASK; + } if (cfg_val & MFP_CFG_DRIVE) { + /* Abstract and program Drive configuration */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_DRIVE_MASK; + } if (cfg_val & MFP_CFG_PULL) { + /* Abstract and program Pullup/down configuration */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_PULL_MASK; + } + writel(val, p_mfpr); + } while (1); + /* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ + readl(p_mfpr); +} diff --git a/include/mfp.h b/include/mfp.h new file mode 100644 index 0000000..176acda --- /dev/null +++ b/include/mfp.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MFP_H +#define __MFP_H + +/* + * Header file for MultiFunctionPin (MFP) Configururation framework + * + * Processors Supported: + * 1. Marvell ARMADA100 Processors + * + * processor to be supported should be added here + */ + +#define MFP_EOC 0xffffffff /* flag to indicate end-of-configuration */ + +/* + * Possible MFP configuration is represented by a 32-bit unsigned integer + * + * bit 0.. 2 - Alternate Function Selection + * bit 4.. 6 - Edge Detection + * bit 7.. 9 - Type of configuration + * bit 10..11 - Drive Strength + * bit 13..15 - Run Mode Pull State + * bit 16..31 - Used to hold MFP number to be configured + * + * to facilitate the definition, the following macros are provided + */ + +#define MFP_AF0 (0x0 << 0) +#define MFP_AF1 (0x1 << 0) +#define MFP_AF2 (0x2 << 0) +#define MFP_AF3 (0x3 << 0) +#define MFP_AF4 (0x4 << 0) +#define MFP_AF5 (0x5 << 0) +#define MFP_AF6 (0x6 << 0) +#define MFP_AF7 (0x7 << 0) +#define MFP_AF_MASK (0x7 << 0) + +#define MFP_LPM_EDGE_NONE (0x0 << 4) +#define MFP_LPM_EDGE_RISE (0x1 << 4) +#define MFP_LPM_EDGE_FALL (0x2 << 4) +#define MFP_LPM_EDGE_BOTH (0x3 << 4) +#define MFP_LPM_EDGE_MASK (0x3 << 4) + +/* unused bits are used to identify config type */ +#define MFP_CFG_AF (0x1 << 7) +#define MFP_CFG_DRIVE (0x1 << 8) +#define MFP_CFG_EDGE (0x1 << 9) +#define MFP_CFG_PULL (0x1 << 3) + +#define MFP_DRIVE_VERY_SLOW (0x0 << 10) +#define MFP_DRIVE_SLOW (0x1 << 10) +#define MFP_DRIVE_MEDIUM (0x2 << 10) +#define MFP_DRIVE_FAST (0x3 << 10) +#define MFP_DRIVE_MASK (0x3 << 10) + +#define MFP_PULL_NONE (0x0 << 13) +#define MFP_PULL_LOW (0x1 << 13) +#define MFP_PULL_HIGH (0x2 << 13) +#define MFP_PULL_BOTH (0x3 << 13) +#define MFP_PULL_FLOAT (0x4 << 13) +#define MFP_PULL_MASK (0x7 << 13) + +#define MFP_PINNO_MASK (0xffff << 16) + +#define MFP_AF(af) (MFP_CFG_AF | MFP_AF##af) +#define MFP_DRIVE(drv) (MFP_CFG_DRIVE | MFP_DRIVE_##drv) +#define MFP_EDGE(edge) (MFP_CFG_EDGE | MFP_LPM_EDGE_##edge) +#define MFP_PULL(pull) (MFP_CFG_PULL | MFP_PULL_##pull) +#define MFP(pin) (MFP_PINNO_MASK & (pin << 16)) + +void mfp_config(u32 *mfp_cfgs); + +#endif /* __MFP_H */ -- 1.5.3.4

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