December 2010 - U-Boot

[U-Boot] [PATCH] p1022ds: fix switching of DIU/LBC signals
by Timur Tabi 02 Dec '10

02 Dec '10

On the P1022, the pins which drive the video display (DIU) are muxed with the local bus controller (LBC), so if the DIU is active, the pins need to be temporarily muxed to LBC whenever accessing NOR flash. The code which handled this transition is checking and changing the wrong bits in PMUXCR. Also add a follow-up read after a write to NOR flash if we're going to mux back to DIU after the write, as described in the P1022 RM. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- I have no idea how this ever worked before. It's a complete mystery to me. board/freescale/p1022ds/diu.c | 45 +++++++++++++++++++++++++++++++++------- 1 files changed, 37 insertions(+), 8 deletions(-) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c index 12b40a0..2259384 100644 --- a/board/freescale/p1022ds/diu.c +++ b/board/freescale/p1022ds/diu.c @@ -32,6 +32,7 @@ #define PMUXCR_ELBCDIU_MASK 0xc0000000 #define PMUXCR_ELBCDIU_NOR16 0x80000000 +#define PMUXCR_ELBCDIU_DIU 0x40000000 /* * DIU Area Descriptor @@ -131,9 +132,8 @@ int platform_diu_init(unsigned int *xres, unsigned int *yres) px_brdcfg0 = in_8(lbc_lcs1_ba); out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); - /* Setting PMUXCR to switch to DVI from ELBC */ - clrsetbits_be32(&gur->pmuxcr, - PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ + clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); pmuxcr = in_be32(&gur->pmuxcr); return fsl_diu_init(*xres, pixel_format, 0); @@ -161,7 +161,7 @@ static int set_mux_to_lbc(void) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; /* Switch the muxes only if they're currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != PMUXCR_ELBCDIU_NOR16) { /* * In DIU mode, the PIXIS can only be accessed indirectly @@ -216,8 +216,16 @@ void flash_write8(u8 value, void *addr) int sw = set_mux_to_lbc(); __raw_writeb(value, addr); - if (sw) + + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write16(u16 value, void *addr) @@ -225,8 +233,15 @@ void flash_write16(u16 value, void *addr) int sw = set_mux_to_lbc(); __raw_writew(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write32(u32 value, void *addr) @@ -234,8 +249,15 @@ void flash_write32(u32 value, void *addr) int sw = set_mux_to_lbc(); __raw_writel(value, addr); - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } void flash_write64(u64 value, void *addr) @@ -244,8 +266,15 @@ void flash_write64(u64 value, void *addr) /* There is no __raw_writeq(), so do the write manually */ *(volatile u64 *)addr = value; - if (sw) + if (sw) { + /* + * To ensure the post-write is completed to eLBC, software must + * perform a dummy read from one valid address from eLBC space + * before changing the eLBC_DIU from NOR mode to DIU mode. + */ + __raw_readb(addr); set_mux_to_diu(); + } } u8 flash_read8(void *addr) -- 1.7.2.3

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[U-Boot] OMAP3: relocation and bss usage (timer, gpmc, ...)
by Alexander Holler 02 Dec '10

02 Dec '10

Hello, browsing through some code searching for a reason why an u-boot compiled with gcc 4.5.1 fails to boot on a beagleboard, I've come through another place where bss is used before relocation: gpmc_init (gpmc_cfg) in arch/arm/cpu/armv7/omap3/mem.c. I haven't fixed it up to now, but I want to inform the people actually working with that board (currently I don't have any to do with that board and just touching at from time to time for fun), that there might be other places than the already mentioned timer_init() and that gpmc_init(). All candidates for such problems could be found in board_init_f() in arch/arm/lib/board.c, escpecially all functions which appear in init_sequence in board.c. Someone should take the time and check them all. ;) Regards, Alexander

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[U-Boot] [PATCH] ARMv7: Fix linker errors across toolchain versions
by Sanjeev Premi 02 Dec '10

02 Dec '10

This patch fixes the linker problems noticed while building the omap3_evm with Codesourcery toolchains 2009q1, 2009q3 and 2010q1. The compilation was tested as success for both omap3_evm and omap3_beagle with toolchain versions 2009q1 and 2010q1. [1] http://marc.info/?l=u-boot&m=129104332808386&w=2 Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- The patch touches all ARMv7 architectures, will need to be reviewed thoroughly. I am getting hang of relocation feature, but definitely hands-on. Impact would have to be reviewd as well. This is the reason for sending the patch early - before i start testing on the evm. arch/arm/cpu/armv7/u-boot.lds | 26 +++++++++++++++----------- 1 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index 5725c30..faf6ad8 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -55,22 +55,26 @@ SECTIONS . = ALIGN(4); - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - .dynsym : { __dynsym_start = .; *(.dynsym) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - _end = .; + OVERLAY : NOCROSSREFS + { + .rel.dyn { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .bss + { + __bss_start = .; + *(.bss) + . = ALIGN(4); + _end = .; + } } /DISCARD/ : { *(.dynstr*) } -- 1.7.2.2

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[U-Boot] [ARM] [davinci] timer.c changes
by Nick Thompson 02 Dec '10

02 Dec '10

I have changed the davinci timer code to work with the, originally at91 only, gd variables: unsigned long timer_rate_hz; unsigned long tbl; unsigned long tbu; unsigned long long timer_reset_value; It does use the timer_reset_value to keep compatibility with places where timers are not used correctly. I have tested it on da830evm and it my board now boots correctly. Has it been agreed on the way forward for these timer fixes? Is it worth me posting the patch? It does seem to me that there would be room for a common layer and a arch specific tbl/tbu emulation layer as suggested here: http://lists.denx.de/pipermail/u-boot/2010-November/081377.html but maybe it would be good to get more boards working prior to release and then look at how they can be made more common later? Nick.

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[U-Boot] [PATCH v3 3/7] [REPOST-1] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
by Prafulla Wadaskar 02 Dec '10

02 Dec '10

Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Please Ignore earlier patch, below bufix is added to this patch Change log v3: Fixed: Read-modify-Write a mfg register as per configuration ANDed with MASK value before ORing for each configuration REPOST-V1: I am sorry for the repost-V1 :-( MASK values changed to relevent (copy paste mistake) Regards.. Prafulla . . drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mfp.h | 97 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mfp.c create mode 100644 include/mfp.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 398024c..f6903d5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MFP) += mfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mfp.c b/drivers/gpio/mfp.c new file mode 100644 index 0000000..f26af97 --- /dev/null +++ b/drivers/gpio/mfp.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com>, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#define MFPR_BASE ARMD1_MFPR_BASE; +#else +#error Unsupported SoC... +#endif + +/* + * mfp_config + * + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin + * configuration registers to configure each GPIO/Function pin on the + * SoC. + * + * This function reads the array of values for + * MFPR_X registers and programms them into respective + * Multi-Function Pin registers. + * It supports - Alternate Function Selection programming. + * + * Whereas, + * The Configureation value is constructed using ARMD_MFP() + * array consists of 32bit values as- + * Bits 31-16 : Mfp instance number (i.e. MFPR no. to be programmed) + * Bits 15-13 : PULL_UP/PULL_DOWN selection + * Bits 11:10 : Pin Driver strength + * Bits 6-4 : Edge detection configuration + * Bits 2-0 : Alternate Function Selection + * + * For more details please refer respective Product Software Manual + */ +void mfp_config(u32 *mfp_cfgs) +{ + u32 *p_mfpr = NULL; + u32 val, cfg_val, mfpr_no; + + do { + cfg_val = *mfp_cfgs++; + /* exit if End of configuration table detected */ + if (cfg_val == MFP_EOC) + break; + /* abstract mfpr tobe programmed from configuration value */ + mfpr_no = (cfg_val & MFP_PINNO_MASK) >> 16; + BUG_ON(mfpr_no >= MFP_PIN_MAX); + + /* the offset address are divided in three regions and not + * consecutive, this corrects the same (Ref: Specs: A1.1) */ + p_mfpr = (u32 *)MFPR_BASE; + if ( mfpr_no < 37) + p_mfpr += (0x004c / 4) + mfpr_no; + else if ( mfpr_no >= 56) + p_mfpr += (0x00e0 / 4) + (mfpr_no - 56); + else + p_mfpr += (mfpr_no - 37); + /*p_mfpr contains address of register to be programmed */ + + /* Read-modify-Write a mfg register as per configuration */ + val = readl(p_mfpr); + if (cfg_val & MFP_CFG_AF) { + /* Abstract and program Afternate-Func Selection */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_AF_MASK; + } if (cfg_val & MFP_CFG_EDGE) { + /* Abstract and program Edge configuration */ + val &= ~MFP_LPM_EDGE_MASK; + val |= cfg_val & MFP_LPM_EDGE_MASK; + } if (cfg_val & MFP_CFG_DRIVE) { + /* Abstract and program Drive configuration */ + val &= ~MFP_DRIVE_MASK; + val |= cfg_val & MFP_DRIVE_MASK; + } if (cfg_val & MFP_CFG_PULL) { + /* Abstract and program Pullup/down configuration */ + val &= ~MFP_PULL_MASK; + val |= cfg_val & MFP_PULL_MASK; + } + writel(val, p_mfpr); + } while (1); + /* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ + readl(p_mfpr); +} diff --git a/include/mfp.h b/include/mfp.h new file mode 100644 index 0000000..176acda --- /dev/null +++ b/include/mfp.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MFP_H +#define __MFP_H + +/* + * Header file for MultiFunctionPin (MFP) Configururation framework + * + * Processors Supported: + * 1. Marvell ARMADA100 Processors + * + * processor to be supported should be added here + */ + +#define MFP_EOC 0xffffffff /* flag to indicate end-of-configuration */ + +/* + * Possible MFP configuration is represented by a 32-bit unsigned integer + * + * bit 0.. 2 - Alternate Function Selection + * bit 4.. 6 - Edge Detection + * bit 7.. 9 - Type of configuration + * bit 10..11 - Drive Strength + * bit 13..15 - Run Mode Pull State + * bit 16..31 - Used to hold MFP number to be configured + * + * to facilitate the definition, the following macros are provided + */ + +#define MFP_AF0 (0x0 << 0) +#define MFP_AF1 (0x1 << 0) +#define MFP_AF2 (0x2 << 0) +#define MFP_AF3 (0x3 << 0) +#define MFP_AF4 (0x4 << 0) +#define MFP_AF5 (0x5 << 0) +#define MFP_AF6 (0x6 << 0) +#define MFP_AF7 (0x7 << 0) +#define MFP_AF_MASK (0x7 << 0) + +#define MFP_LPM_EDGE_NONE (0x0 << 4) +#define MFP_LPM_EDGE_RISE (0x1 << 4) +#define MFP_LPM_EDGE_FALL (0x2 << 4) +#define MFP_LPM_EDGE_BOTH (0x3 << 4) +#define MFP_LPM_EDGE_MASK (0x3 << 4) + +/* unused bits are used to identify config type */ +#define MFP_CFG_AF (0x1 << 7) +#define MFP_CFG_DRIVE (0x1 << 8) +#define MFP_CFG_EDGE (0x1 << 9) +#define MFP_CFG_PULL (0x1 << 3) + +#define MFP_DRIVE_VERY_SLOW (0x0 << 10) +#define MFP_DRIVE_SLOW (0x1 << 10) +#define MFP_DRIVE_MEDIUM (0x2 << 10) +#define MFP_DRIVE_FAST (0x3 << 10) +#define MFP_DRIVE_MASK (0x3 << 10) + +#define MFP_PULL_NONE (0x0 << 13) +#define MFP_PULL_LOW (0x1 << 13) +#define MFP_PULL_HIGH (0x2 << 13) +#define MFP_PULL_BOTH (0x3 << 13) +#define MFP_PULL_FLOAT (0x4 << 13) +#define MFP_PULL_MASK (0x7 << 13) + +#define MFP_PINNO_MASK (0xffff << 16) + +#define MFP_AF(af) (MFP_CFG_AF | MFP_AF##af) +#define MFP_DRIVE(drv) (MFP_CFG_DRIVE | MFP_DRIVE_##drv) +#define MFP_EDGE(edge) (MFP_CFG_EDGE | MFP_LPM_EDGE_##edge) +#define MFP_PULL(pull) (MFP_CFG_PULL | MFP_PULL_##pull) +#define MFP(pin) (MFP_PINNO_MASK & (pin << 16)) + +void mfp_config(u32 *mfp_cfgs); + +#endif /* __MFP_H */ -- 1.5.3.4

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[U-Boot] U-boot networking not working
by Mark Underwood 02 Dec '10

02 Dec '10

Hi, I've got an sbc6000x from www.armkits.com. I've been working through how to put debian onto this board and was making some progress (im just a beginner), but now I dont have network access when at the U-boot prompt. The Board is connected to the network as the link light is on on the interface. As soon as I try to ping the board itself ie ping 192.192.192.200 (the default ip address) the link light goes out. this is from the command line U-Boot> ping 192.192.192.200 dm9000 i/o: 0x30000000, id: 0x90000a46 DM9000: running in 16 bit mode MAC: de:ad:be:ef:01:01 operating at 100M full duplex mode ping failed; host 192.192.192.200 is not alive now if I go ahead and boot the board i can ping once im in the linux root file system that is currently on the board (I've changed the IP address on bootup in the linux image.) ~ $ ping 192.168.0.21 PING 192.168.0.21 (192.168.0.21): 56 data bytes 64 bytes from 192.168.0.21: icmp_seq=0 ttl=64 time=0.5 ms 64 bytes from 192.168.0.21: icmp_seq=1 ttl=64 time=0.3 ms 64 bytes from 192.168.0.21: icmp_seq=2 ttl=64 time=0.3 ms is there a setting in u-boot that could mean that the network is turned off? following are the environment variables of u-boot U-Boot> printenv bootcmd=nand read 0x22000000 0x1A0000 0x200000; bootm 0x22000000 bootdelay=3 baudrate=115200 ethaddr=DE:AD:BE:EF:01:01 ipaddr=192.192.192.200 serverip=192.192.192.105 gatewayip=192.192.192.101 netmask=255.255.255.0 splashimage=0x21000000 bootlogo=0 lcdtype=480x272 bootargs=console=ttyS0,115200 tft=480x272 root=/dev/mtdblock6 mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,1M(logo)ro,2M(linux),-(root) rw rootfstype=yaffs2 Environment size: 455/131067 bytes im using u-boot 1.3.4. Any help with this would be great! Regards Mark

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[U-Boot] ulong type size?
by Jason Liu 02 Dec '10

02 Dec '10

Hi there, I have one problem when support more than 4GB NAND flash in u-boot. I found that there used ulong type in common/cmd_nand.c, but it turned out that ulong is 32bit in my build environment, the gcc version is as the following? Does anyone meet the same problem? r64343@r64343-desktop:~/work_space/linux-2.6-imx$ arm-none-linux-gnueabi-gcc -v Using built-in specs. Target: arm-none-linux-gnueabi Configured with: /scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/src/gcc-4.3/configure --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu --target=arm-none-linux-gnueabi --enable-threads --disable-libmudflap --disable-libssp --disable-libstdcxx-pch --with-gnu-as --with-gnu-ld --with-specs='%{funwind-tables|fno-unwind-tables|mabi=*|ffreestanding|nostdlib:;:-funwind-tables}' --enable-languages=c,c++ --enable-shared --enable-symvers=gnu --enable-__cxa_atexit --with-pkgversion='Sourcery G++ Lite 2009q1-203' --with-bugurl=https://support.codesourcery.com/GNUToolchain/ --disable-nls --prefix=/opt/codesourcery --with-sysroot=/opt/codesourcery/arm-none-linux-gnueabi/libc --with-build-sysroot=/scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/lite/install/arm-none-linux-gnueabi/libc --with-gmp=/scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/lite/obj/host-libs-2009q1-203-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr --with-mpfr=/scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/lite/obj/host-libs-2009q1-203-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr --disable-libgomp --enable-poison-system-directories --with-build-time-tools=/scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/lite/install/arm-none-linux-gnueabi/bin --with-build-time-tools=/scratch/mitchell/builds/4.3-arm-none-linux-gnueabi-respin/lite/install/arm-none-linux-gnueabi/bin Thread model: posix gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) BR, Jason

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[U-Boot] [PATCH] revert "tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode"
by Zhao Chenhui 02 Dec '10

02 Dec '10

On P2020DS and MPC8572DS, the link to SGMII card which use Vitesse VSC8234 PHY can't come up. Current TBI PHY settings(TBICR_SETTINGS) for SGMII mode cause link problems. Revert commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4, and fix it. Signed-off-by: Zhao Chenhui <b26998(a)freescale.com> --- drivers/net/tsec.c | 2 +- include/configs/XPEDITE5370.h | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9b5dd92..862b0db 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -290,10 +290,10 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, | TBIANA_FULL_DUPLEX \ ) -/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ #ifndef CONFIG_TSEC_TBICR_SETTINGS #define TBICR_SETTINGS ( \ TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 8225fff..aa1d1a8 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -370,6 +370,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define TSEC2_PHYIDX 0 #define CONFIG_HAS_ETH1 +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + /* * Command configuration. */ -- 1.6.4.1

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[U-Boot] the mips cache code question ?
by 奥刘 02 Dec '10

02 Dec '10

Dear All: Recently , i have build a embedded environment with Uboot . And My Chip is adm5120 , mips4kc code. In the file .\cpu\mips\cache.s , i found some code confounded . line 152 to line 156 : cache_op Index_Store_Tag_I t0 PTR_ADDU t0, a2 bne t0, t1, 1b /* fill once, so data field parity is correct */ PTR_LI t0, INDEX_BASE the code 'PTR_LI t0, INDEX_BASE' is in the branch delay slot , so this instruction will be implement every branch cycle. Is it right ? Then the cache operation logic seems wrong .

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[U-Boot] Hello dear
by faye fransica 02 Dec '10

02 Dec '10

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