December 2010 - U-Boot

Re: [U-Boot] [PATCH] MTD: Add support for S25FL032P spi nor-flash
by Macpaul Lin 03 Dec '10

03 Dec '10

> This patch introduces an extra mask-field in spansion_spi_flash_params > to support flash chips with 1-byte extended ID (like the S25FL032P). > Signed-off-by: David Jander <david(a)protonic.nl> The extension ID has been checked with the datasheet. http://www.spansion.com/Support/Datasheets/S25FL032P_00_05_e.pdf at Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh): # Extended bytes: byte 3: 4Dh However S25FL128P series has 2 extended bytes. http://www.spansion.com/Support/Datasheets/S25FL128P_00_08_e.pdf > --- > drivers/mtd/spi/spansion.c | 19 ++++++++++++++++++- > 1 files changed, 18 insertions(+), 1 deletions(-) > +#define SPSN_EXT_ID_S25FL032P 0x4d00 -- Best regards, Macpaul Lin

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[U-Boot] [PATCH v3 3/7] [REPOST-2] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
by Prafulla Wadaskar 03 Dec '10

03 Dec '10

Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers For ex. ARMADA100. These registers are programmed to expose the specific functionality associated with respective SoC Pins This driver provides configuration APIs, using them, configuration need to be done in board specific code for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality int board_early_init_f(void) { u32 mfp_cfg[] = { /* Console on UART1 */ MFP107_UART1_RXD, MFP108_UART1_TXD, MFP_EOC /*End of configureation*/ }; /* configure MFP's */ mfp_config(mfp_cfg); return 0; } Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Please Ignore earlier patch, below bufix is added to this patch Change log v3: Fixed: Read-modify-Write a mfg register as per configuration ANDed with MASK value before ORing for each configuration REPOST-V1: I am sorry for the repost-V1 :-( MASK values changed to relevent (copy paste mistake) Change log v3-repost-2 Soc specific pointer updation code is replaced by a macro MFPR_PTR_UPDATE, will be put in asm/arch/mfp.c Regards.. Prafulla . . drivers/gpio/Makefile | 1 + drivers/gpio/mfp.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mfp.h | 97 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mfp.c create mode 100644 include/mfp.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 398024c..f6903d5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MFP) += mfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mfp.c b/drivers/gpio/mfp.c new file mode 100644 index 0000000..db71a74 --- /dev/null +++ b/drivers/gpio/mfp.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com>, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <mfp.h> +#include <asm/arch/mfp.h> +#ifdef CONFIG_ARMADA100 +#include <asm/arch/armada100.h> +#define MFPR_BASE ARMD1_MFPR_BASE; +#else +#error Unsupported SoC... +#endif + +/* + * mfp_config + * + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin + * configuration registers to configure each GPIO/Function pin on the + * SoC. + * + * This function reads the array of values for + * MFPR_X registers and programms them into respective + * Multi-Function Pin registers. + * It supports - Alternate Function Selection programming. + * + * Whereas, + * The Configureation value is constructed using ARMD_MFP() + * array consists of 32bit values as- + * Bits 31-16 : Mfp instance number (i.e. MFPR no. to be programmed) + * Bits 15-13 : PULL_UP/PULL_DOWN selection + * Bits 11:10 : Pin Driver strength + * Bits 6-4 : Edge detection configuration + * Bits 2-0 : Alternate Function Selection + * + * For more details please refer respective Product Software Manual + */ +void mfp_config(u32 *mfp_cfgs) +{ + u32 *p_mfpr = NULL; + u32 val, cfg_val, mfpr_no; + + do { + cfg_val = *mfp_cfgs++; + /* exit if End of configuration table detected */ + if (cfg_val == MFP_EOC) + break; + /* abstract mfpr tobe programmed from configuration value */ + mfpr_no = (cfg_val & MFP_PINNO_MASK) >> 16; + BUG_ON(mfpr_no >= MFP_PIN_MAX); + + p_mfpr = (u32 *)MFPR_BASE; + MFPR_PTR_UPDATE(p_mfpr, mfpr_no); + /*p_mfpr contains address of register to be programmed */ + + /* Read-modify-Write a mfg register as per configuration */ + val = readl(p_mfpr); + if (cfg_val & MFP_CFG_AF) { + /* Abstract and program Afternate-Func Selection */ + val &= ~MFP_AF_MASK; + val |= cfg_val & MFP_AF_MASK; + } if (cfg_val & MFP_CFG_EDGE) { + /* Abstract and program Edge configuration */ + val &= ~MFP_LPM_EDGE_MASK; + val |= cfg_val & MFP_LPM_EDGE_MASK; + } if (cfg_val & MFP_CFG_DRIVE) { + /* Abstract and program Drive configuration */ + val &= ~MFP_DRIVE_MASK; + val |= cfg_val & MFP_DRIVE_MASK; + } if (cfg_val & MFP_CFG_PULL) { + /* Abstract and program Pullup/down configuration */ + val &= ~MFP_PULL_MASK; + val |= cfg_val & MFP_PULL_MASK; + } + writel(val, p_mfpr); + } while (1); + /* + * perform a read-back of any MFPR register to make sure the + * previous writings are finished + */ + readl(p_mfpr); +} diff --git a/include/mfp.h b/include/mfp.h new file mode 100644 index 0000000..176acda --- /dev/null +++ b/include/mfp.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MFP_H +#define __MFP_H + +/* + * Header file for MultiFunctionPin (MFP) Configururation framework + * + * Processors Supported: + * 1. Marvell ARMADA100 Processors + * + * processor to be supported should be added here + */ + +#define MFP_EOC 0xffffffff /* flag to indicate end-of-configuration */ + +/* + * Possible MFP configuration is represented by a 32-bit unsigned integer + * + * bit 0.. 2 - Alternate Function Selection + * bit 4.. 6 - Edge Detection + * bit 7.. 9 - Type of configuration + * bit 10..11 - Drive Strength + * bit 13..15 - Run Mode Pull State + * bit 16..31 - Used to hold MFP number to be configured + * + * to facilitate the definition, the following macros are provided + */ + +#define MFP_AF0 (0x0 << 0) +#define MFP_AF1 (0x1 << 0) +#define MFP_AF2 (0x2 << 0) +#define MFP_AF3 (0x3 << 0) +#define MFP_AF4 (0x4 << 0) +#define MFP_AF5 (0x5 << 0) +#define MFP_AF6 (0x6 << 0) +#define MFP_AF7 (0x7 << 0) +#define MFP_AF_MASK (0x7 << 0) + +#define MFP_LPM_EDGE_NONE (0x0 << 4) +#define MFP_LPM_EDGE_RISE (0x1 << 4) +#define MFP_LPM_EDGE_FALL (0x2 << 4) +#define MFP_LPM_EDGE_BOTH (0x3 << 4) +#define MFP_LPM_EDGE_MASK (0x3 << 4) + +/* unused bits are used to identify config type */ +#define MFP_CFG_AF (0x1 << 7) +#define MFP_CFG_DRIVE (0x1 << 8) +#define MFP_CFG_EDGE (0x1 << 9) +#define MFP_CFG_PULL (0x1 << 3) + +#define MFP_DRIVE_VERY_SLOW (0x0 << 10) +#define MFP_DRIVE_SLOW (0x1 << 10) +#define MFP_DRIVE_MEDIUM (0x2 << 10) +#define MFP_DRIVE_FAST (0x3 << 10) +#define MFP_DRIVE_MASK (0x3 << 10) + +#define MFP_PULL_NONE (0x0 << 13) +#define MFP_PULL_LOW (0x1 << 13) +#define MFP_PULL_HIGH (0x2 << 13) +#define MFP_PULL_BOTH (0x3 << 13) +#define MFP_PULL_FLOAT (0x4 << 13) +#define MFP_PULL_MASK (0x7 << 13) + +#define MFP_PINNO_MASK (0xffff << 16) + +#define MFP_AF(af) (MFP_CFG_AF | MFP_AF##af) +#define MFP_DRIVE(drv) (MFP_CFG_DRIVE | MFP_DRIVE_##drv) +#define MFP_EDGE(edge) (MFP_CFG_EDGE | MFP_LPM_EDGE_##edge) +#define MFP_PULL(pull) (MFP_CFG_PULL | MFP_PULL_##pull) +#define MFP(pin) (MFP_PINNO_MASK & (pin << 16)) + +void mfp_config(u32 *mfp_cfgs); + +#endif /* __MFP_H */ -- 1.5.3.4

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[U-Boot] [PATCH] include/linux/mii.h: update for supporting GE
by Macpaul Lin 03 Dec '10

03 Dec '10

This file has been synced (copy) from Linux source code. This commit was based on kernel 2.6.32. It updates gigabit related phy registers and basic definitions. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- include/linux/mii.h | 270 +++++++++++++++++++++++++++++++++++++-------------- 1 files changed, 197 insertions(+), 73 deletions(-) diff --git a/include/linux/mii.h b/include/linux/mii.h index 7c63095..359fba8 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -8,99 +8,184 @@ #ifndef __LINUX_MII_H__ #define __LINUX_MII_H__ +#include <linux/types.h> + /* Generic MII registers. */ -#define MII_BMCR 0x00 /* Basic mode control register */ -#define MII_BMSR 0x01 /* Basic mode status register */ -#define MII_PHYSID1 0x02 /* PHYS ID 1 */ -#define MII_PHYSID2 0x03 /* PHYS ID 2 */ -#define MII_ADVERTISE 0x04 /* Advertisement control reg */ -#define MII_LPA 0x05 /* Link partner ability reg */ -#define MII_EXPANSION 0x06 /* Expansion register */ -#define MII_DCOUNTER 0x12 /* Disconnect counter */ -#define MII_FCSCOUNTER 0x13 /* False carrier counter */ -#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ -#define MII_SREVISION 0x16 /* Silicon revision */ -#define MII_RESV1 0x17 /* Reserved... */ -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ -#define MII_PHYADDR 0x19 /* PHY address */ -#define MII_RESV2 0x1a /* Reserved... */ -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ -#define MII_NCONFIG 0x1c /* Network interface config */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ /* Basic mode control register. */ -#define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ -#define BMCR_CTST 0x0080 /* Collision test */ -#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -#define BMCR_RESET 0x8000 /* Reset the DP83840 */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ +#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset the DP83840 */ /* Basic mode status register. */ -#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -#define BMSR_JCD 0x0002 /* Jabber detected */ -#define BMSR_LSTATUS 0x0004 /* Link status */ -#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -#define BMSR_RESV 0x07c0 /* Unused... */ -#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ /* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_RESV 0x1c00 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) + ADVERTISE_100HALF | ADVERTISE_100FULL) /* Link partner ability register. */ -#define LPA_SLCT 0x001f /* Same as advertise selector */ -#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -#define LPA_RESV 0x1c00 /* Unused... */ -#define LPA_RFAULT 0x2000 /* Link partner faulted */ -#define LPA_LPACK 0x4000 /* Link partner acked us */ -#define LPA_NPAGE 0x8000 /* Next page bit */ +#define LPA_SLCT 0x001f /* Same as advertise selector */ +#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ +#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ +#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ +#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ +#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ +#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ +#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ +#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ +#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ +#define LPA_PAUSE_CAP 0x0400 /* Can pause */ +#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ +#define LPA_RESV 0x1000 /* Unused... */ +#define LPA_RFAULT 0x2000 /* Link partner faulted */ +#define LPA_LPACK 0x4000 /* Link partner acked us */ +#define LPA_NPAGE 0x8000 /* Next page bit */ #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ -#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ -#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ -#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ -#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ -#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ -#define EXPANSION_RESV 0xffe0 /* Unused... */ +#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ +#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ +#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ +#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ +#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ +#define EXPANSION_RESV 0xffe0 /* Unused... */ + +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ -#define NWAYTEST_RESV1 0x00ff /* Unused... */ -#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ -#define NWAYTEST_RESV2 0xfe00 /* Unused... */ +#define NWAYTEST_RESV1 0x00ff /* Unused... */ +#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ +#define NWAYTEST_RESV2 0xfe00 /* Unused... */ + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ + +/* 1000BASE-T Status register */ +#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ +#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ +#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ +#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ + +/* Flow control flags */ +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 + +/* This structure is used in all SIOCxMIIxxx ioctl calls */ +struct mii_ioctl_data { + __u16 phy_id; + __u16 reg_num; + __u16 val_in; + __u16 val_out; +}; + +#ifdef __KERNEL__ + +#include <linux/if.h> + +struct ethtool_cmd; + +struct mii_if_info { + int phy_id; + int advertising; + int phy_id_mask; + int reg_num_mask; + + unsigned int full_duplex : 1; /* is full duplex? */ + unsigned int force_media : 1; /* is autoneg. disabled? */ + unsigned int supports_gmii : 1; /* are GMII registers supported? */ + + struct net_device *dev; + int (*mdio_read) (struct net_device *dev, int phy_id, int location); + void (*mdio_write) (struct net_device *dev, int phy_id, int location, int val); +}; + +extern int mii_link_ok (struct mii_if_info *mii); +extern int mii_nway_restart (struct mii_if_info *mii); +extern int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd); +extern int mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd); +extern int mii_check_gmii_support(struct mii_if_info *mii); +extern void mii_check_link (struct mii_if_info *mii); +extern unsigned int mii_check_media (struct mii_if_info *mii, + unsigned int ok_to_print, + unsigned int init_media); +extern int generic_mii_ioctl(struct mii_if_info *mii_if, + struct mii_ioctl_data *mii_data, int cmd, + unsigned int *duplex_changed); + + +static inline struct mii_ioctl_data *if_mii(struct ifreq *rq) +{ + return (struct mii_ioctl_data *) &rq->ifr_ifru; +} /** @@ -114,7 +199,7 @@ * * The one exception to IEEE 802.3u is that 100baseT4 is placed * between 100T-full and 100T-half. If your phy does not support - * 100T4 this is fine. If your phy places 100T4 elsewhere in the + * 100T4 this is fine. If your phy places 100T4 elsewhere in the * priority order, you will need to roll your own function. */ static inline unsigned int mii_nway_result (unsigned int negotiated) @@ -154,5 +239,44 @@ static inline unsigned int mii_duplex (unsigned int duplex_lock, return 0; } +/** + * mii_advertise_flowctrl - get flow control advertisement flags + * @cap: Flow control capabilities (FLOW_CTRL_RX, FLOW_CTRL_TX or both) + */ +static inline u16 mii_advertise_flowctrl(int cap) +{ + u16 adv = 0; + + if (cap & FLOW_CTRL_RX) + adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + if (cap & FLOW_CTRL_TX) + adv ^= ADVERTISE_PAUSE_ASYM; + + return adv; +} + +/** + * mii_resolve_flowctrl_fdx + * @lcladv: value of MII ADVERTISE register + * @rmtadv: value of MII LPA register + * + * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3 + */ +static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv) +{ + u8 cap = 0; + + if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) { + cap = FLOW_CTRL_TX | FLOW_CTRL_RX; + } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) { + if (lcladv & ADVERTISE_PAUSE_CAP) + cap = FLOW_CTRL_RX; + else if (rmtadv & ADVERTISE_PAUSE_CAP) + cap = FLOW_CTRL_TX; + } + + return cap; +} +#endif /* __KERNEL__ */ #endif /* __LINUX_MII_H__ */ -- 1.7.3.2

2 1

[U-Boot] Ein Stellenangebot in Logistik-Bereich
by nancy.lopez＠aeromensajeria.com 03 Dec '10

03 Dec '10

Sehr geehrte Ich heibe Christian Schroeder und ich habe ein Angebot fur Sie! Unser Unternehmen Jasckson Logistic sucht im Moment neue Arbeitskrafte! Wir haben Ihre Bewerbungsunterlagen bei uns vor einige Zeit liegen gefunden und jetzt mochten wir Ihnen eine Stelle von unseren AuBendienstvertreter anbieten. Was spricht dafur? Keine vorherige Erfahrung notig! wir machen gratis ein Training fur Sie, falls Sie mit uns kooperieren. Schauen Sie, was wir Ihnen anbieten: Stelle: AuBendienstvertreter Bedingungen: Deutsche Staatsangehorigkeit, FlieBendes Deutsch, Grundkenntnisse von Microsoft Word und Microsoft Excel, Grundkenntnisse von Konsumelektronik PC mit Email- und Moglichkeit die Emails min. 2mal taglich zu prufen Drucker, Scanner Volljahrigkeit Beschreibung: - Briefe vom unseren Mitarbeiter regelmaBig empfangen, - Einen Bericht ausfertigen und ihn an den Obermanager verschicken (Der Arbeitnehmer ist einem Obermanager unterordnet), - die angekommene Postsendungen, gemaB unserer Vorschriften, weiterzuleiten, - die Unterlagen, mit Angabe aller Details der Artikel, auszufullen (Der Arbeitnehmer bekommt alle ausfuhrlichen Dokumente fur jede Verpackung per Email), - die Ware versenden. Personliche Eigenschaften: Ehrlichkeit Geselligkeit Teamfahigkeit Hoflichkeit Die Vergutung: 40. pro jede erfolgreich versendete Postsendung (ca.3000 . monatlich) mit Check oder per Uberweisung einmal pro Monat. Wenn Sie daran interessiert sind, schreiben Sie mir unter: job.ulrichraade(a)gmail.com Danke, Christian Schroeder HR Department Jasckson Logistic

1 0

[U-Boot] [PATCH] tsec: Revert to setting TBICR_ANEG_ENABLE by default for SGMII
by Kumar Gala 03 Dec '10

03 Dec '10

The following commit: commit 46e91674fb4b6d06c6a4984c0b5ac7d9a16923f4 Author: Peter Tyser <ptyser(a)xes-inc.com> Date: Tue Nov 3 17:52:07 2009 -0600 tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode Removed setting Auto-Neg by default, however this is believed to be proper default configuration for initialization of the TBI interface. Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require Auto-Neg to be disabled to function properly. This addresses a breakage on the P2020 DS & MPC8572 DS boards when used with an SGMII riser card. We also remove setting CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the default setting is sufficient for them. Additionally, we clean up the code a bit to remove an unnecessary second define. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/net/tsec.c | 9 ++++----- include/configs/P1_P2_RDB.h | 8 -------- include/configs/xpedite537x.h | 6 ++++++ include/configs/xpedite550x.h | 6 ++++++ 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9b5dd92..77908d1 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -292,13 +292,12 @@ static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ #ifndef CONFIG_TSEC_TBICR_SETTINGS -#define TBICR_SETTINGS ( \ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) -#else -#define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS #endif /* CONFIG_TSEC_TBICR_SETTINGS */ /* Configure the TBI for SGMII operation */ @@ -311,7 +310,7 @@ static void tsec_configure_serdes(struct tsec_private *priv) tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, - TBICR_SETTINGS); + CONFIG_TSEC_TBICR_SETTINGS); } /* Discover which PHY is attached to the device, and configure it diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a21afb7..2dfee3d 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -437,14 +437,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - #endif /* CONFIG_TSEC_ENET */ /* diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index e0a1fa4..9d87eaf 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -375,6 +375,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_ETHPRIME "eTSEC2" +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 42d1f69..407ee66 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -345,6 +345,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_ETHPRIME "eTSEC2" +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -- 1.7.2.3

2 2

[U-Boot] Try to fix Board eb_cpux9k2
by Jens Scharsig 02 Dec '10

02 Dec '10

Dear Albert ARIBAUD, I have tried to start update the eb_cpux9k2 board. I can compile board without errors from current tree. But the board hangs on NAND detection. If I disable NAND support, the board starts and I can also start Linux. A second problem, the board does not restart (reset command). I find out that a NULL pointer used by reset code, was also relocated. I have currently no access to a BDI2000. But I think, this problems are not board specific. It is possible, there are problems with vector tables or memory protection Any suggestions? The board use 920t on at91rm9200 soc regard Jens Scharsig

5 21

[U-Boot] [PATCH] powerpc/8xxx: Fix _POST_WORD_ADDR on 85xx & 86xx systems
by Kumar Gala 02 Dec '10

02 Dec '10

We intended to use the PIC TFRR register however we where missing adding in the PIC register base offset from IMMR when we defined _POST_WORD_ADDR. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/post.h | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/post.h b/include/post.h index 957ce3b..519cef1 100644 --- a/include/post.h +++ b/include/post.h @@ -58,11 +58,13 @@ #elif defined (CONFIG_MPC85xx) #include <asm/immap_85xx.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr)) +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \ + offsetof(ccsr_pic_t, tfrr)) #elif defined (CONFIG_MPC86xx) #include <asm/immap_86xx.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr)) +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \ + offsetof(ccsr_pic_t, tfrr)) #elif defined (CONFIG_4xx) #define _POST_WORD_ADDR \ -- 1.7.2.3

2 1

[U-Boot] [RFC PATCH] ARM: S3C64XX: add support for mini6410
by Darius Augulis 02 Dec '10

02 Dec '10

Add support for mini6410 from FriendlyARM Signed-off-by: Darius Augulis <augulis.darius(a)gmail.com> --- MAKEALL | 1 Makefile | 4 arch/arm/cpu/arm1176/s3c64xx/Makefile | 6 - board/friendly_arm/mini6410/Makefile | 59 +++++ board/friendly_arm/mini6410/config.mk | 5 board/friendly_arm/mini6410/lowlevel_init.S | 256 +++++++++++++++++++++++ board/friendly_arm/mini6410/mini6410.c | 99 +++++++++ boards.cfg | 1 include/configs/mini6410.h | 137 ++++++++++++ nand_spl/board/friendly_arm/mini6410/Makefile | 107 ++++++++++ nand_spl/board/friendly_arm/mini6410/config.mk | 7 + nand_spl/board/friendly_arm/mini6410/u-boot.lds | 85 ++++++++ nand_spl/nand_boot_s3c.c | 131 ++++++++++++ 13 files changed, 896 insertions(+), 2 deletions(-) create mode 100644 board/friendly_arm/mini6410/Makefile create mode 100644 board/friendly_arm/mini6410/config.mk create mode 100644 board/friendly_arm/mini6410/lowlevel_init.S create mode 100644 board/friendly_arm/mini6410/mini6410.c create mode 100644 include/configs/mini6410.h create mode 100644 nand_spl/board/friendly_arm/mini6410/Makefile create mode 100644 nand_spl/board/friendly_arm/mini6410/config.mk create mode 100644 nand_spl/board/friendly_arm/mini6410/u-boot.lds create mode 100644 nand_spl/nand_boot_s3c.c diff --git a/MAKEALL b/MAKEALL index 767d561..556aa82 100755 --- a/MAKEALL +++ b/MAKEALL @@ -404,6 +404,7 @@ LIST_ARM11=" \ imx31_litekit \ imx31_phycore \ imx31_phycore_eet \ + mini6410 \ mx31ads \ mx31pdk \ mx31pdk_nand \ diff --git a/Makefile b/Makefile index f0c2703..4dab98d 100644 --- a/Makefile +++ b/Makefile @@ -1087,6 +1087,10 @@ smdk6400_config : unconfig @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk +mini6410_config : unconfig + @mkdir -p $(obj)include + @$(MKCONFIG) mini6410 arm arm1176 mini6410 friendly_arm s3c64xx + #======================================================================== # MIPS #======================================================================== diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile index b527939..6ce2b06 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile @@ -1,4 +1,7 @@ # +# (C) Copyright 2010 +# Darius Augulis, <augulis.darius(a)gmail.com> +# # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # @@ -30,8 +33,7 @@ LIB = $(obj)lib$(SOC).a SOBJS = reset.o -COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o -COBJS-y += timer.o +COBJS-y += timer.o cpu_init.o speed.o OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/board/friendly_arm/mini6410/Makefile b/board/friendly_arm/mini6410/Makefile new file mode 100644 index 0000000..a1dbc41 --- /dev/null +++ b/board/friendly_arm/mini6410/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2010 +# Darius Augulis, <augulis.darius(a)gmail.com> +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS += mini6410.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +.PHONY: all + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/friendly_arm/mini6410/config.mk b/board/friendly_arm/mini6410/config.mk new file mode 100644 index 0000000..5ec9fa9 --- /dev/null +++ b/board/friendly_arm/mini6410/config.mk @@ -0,0 +1,5 @@ +ifndef CONFIG_NAND_SPL +CONFIG_SYS_TEXT_BASE = 0x57E00000 +else +CONFIG_SYS_TEXT_BASE = 0x0C000000 +endif diff --git a/board/friendly_arm/mini6410/lowlevel_init.S b/board/friendly_arm/mini6410/lowlevel_init.S new file mode 100644 index 0000000..d550ea2 --- /dev/null +++ b/board/friendly_arm/mini6410/lowlevel_init.S @@ -0,0 +1,256 @@ +/* + * MINI6410: Board initialization + * + * Copyright (C) 2010 Darius Augulis <augulis.darius(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/arch/s3c6400.h> + +#ifdef CONFIG_SERIAL1 +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) +#elif defined(CONFIG_SERIAL2) +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) +#else +#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) +#endif + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + mov r12, lr + + /* LED on only #8 */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x55540000 + str r1, [r0, #GPNCON_OFFSET] + + ldr r1, =0x55555555 + str r1, [r0, #GPNPUD_OFFSET] + + ldr r1, =0xf000 + str r1, [r0, #GPNDAT_OFFSET] + +#ifndef CONFIG_NAND_SPL + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x1 + str r1, [r0, #GPECON_OFFSET] + ldr r1, =0x0 + str r1, [r0, #GPEDAT_OFFSET] +#endif + + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x2A5AAAAA + str r1, [r0, #GPPCON_OFFSET] + ldr r1, =0x0 + str r1, [r0, #GPPDAT_OFFSET] + + + ldr r1, =0x55555555 + str r1, [r0, #MEM1DRVCON_OFFSET] + + /* Disable Watchdog */ + ldr r0, =0x7e000000 @0x7e004000 + orr r0, r0, #0x4000 + mov r1, #0 + str r1, [r0] + + /* External interrupt pending clear */ + ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ + ldr r1, [r0] + str r1, [r0] + + ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 + ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 + + /* Disable all interrupts (VIC0 and VIC1) */ + mvn r3, #0x0 + str r3, [r0, #oINTMSK] + str r3, [r1, #oINTMSK] + + /* Set all interrupts as IRQ */ + mov r3, #0x0 + str r3, [r0, #oINTMOD] + str r3, [r1, #oINTMOD] + + /* Pending Interrupt Clear */ + mov r3, #0x0 + str r3, [r0, #oVECTADDR] + str r3, [r1, #oVECTADDR] + + /* init system clock */ + bl system_clock_init + +#ifndef CONFIG_NAND_SPL + /* for UART */ + bl uart_asm_init +#endif + +#ifdef CONFIG_BOOT_NAND + /* simple init for NAND */ + bl nand_asm_init +#endif + + /* Memory subsystem address 0x7e00f120 */ + ldr r0, =ELFIN_MEM_SYS_CFG + + /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ + mov r1, #S3C64XX_MEM_SYS_CFG_NAND + str r1, [r0] + + bl mem_ctrl_asm_init + +1: + mov lr, r12 + mov pc, lr + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ + +#ifdef CONFIG_SYNC_MODE + ldr r1, [r0, #OTHERS_OFFSET] + mov r2, #0x40 + orr r1, r1, r2 + str r1, [r0, #OTHERS_OFFSET] + + nop + nop + nop + nop + nop + + ldr r2, =0x80 + orr r1, r1, r2 + str r1, [r0, #OTHERS_OFFSET] + +check_syncack: + ldr r1, [r0, #OTHERS_OFFSET] + ldr r2, =0xf00 + and r1, r1, r2 + cmp r1, #0xf00 + bne check_syncack +#else /* ASYNC Mode */ + nop + nop + nop + nop + nop + + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0xC0 + orr r1, r1, #0x40 + str r1, [r0, #OTHERS_OFFSET] + +wait_for_async: + ldr r1, [r0, #OTHERS_OFFSET] + and r1, r1, #0xf00 + cmp r1, #0x0 + bne wait_for_async + + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0x40 + str r1, [r0, #OTHERS_OFFSET] +#endif + + mov r1, #0xff00 + orr r1, r1, #0xff + str r1, [r0, #APLL_LOCK_OFFSET] + str r1, [r0, #MPLL_LOCK_OFFSET] + + /* Set Clock Divider */ + ldr r1, [r0, #CLK_DIV0_OFFSET] + bic r1, r1, #0x30000 + bic r1, r1, #0xff00 + bic r1, r1, #0xff + ldr r2, =CLK_DIV_VAL + orr r1, r1, r2 + str r1, [r0, #CLK_DIV0_OFFSET] + + ldr r1, =APLL_VAL + str r1, [r0, #APLL_CON_OFFSET] + ldr r1, =MPLL_VAL + str r1, [r0, #MPLL_CON_OFFSET] + + /* FOUT of EPLL is 96MHz */ + ldr r1, =0x80200203 + str r1, [r0, #EPLL_CON0_OFFSET] + ldr r1, =0x0 + str r1, [r0, #EPLL_CON1_OFFSET] + + /* APLL, MPLL, EPLL select to Fout */ + ldr r1, [r0, #CLK_SRC_OFFSET] + orr r1, r1, #0x7 + str r1, [r0, #CLK_SRC_OFFSET] + + /* wait at least 200us to stablize all clock */ + mov r1, #0x10000 +1: subs r1, r1, #1 + bne 1b + + /* Synchronization for VIC port */ +#if defined(CONFIG_SYNC_MODE) + ldr r1, [r0, #OTHERS_OFFSET] + orr r1, r1, #0x20 + str r1, [r0, #OTHERS_OFFSET] +#else + ldr r1, [r0, #OTHERS_OFFSET] + bic r1, r1, #0x20 + str r1, [r0, #OTHERS_OFFSET] +#endif + mov pc, lr + + +#ifndef CONFIG_NAND_SPL +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* set GPIO to enable UART */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x220022 + str r1, [r0, #GPACON_OFFSET] + mov pc, lr +#endif + +#ifdef CONFIG_BOOT_NAND +/* + * NAND Interface init for SMDK6400 + */ +nand_asm_init: + ldr r0, =ELFIN_NAND_BASE + ldr r1, [r0, #NFCONF_OFFSET] + orr r1, r1, #0x70 + orr r1, r1, #0x7700 + str r1, [r0, #NFCONF_OFFSET] + + ldr r1, [r0, #NFCONT_OFFSET] + orr r1, r1, #0x07 + str r1, [r0, #NFCONT_OFFSET] + + mov pc, lr +#endif diff --git a/board/friendly_arm/mini6410/mini6410.c b/board/friendly_arm/mini6410/mini6410.c new file mode 100644 index 0000000..b96a23c --- /dev/null +++ b/board/friendly_arm/mini6410/mini6410.c @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2010 + * Darius Augulis, <augulis.darius(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/arch/s3c6400.h> + +/* ------------------------------------------------------------------------- */ + +DECLARE_GLOBAL_DATA_PTR; + +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" + : "=r" (loops) : "0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +#define DM9000_Tacs (0x0) // 0clk address set-up +#define DM9000_Tcos (0x4) // 4clk chip selection set-up +#define DM9000_Tacc (0xE) // 14clk access cycle +#define DM9000_Tcoh (0x1) // 1clk chip selection hold +#define DM9000_Tah (0x4) // 4clk address holding time +#define DM9000_Tacp (0x6) // 6clk page mode access cycle +#define DM9000_PMC (0x0) // normal(1data)page mode configuration + +static void dm9000_pre_init(void) +{ + SROM_BW_REG &= ~(0xf << 4); + SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); + SROM_BC1_REG = ((DM9000_Tacs << 28) + (DM9000_Tcos << 24 ) + + (DM9000_Tacc << 16) + (DM9000_Tcoh << 12) + + (DM9000_Tah << 8) + (DM9000_Tacp << 4) + (DM9000_PMC)); + +} + +int board_init(void) +{ + dm9000_pre_init(); + + gd->bd->bi_arch_number = MACH_TYPE; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int dram_init (void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("Board: MINI6410\n"); + return 0; +} +#endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif diff --git a/boards.cfg b/boards.cfg index 08e531e..54b3015 100644 --- a/boards.cfg +++ b/boards.cfg @@ -354,6 +354,7 @@ PM826_ROMBOOT_BIGFLASH powerpc mpc8260 pm826 - - PM826:BOOT_ROM,FLASH_32MB, imx31_litekit arm arm1136 - logicpd mx31 omap2420h4 arm arm1136 - ti omap24xx tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x +mini6410 arm arm1176 mini6410 friendly_arm s3c64xx armadillo arm arm720t modnet50 arm arm720t lpc2292sodimm arm arm720t - - lpc2292 diff --git a/include/configs/mini6410.h b/include/configs/mini6410.h new file mode 100644 index 0000000..e2dcbd4 --- /dev/null +++ b/include/configs/mini6410.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2010 + * Darius Augulis <augulis.darius(a)gmail.com> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_S3C6410 1 +#define CONFIG_S3C64XX 1 +#define CONFIG_MINI6410 1 + +#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_NAND_U_BOOT 1 + +#define CONFIG_PERIPORT_REMAP +#define CONFIG_PERIPORT_BASE 0x70000000 +#define CONFIG_PERIPORT_SIZE 0x13 + +/* Relocation and internal SRAM options */ +#define CONFIG_SYS_IRAM_BASE 0x0C000000 /* Internal SRAM base address */ +#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */ +#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE) + +/* SDRAM options */ +#define CONFIG_SYS_SDRAM_BASE 0x50000000 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_TEXT_BASE /* 126MiB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +/* Environment options */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_IS_IN_NAND + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "MINI6410 # " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 384 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_IDENT_STRING " for MINI6410" + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK_FREQ 12000000 +#define MACH_TYPE 2520 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_CLK_533_133_66 +#define CONFIG_SYNC_MODE + +/* Network */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_NO_SROM 1 +#define CONFIG_DM9000_BASE 0x18000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+4) +#define CONFIG_ETHADDR 00:01:02:03:04:05 +#define CONFIG_IPADDR 192.168.1.20 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* serial console configuration */ +#define CONFIG_SERIAL1 1 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BOOTCOMMAND "nand read 50100000 100000 300000; bootm 50100000" +#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw console=ttySAC0 mini6410=0" + +/* Command definition */ +#include <config_cmd_default.h> +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SAVEENV + +/* NAND configuration */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x70200010 +#define CONFIG_BOOT_NAND +#define CONFIG_NAND +#define CONFIG_NAND_S3C64XX + +#define CONFIG_SYS_NAND_PAGE_SIZE (2 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (CONFIG_SYS_NAND_PAGE_SIZE * CONFIG_SYS_NAND_PAGE_COUNT) + +#define CONFIG_SYS_NAND_U_BOOT_DST 0x57E00000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) + +#endif /* __CONFIG_H */ diff --git a/nand_spl/board/friendly_arm/mini6410/Makefile b/nand_spl/board/friendly_arm/mini6410/Makefile new file mode 100644 index 0000000..71aaed1 --- /dev/null +++ b/nand_spl/board/friendly_arm/mini6410/Makefile @@ -0,0 +1,107 @@ +# +# (C) Copyright 2010 +# Darius Augulis, <augulis.darius(a)gmail.com> +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL + +SOBJS = start.o cpu_init.o lowlevel_init.o +COBJS = nand_boot_s3c.o s3c64xx.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +$(nandobj)u-boot.lds: $(LDSCRIPT) + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + +# create symbolic links for common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@ + +# from SoC directory +$(obj)cpu_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@ + +# from board directory +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/board/friendly_arm/mini6410/lowlevel_init.S $@ + +# from nand_spl directory +$(obj)nand_boot_s3c.c: + @rm -f $@ + @ln -s $(TOPDIR)/nand_spl/nand_boot_s3c.c $@ + +$(obj)s3c64xx.c: + @rm -f $@ + @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@ + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/friendly_arm/mini6410/config.mk b/nand_spl/board/friendly_arm/mini6410/config.mk new file mode 100644 index 0000000..d682446 --- /dev/null +++ b/nand_spl/board/friendly_arm/mini6410/config.mk @@ -0,0 +1,7 @@ +# PAD_TO used to generate a 4kByte binary needed for the combined image +# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096 +PAD_TO := $(shell expr $$(($(CONFIG_SYS_TEXT_BASE) + 4096))) + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/nand_spl/board/friendly_arm/mini6410/u-boot.lds b/nand_spl/board/friendly_arm/mini6410/u-boot.lds new file mode 100644 index 0000000..4ee6d17 --- /dev/null +++ b/nand_spl/board/friendly_arm/mini6410/u-boot.lds @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2010 + * Darius Augulis, <augulis.darius(a)gmail.com> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + cpu_init.o (.text) + nand_boot_s3c.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + + . = ALIGN(4); + __rel_dyn_start = .; + .rel.dyn : { *(.rel.dyn) } + __rel_dyn_end = .; + + __dynsym_start = .; + .dynsym : { *(.dynsym) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/nand_spl/nand_boot_s3c.c b/nand_spl/nand_boot_s3c.c new file mode 100644 index 0000000..d0c5534 --- /dev/null +++ b/nand_spl/nand_boot_s3c.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2010 + * Darius Augulis, <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <asm/arch/s3c6400.h> + +static void disable_ce(void) +{ + int val = readl(NFCONT); + writel(val | (1 << 1), NFCONT); +} + +static void enable_ce(void) +{ + int val = readl(NFCONT); + writel(val & ~(1 << 1), NFCONT); +} + +static int nand_is_ready(void) +{ + return readl(NFSTAT) & 0x01; +} + +static void nand_read_page(unsigned int block, unsigned int page, uchar *buf) +{ + int i; + + writel(NAND_CMD_READ0, NFCMMD); + + writel(0, NFADDR); + writel(0, NFADDR); + writel((page & 0x3f) | ((block << 6) & 0xC0), NFADDR); + writel((block >> 2) & 0xff, NFADDR); + writel((block >> 16) & 0xff, NFADDR); + + writel(NAND_CMD_READSTART, NFCMMD); + + while(!nand_is_ready()); + + for(i = 0; i < CONFIG_SYS_NAND_PAGE_SIZE; i++) + buf[i] = readb(NFDATA); +} + +static int nand_load(unsigned int offs, unsigned int uboot_size, uchar *dst) +{ + unsigned int block, lastblock, page; + + /* offs has to be aligned to a page address! */ + block = offs / CONFIG_SYS_NAND_BLOCK_SIZE; + lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE; + page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE; + + while (block <= lastblock) { + while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + nand_read_page(block, page, dst); + dst += CONFIG_SYS_NAND_PAGE_SIZE; + page++; + } + page = 0; + block++; + } + + return; +} + +#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +void board_init_f (ulong bootflag) +{ + relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, + CONFIG_SYS_TEXT_BASE); +} +#endif + +static void nand_init_hw(void) +{ + int val; + + /* Set timing */ + val = readl(NFCONF); + writel(val | 0x7770, NFCONF); + + /* Enable NFC, release both CE's */ + val = readl(NFCONT); + writel(val | 0x07, NFCONT); +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + /* Init nand controller */ + nand_init_hw(); + + enable_ce(); + + /* Load U-Boot image from NAND into RAM */ + nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + + disable_ce(); + + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + (*uboot)(); +}

3 8

[U-Boot] [STATUS] v2010.12-rc2 released
by Wolfgang Denk 02 Dec '10

02 Dec '10

Hello everybody. I apologise for being a bit late with this announcement: * U-Boot v2010.12-rc2 was released on Sunday, November 28. * Release "v2010.12" is (still) scheduled in 13 days: on December 13, 2010. Please help testing, and check if all your relevant patches have been included. Current status is still a bit wobbly. Power Architecture appears to look reasonably well again. ARM has still a lot of broken boards (which is not unexpected), but a number of fixes have been sent recently, so I guess we will see some improvment in the next few days. I didn't test much for other architectures. Comments and especially patches welcome. If posssible I'l like to have a -rc3 next weekend, after which I will really accept clear bug fixes only. Note that we have a "next" branch again, so custodians can send out pull requests of new stuff for "next". Thanks, and best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Bugs are by far the largest and most successful class of entity, with nearly a million known species. In this res- pect they outnumber all the other known creatures about four to one. -- Professor Snope's Encyclopedia of Animal

12 13

[U-Boot] [PATCH] omap3evm: Clean-up EVM detection code.
by Sanjeev Premi 02 Dec '10

02 Dec '10

This patch does following changes: * Change the type (u8 -> int) for omap3_evm_version. * Introduce an 'undefined' board revision for init value. * Use of #define instead of magic numbers Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- board/ti/evm/evm.c | 39 +++++++++++++++++++++++---------------- board/ti/evm/evm.h | 17 +++++++---------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 09d14f7..8d9ce73 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -37,36 +37,43 @@ #include <asm/mach-types.h> #include "evm.h" -static u8 omap3_evm_version; +static int omap3_evm_version = OMAP3EVM_BOARD_UNDEF; -u8 get_omap3_evm_rev(void) +int get_omap3_evm_rev(void) { return omap3_evm_version; } +/** + * The board revision can be ascertained only by identifying the + * Ethernet chipset used on the board. + * + * The revision can be read from ID_REV register on the PHY. + */ static void omap3_evm_get_revision(void) { -#if defined(CONFIG_CMD_NET) - /* - * Board revision can be ascertained only by identifying - * the Ethernet chipset. - */ - unsigned int smsc_id; +#define CONFIG_SMC911X_ID_REV (CONFIG_SMC911X_BASE + 0x50) - /* Ethernet PHY ID is stored at ID_REV register */ - smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000; - printf("Read back SMSC id 0x%x\n", smsc_id); +#define SMSC_ID_9115 0x01150000 /* SMSC9115 chipset */ +#define SMSC_ID_9220 0x92200000 /* SMSC9220 chipset */ + +#if defined(CONFIG_CMD_NET) + unsigned int smsc_id = readl(CONFIG_SMC911X_ID_REV) & 0xFFFF0000; switch (smsc_id) { - /* SMSC9115 chipset */ - case 0x01150000: + case SMSC_ID_9115: omap3_evm_version = OMAP3EVM_BOARD_GEN_1; break; - /* SMSC 9220 chipset */ - case 0x92200000: + case SMSC_ID_9220: + omap3_evm_version = OMAP3EVM_BOARD_GEN_2; + break; default: + printf ("Unknown board revision."); + /* + * Assume the latest revision + */ omap3_evm_version = OMAP3EVM_BOARD_GEN_2; - } + } #else #if defined(CONFIG_STATIC_BOARD_REV) /* diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h index a76deb8..de96504 100644 --- a/board/ti/evm/evm.h +++ b/board/ti/evm/evm.h @@ -34,18 +34,15 @@ const omap3_sysinfo sysinfo = { }; /* - * OMAP35x EVM revision - * Run time detection of EVM revision is done by reading Ethernet - * PHY ID - - * GEN_1 = 0x01150000 - * GEN_2 = 0x92200000 + * OMAP35x EVM Revision. + * The revision can be detected only based on Ethernet PHY ID. */ -enum { - OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */ - OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */ -}; +#define OMAP3EVM_BOARD_UNDEF -1 /* EVM revision not detected */ + +#define OMAP3EVM_BOARD_GEN_1 1 /* EVM Rev between A - D */ +#define OMAP3EVM_BOARD_GEN_2 2 /* EVM Rev >= Rev E */ -u8 get_omap3_evm_rev(void); +int get_omap3_evm_rev(void); #if defined(CONFIG_CMD_NET) static void setup_net_chip(void); -- 1.7.2.2

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