December 2010 - U-Boot

[U-Boot] u-boot for P2020-RDB
by Zvi Vered 16 Dec '10

16 Dec '10

Hello, I built u-boot-2010.09 for Freescale's P2020-RDB. It works great !!! The setup I used for SW4 is according to the startup guide. SW4[7] is on. When SW4[7] is off u-boot hangs. It means: "boot sequencer enabled and configuration information loaded from I2C ROM. A valid ROM must be present. If not the card will hang". I do not need the I2C ROM but for some reason, vxWorks 6.8 needs it. I'm using u-boot to download vxWorks via tftp and run it (using bootelf) What does u-boot hangs when SW4[7] is off ? What should this I2C ROM contain ? How can I flash this ROM ? According to the manual, this board contains I2C ROM. Thanks, Zvika Vered

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Re: [U-Boot] NEC OHCI chip bug
by gavinguo＠andestech.com 16 Dec '10

16 Dec '10

Hi Martin, > are you sure it is that NEC bug? We had a similar error message when the > PCI bridge was not properly setup and the OHCI could not access RAM > through PCI (DMA), hence the "unrecoverable error". The bus/dev/func/ number of OHCI host controller are 0/8/0 and 0/8/1, bus number is 0 of both devices. I think that PCI bridge need setup if the bus number is other than 0? Is that correct? Thanks Regards, Gavin

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[U-Boot] [PATCH v2] BLOCK: Add freescale IMX51 PATA driver
by Marek Vasut 16 Dec '10

16 Dec '10

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- v2: Use structures instead of defines as Wolfgang proposed drivers/block/Makefile | 1 + drivers/block/mxc_ata.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+), 0 deletions(-) create mode 100644 drivers/block/mxc_ata.c diff --git a/drivers/block/Makefile b/drivers/block/Makefile index e27175b..aa7dc87 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o COBJS-$(CONFIG_LIBATA) += libata.o COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o +COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o diff --git a/drivers/block/mxc_ata.c b/drivers/block/mxc_ata.c new file mode 100644 index 0000000..62c5cf4 --- /dev/null +++ b/drivers/block/mxc_ata.c @@ -0,0 +1,149 @@ +/* + * Freescale iMX51 ATA driver + * + * Copyright (C) 2010 Marek Vasut <marek.vasut(a)gmail.com> + * + * Based on code by: + * Mahesh Mahadevan <mahesh.mahadevan(a)freescale.com> + * + * Based on code from original FSL ATA driver, which is + * part of eCos, the Embedded Configurable Operating System. + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <config.h> +#include <asm/byteorder.h> +#include <asm/io.h> +#include <ide.h> + +#include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +/* MXC ATA register offsets */ +struct mxc_ata_config_regs { + u8 time_off; /* 0x00 */ + u8 time_on; + u8 time_1; + u8 time_2w; + u8 time_2r; + u8 time_ax; + u8 time_pio_rdx; + u8 time_4; + u8 time_9; + u8 time_m; + u8 time_jn; + u8 time_d; + u8 time_k; + u8 time_ack; + u8 time_env; + u8 time_udma_rdx; + u8 time_zah; /* 0x10 */ + u8 time_mlix; + u8 time_dvh; + u8 time_dzfs; + u8 time_dvs; + u8 time_cvh; + u8 time_ss; + u8 time_cyc; + u32 fifo_data_32; /* 0x18 */ + u32 fifo_data_16; + u32 fifo_fill; + u32 ata_control; + u32 interrupt_pending; + u32 interrupt_enable; + u32 interrupt_clear; + u32 fifo_alarm; +}; + +struct mxc_data_hdd_regs { + u32 drive_data; /* 0xa0 */ + u32 drive_features; + u32 drive_sector_count; + u32 drive_sector_num; + u32 drive_cyl_low; + u32 drive_cyl_high; + u32 drive_dev_head; + u32 command; + u32 status; + u32 alt_status; +}; + +/* PIO timing table */ +#define NR_PIO_SPECS 5 +uint16_t pio_t0[NR_PIO_SPECS] = { 600, 383, 240, 180, 120 }; +uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 }; +uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 }; +uint16_t pio_t2_16[NR_PIO_SPECS] = { 165, 125, 100, 80, 70 }; +uint16_t pio_t2i[NR_PIO_SPECS] = { 40, 0, 0, 0, 0 }; +uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; +uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; +uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; + +#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) +static void set_ata_bus_timing(unsigned char mode) +{ + uint32_t val; + uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); + + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + + if (mode >= NR_PIO_SPECS) + return; + + /* Write TIME_OFF/ON/1/2W */ + val = (3 << REG2OFF(&ata_cfg_regs->time_off)) | + (3 << REG2OFF(&ata_cfg_regs->time_on)) | + (((pio_t1[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_1)) | + (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2w)); + writel(val, &ata_cfg_regs->time_off); + + /* Write TIME_2R/AX/RDX/4 */ + val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2r)) | + (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_cfg_regs->time_ax)) | + (1 << REG2OFF(&ata_cfg_regs->time_pio_rdx)) | + (((pio_t4[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_4)); + writel(val, &ata_cfg_regs->time_2r); + + /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ + val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_9)); + writel(val, &ata_cfg_regs->time_9); +} + +int ide_preinit(void) +{ + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + + /* 46.3.3.4 @ FSL iMX51 manual */ + /* FIFO normal op., drive reset */ + writel(0x80, &ata_cfg_regs->ata_control); + /* FIFO normal op., drive not reset */ + writel(0xc0, &ata_cfg_regs->ata_control); + + /* Configure the PIO timing */ + set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); + + /* 46.3.3.4 @ FSL iMX51 manual */ + /* Drive not reset, IORDY handshake */ + writel(0x41, &ata_cfg_regs->ata_control); + + return 0; +} -- 1.7.2.3

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[U-Boot] [PATCH] tools: fw_printenv supports mmc device
by y＠samsung.com 16 Dec '10

16 Dec '10

From: Donghwa Lee <dh09.lee(a)samsung.com> I modified fw_printenv tools to use /dev/mmcblk0 node. Original fw_printenv tool can be access MTD devices, but, in some cases, environment variables can be stored other memory devices, for example, mmc devices. So, I modified a few code to use /dev/mmcblk0. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- tools/env/fw_env.c | 13 ++++++++++--- tools/env/fw_env.config | 7 +++++-- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 8ff7052..5a707f6 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -855,6 +855,7 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, } erase.start = blockstart; +#ifndef CONFIG_ENV_IS_IN_MMC ioctl (fd, MEMUNLOCK, &erase); if (ioctl (fd, MEMERASE, &erase) != 0) { @@ -863,7 +864,7 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, strerror (errno)); return -1; } - +#endif if (lseek (fd, blockstart, SEEK_SET) == -1) { fprintf (stderr, "Seek error on %s: %s\n", @@ -880,8 +881,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, return -1; } +#ifndef CONFIG_ENV_IS_IN_MMC ioctl (fd, MEMLOCK, &erase); - +#endif processed += blocklen; block_seek = 0; blockstart += blocklen; @@ -964,9 +966,10 @@ static int flash_write (int fd_current, int fd_target, int dev_target) static int flash_read (int fd) { - struct mtd_info_user mtdinfo; int rc; +#ifndef CONFIG_ENV_IS_IN_MMC + struct mtd_info_user mtdinfo; rc = ioctl (fd, MEMGETINFO, &mtdinfo); if (rc < 0) { perror ("Cannot get MTD information"); @@ -982,6 +985,10 @@ static int flash_read (int fd) rc = flash_read_buf (dev_current, fd, environment.image, CONFIG_ENV_SIZE, DEVOFFSET (dev_current), mtdinfo.type); +#else + rc = flash_read_buf (dev_current, fd, environment.image, CONFIG_ENV_SIZE, + DEVOFFSET (dev_current), 0); +#endif return (rc != CONFIG_ENV_SIZE) ? -1 : 0; } diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index c8f12cf..228ded8 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -4,8 +4,11 @@ # Notice, that the "Number of sectors" is ignored on NOR. # MTD device name Device offset Env. size Flash sector size Number of sectors -/dev/mtd1 0x0000 0x4000 0x4000 -/dev/mtd2 0x0000 0x4000 0x4000 +#/dev/mtd1 0x0000 0x4000 0x4000 +#/dev/mtd2 0x0000 0x4000 0x4000 # NAND example #/dev/mtd0 0x4000 0x4000 0x20000 2 + +# MMC device name Device offset Env. size Flash sector size Number of sectors +/dev/mmcblk0 0x7000 0x1000 0x1000 -- 1.6.0.4

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[U-Boot] [PATCH v2 00/12] Go to common initdram() on 85xx-based boards
by Becky Bruce 16 Dec '10

16 Dec '10

This patch series consists of a bunch of cleanups that allow us to use a common initdram() on all of the non-corenet 85xx-based boards. Also, switch to using phys_size_t to represent the size of memory returned. Most of these patches are just code rearranges or renaming things to get a common scheme in place. There are also lots of cleanups - the various initdram() implementations had a variety of issues that I have hopefully fixed. This is a large patch series, and I've had to hack on a bunch of different boards that I know nothing about, so I'd appreciate any review commentary. I have tested this on 8572DS and confirmed that the results of a MAKEALL powerpc are the same before and after this series. Changes from V1: - Removed prints from initdram() as suggested by Peter - Changed spacing of 36-bit DRAM size warning messages to better line up after the removal of the excess prints from initdram() - Switched sdram_init() to be a weak function - renamed sdram_init() to lbc_sdram_init() Diffstat below. Cheers, Becky arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/cpu.c | 51 ++++++++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 6 ++- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 5 +- arch/powerpc/cpu/mpc8xxx/fsl_lbc.c | 10 +++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 4 + board/atum8548/atum8548.c | 25 +-------- board/freescale/mpc8536ds/mpc8536ds.c | 21 ------- board/freescale/mpc8540ads/mpc8540ads.c | 56 +----------------- board/freescale/mpc8540ads/tlb.c | 19 ------ board/freescale/mpc8541cds/mpc8541cds.c | 46 +-------------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ------ board/freescale/mpc8548cds/mpc8548cds.c | 41 +------------- board/freescale/mpc8555cds/mpc8555cds.c | 48 +--------------- board/freescale/mpc8560ads/mpc8560ads.c | 56 +----------------- board/freescale/mpc8560ads/tlb.c | 19 ------ board/freescale/mpc8568mds/mpc8568mds.c | 41 +------------- board/freescale/mpc8569mds/mpc8569mds.c | 36 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 19 ------ board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +----- board/freescale/p2020ds/p2020ds.c | 34 ++--------- board/mpc8540eval/mpc8540eval.c | 52 +--------------- board/pm854/law.c | 5 +- board/pm854/pm854.c | 62 +------------------- board/pm854/tlb.c | 18 +----- board/pm856/law.c | 5 +- board/pm856/pm856.c | 57 +------------------ board/pm856/tlb.c | 18 +----- board/sbc8548/sbc8548.c | 48 +--------------- board/sbc8548/tlb.c | 34 ++++------- board/sbc8560/sbc8560.c | 93 +----------------------------- board/socrates/sdram.c | 15 +----- board/stx/stxgp3/stxgp3.c | 32 ---------- board/stx/stxssa/stxssa.c | 33 ----------- board/tqc/tqm85xx/sdram.c | 70 +++++++---------------- board/tqc/tqm85xx/tlb.c | 47 --------------- board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 --------------- board/xes/xpedite517x/xpedite517x.c | 13 ++++ doc/README.mpc85xxads | 4 +- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540EVAL.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 7 -- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/PM854.h | 8 +-- include/configs/PM856.h | 8 +-- include/configs/SBC8540.h | 2 +- include/configs/TQM85xx.h | 6 ++- include/configs/sbc8560.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 1 - 56 files changed, 186 insertions(+), 1110 deletions(-)

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[U-Boot] 85xx board maintainership / anyone care?
by Kumar Gala 15 Dec '10

15 Dec '10

There are a few 85xx boards that I'm wondering if anyone cares about or is acting as a maintainer: ATUM8548 (Robert Lazarski) MPC8540EVAL PM854 PM856 socrates (Sergei Poselenov) sbc8540 sbc8560 sbc8548 (Joe Hamman) stxgp3 (Dan Malek) stxssa (Dan Malek) I'd like to remove support for any of these unmaintained or uncared for boards for post v2010.12. thanks - k

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[U-Boot] [PATCH 1/2][v2] PBL: add support for boot from SPI flash.
by Shaohui Xie 15 Dec '10

15 Dec '10

PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806(a)freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> Signed-off-by: Shaohui Xie <b21989(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ board/freescale/corenet_ds/config.mk | 6 ++++++ board/freescale/corenet_ds/tlb.c | 9 +++++++++ boards.cfg | 1 + include/configs/corenet_ds.h | 31 +++++++++++++++++++++++++++++-- 5 files changed, 62 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 27236a0..cff7ac3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -139,6 +139,20 @@ static void enable_cpc(void) for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { u32 cpccfg0 = in_be32(&cpc->cpccfg0); size += CPC_CFG0_SZ_K(cpccfg0); + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { + /* find and disable LAW of SRAM */ + struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + + if (law.index == -1) { + printf("\nFatal error happened\n"); + return; + } else + disable_law(law.index); + + clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); + out_be32(&cpc->cpccsr0, 0); + out_be32(&cpc->cpcsrcr0, 0); + } out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); /* Read back to sync write */ @@ -155,6 +169,9 @@ void invalidate_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + /* skip CPC when it used as all SRAM */ + if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) + continue; /* Flash invalidate the CPC and clear all the locks */ out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk index 15bbf20..31b3379 100644 --- a/board/freescale/corenet_ds/config.mk +++ b/board/freescale/corenet_ds/config.mk @@ -24,4 +24,10 @@ # P4080DS board # +ifeq ($(CONFIG_PBL_BOOT_INDIRECT), y) +RESET_VECTOR_ADDRESS = 0xfffffffc +endif + +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffffffc +endif diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 1ae0416..08f91a7 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -51,9 +51,18 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + * */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, diff --git a/boards.cfg b/boards.cfg index 6c2a667..168d6f5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -195,6 +195,7 @@ P1022DS powerpc mpc85xx p1022ds freescale P2020DS powerpc mpc85xx p2020ds freescale stxgp3 powerpc mpc85xx stxgp3 stx P4080DS powerpc mpc85xx corenet_ds freescale +P4080DS_PBL_BOOT_INDIRECT powerpc mpc85xx corenet_ds freescale - P4080DS:PBL_BOOT_INDIRECT,SYS_TEXT_BASE=0xFFF80000 sbc8540 powerpc mpc85xx sbc8560 - - SBC8540 sbc8548 powerpc mpc85xx sbc8548 - - sbc8548 sbc8560 powerpc mpc85xx sbc8560 - - sbc8560 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2ac59e5..0776c3b 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -28,6 +28,11 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_PBL_BOOT_INDIRECT +#define CONFIG_RAMBOOT_PBL 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xfff80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -58,11 +63,17 @@ #ifdef CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_NOWHERE #else -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #endif +#if defined(CONFIG_RAMBOOT_PBL) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#else + #define CONFIG_ENV_IS_IN_FLASH + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif + #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ @@ -93,6 +104,19 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + + +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ @@ -185,6 +209,10 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} @@ -456,7 +484,6 @@ /* * Environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -- 1.6.4

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[U-Boot] [PATCH] ppc4xx: Fix missing linker scripts for partial linking
by Stefan Roese 15 Dec '10

15 Dec '10

This patch fixes the acadia_nand and kilauea_nand linker scripts which have been missing in commit ee8028b7 [ppc4xx: Cleanup for partial linking and --gc-sections] Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Bernhard Weirich <Bernhard.Weirich(a)riedel.net> --- board/amcc/acadia/u-boot-nand.lds | 49 ++++++----------------------------- board/amcc/kilauea/u-boot-nand.lds | 49 ++++++----------------------------- 2 files changed, 18 insertions(+), 80 deletions(-) diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index e256b19..c2a04c7 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -26,34 +26,12 @@ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/ppc4xx/start.o (.text) + arch/powerpc/cpu/ppc4xx/start.o (.text*) /* Align to next NAND block */ . = ALIGN(0x4000); @@ -61,8 +39,7 @@ SECTIONS /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); - *(.text) - *(.got1) + *(.text*) } _etext = .; PROVIDE (etext = .); @@ -70,9 +47,6 @@ SECTIONS { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -80,23 +54,19 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + KEEP(*(.got)) _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -122,9 +92,8 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.bss*) + *(.sbss*) *(COMMON) . = ALIGN(4); } diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index e256b19..c2a04c7 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -26,34 +26,12 @@ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } .text : { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/powerpc/cpu/ppc4xx/start.o (.text) + arch/powerpc/cpu/ppc4xx/start.o (.text*) /* Align to next NAND block */ . = ALIGN(0x4000); @@ -61,8 +39,7 @@ SECTIONS /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); - *(.text) - *(.got1) + *(.text*) } _etext = .; PROVIDE (etext = .); @@ -70,9 +47,6 @@ SECTIONS { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ . = (. + 0x00FF) & 0xFFFFFF00; @@ -80,23 +54,19 @@ SECTIONS PROVIDE (erotext = .); .reloc : { - *(.got) + KEEP(*(.got)) _GOT2_TABLE_ = .; - *(.got2) + KEEP(*(.got2)) _FIXUP_TABLE_ = .; - *(.fixup) + KEEP(*(.fixup)) } __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; __fixup_entries = (. - _FIXUP_TABLE_)>>2; .data : { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS + *(.data*) + *(.sdata*) } _edata = .; PROVIDE (edata = .); @@ -122,9 +92,8 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) + *(.bss*) + *(.sbss*) *(COMMON) . = ALIGN(4); } -- 1.7.3.3

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[U-Boot] NEC OHCI chip bug
by Martin Mueller 15 Dec '10

15 Dec '10

Hi Gavin , > We need NEC pci-to-usb host controller work on U-boot. Because > using Faraday technology PCI controller, I need to complete the PCI > driver first. Now the PCI driver is completed. At this time, the > NEC host controller can work. When plugging a keyboard, 2 devices > can be found showing on console. But things are not as easy as we > think, OHCI host controller encounter an "Unrecoverable Error" > when getting device descriptor from keyboard. In the Linux kernel, > I found that there is a workaround if the OHCI host controller is > NEC's. The following link explain more detail: > http://www.mail-archive.com/linux-usb-devel@lists.sourceforge.net/msg54465.… > After looking at the source code in U-boot, it seems that there > isn't any workaround about the NEC's bug ? Any idea about how to > get the controller, or do I need to implement the workaround by > myself ?? are you sure it is that NEC bug? We had a similar error message when the PCI bridge was not properly setup and the OHCI could not access RAM through PCI (DMA), hence the "unrecoverable error". Martin

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Re: [U-Boot] NEC OHCI chip bug
by gavinguo＠andestech.com 15 Dec '10

15 Dec '10

> Seems you have to implement this workaround for U-Boot. Patches > welcome. Ok, I will try my best to figure out how to implement this one. > And *PLEASE* restrict your line length to some 70 or so characters. Thank you for the reminder. I have modified the setting to 70 characters a line. Regards, Gavin Guo

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