December 2010 - U-Boot

[U-Boot] [PATCH] Blackfin: dnp5370: new board port
by Mike Frysinger 19 Dec '10

19 Dec '10

From: Andreas Schallenberg <Andreas.Schallenberg(a)3alitydigital.de> Info about the hardware can be found here: http://www.dilnetpc.com/dnp0086.htm Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg(a)3alitydigital.de> Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- board/dnp5370/Makefile | 54 ++++++++++++++++++++ board/dnp5370/config.mk | 29 +++++++++++ board/dnp5370/dnp5370.c | 104 +++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + doc/README.dnp5370 | 67 +++++++++++++++++++++++++ include/configs/dnp5370.h | 119 +++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 374 insertions(+), 0 deletions(-) create mode 100644 board/dnp5370/Makefile create mode 100644 board/dnp5370/config.mk create mode 100644 board/dnp5370/dnp5370.c create mode 100644 doc/README.dnp5370 create mode 100644 include/configs/dnp5370.h diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile new file mode 100644 index 0000000..bfeaf79 --- /dev/null +++ b/board/dnp5370/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2007 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/dnp5370/config.mk b/board/dnp5370/config.mk new file mode 100644 index 0000000..8227506 --- /dev/null +++ b/board/dnp5370/config.mk @@ -0,0 +1,29 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf537-0.3 diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c new file mode 100644 index 0000000..da9eb5f --- /dev/null +++ b/board/dnp5370/dnp5370.c @@ -0,0 +1,104 @@ +/* + * U-boot - main board file + * + * (C) Copyright 2010 3ality Digital Systems + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/blackfin.h> +#include <asm/net.h> +#include <net.h> +#include <netdev.h> +#include <asm/gpio.h> + +static void disable_external_watchdog(void) +{ +#ifdef CONFIG_DNP5370_EXT_WD_DISABLE + /* disable external HW watchdog with PH13 = WD1 = 1 */ + gpio_request(GPIO_PH13, "ext_wd"); + gpio_direction_output(GPIO_PH13, 1); +#endif +} + +int checkboard(void) +{ + printf("Board: SSV DilNet DNP5370\n"); + return 0; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ +#ifdef CONFIG_SYS_NO_FLASH +# define USE_MAC_IN_FLASH 0 +#else +# define USE_MAC_IN_FLASH 1 +#endif + bool valid_mac = false; + + if (USE_MAC_IN_FLASH) { + /* we cram the MAC in the last flash sector */ + uchar *board_mac_addr = (uchar *)0x202F0000; + if (is_valid_ether_addr(board_mac_addr)) { + memcpy(mac_addr, board_mac_addr, 6); + valid_mac = true; + } + } + + if (!valid_mac) { + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + } + + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif + +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + disable_external_watchdog(); + +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + +#ifndef CONFIG_SYS_NO_FLASH + /* we use the last sector for the MAC address / POST LDR */ + extern flash_info_t flash_info[]; + flash_protect(FLAG_PROTECT_SET, 0x202F0000, 0x202FFFFF, &flash_info[0]); +#endif + + return 0; +} diff --git a/boards.cfg b/boards.cfg index a69cb85..082ae2e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -306,6 +306,7 @@ cm-bf537e blackfin blackfin cm-bf537u blackfin blackfin cm-bf548 blackfin blackfin cm-bf561 blackfin blackfin +dnp5370 blackfin blackfin ibf-dsp561 blackfin blackfin ip04 blackfin blackfin tcm-bf518 blackfin blackfin diff --git a/doc/README.dnp5370 b/doc/README.dnp5370 new file mode 100644 index 0000000..0172698 --- /dev/null +++ b/doc/README.dnp5370 @@ -0,0 +1,67 @@ +This document describes the board support for +Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module. +The distributor is SSV (http://www.ssv-embedded.de), + +The module used to develop the support files contains: + +* Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM) + +* RAM: 32 MB SDRAM + Hynix HY57V561620FTP-H 810EA + Connected to Blackfin via "Expansion Bus" + Address range 0x0000.0000 - 0x1fff.ffff + +* NOR flash: 32 MBit (4 MByte) + Exel Semiconductor ES29LVS320EB + Connected to Blackfin via "Expansion Bus", + Chip Selects 0, 1 and 2, each is connected + to a 1 MB memory bank at Blackfin, therefore + only 3 MB accessible. + Address range 0x2000.0000 - 0x202f.ffff + CFI compatible + + Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com). + +* NAND flash: 64 MBit (8 MByte) + Atmel 45DB642D-CNU + Connected to Blackfin via SPI + CFI compatible + +* Davicom DM9161EP Ethernet PHY + +* A SD card reader, connected via SPI + +* Hardware watchdog MAX823 or TPS3823 + +(other devices not listed here) + +To run it, the module must be inserted in a 64 pin DIL socket +on another board, e.g. DNP/EVA13 (together: SSV SK28). + +The Blackfin is booted from NOR flash. The NOR flash data begins +with the U-Boot code and is then followed by the Linux code. +Finally, the MAC is stored in the last sector. +You may need to adjust these settings to your needs. +The memory map used to develop the board support is: + +Memory map: +0x00000000 .. 0x01ffffff SDRAM +0x20000000 .. 0x202fffff NOR flash + +RAM use: +0x01f9bffc .. 0x01fbbffb U-Boot stack +0x01f9c000 .. 0x01f9ffff U-Boot global data +0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM +0x01fc0000 .. 0x01ffffff U-Boot execution RAM + +NOR flash use: +0x20000000 .. 0x0002ffff U-Boot +0x20004000 .. 0x20005fff U-Boot environment +0x20030000 .. 0x202effff Linux kernel image +0x202f0000 .. 0x202fffff MAC address sector + +NOR flash is 0x00300000 (3145728) bytes large (3 MB). +Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB) +Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB) + +The module is hardwired to BYPASS boot mode. diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h new file mode 100644 index 0000000..e4a42ae --- /dev/null +++ b/include/configs/dnp5370.h @@ -0,0 +1,119 @@ +/* + * U-boot - Configuration file for SSV DNP5370 board + */ + +#ifndef __CONFIG_DNP5370_H__ +#define __CONFIG_DNP5370_H__ + +/* this must come first */ +#include <asm/config-pre.h> + +/* + * Processor Settings + */ +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +#define CONFIG_CLKIN_HZ 25000000 +#define CONFIG_CLKIN_HALF 0 +#define CONFIG_PLL_BYPASS 0 +#define CONFIG_VCO_MULT 24 +#define CONFIG_CCLK_DIV 1 +#define CONFIG_SCLK_DIV 5 + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x03a0 +#define CONFIG_EBIU_SDBCTL_VAL 0x0013 +#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d + +#define CONFIG_EBIU_AMGCTL_VAL 0xF7 +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + +/* + * Network Settings + */ +#define CONFIG_IPADDR 10.100.100.21 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_GATEWAYIP 10.100.100.1 +#define CONFIG_SERVERIP 10.100.100.12 +#define CONFIG_ROOTPATH /romfs + +#define CONFIG_NET_MULTI 1 +#define CONFIG_BFIN_MAC 1 +#define CONFIG_PHY_ADDR 0 +#define CONFIG_RMII 1 + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +/* + * Flash Settings + * + * Only 3 MB of the 4 MB NOR flash are addressable. + * But limiting the flash size does not seem to work. + * It seems the CFI detection has precedence. + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */ + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x20004000 +#define CONFIG_ENV_SIZE 0x00002000 +#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */ + +#define ENV_IS_EMBEDDED + +/* + * Misc Settings + */ +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_STRINGS +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_SYS_LONGHELP + +/* This disables the hardware watchdog (not inside the bfin) */ +#define CONFIG_DNP5370_EXT_WD_DISABLE 1 + +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTCOMMAND "bootm 0x20030000" +#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2" + +/* Convenience commands to update Linux in NOR flash */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fetchme=tftpboot 0x01000000 uImage;" \ + "iminfo\0"\ + "flashme=protect off 0x20030000 0x2003ffff;" \ + "erase 0x20030000 0x202effff;" \ + "cp.b 0x01000000 0x20030000 0x2c0000\0" \ + "runme=bootm 0x01000000\0" + +/* this sets up the default list of enabled commands */ +#include <config_cmd_default.h> + +#endif -- 1.7.3.2

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[U-Boot] [PATCH] Blackfin: bf518f-ezbrd: don't require SPI logic all the time
by Mike Frysinger 19 Dec '10

19 Dec '10

Only the first run of boards had a ksz switch on it, so if building for a newer silicon rev or SPI is disabled, don't bother checking for the ksz. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- board/bf518f-ezbrd/bf518f-ezbrd.c | 30 ++++++++++++++++++++++-------- 1 files changed, 22 insertions(+), 8 deletions(-) diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index ff1ac4c..4bd02ee 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -57,6 +57,13 @@ static void board_init_enetaddr(uchar *mac_addr) eth_setenv_enetaddr("ethaddr", mac_addr); } +/* Only the first run of boards had a KSZ switch */ +#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0 +# define KSZ_POSSIBLE 1 +#else +# define KSZ_POSSIBLE 0 +#endif + #define KSZ_MAX_HZ 5000000 #define KSZ_WRITE 0x02 @@ -109,17 +116,16 @@ static int ksz8893m_reset(struct spi_slave *slave) return ret; } -int board_eth_init(bd_t *bis) +static int board_ksz_init(void) { - static bool switch_is_alive = false, phy_is_ksz = true; - int ret; + static bool switch_is_alive = false; if (!switch_is_alive) { struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3); if (slave) { if (!spi_claim_bus(slave)) { - phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88); - ret = phy_is_ksz ? ksz8893m_reset(slave) : 0; + bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88); + int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0; switch_is_alive = (ret == 0); spi_release_bus(slave); } @@ -127,10 +133,18 @@ int board_eth_init(bd_t *bis) } } - if (switch_is_alive) - return bfin_EMAC_initialize(bis); - else + if (!switch_is_alive) return -1; + else + return 0; +} + +int board_eth_init(bd_t *bis) +{ + if (KSZ_POSSIBLE) + if (board_ksz_init() == -1) + return 0; + return bfin_EMAC_initialize(bis); } #endif -- 1.7.3.3

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[U-Boot] Blizzard Entertainment : Account Investigation - Informations needed
by Blizzard Entertainment 19 Dec '10

19 Dec '10

Greetings, An investigation of your World of Warcraft account has found strong evidence that the account in question is being sold or traded. As you may not be aware of, this conflicts with Blizzard's EULA under section 4 Paragraph B which can be found here: http://www.worldofwarcraft.com/legal/eula.html and Section 8 of the Terms of Use found here: http://www.worldofwarcraft.com/legal/termsofuse.html The investigation will be continued by Blizzard administration to determine the action to be taken against your account. If your account is found violating the EULA and Terms of Use, your account can, and will be suspended/closed/or terminated. In order to keep this from occurring, you should immediately verify that you are the original owner of the account. To Confirm your identity please follow instructions on this webpage: http://www.battlenet-support.com/login.xmlref=2Faccount2fmanagment2Fwam14Ac… Only Account Administration will be able to assist with account retrieval issues. Thank you for your time and attention to this matter, and your continued interest in World of Warcraft. Sincerely, Account Administration Blizzard Entertainment

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[U-Boot] A small hickup when switching over to out-of-tree building
by Reinhard Meyer 19 Dec '10

19 Dec '10

Hello, when switching from in-tree building to out-of-tree building (BUILD_DIR=<path>) the files *_autogenerated.h left in the in-tree include directory will be included instead of the files in <path>/include. That will cause a newly built u-boot to display some old date and version! One has to remove them manually or do a "make clean" without BUILD_DIR set to fix the issue. Best Regards, Reinhard

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Re: [U-Boot] HAJIA MUNNA
by Faz Zaxxy 19 Dec '10

19 Dec '10

Good day to you, I am so sorry for sending you this unsolicited and unexpected mail. I got your contact from the Business Directory page at my agent’s office, and I decided to contact you directly for the purposes of assistance and corporation. My full Name is Mrs Munna Muhammad with my son Ibraheem Muhammad we are from Congo, we are temporary in U.A.E searching for a reliable and experience business partner. We have about $12.5 Million Dollars and I would need your assistance in the area of investing it either here in U.A.E or any country of your choice under your guidance. So I am only soliciting for your assistance to help me invest in a profitable business. Our Business is totally free of risk and trouble. If God has touched you and you are willing to assist us in this course, please give me your confidential contact phone number so that my son Ibraheem could contact you on the phone and discuss in details. I’ill be looking forward to your reply: munna.muhammad(a)yahoo.com Best Regards,Mrs. Munna Muhammad

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[U-Boot] season of love
by nadia faruk 19 Dec '10

19 Dec '10

>From Mrs. Nadia Faruk. Dear God’s elect, I am writing this mail wishing it to meet you in good health, for myself is in a very bad health condition in which I wake up every morning with eyes full of tears. I am Mrs. Nadia Faruk. Am contacting you from a hospital bed here in Tunisia. I am telling you this as I am left with no option but to be open to you. Am married to late Mr. Usman Faruk who until his death in October 2005 was a solid mineral engineer with the Burkina Faso mining co-operation. We were married for thirteen years without any child until the day he collapse and died in his office due to heart related problem and since then I decided not to marry again. When my husband was alive he deposited the sum of five million five hundred thousand euro (€5.5 million) with the African development bank in Ouagadougou the capital city of Burkina Faso. He made this deposit for exportation of gold from the Burkina Faso mining co-operation before his untimely death. Now I will die of cancer for my doctor has made it clear that I will not last another six months and For reasons which I do not know, my husband relatives never supported my marriage with their brother and now they wish that I die sooner and keep pestering me with questions to know if I have any assets so they can take it and share among themselves. The cancer is not the main problem but the partial stroke that sometimes hinders me from reading, but to god be the glory. Having considered my position, I have decided to hand the money over to you with instruction that you take 30% for yourself and your family and use 70% and build an orphanage home for the motherless babies because I am an orphan and have no relatives. Please you must follow this instruction or we will forget about it for am doing it so that heaven will receive my soul where I know my husband is already waiting for me. Once I hear from you then I will direct you on what to do to get all the help you may need. I will be waiting for your response and do have a nice day. Mrs. Nadia faruk

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[U-Boot] [PATCH] DaVinci DM365: Adding MMC/SD support for DM365 EVM
by s-paulraj＠ti.com 19 Dec '10

19 Dec '10

From: Sandeep Paulraj <s-paulraj(a)ti.com> The patch adds support for MMC/SD in the DM365 EVM Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- board/davinci/dm365evm/dm365evm.c | 49 ++++++++++++++++++++++++++++++++++++ include/configs/davinci_dm365evm.h | 22 ++++++++++++++++ 2 files changed, 71 insertions(+), 0 deletions(-) diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index bc681f7..5fb7611 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -25,6 +25,10 @@ #include <asm/arch/gpio_defs.h> #include <netdev.h> #include <asm/arch/davinci_misc.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -101,3 +105,48 @@ int board_nand_init(struct nand_chip *nand) return 0; } #endif + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .input_clk = 121500000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +#ifdef CONFIG_DAVINCI_MMC_SD1 +static struct davinci_mmc mmc_sd1 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, + .input_clk = 121500000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; +#endif + +int board_mmc_init(bd_t *bis) +{ + int err; + + /* Add slot-0 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd0); + if (err) + return err; + +#ifdef CONFIG_DAVINCI_MMC_SD1 +#define PUPDCTL1 0x01c4007c + /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */ + writel((readl(PINMUX4) | 0x55400000), PINMUX4); + writel((readl(PINMUX0) | 0x00010000), PINMUX0); + + /* Configure MMC/SD pins as pullup */ + writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1); + + /* Add slot-1 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd1); +#endif + + return err; +} +#endif diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index a36e138..2825050 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -85,6 +85,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC +#define CONFIG_DAVINCI_MMC_SD1 +#define CONFIG_MMC_MBLOCK + #define PINMUX4_USBDRVBUS_BITCLEAR 0x3000 #define PINMUX4_USBDRVBUS_BITSET 0x2000 @@ -137,6 +144,13 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#endif + #ifdef CONFIG_NAND_DAVINCI #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS @@ -168,6 +182,14 @@ #undef CONFIG_ENV_IS_IN_FLASH #endif +#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_CMD_ENV +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ +#define CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_IS_IN_FLASH +#endif + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND \ "dhcp;bootm" -- 1.6.0.4

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[U-Boot] [PATCH] DaVinci DM355: Adding MMC/SD support for DM355 EVM
by s-paulraj＠ti.com 19 Dec '10

19 Dec '10

From: Sandeep Paulraj <s-paulraj(a)ti.com> The patch adds support for MMC/SD in the DM355 EVM Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- board/davinci/dm355evm/dm355evm.c | 41 ++++++++++++++++++++++++++++++++++++ include/configs/davinci_dm355evm.h | 22 +++++++++++++++++++ 2 files changed, 63 insertions(+), 0 deletions(-) diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index b9260b8..112851a 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -25,6 +25,10 @@ #include <asm/arch/davinci_misc.h> #include <net.h> #include <netdev.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -114,3 +118,40 @@ int board_nand_init(struct nand_chip *nand) } #endif + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .input_clk = 108000000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_1, +}; + +#ifdef CONFIG_DAVINCI_MMC_SD1 +static struct davinci_mmc mmc_sd1 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, + .input_clk = 108000000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_1, +}; +#endif + +int board_mmc_init(bd_t *bis) +{ + int err; + + /* Add slot-0 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd0); + if (err) + return err; + +#ifdef CONFIG_DAVINCI_MMC_SD1 + /* Add slot-1 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd1); +#endif + + return err; +} +#endif diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 90f8e7c..56d0ac9 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -76,6 +76,13 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DAVINCI_MMC +#define CONFIG_DAVINCI_MMC_SD1 +#define CONFIG_MMC_MBLOCK + /* USB: OTG connector */ /* NYET -- #define CONFIG_USB_DAVINCI */ @@ -93,6 +100,13 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES +#ifdef CONFIG_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#endif + #ifdef CONFIG_NAND_DAVINCI #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS @@ -134,6 +148,14 @@ #undef CONFIG_ENV_IS_IN_FLASH #endif +#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_CMD_ENV +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ +#define CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_IS_IN_FLASH +#endif + #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND \ "dhcp;bootm" -- 1.6.0.4

1 0

[U-Boot] [PATCH v2] ftgmac100: support of gigabit eth ftgmac100
by Macpaul Lin 19 Dec '10

19 Dec '10

Add Faraday's ftgmac100 (gigabit ethernet) MAC controller's driver. Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> --- Changes for v2: - Coding Style cleanup - Makefile Order sorted - Volatile statement eliminated - Error handling added - Autonegotiation timeout value rechecked - Link speed detection code is reduced - Logic of autonegotiation and Link speed update reorganized - Redundent registers offset table cleared - The explaination of sub configuration of this driver has moved into README README | 12 + drivers/net/Makefile | 1 + drivers/net/ftgmac100.c | 576 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ftgmac100.h | 255 +++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 845 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ftgmac100.c create mode 100644 drivers/net/ftgmac100.h diff --git a/README b/README index 68f5fb0..d7a23cd 100644 --- a/README +++ b/README @@ -861,6 +861,18 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_FTGMAC100 + Support for Faraday's FTGMAC100 Gigabit SoC Ethernet + + CONFIG_FTGMAC100_EGIGA + Define this to use GE link update with gigabit PHY. + Define this if FTGMAC100 is connected to gigabit PHY. + If your system has 10/100 PHY only, it might not occur + wrong behavior. Because PHY usually return timeout or + useless data when polling gigabit status and gigabit + control registers. This behavior won't affect the + correctnessof 10/100 link speed update. + CONFIG_SMC911X Support for SMSC's LAN911x and LAN921x chips diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b605eea..fd9d0b4 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c new file mode 100644 index 0000000..336e1b8 --- /dev/null +++ b/drivers/net/ftgmac100.c @@ -0,0 +1,576 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> +#include <linux/mii.h> + +#include "ftgmac100.h" + +#define ETH_ZLEN 60 + +#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* RBSR - hw default init value is also 0x640 */ +#define RBSR_DEFAULT_VALUE 0x640 + +/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */ +#define PKTBUFSTX 4 /* must be power of 2 */ + +struct ftgmac100_data { + struct ftgmac100_txdes txdes[PKTBUFSTX]; + struct ftgmac100_rxdes rxdes[PKTBUFSRX]; + int tx_index; + int rx_index; + int phy_addr; +}; + + +/****************************************************************************** + * struct mii_bus functions + *****************************************************************************/ +static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr, + int regnum) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIRD; + + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { + int data; + + data = readl(&ftgmac100->phydata); + return FTGMAC100_PHYDATA_MIIRDATA(data); + } + + mdelay(10); + } + + debug("mdio read timed out\n"); + return -1; +} + +static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr, + int regnum, u16 value) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + int phycr; + int data; + int i; + + phycr = readl(&ftgmac100->phycr); + + /* preserve MDC cycle threshold */ + phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; + + phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) + | FTGMAC100_PHYCR_REGAD(regnum) + | FTGMAC100_PHYCR_MIIWR; + + data = FTGMAC100_PHYDATA_MIIWDATA(value); + + writel(data, &ftgmac100->phydata); + writel(phycr, &ftgmac100->phycr); + + for (i = 0; i < 10; i++) { + phycr = readl(&ftgmac100->phycr); + + if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) { + debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \ + "phy_addr: %x\n", phy_addr); + return 0; + } + + mdelay(1); + } + + debug("mdio write timed out\n"); + return -1; +} + +int ftgmac100_phy_read(struct eth_device *dev, int addr, + int reg, u16 *value) +{ + *value = ftgmac100_mdiobus_read(dev , addr, reg); + + if (*value == -1) + return -1; + else + return 0; +} + +int ftgmac100_phy_write(struct eth_device *dev, int addr, + int reg, u16 value) +{ + if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1) + return -1; + else + return 0; +} + +static int ftgmac100_phy_reset(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + int i; + u16 status, adv; + + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_ADVERTISE, adv); + printf("%s: Starting autonegotiation...\n", dev->name); + + ftgmac100_phy_write(dev, priv->phy_addr, + MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_ANEGCOMPLETE) + break; + mdelay(1); + } + + if (status & BMSR_ANEGCOMPLETE) { + printf("%s: Autonegotiation complete\n", dev->name); + } else { + printf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->name, status); + return 0; + } + + return 1; +} + +static int ftgmac100_phy_init(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + + int phy_addr; + u16 phy_id, status, adv, lpa, stat_ge; + int media, speed, duplex; + int i; + + /* Check if the PHY is up to snuff... */ + for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) { + ftgmac100_phy_read(dev, phy_addr, + MII_PHYSID1, &phy_id); + + /* + * When it is unable to found PHY, + * the interface usually return 0xffff or 0x0000 + */ + if (phy_id != 0xffff && phy_id != 0x0) { + printf("%s: found PHY at 0x%02x\n", + dev->name, phy_addr); + priv->phy_addr = phy_addr; + break; + } + } + + if (phy_id == 0xffff || phy_id == 0x0) { + printf("%s: no PHY present\n", dev->name); + return 0; + } + + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + ftgmac100_phy_reset(dev); + + for (i = 0; i < 100000 / 100; i++) { + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &status); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } + + if (!(status & BMSR_LSTATUS)) { + printf("%s: link down\n", dev->name); + return 0; + } else { + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); + + speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF) + ? 1 : 0); + + duplex = ((stat_ge & LPA_1000FULL) + ? 1 : 0); + + if (speed) { /* Speed is 1000 */ + printf("%s: link up, 1000bps %s-duplex\n", + dev->name, + duplex ? "full" : "half"); + return 0; + } +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, + MII_ADVERTISE, &adv); + ftgmac100_phy_read(dev, priv->phy_addr, + MII_LPA, &lpa); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + printf("%s: link up, %sMbps %s-duplex\n", + dev->name, + speed ? "100" : "10", + duplex ? "full" : "half"); + + return 1; + } +} + +static int ftgmac100_update_link_speed(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + + unsigned short stat_fe; + unsigned short stat_ge; + unsigned int maccr; + +#ifdef CONFIG_FTGMAC100_EGIGA + /* 1000 Base-T Status Register */ + ftgmac100_phy_read(dev, priv->phy_addr, + MII_STAT1000, &stat_ge); +#endif + + ftgmac100_phy_read(dev, priv->phy_addr, + MII_BMSR, &stat_fe); + + if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */ + return 0; + + /* read MAC control register and clear related bits */ + maccr = readl(&ftgmac100->maccr) & + ~(FTGMAC100_MACCR_GIGA_MODE | + FTGMAC100_MACCR_FAST_MODE | + FTGMAC100_MACCR_FULLDUP); + +#ifdef CONFIG_FTGMAC100_EGIGA + if (stat_ge & LPA_1000FULL) + /* set gmac for 1000BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP; + + if (stat_ge & LPA_1000HALF) + /* set gmac for 1000BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_GIGA_MODE; +#endif + + if (stat_fe & BMSR_100FULL) + /* set MII for 100BaseTX and Full Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP; + + if (stat_fe & BMSR_10FULL) + /* set MII for 10BaseT and Full Duplex */ + maccr |= FTGMAC100_MACCR_FULLDUP; + + if (stat_fe & BMSR_100HALF) + /* set MII for 100BaseTX and Half Duplex */ + maccr |= FTGMAC100_MACCR_FAST_MODE; + + if (stat_fe & BMSR_10HALF) + /* set MII for 10BaseT and Half Duplex */ + /* we have already clear these bits, do nothing */ + ; + + /* update MII config into maccr */ + writel(maccr, &ftgmac100->maccr); + + return 1; +} + +/* + * Reset MAC + */ +static void ftgmac100_reset(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr); + + while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftgmac100_set_mac(struct eth_device *dev, + const unsigned char *mac) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] + << 16 | mac[4] << 8 | mac[5]; + + debug("%s(%x %x)\n", __func__, maddr, laddr); + + writel(maddr, &ftgmac100->mac_madr); + writel(laddr, &ftgmac100->mac_ladr); +} + +static void ftgmac100_set_mac_from_env(struct eth_device *dev) +{ + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + + ftgmac100_set_mac(dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftgmac100_halt(struct eth_device *dev) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + + debug("%s()\n", __func__); + + writel(0, &ftgmac100->maccr); +} + +static int ftgmac100_init(struct eth_device *dev, bd_t *bd) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *txdes = priv->txdes; + struct ftgmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug("%s()\n", __func__); + + ftgmac100_reset(dev); + + /* set the ethernet address */ + ftgmac100_set_mac_from_env(dev); + + /* disable all interrupts */ + writel(0, &ftgmac100->ier); + + /* initialize descriptors */ + priv->tx_index = 0; + priv->rx_index = 0; + + txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR; + + for (i = 0; i < PKTBUFSTX; i++) { + /* TXBUF_BADR */ + txdes[i].txdes3 = 0; + txdes[i].txdes1 = 0; + } + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + } + + /* transmit ring */ + writel((unsigned int)txdes, &ftgmac100->txr_badr); + + /* receive ring */ + writel((unsigned int)rxdes, &ftgmac100->rxr_badr); + + /* poll receive descriptor automatically */ + writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc); + + /* config receive buffer size register */ + writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr); + + /* enable transmitter, receiver */ + maccr = FTGMAC100_MACCR_TXMAC_EN | + FTGMAC100_MACCR_RXMAC_EN | + FTGMAC100_MACCR_TXDMA_EN | + FTGMAC100_MACCR_RXDMA_EN | + FTGMAC100_MACCR_CRC_APD | + FTGMAC100_MACCR_FULLDUP | + FTGMAC100_MACCR_RX_RUNT | + FTGMAC100_MACCR_RX_BROADPKT; + + writel(maccr, &ftgmac100->maccr); + + if (!ftgmac100_phy_init(dev)) { + if (!ftgmac100_update_link_speed(dev)) + return -1; + } + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftgmac100_recv(struct eth_device *dev) +{ + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY)) + return -1; + + if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR | + FTGMAC100_RXDES0_CRC_ERR | + FTGMAC100_RXDES0_FTL | + FTGMAC100_RXDES0_RUNT | + FTGMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0); + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + NetReceive((void *)curr_des->rxdes3, rxlen); + + /* release buffer to DMA */ + curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftgmac100_send(struct eth_device *dev, void *packet, int length) +{ + struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase; + struct ftgmac100_data *priv = dev->priv; + struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index]; + int start; + + if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + debug("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < ETH_ZLEN) ? ETH_ZLEN : length; + + /* initiate a transmit sequence */ + curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */ + + /* only one descriptor on TXBUF */ + curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR; + curr_des->txdes0 |= FTGMAC100_TXDES0_FTS | + FTGMAC100_TXDES0_LTS | + FTGMAC100_TXDES0_TXBUF_SIZE(length) | + FTGMAC100_TXDES0_TXDMA_OWN ; + + /* start transmit */ + writel(1, &ftgmac100->txpd); + + /* wait for transfer to succeed */ + start = get_timer(0); + while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) { + if (get_timer(0) >= 5) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + + priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX; + + return 0; +} + +int ftgmac100_initialize(bd_t *bd) +{ + struct eth_device *dev; + struct ftgmac100_data *priv; + + dev = malloc(sizeof *dev); + if (!dev) { + printf("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + priv = memalign(16, sizeof(struct ftgmac100_data)); + if (!priv) { + printf("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(*priv)); + + sprintf(dev->name, "FTGMAC100"); + dev->iobase = CONFIG_FTGMAC100_BASE; + dev->init = ftgmac100_init; + dev->halt = ftgmac100_halt; + dev->send = ftgmac100_send; + dev->recv = ftgmac100_recv; + dev->priv = priv; + + eth_register(dev); + + return 1; + +free_dev: + free(dev); +out: + return 0; +} diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h new file mode 100644 index 0000000..46b7369 --- /dev/null +++ b/drivers/net/ftgmac100.h @@ -0,0 +1,255 @@ +/* + * Faraday FTGMAC100 Ethernet + * + * (C) Copyright 2010 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * (C) Copyright 2010 Andes Technology + * Macpaul Lin <macpaul(a)andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTGMAC100_H +#define __FTGMAC100_H + +/* The registers offset table of ftgmac100 */ +struct ftgmac100 { + unsigned int isr; /* 0x00 */ + unsigned int ier; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int hptxpd; /* 0x28 */ + unsigned int hptxpd_badr; /* 0x2c */ + unsigned int itc; /* 0x30 */ + unsigned int aptc; /* 0x34 */ + unsigned int dblac; /* 0x38 */ + unsigned int dmafifos; /* 0x3c */ + unsigned int revr; /* 0x40 */ + unsigned int fear; /* 0x44 */ + unsigned int tpafcr; /* 0x48 */ + unsigned int rbsr; /* 0x4c */ + unsigned int maccr; /* 0x50 */ + unsigned int macsr; /* 0x54 */ + unsigned int tm; /* 0x58 */ + unsigned int resv1; /* 0x5c */ /* not defined in spec */ + unsigned int phycr; /* 0x60 */ + unsigned int phydata; /* 0x64 */ + unsigned int fcr; /* 0x68 */ + unsigned int bpr; /* 0x6c */ + unsigned int wolcr; /* 0x70 */ + unsigned int wolsr; /* 0x74 */ + unsigned int wfcrc; /* 0x78 */ + unsigned int resv2; /* 0x7c */ /* not defined in spec */ + unsigned int wfbm1; /* 0x80 */ + unsigned int wfbm2; /* 0x84 */ + unsigned int wfbm3; /* 0x88 */ + unsigned int wfbm4; /* 0x8c */ + unsigned int nptxr_ptr; /* 0x90 */ + unsigned int hptxr_ptr; /* 0x94 */ + unsigned int rxr_ptr; /* 0x98 */ + unsigned int resv3; /* 0x9c */ /* not defined in spec */ + unsigned int tx; /* 0xa0 */ + unsigned int tx_mcol_scol; /* 0xa4 */ + unsigned int tx_ecol_fail; /* 0xa8 */ + unsigned int tx_lcol_und; /* 0xac */ + unsigned int rx; /* 0xb0 */ + unsigned int rx_bc; /* 0xb4 */ + unsigned int rx_mc; /* 0xb8 */ + unsigned int rx_pf_aep; /* 0xbc */ + unsigned int rx_runt; /* 0xc0 */ + unsigned int rx_crcer_ftl; /* 0xc4 */ + unsigned int rx_col_lost; /* 0xc8 */ +}; + +/* + * Interrupt status register & interrupt enable register + */ +#define FTGMAC100_INT_RPKT_BUF (1 << 0) +#define FTGMAC100_INT_RPKT_FIFO (1 << 1) +#define FTGMAC100_INT_NO_RXBUF (1 << 2) +#define FTGMAC100_INT_RPKT_LOST (1 << 3) +#define FTGMAC100_INT_XPKT_ETH (1 << 4) +#define FTGMAC100_INT_XPKT_FIFO (1 << 5) +#define FTGMAC100_INT_NO_NPTXBUF (1 << 6) +#define FTGMAC100_INT_XPKT_LOST (1 << 7) +#define FTGMAC100_INT_AHB_ERR (1 << 8) +#define FTGMAC100_INT_PHYSTS_CHG (1 << 9) +#define FTGMAC100_INT_NO_HPTXBUF (1 << 10) + +/* + * Interrupt timer control register + */ +#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) +#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7) +#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) +#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15) + +/* + * Automatic polling timer control register + */ +#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * DMA burst length and arbitration control register + */ +#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) +#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) +#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6) +#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) +#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) +#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) +#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) +#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) +#define FTGMAC100_DBLAC_IFG_INC (1 << 23) + +/* + * DMA FIFO status register + */ +#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) +#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) +#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) +#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) +#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) +#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26) +#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27) +#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28) +#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29) +#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30) +#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31) + +/* + * Receive buffer size register + */ +#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) + +/* + * MAC control register + */ +#define FTGMAC100_MACCR_TXDMA_EN (1 << 0) +#define FTGMAC100_MACCR_RXDMA_EN (1 << 1) +#define FTGMAC100_MACCR_TXMAC_EN (1 << 2) +#define FTGMAC100_MACCR_RXMAC_EN (1 << 3) +#define FTGMAC100_MACCR_RM_VLAN (1 << 4) +#define FTGMAC100_MACCR_HPTXR_EN (1 << 5) +#define FTGMAC100_MACCR_LOOP_EN (1 << 6) +#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) +#define FTGMAC100_MACCR_FULLDUP (1 << 8) +#define FTGMAC100_MACCR_GIGA_MODE (1 << 9) +#define FTGMAC100_MACCR_CRC_APD (1 << 10) +#define FTGMAC100_MACCR_RX_RUNT (1 << 12) +#define FTGMAC100_MACCR_JUMBO_LF (1 << 13) +#define FTGMAC100_MACCR_RX_ALL (1 << 14) +#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) +#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) +#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_FAST_MODE (1 << 19) +#define FTGMAC100_MACCR_SW_RST (1 << 31) + +/* + * PHY control register + */ +#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f +#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) +#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTGMAC100_PHYCR_MIIRD (1 << 26) +#define FTGMAC100_PHYCR_MIIWR (1 << 27) + +/* + * PHY data register + */ +#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) +#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftgmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* not used by HW */ + unsigned int txdes3; /* TXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) +#define FTGMAC100_TXDES0_EDOTR (1 << 15) +#define FTGMAC100_TXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_TXDES0_LTS (1 << 28) +#define FTGMAC100_TXDES0_FTS (1 << 29) +#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) + +#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) +#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) +#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) +#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) +#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) +#define FTGMAC100_TXDES1_LLC (1 << 22) +#define FTGMAC100_TXDES1_TX2FIC (1 << 30) +#define FTGMAC100_TXDES1_TXIC (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftgmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* not used by HW */ + unsigned int rxdes3; /* RXBUF_BADR */ +} __attribute__ ((aligned(16))); + +#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) +#define FTGMAC100_RXDES0_EDORR (1 << 15) +#define FTGMAC100_RXDES0_MULTICAST (1 << 16) +#define FTGMAC100_RXDES0_BROADCAST (1 << 17) +#define FTGMAC100_RXDES0_RX_ERR (1 << 18) +#define FTGMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTGMAC100_RXDES0_FTL (1 << 20) +#define FTGMAC100_RXDES0_RUNT (1 << 21) +#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) +#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) +#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) +#define FTGMAC100_RXDES0_LRS (1 << 28) +#define FTGMAC100_RXDES0_FRS (1 << 29) +#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) + +#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff +#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) +#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) +#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) +#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) +#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) +#define FTGMAC100_RXDES1_LLC (1 << 22) +#define FTGMAC100_RXDES1_DF (1 << 23) +#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) +#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) +#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) +#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) + +#endif /* __FTGMAC100_H */ diff --git a/include/netdev.h b/include/netdev.h index 7f66419..1a542e8 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -61,6 +61,7 @@ int ethoc_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); int fecmxc_initialize (bd_t *bis); +int ftgmac100_initialize(bd_t *bits); int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -- 1.7.3.2

2 1

[U-Boot] [PATCH] Davinci MMCSD Support
by s-paulraj＠ti.com 19 Dec '10

19 Dec '10

From: Sandeep Paulraj <s-paulraj(a)ti.com> Added support for MMC/SD cards for Davinci. This feature is enabled by CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC options. This is tested on DM355 and DM365 EVMs with both the available mmc controllers. Signed-off-by: Alagu Sankar <alagusankar(a)embwise.com> Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- This patch has been in a TI tree for a very long time and the original authors seem busy. In my spare time I am attempting to get it upstream arch/arm/include/asm/arch-davinci/sdmmc_defs.h | 175 ++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/davinci_mmc.c | 404 ++++++++++++++++++++++++ 3 files changed, 580 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-davinci/sdmmc_defs.h create mode 100644 drivers/mmc/davinci_mmc.c diff --git a/arch/arm/include/asm/arch-davinci/sdmmc_defs.h b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h new file mode 100644 index 0000000..853fd40 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/sdmmc_defs.h @@ -0,0 +1,175 @@ +/* + * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c + * + * Copyright (C) 2010 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _SDMMC_DEFS_H_ +#define _SDMMC_DEFS_H_ + +#include <asm/arch/hardware.h> + +/* MMC Control Reg fields */ +#define MMCCTL_DATRST (1 << 0) +#define MMCCTL_CMDRST (1 << 1) +#define MMCCTL_WIDTH_4_BIT (1 << 2) +#define MMCCTL_DATEG_DISABLED (0 << 6) +#define MMCCTL_DATEG_RISING (1 << 6) +#define MMCCTL_DATEG_FALLING (2 << 6) +#define MMCCTL_DATEG_BOTH (3 << 6) +#define MMCCTL_PERMDR_LE (0 << 9) +#define MMCCTL_PERMDR_BE (1 << 9) +#define MMCCTL_PERMDX_LE (0 << 10) +#define MMCCTL_PERMDX_BE (1 << 10) + +/* MMC Clock Control Reg fields */ +#define MMCCLK_CLKEN (1 << 8) +#define MMCCLK_CLKRT_MASK (0xFF << 0) + +/* MMC Status Reg0 fields */ +#define MMCST0_DATDNE (1 << 0) +#define MMCST0_BSYDNE (1 << 1) +#define MMCST0_RSPDNE (1 << 2) +#define MMCST0_TOUTRD (1 << 3) +#define MMCST0_TOUTRS (1 << 4) +#define MMCST0_CRCWR (1 << 5) +#define MMCST0_CRCRD (1 << 6) +#define MMCST0_CRCRS (1 << 7) +#define MMCST0_DXRDY (1 << 9) +#define MMCST0_DRRDY (1 << 10) +#define MMCST0_DATED (1 << 11) +#define MMCST0_TRNDNE (1 << 12) + +#define MMCST0_ERR_MASK (0x00F8) + +/* MMC Status Reg1 fields */ +#define MMCST1_BUSY (1 << 0) +#define MMCST1_CLKSTP (1 << 1) +#define MMCST1_DXEMP (1 << 2) +#define MMCST1_DRFUL (1 << 3) +#define MMCST1_DAT3ST (1 << 4) +#define MMCST1_FIFOEMP (1 << 5) +#define MMCST1_FIFOFUL (1 << 6) + +/* MMC INT Mask Reg fields */ +#define MMCIM_EDATDNE (1 << 0) +#define MMCIM_EBSYDNE (1 << 1) +#define MMCIM_ERSPDNE (1 << 2) +#define MMCIM_ETOUTRD (1 << 3) +#define MMCIM_ETOUTRS (1 << 4) +#define MMCIM_ECRCWR (1 << 5) +#define MMCIM_ECRCRD (1 << 6) +#define MMCIM_ECRCRS (1 << 7) +#define MMCIM_EDXRDY (1 << 9) +#define MMCIM_EDRRDY (1 << 10) +#define MMCIM_EDATED (1 << 11) +#define MMCIM_ETRNDNE (1 << 12) + +#define MMCIM_MASKALL (0xFFFFFFFF) + +/* MMC Resp Tout Reg fields */ +#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */ +#define MMCTOR_TOD_20_16_SHIFT (8) + +/* MMC Data Read Tout Reg fields */ +#define MMCTOD_TOD_0_15_MASK (0xFFFF) + +/* MMC Block len Reg fields */ +#define MMCBLEN_BLEN_MASK (0xFFF) + +/* MMC Num Blocks Reg fields */ +#define MMCNBLK_NBLK_MASK (0xFFFF) +#define MMCNBLK_NBLK_MAX (0xFFFF) + +/* MMC Num Blocks Counter Reg fields */ +#define MMCNBLC_NBLC_MASK (0xFFFF) + +/* MMC Cmd Reg fields */ +#define MMCCMD_CMD_MASK (0x3F) +#define MMCCMD_PPLEN (1 << 7) +#define MMCCMD_BSYEXP (1 << 8) +#define MMCCMD_RSPFMT_NONE (0 << 9) +#define MMCCMD_RSPFMT_R1567 (1 << 9) +#define MMCCMD_RSPFMT_R2 (2 << 9) +#define MMCCMD_RSPFMT_R3 (3 << 9) +#define MMCCMD_DTRW (1 << 11) +#define MMCCMD_STRMTP (1 << 12) +#define MMCCMD_WDATX (1 << 13) +#define MMCCMD_INITCK (1 << 14) +#define MMCCMD_DCLR (1 << 15) +#define MMCCMD_DMATRIG (1 << 16) + +/* FIFO control Reg fields */ +#define MMCFIFOCTL_FIFORST (1 << 0) +#define MMCFIFOCTL_FIFODIR (1 << 1) +#define MMCFIFOCTL_FIFOLEV (1 << 2) +#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ +#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ +#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ +#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ + +/* Davinci MMC Register definitions */ +struct davinci_mmc_regs { + dv_reg mmcctl; + dv_reg mmcclk; + dv_reg mmcst0; + dv_reg mmcst1; + dv_reg mmcim; + dv_reg mmctor; + dv_reg mmctod; + dv_reg mmcblen; + dv_reg mmcnblk; + dv_reg mmcnblc; + dv_reg mmcdrr; + dv_reg mmcdxr; + dv_reg mmccmd; + dv_reg mmcarghl; + dv_reg mmcrsp01; + dv_reg mmcrsp23; + dv_reg mmcrsp45; + dv_reg mmcrsp67; + dv_reg mmcdrsp; + dv_reg mmcetok; + dv_reg mmccidx; + dv_reg mmcckc; + dv_reg mmctorc; + dv_reg mmctodc; + dv_reg mmcblnc; + dv_reg sdioctl; + dv_reg sdiost0; + dv_reg sdioien; + dv_reg sdioist; + dv_reg mmcfifoctl; +}; + +/* Davinci MMC board definitions */ +struct davinci_mmc { + struct davinci_mmc_regs *reg_base; /* Register base address */ + uint input_clk; /* Input clock to MMC controller */ + uint host_caps; /* Host capabilities */ + uint voltages; /* Host supported voltages */ + uint version; /* MMC Controller version */ +}; + +enum { + MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ + MMC_CTLR_VERSION_2, /* DA830 */ +}; + +int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host); + +#endif /* _SDMMC_DEFS_H */ diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 68afd30..3496f0a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libmmc.o COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o +COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o COBJS-$(CONFIG_GENERIC_MMC) += mmc.o COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c new file mode 100644 index 0000000..4e572dc --- /dev/null +++ b/drivers/mmc/davinci_mmc.c @@ -0,0 +1,404 @@ +/* + * Davinci MMC Controller Driver + * + * Copyright (C) 2010 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include <mmc.h> +#include <part.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/sdmmc_defs.h> + +#define DAVINCI_MAX_BLOCKS (32) +#define WATCHDOG_COUNT (100000) + +#define get_val(addr) REG(addr) +#define set_val(addr, val) REG(addr) = (val) +#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val))) +#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val))) + +/* Set davinci clock prescalar value based on the required clock in HZ */ +static void dmmc_set_clock(struct mmc *mmc, uint clock) +{ + struct davinci_mmc *host = mmc->priv; + struct davinci_mmc_regs *regs = host->reg_base; + uint clkrt, sysclk2, act_clock; + + if (clock < mmc->f_min) + clock = mmc->f_min; + if (clock > mmc->f_max) + clock = mmc->f_max; + + set_val(&regs->mmcclk, 0); + sysclk2 = host->input_clk; + clkrt = (sysclk2 / (2 * clock)) - 1; + + /* Calculate the actual clock for the divider used */ + act_clock = (sysclk2 / (2 * (clkrt + 1))); + + /* Adjust divider if actual clock exceeds the required clock */ + if (act_clock > clock) + clkrt++; + + /* check clock divider boundary and correct it */ + if (clkrt > 0xFF) + clkrt = 0xFF; + + set_val(&regs->mmcclk, (clkrt | MMCCLK_CLKEN)); +} + +/* Status bit wait loop for MMCST1 */ +static int +dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) +{ + uint mmcstatus1, wdog = WATCHDOG_COUNT; + mmcstatus1 = get_val(&regs->mmcst1); + while (--wdog && ((get_val(&regs->mmcst1) & status) != status)) + udelay(10); + + if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT)) + udelay(100); + + if (wdog == 0) + return COMM_ERR; + + return 0; +} + +/* Busy bit wait loop for MMCST1 */ +static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) +{ + uint mmcstatus1, wdog = WATCHDOG_COUNT; + + mmcstatus1 = get_val(&regs->mmcst1); + while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY)) + udelay(10); + + if (wdog == 0) + return COMM_ERR; + + return 0; +} + +/* Status bit wait loop for MMCST0 - Checks for error bits as well */ +static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, + uint *cur_st, uint st_ready, uint st_error) +{ + uint wdog = WATCHDOG_COUNT; + uint mmcstatus = *cur_st; + + while (wdog--) { + if (mmcstatus & st_ready) { + *cur_st = mmcstatus; + mmcstatus = get_val(&regs->mmcst1); + return 0; + } else if (mmcstatus & st_error) { + if (mmcstatus & MMCST0_TOUTRS) + return TIMEOUT; + printf("[ ST0 ERROR %x]\n", mmcstatus); + /* + * Ignore CRC errors as some MMC cards fail to + * initialize on DM365-EVM on the SD1 slot + */ + if (mmcstatus & MMCST0_CRCRS) + return 0; + return COMM_ERR; + } + udelay(10); + + mmcstatus = get_val(&regs->mmcst0); + } + + printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, + get_val(&regs->mmcst1)); + return COMM_ERR; +} + +/* + * Sends a command out on the bus. Takes the mmc pointer, + * a command pointer, and an optional data pointer. + */ +static int +dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + struct davinci_mmc *host = mmc->priv; + volatile struct davinci_mmc_regs *regs = host->reg_base; + uint mmcstatus, status_rdy, status_err; + uint i, cmddata, bytes_left = 0; + int fifo_words, fifo_bytes, err; + char *data_buf = NULL; + + /* Clear status registers */ + mmcstatus = get_val(&regs->mmcst0); + fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8; + fifo_bytes = fifo_words << 2; + + /* Wait for any previous busy signal to be cleared */ + dmmc_busy_wait(regs); + + cmddata = cmd->cmdidx; + cmddata |= MMCCMD_PPLEN; + + /* Send init clock for CMD0 */ + if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE) + cmddata |= MMCCMD_INITCK; + + switch (cmd->resp_type) { + case MMC_RSP_R1b: + cmddata |= MMCCMD_BSYEXP; + /* Fall-through */ + case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */ + cmddata |= MMCCMD_RSPFMT_R1567; + break; + case MMC_RSP_R2: + cmddata |= MMCCMD_RSPFMT_R2; + break; + case MMC_RSP_R3: /* R3, R4 */ + cmddata |= MMCCMD_RSPFMT_R3; + break; + } + + set_val(&regs->mmcim, 0); + + if (data) { + /* clear previous data transfer if any and set new one */ + bytes_left = (data->blocksize * data->blocks); + + /* Reset FIFO - Always use 32 byte fifo threshold */ + set_val(&regs->mmcfifoctl, + (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); + + if (host->version == MMC_CTLR_VERSION_2) + cmddata |= MMCCMD_DMATRIG; + + cmddata |= MMCCMD_WDATX; + if (data->flags == MMC_DATA_READ) { + set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV); + } else if (data->flags == MMC_DATA_WRITE) { + set_val(&regs->mmcfifoctl, + (MMCFIFOCTL_FIFOLEV | + MMCFIFOCTL_FIFODIR)); + cmddata |= MMCCMD_DTRW; + } + + set_val(&regs->mmctod, 0xFFFF); + set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK)); + set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK)); + + if (data->flags == MMC_DATA_WRITE) { + uint val; + data_buf = (char *)data->src; + /* For write, fill FIFO with data before issue of CMD */ + for (i = 0; (i < fifo_words) && bytes_left; i++) { + memcpy((char *)&val, data_buf, 4); + set_val(&regs->mmcdxr, val); + data_buf += 4; + bytes_left -= 4; + } + } + } else { + set_val(&regs->mmcblen, 0); + set_val(&regs->mmcnblk, 0); + } + + set_val(&regs->mmctor, 0x1FFF); + + /* Send the command */ + set_val(&regs->mmcarghl, cmd->cmdarg); + set_val(&regs->mmccmd, cmddata); + + status_rdy = MMCST0_RSPDNE; + status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD | + MMCST0_CRCWR | MMCST0_CRCRD); + if (cmd->resp_type & MMC_RSP_CRC) + status_err |= MMCST0_CRCRS; + + mmcstatus = get_val(&regs->mmcst0); + err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err); + if (err) + return err; + + /* For R1b wait for busy done */ + if (cmd->resp_type == MMC_RSP_R1b) + dmmc_busy_wait(regs); + + /* Collect response from controller for specific commands */ + if (mmcstatus & MMCST0_RSPDNE) { + /* Copy the response to the response buffer */ + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = get_val(&regs->mmcrsp67); + cmd->response[1] = get_val(&regs->mmcrsp45); + cmd->response[2] = get_val(&regs->mmcrsp23); + cmd->response[3] = get_val(&regs->mmcrsp01); + } else if (cmd->resp_type & MMC_RSP_PRESENT) { + cmd->response[0] = get_val(&regs->mmcrsp67); + } + } + + if (data == NULL) + return 0; + + if (data->flags == MMC_DATA_READ) { + /* check for DATDNE along with DRRDY as the controller might + * set the DATDNE without DRRDY for smaller transfers with + * less than FIFO threshold bytes + */ + status_rdy = MMCST0_DRRDY | MMCST0_DATDNE; + status_err = MMCST0_TOUTRD | MMCST0_CRCRD; + data_buf = data->dest; + } else { + status_rdy = MMCST0_DXRDY | MMCST0_DATDNE; + status_err = MMCST0_CRCWR; + } + + /* Wait until all of the blocks are transferred */ + while (bytes_left) { + err = dmmc_check_status(regs, &mmcstatus, status_rdy, + status_err); + if (err) + return err; + + if (data->flags == MMC_DATA_READ) { + /* + * MMC controller sets the Data receive ready bit + * (DRRDY) in MMCST0 even before the entire FIFO is + * full. This results in erratic behavior if we start + * reading the FIFO soon after DRRDY. Wait for the + * FIFO full bit in MMCST1 for proper FIFO clearing. + */ + if (bytes_left > fifo_bytes) + dmmc_wait_fifo_status(regs, 0x4a); + else if (bytes_left == fifo_bytes) + dmmc_wait_fifo_status(regs, 0x40); + + for (i = 0; bytes_left && (i < fifo_words); i++) { + cmddata = get_val(&regs->mmcdrr); + memcpy(data_buf, (char *)&cmddata, 4); + data_buf += 4; + bytes_left -= 4; + } + } else { + /* + * MMC controller sets the Data transmit ready bit + * (DXRDY) in MMCST0 even before the entire FIFO is + * empty. This results in erratic behavior if we start + * writing the FIFO soon after DXRDY. Wait for the + * FIFO empty bit in MMCST1 for proper FIFO clearing. + */ + dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP); + for (i = 0; bytes_left && (i < fifo_words); i++) { + memcpy((char *)&cmddata, data_buf, 4); + set_val(&regs->mmcdxr, cmddata); + data_buf += 4; + bytes_left -= 4; + } + dmmc_busy_wait(regs); + } + } + + err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err); + if (err) + return err; + + return 0; +} + +/* Initialize Davinci MMC controller */ +static int dmmc_init(struct mmc *mmc) +{ + struct davinci_mmc *host = mmc->priv; + struct davinci_mmc_regs *regs = host->reg_base; + + /* Clear status registers explicitly - soft reset doesn't clear it + * If Uboot is invoked from UBL with SDMMC Support, the status + * registers can have uncleared bits + */ + get_val(&regs->mmcst0); + get_val(&regs->mmcst1); + + /* Hold software reset */ + set_bit(&regs->mmcctl, MMCCTL_DATRST); + set_bit(&regs->mmcctl, MMCCTL_CMDRST); + udelay(10); + + set_val(&regs->mmcclk, 0x0); + set_val(&regs->mmctor, 0x1FFF); + set_val(&regs->mmctod, 0xFFFF); + + /* Clear software reset */ + clear_bit(&regs->mmcctl, MMCCTL_DATRST); + clear_bit(&regs->mmcctl, MMCCTL_CMDRST); + + udelay(10); + + /* Reset FIFO - Always use the maximum fifo threshold */ + set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST)); + set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV); + + return 0; +} + +/* Set buswidth or clock as indicated by the GENERIC_MMC framework */ +static void dmmc_set_ios(struct mmc *mmc) +{ + struct davinci_mmc *host = mmc->priv; + struct davinci_mmc_regs *regs = host->reg_base; + + /* Set the bus width */ + if (mmc->bus_width == 4) + set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT); + else + clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT); + + /* Set clock speed */ + if (mmc->clock) + dmmc_set_clock(mmc, mmc->clock); +} + +/* Called from board_mmc_init during startup. Can be called multiple times + * depending on the number of slots available on board and controller + */ +int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) +{ + struct mmc *mmc; + + mmc = malloc(sizeof(struct mmc)); + memset(mmc, 0, sizeof(struct mmc)); + + sprintf(mmc->name, "davinci"); + mmc->priv = host; + mmc->send_cmd = dmmc_send_cmd; + mmc->set_ios = dmmc_set_ios; + mmc->init = dmmc_init; + + mmc->f_min = 200000; + mmc->f_max = 25000000; + mmc->voltages = host->voltages; + mmc->host_caps = host->host_caps; + +#ifdef CONFIG_MMC_MBLOCK + mmc->b_max = DAVINCI_MAX_BLOCKS; +#endif + mmc_register(mmc); + + return 0; +} + -- 1.6.0.4

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