October 2010 - U-Boot

[U-Boot] Sam9g45 USB CDC
by Marcel 09 Oct '10

09 Oct '10

Hi, It looks like I've got most thing implemented regarding USB CDC for the Sam9g45. I do however have some basic questions. One of the things is that I don't see any descriptors in Windows. I installed some inf file found on the net for Ethernet RNDIS but maybe that was wrong. Is there any Windows driver available for the Linux CDC interface ? Second I connected the device to my Linux host and dmesg says looks a bit better : usb 1-4: USB disconnect, address 39 usb 1-4: new high speed USB device using ehci_hcd and address 40 usb 1-4: New USB device found, idVendor=0525, idProduct=a4a1 usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=0 usb 1-4: Product: Ethernet Gadget usb 1-4: Manufacturer: Atmel AT91SAM9G45 usb 1-4: configuration #1 chosen from 1 choice lusb output is shown below. I see the following line : iMacAddress 3 (??) Is this normal or did I perhaps miss something crucial here ? One thing I notice is that things are rather slow in Linux and probably also the reason why things don't work in windows yet. It takes a couple of seconds for lsusb to show information and my guess is that still something is wrong. Best regards, Marcel $lsusb -v -d 0525:a4a1 Bus 001 Device 036: ID 0525:a4a1 Netchip Technology, Inc. Linux-USB Ethernet Gadget Device Descriptor: bLength 18 bDescriptorType 1 bcdUSB 2.00 bDeviceClass 2 Communications bDeviceSubClass 0 bDeviceProtocol 0 bMaxPacketSize0 64 idVendor 0x0525 Netchip Technology, Inc. idProduct 0xa4a1 Linux-USB Ethernet Gadget bcdDevice 3.18 iManufacturer 1 iProduct 2 iSerial 0 bNumConfigurations 1 Configuration Descriptor: bLength 9 bDescriptorType 2 wTotalLength 80 bNumInterfaces 2 bConfigurationValue 1 iConfiguration 7 bmAttributes 0xc0 Self Powered MaxPower 2mA Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 0 bAlternateSetting 0 bNumEndpoints 1 bInterfaceClass 2 Communications bInterfaceSubClass 6 Ethernet Networking bInterfaceProtocol 0 iInterface 5 CDC Header: bcdCDC 1.10 CDC Union: bMasterInterface 0 bSlaveInterface 1 CDC Ethernet: iMacAddress 3 (??) bmEthernetStatistics 0x00000000 wMaxSegmentSize 1536 wNumberMCFilters 0x0000 bNumberPowerFilters 0 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x83 EP 3 IN bmAttributes 3 Transfer Type Interrupt Synch Type None Usage Type Data wMaxPacketSize 0x0010 1x 16 bytes bInterval 9 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 1 bAlternateSetting 0 bNumEndpoints 0 bInterfaceClass 10 CDC Data bInterfaceSubClass 0 Unused bInterfaceProtocol 0 iInterface 0 Interface Descriptor: bLength 9 bDescriptorType 4 bInterfaceNumber 1 bAlternateSetting 1 bNumEndpoints 2 bInterfaceClass 10 CDC Data bInterfaceSubClass 0 Unused bInterfaceProtocol 0 iInterface 4 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x81 EP 1 IN bmAttributes 2 Transfer Type Bulk Synch Type None Usage Type Data wMaxPacketSize 0x0200 1x 512 bytes bInterval 0 Endpoint Descriptor: bLength 7 bDescriptorType 5 bEndpointAddress 0x02 EP 2 OUT bmAttributes 2 Transfer Type Bulk Synch Type None Usage Type Data wMaxPacketSize 0x0200 1x 512 bytes bInterval 0 can't get device qualifier: Connection timed out can't get debug descriptor: Connection timed out cannot read device status, Connection timed out (110)

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[U-Boot] NAND on AVR32
by David Collier 09 Oct '10

09 Oct '10

Apologies if this is a double -post - I didn't get it back in my feed from the mailing list.... maybe it is awaiting approval or something. But I'm off on holiday, and I'd really like it to be "out there" ----------------------------------------------------------------- I thought the whole point of using this linux and u-boot stuff was that whatever you did, someone else had done it first and you just had to copy them. Well I've been caught out Smile I want to ditch using the uSD card at all on our AVR32 board , and use NAND where we have been using uSD. I have a Linux disk working out of NAND - quite easy as Linux pretty much knew how, once you told it you had a chip. But the u-boot seems to have no clue about NAND on the AVR32 - it doesn't set up the hardware to get to it at all, and there's no code set up in the target board header and code files for any AVR32-based board, as far as I can see!!! I have found some stuff in support for other Atmel devices, which seems relevant. Plus of course the Linux sources. I'm totally in the dark about what u-boot can or should do with ecc ..... ------------ So far I've worked out that I've got to 1. in cpu.c add set up MODE3, CYCLE3, SETUP3, PULSE3 registers for cs3 timing. 2. in <target>.c/board_early_init_f add hmatrix_slave_write call to enable nand in ebi 3. in <target>.c/board_early_init_f set up chip select(s) and busy(s) in the GPIO setup to point the right way, and initially turn everything off 4 in <target>.h #undef CONFIG_NAND_LEGACY #define CONFIG_CMD_NAND #define CONFIG_JFFS2_NAND #define CFG_MAX_NAND_DEVICE #define NAND_MAX_CHIPS #define CFG_NAND_BASE 0x0c000000 I'm still pretty woolly about these though CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MTD_PARTITIONS 5. create a file called nand.c in the same directory as my <target>.c - I've based mine on the one for the at91sam9261ek. This needs to implement board_nand_init which must set up service routines cmd_ctrl to alter ALE,CLE etc dev_ready to read the "chip ready" status chip_delay - no idea! so far I've no clue how this file gets included in the make of u-boot. Any and all advice welcome - especially if someone HAS got there first. TVM David

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[U-Boot] ARMV7: OMAP4: Implement relocation for Panda and OMAP4430SDP
by Steve Sakoman 08 Oct '10

08 Oct '10

This patch fixes the build breakage introduced by the recent relocation changes for ARMV7 Signed-off-by: Steve Sakoman <steve(a)sakoman.com> --- diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index 8c1f395..24a66f5 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -102,8 +102,13 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) gd->bd->bi_dram[0].start = 0x80000000; gd->bd->bi_dram[0].size = sdram_size(); +#else + gd->ram_size = sdram_size(); +#endif + return 0; } diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk index 7382263..7176c14 100644 --- a/board/ti/panda/config.mk +++ b/board/ti/panda/config.mk @@ -27,6 +27,4 @@ # 8000'0000 - 9fff'ffff (512 MB) # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 # (mem base + reserved) - -# Let's place u-boot 1MB before the end of SDRAM. -TEXT_BASE = 0x9ff00000 +TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk index 7382263..7bb9473 100644 --- a/board/ti/sdp4430/config.mk +++ b/board/ti/sdp4430/config.mk @@ -28,5 +28,4 @@ # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 # (mem base + reserved) -# Let's place u-boot 1MB before the end of SDRAM. -TEXT_BASE = 0x9ff00000 +TEXT_BASE = 0x80e80000 diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 2618f7d..b52ca19 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -139,12 +139,6 @@ #undef CONFIG_CMD_IMLS /* List all found images */ /* - * Enabling relocation of u-boot by default - * Relocation can be skipped if u-boot is copied to the TEXT_BASE - */ -#undef CONFIG_SKIP_RELOCATE_UBOOT - -/* * Environment setup */ @@ -233,4 +227,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 8274577..174d73f 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -144,12 +144,6 @@ #undef CONFIG_CMD_IMLS /* List all found images */ /* - * Enabling relocation of u-boot by default - * Relocation can be skipped if u-boot is copied to the TEXT_BASE - */ -#undef CONFIG_SKIP_RELOCATE_UBOOT - -/* * Environment setup */ @@ -238,4 +232,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */

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[U-Boot] MPC8377 system bring up
by André Schwarz 08 Oct '10

08 Oct '10

Kim, Timur, we got a new board out of production these days. It's a MPC8377 based system with PCI/PCIe peripherals and Nor+Nand-Flash on LocalBus ... nothing special. Nevertheless I need a little help. No basic errors so far, i.e. power, clocks and reset are working fine. Made a new Board definition (U-Boot top-of-tree) by copying the MPC837xERDB.h config file. Changes I've done : - completely removed VSC7385 stuff (also at BAT3). - removed PCISLAVE stuff since this is host only. - removed TSEC2 from HRCWH since there's only TSEC1. - CONFIG_SYS_FLASH_BASE = 0xFC000000 since we have 64MiB Nor (S29GL512 in 16-Bit mode). - Adjusted TEXT_BASE to 0xFC000000 - BAT4 size changed to BATU_BL_64M. - removed Date and RTC stuff. Compilation works fine and HRCW generation yields 0xa0606002 0x25040000 which looks sane to me. I'm working with bdi2000 and started with MPC8377E-RDB.cfg ... my mods are : - changed LBLAWBAR0 to 0xfc000000 and size 64MiB. - changed OR0/BRO to also match 0xfc000000. - HRCW override ti above values. - Flash size and IP stuff. I can access RAM and whole 64MiB flash without problems. Programming U-Boot @ 0xfc000000 works fine as well as a verification after power cycling the board. Removing the bdi2000, connecting RS-232 and restarting the board yields nothing. No activities ... not even an assertion of ~LCS0. Of course the CFG_RESET_SOURCE is 0b0000 which indicates "Boot from Nor". I'd at least expect a few cycles for HRCW fetch ... hmmm. Are there any obvious issues I have missed so far ? Reagrds, André MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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[U-Boot] [PATCH] Crash in env_relocate_spec() of env_mmc.c
by Stefano Babic 08 Oct '10

08 Oct '10

mmc_initialize is not called at the startup if the relocation takes place and the environment is stored into a MMC card. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/lib/board.c | 10 +++++----- common/env_mmc.c | 11 +++++------ 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 5f2dfd0..704ddcb 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -775,6 +775,11 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif +#ifdef CONFIG_GENERIC_MMC + puts ("MMC: "); + mmc_initialize (bd); +#endif + #if defined(CONFIG_CMD_ONENAND) onenand_init(); #endif @@ -854,11 +859,6 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); board_late_init (); #endif -#ifdef CONFIG_GENERIC_MMC - puts ("MMC: "); - mmc_initialize (gd->bd); -#endif - #ifdef CONFIG_BITBANGMII bb_miiphy_init(); #endif diff --git a/common/env_mmc.c b/common/env_mmc.c index 14203b6..cb7c448 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -130,24 +130,23 @@ void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + char buf[CONFIG_ENV_SIZE]; if (init_mmc_for_env(mmc)) return; - if (read_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, env_ptr)) - return use_default(); - - if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) + if (read_env(mmc, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) return use_default(); gd->env_valid = 1; + + env_import(buf, 1); #endif } #if !defined(ENV_IS_EMBEDDED) static void use_default() { - puts ("*** Warning - bad CRC or MMC, using default environment\n\n"); - set_default_env(); + set_default_env("*** Warning - bad CRC or MMC, using default environment\n\n"); } #endif -- 1.6.3.3

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[U-Boot] [PATCH] Adding fixed sdram setting for cornet_ds board
by York Sun 08 Oct '10

08 Oct '10

800, 900, 1000, 1200MT/s data rate parameters are added for fixed sdram setting. SPD based parameters and fixed parameters can be toggled by hwconfig. To use fixed parameters, hwconfig=fsl_ddr:sdram=fixed To use SPD parameters, hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1 Signed-off-by: York Sun <yorksun(a)freescale.com> --- board/freescale/corenet_ds/corenet_ds.c | 15 -- board/freescale/corenet_ds/ddr.c | 315 ++++++++++++++++++++++++++++++- include/configs/corenet_ds.h | 57 ------ 3 files changed, 314 insertions(+), 73 deletions(-) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 1107743..b5a1332 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -29,7 +29,6 @@ #include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_law.h> -#include <asm/fsl_ddr_sdram.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> #include <asm/fsl_liodn.h> @@ -239,20 +238,6 @@ int misc_init_r(void) return 0; } -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - - setup_ddr_tlbs(dram_size / 0x100000); - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_MP void board_lmb_reserve(struct lmb *lmb) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index ce87b56..d387a92 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -8,9 +8,289 @@ #include <common.h> #include <i2c.h> - +#include <hwconfig.h> +#include <asm/mmu.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); + +#define CONFIG_SYS_SDRAM_SIZE 4096 + +#define DATARATE_800MHZ 800000000 +#define DATARATE_900MHZ 900000000 +#define DATARATE_1000MHZ 1000000000 +#define DATARATE_1200MHZ 1200000000 + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + if (sysinfo.freqDDRBus <= DATARATE_800MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_900MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_900, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_1000MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_1000, sizeof(ddr_cfg_regs)); + else if (sysinfo.freqDDRBus <= DATARATE_1200MHZ) + memcpy(&ddr_cfg_regs, &ddr_cfg_regs_1200, sizeof(ddr_cfg_regs)); + else + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, sysinfo.freqDDRBus)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS; + ddr_cfg_regs.cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS; + ddr_cfg_regs.cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS; + ddr_cfg_regs.cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS; + ddr_cfg_regs.cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG; + ddr_cfg_regs.cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG; + ddr_cfg_regs.cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG; + ddr_cfg_regs.cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (CONFIG_SYS_DDR_CS0_CONFIG & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + lawbar1_target_id = LAW_TRGT_IF_DDR_2; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2, + ddr_size / 2, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } + return ddr_size; +} static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -168,3 +448,36 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Enable ZQ calibration */ popts->zq_en = 1; } + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + int use_spd = 0; + + puts("Initializing...."); + + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub("fsl_ddr", "sdram")) { + if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) + use_spd = 1; + else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; + + if (use_spd) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 0a0e1e8..6ac35d3 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -134,63 +134,6 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 -#else -#define CONFIG_SYS_SDRAM_SIZE 4096 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x01031000 -#define CONFIG_SYS_DDR_TIMING_0 0x55440804 -#define CONFIG_SYS_DDR_TIMING_1 0x74713a66 -#define CONFIG_SYS_DDR_TIMING_2 0x0fb8911b -#define CONFIG_SYS_DDR_MODE_1 0x00421850 -#define CONFIG_SYS_DDR_MODE_2 0x00100000 -#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x10400100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03401500 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655a608 -#define CONFIG_SYS_DDR_CONTROL 0xc7048000 -#define CONFIG_SYS_DDR_CONTROL2 0x24400011 -#define CONFIG_SYS_DDR_CDR1 0x00000000 -#define CONFIG_SYS_DDR_CDR2 0x00000000 -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 -#define CONFIG_SYS_DDR_DEBUG_18 0x40100400 - -#define CONFIG_SYS_DDR2_CS0_BNDS 0x008000bf -#define CONFIG_SYS_DDR2_CS1_BNDS 0x00C000ff -#define CONFIG_SYS_DDR2_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG -#define CONFIG_SYS_DDR2_CS1_CONFIG CONFIG_SYS_DDR_CS1_CONFIG -#define CONFIG_SYS_DDR2_TIMING_3 CONFIG_SYS_DDR_TIMING_3 -#define CONFIG_SYS_DDR2_TIMING_0 CONFIG_SYS_DDR_TIMING_0 -#define CONFIG_SYS_DDR2_TIMING_1 CONFIG_SYS_DDR_TIMING_1 -#define CONFIG_SYS_DDR2_TIMING_2 CONFIG_SYS_DDR_TIMING_2 -#define CONFIG_SYS_DDR2_MODE_1 CONFIG_SYS_DDR_MODE_1 -#define CONFIG_SYS_DDR2_MODE_2 CONFIG_SYS_DDR_MODE_2 -#define CONFIG_SYS_DDR2_MODE_CTRL CONFIG_SYS_DDR_MODE_CTRL -#define CONFIG_SYS_DDR2_INTERVAL CONFIG_SYS_DDR_INTERVAL -#define CONFIG_SYS_DDR2_DATA_INIT CONFIG_SYS_DDR_DATA_INIT -#define CONFIG_SYS_DDR2_CLK_CTRL CONFIG_SYS_DDR_CLK_CTRL -#define CONFIG_SYS_DDR2_TIMING_4 CONFIG_SYS_DDR_TIMING_4 -#define CONFIG_SYS_DDR2_TIMING_5 CONFIG_SYS_DDR_TIMING_5 -#define CONFIG_SYS_DDR2_ZQ_CNTL CONFIG_SYS_DDR_ZQ_CNTL -#define CONFIG_SYS_DDR2_WRLVL_CNTL CONFIG_SYS_DDR_WRLVL_CNTL -#define CONFIG_SYS_DDR2_CONTROL CONFIG_SYS_DDR_CONTROL -#define CONFIG_SYS_DDR2_CONTROL2 CONFIG_SYS_DDR_CONTROL2 -#define CONFIG_SYS_DDR2_CDR1 CONFIG_SYS_DDR_CDR1 -#define CONFIG_SYS_DDR2_CDR2 CONFIG_SYS_DDR_CDR2 -#define CONFIG_SYS_DDR2_ERR_INT_EN CONFIG_SYS_DDR_ERR_INT_EN -#define CONFIG_SYS_DDR2_ERR_DIS CONFIG_SYS_DDR_ERR_DIS -#define CONFIG_SYS_DDR2_SBE CONFIG_SYS_DDR_SBE -#define CONFIG_SYS_DDR2_DEBUG_18 CONFIG_SYS_DDR_DEBUG_18 - #endif /* -- 1.7.0.4

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[U-Boot] Crash in env_relocate_spec() of env_mmc.c
by Steve Sakoman 08 Oct '10

08 Oct '10

I've been attempting to get the OMAP4 boards working post the ARM relocation changes. Panda was simple. The OMAP4430SDP is proving to be more challenging, as it freezes after printing the DRAM size message. Adding a few printfs revealed that the crash occurs in env_mmc.c's env_relocate_spec() routine. Has anyone else run into this issue? Any advice? Steve

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[U-Boot] Question about PCIe configuration
by Carlos Roberto Moratelli 08 Oct '10

08 Oct '10

Hi, I am trying to map a PCIe peripherical on my MPC8536 custom board. I already have u-boot and linux kernel running fine on this board. The peripherical is on PCIe1 port. Compiling u-boot using debug flag I have the following log: pci_init_board: devdisr=40900, sdrs2_io_sel=7, io_sel=7 Serdes2 disalbed PCIE3: disabled PCIE1: disabled PCIE2: disabled PCI: 32 bit, 66 MHz, sync, host, arbiter (base address ffe08000) with errors. Clearing. Now 0x0b200091Outbound memory range: f0000000:100000000 PCICSRBAR @ 0xeff00000 R0 bus_start: 0 phys_start: 0 size: 8000000 R64 bus_start: 1000000000 phys_start: 0 size: 8000000 PCI reg:0 0000000c00000000:00000000f0000000 0000000010000000 00000000 PCI reg:1 0000000fffc00000:0000000000000000 0000000000010000 00000001 PCI reg:2 0000000fffe00000:00000000eff00000 0000000000100000 00000100 PCI reg:3 0000000000000000:0000000000000000 0000000008000000 00000108 PCI reg:4 0000000000000000:0000001000000000 0000000008000000 00000108 Scanning PCI bus 00 PCIE1 on bus 00 - 00 Running pci command I can see: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1957 0x0050 Processor 0x20 I don't know if I am correct, but I understand that the PCIe controller identify itself. However, the PCIe peripherical was not found. Bellow, the default PCIe1 configuration to MPC8536DS target. Could something in this configuration prevent the PCIe peripherical to be found? I have CONFIG_PHYS_64BIT enabled. /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull #else #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ Thank you. Carlos R. Moratelli

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[U-Boot] u-boot vs. Cavium 5010 pci init
by sywang 08 Oct '10

08 Oct '10

Hello, everyone, Do you know what bugs or problems there are on u-boot with Cavium CN5010 PCI init? Now I have the following on the board with Cavium CN5010. The board will hang when PCI init with the U-boot. Any suggestions are welcome. How to identify if the issue's cause is HW or SW? Thanks! Shuyou

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[U-Boot] [PATCH] include/compiler.h: remove uint typedef for __MACH__
by Andreas Bießmann 08 Oct '10

08 Oct '10

uint is typedefed twice if __MACH__ is defined. This generates an error when calling MAKEALL for netstar bord on OS X. This patch removes the typedef for __MACH__ case in favor of general definiton some lines below. Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- include/compiler.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/compiler.h b/include/compiler.h index 23f4b83..91dbe56 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -47,7 +47,6 @@ #elif defined(__MACH__) # include <machine/endian.h> typedef unsigned long ulong; -typedef unsigned int uint; #endif typedef uint8_t __u8; -- 1.7.3

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