October 2010 - U-Boot

[U-Boot] [PATCH] da850evm: basic MII EMAC support
by Ben Gardiner 12 Oct '10

12 Oct '10

The current da850evm support in u-boot/master [1] omits any use of the davinci EMAC. This patch adds basic support for the EMAC using the MII PHY found on the baseboard of the EVM. The MAC address is read from the environment variable 'ethadd'. Note that this is different from the da850evm support in the u-boot omapl1 tree where the MAC address is read from SPI flash [2]. CC: Sandeep Paulraj <s-paulraj(a)ti.com> CC: Sudhakar Rajashekhara <sudhakar.raj(a)ti.com> [1] http://git.denx.de/?p=u-boot.git [2] http://arago-project.org/git/projects/?p=u-boot-omapl1.git --- I am submitting this patch for inclusion in v2010.12, not v2010.09 since it introduces a new feature. --- board/davinci/da8xxevm/da850evm.c | 60 +++++++++++++++++++++++++++++++++++++ include/configs/da850evm.h | 15 +++++++++ 2 files changed, 75 insertions(+), 0 deletions(-) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index eeb456c..30645e5 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -23,7 +23,11 @@ #include <common.h> #include <i2c.h> +#include <net.h> +#include <netdev.h> #include <asm/arch/hardware.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> #include <asm/io.h> #include "../common/misc.h" #include "common.h" @@ -48,6 +52,28 @@ static const struct pinmux_config uart_pins[] = { { pinmux(4), 2, 5 } }; +#ifdef CONFIG_DRIVER_TI_EMAC +const struct pinmux_config emac_pins[] = { + { pinmux(2), 8, 1 }, + { pinmux(2), 8, 2 }, + { pinmux(2), 8, 3 }, + { pinmux(2), 8, 4 }, + { pinmux(2), 8, 5 }, + { pinmux(2), 8, 6 }, + { pinmux(2), 8, 7 }, + { pinmux(3), 8, 0 }, + { pinmux(3), 8, 1 }, + { pinmux(3), 8, 2 }, + { pinmux(3), 8, 3 }, + { pinmux(3), 8, 4 }, + { pinmux(3), 8, 5 }, + { pinmux(3), 8, 6 }, + { pinmux(3), 8, 7 }, + { pinmux(4), 8, 0 }, + { pinmux(4), 8, 1 } +}; +#endif /* CONFIG_DRIVER_TI_EMAC */ + /* I2C pin muxer settings */ static const struct pinmux_config i2c_pins[] = { { pinmux(4), 2, 2 }, @@ -102,6 +128,14 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; +#ifdef CONFIG_DRIVER_TI_EMAC + if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) + return 1; + /* set cfgchip3 to select MII */ + writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8), + &davinci_syscfg_regs->cfgchip3); +#endif /* CONFIG_DRIVER_TI_EMAC */ + /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), @@ -109,3 +143,29 @@ int board_init(void) return 0; } + +#ifdef CONFIG_DRIVER_TI_EMAC + +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + u_int8_t mac_addr[6]; + + /* read the address from env */ + if (!eth_getenv_enetaddr("ethaddr", mac_addr)) + return -1; + + /* provide the resulting addr to the driver */ + davinci_eth_set_mac_addr(mac_addr); + + /* finally, initialise the driver */ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 357715d..432c5e6 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -26,6 +26,7 @@ /* * Board */ +#define CONFIG_DRIVER_TI_EMAC /* * SoC Configuration @@ -79,6 +80,20 @@ #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* + * Network & Ethernet Configuration + */ +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONFIG_EMAC_MDIO_PHY_NUM 0 +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI +#endif + +/* * U-Boot general configuration */ #define CONFIG_BOOTFILE "uImage" /* Boot file name */ -- 1.7.0.4

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[U-Boot] [PATCH] mpc5xxx_fec: add call to reset_phy() after PHY initialization
by Ilya Yanok 12 Oct '10

12 Oct '10

Some boards need their board-specific PHY quirks to be called to PHY to work normally. As mpc5xxx_fec driver uses on demand PHY initialization and can even reinit PHY during normal operation we can't count on reset_phy() call from arch/<arch>/lib/board.c (it is most likely called _before_ we init the PHY from the driver) so we need to add call to reset_phy() directly in the driver. Cc: Ben Warren <biggerbadderben(a)gmail.com> Signed-off-by: Ilya Yanok <yanok(a)emcraft.com> --- drivers/net/mpc5xxx_fec.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index c88e596..bc8c922 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -250,6 +250,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) mpc5xxx_fec_init_phy(dev, bis); /* + * Call board-specific PHY fixups (if any) + */ +#ifdef CONFIG_RESET_PHY_R + reset_phy(); +#endif + + /* * Initialize RxBD/TxBD rings */ mpc5xxx_fec_rbd_init(fec); -- 1.6.2.5

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[U-Boot] Driver for RTC (PT7C4338) chip
by Jain Priyanka-B32167 12 Oct '10

12 Oct '10

Hi, One of our board has PT7C4338 (Pericom Technology Inc.) as RTC chip. Does anyone has any idea if u-boot has support for this chip? If yes, what is the location of this RTC driver in u-boot? Thanks alot Priyanka

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[U-Boot] [PATCH V2 1/3] Kirkwood: dram_init is moved to dram.c
by Prafulla Wadaskar 12 Oct '10

12 Oct '10

For all Kirkwood boards so far dram_init function is duplicated dram_init function is moved to dram.c and relevant code from all board specific files removed If any board needs specific dram init handling than standard one, then, a macro CONFIG_SYS_BOARD_DRAM_INIT should be defined in board config header file and the dram_init function can be put in board specific source file For ex. keymile boards Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog v2: dram_init only performed for consecutive memory removed CONFIG_SYS_WITHOUT_RELOC dependency dram_init_banksize added to avoid re-configuration of dram bank 0 arch/arm/cpu/arm926ejs/kirkwood/dram.c | 38 +++++++++++++++++++++++ board/Marvell/guruplug/guruplug.c | 11 ------ board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 11 ------ board/Marvell/openrd_base/openrd_base.c | 11 ------ board/Marvell/rd6281a/rd6281a.c | 11 ------ board/Marvell/sheevaplug/sheevaplug.c | 11 ------ include/configs/keymile-common.h | 1 + 7 files changed, 39 insertions(+), 55 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 8f2a18a..cb29f97 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -23,8 +23,11 @@ */ #include <config.h> +#include <common.h> #include <asm/arch/kirkwood.h> +DECLARE_GLOBAL_DATA_PTR; + #define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) #define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) /* @@ -56,3 +59,38 @@ u32 kw_sdram_bs(enum memory_bank bank) result += 0x01000000; return result; } + +#ifndef CONFIG_SYS_BOARD_DRAM_INIT +int dram_init(void) +{ + int i; + + gd->ram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + /* + * It is assumed that all memory banks are consecutive + * and without gaps. + * If the gap is found, ram_size will be reported for + * consecutive memory only + */ + if (gd->bd->bi_dram[i].start != gd->ram_size) + break; + + gd->ram_size += gd->bd->bi_dram[i].size; + + } + return 0; +} + +/* + * If this function is not defined here, + * board.c alters dram bank zero configuration defined above. + */ +void dram_init_banksize(void) +{ + dram_init(); +} +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ + diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index c028a53..4df4e9b 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R void mv_phy_88e1121_init(char *name) { diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index c959bf8..93d1400 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -110,17 +110,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_MV88E61XX_SWITCH void reset_phy(void) { diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c index c00a08a..d006b2d 100644 --- a/board/Marvell/openrd_base/openrd_base.c +++ b/board/Marvell/openrd_base/openrd_base.c @@ -113,17 +113,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 8713a3c..0d76146 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -109,17 +109,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - void mv_phy_88e1116_init(char *name) { u16 reg; diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 547126a..173a7b8 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -108,17 +108,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = kw_sdram_bar(i); - gd->bd->bi_dram[i].size = kw_sdram_bs(i); - } - return 0; -} - #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 6c14ca0..62d21f6 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -85,6 +85,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */ /* * How to get access to the slot ID. Put this here to make it easy -- 1.5.3.3

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[U-Boot] [PATCH V3] orion5x: optimize window size computation
by Albert Aribaud 12 Oct '10

12 Oct '10

Signed-off-by: Chris Moore <moore(a)free.fr> Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- V1 Initial submission V2 Double Signed-off-by as requested V3 Fixed unit mistake and moved to standard units arch/arm/cpu/arm926ejs/orion5x/cpu.c | 32 +++++++++++++++++++++----------- 1 files changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 260f88b..22207cb 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -48,24 +48,34 @@ void reset_cpu(unsigned long ignored) } /* - * Window Size + * Compute Window Size field value from size expressed in bytes * Used with the Base register to set the address window size and location. * Must be programmed from LSB to MSB as sequence of ones followed by * sequence of zeros. The number of ones specifies the size of the window in - * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). - * NOTE: A value of 0x0 specifies 64-KByte size. + * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB). + * NOTES: + * 1) A sizeval equal to 0x0 specifies 4 GiB. + * 2) A return value of 0x0 specifies 64 KiB. */ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) { - int i; - unsigned int j = 0; - u32 val = sizeval >> 1; - - for (i = 0; val >= 0x10000; i++) { - j |= (1 << i); - val = val >> 1; - } - return 0x0000ffff & j; + /* + * Calculate the number of 64 KiB blocks needed minus one (rounding up). + * For sizeval > 0 this is equivalent to: + * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1 + */ + sizeval = (sizeval - 1) >> 16; + + /* + * Propagate 'one' bits to the right by 'oring' them. + * We need only treat bits 15-0. + */ + sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */ + sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */ + sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */ + sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/ + + return sizeval; } /* -- 1.7.0.4

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[U-Boot] [PATCH v2] Kirkwood: print_cpuinfo fixed for valid devid revid
by Prafulla Wadaskar 12 Oct '10

12 Oct '10

From: Prafulla Wadaskar <[prafulla(a)marvell.com]> Earlier Device Identification register was used to detect the type for SoC, considering 88F6282 support to be added, It is not possible to detect the same using current algorithm. With this patch, device ID is being read using PCIE devid register, also valid chip revision ID will also be read and displayed Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: v2: Updated as per review comments for V1 debug replaced by printf, sprintf removed (??) kept as it is since we dont know future references for revid arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 34 ++++++++++++++++++++--------- arch/arm/include/asm/arch-kirkwood/cpu.h | 2 + 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index 82c978b..b4a4c04 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -54,10 +54,11 @@ unsigned char get_random_hex(void) u8 outbuf[BUFLEN]; /* - * in case of 88F6281/88F6192 A0, + * in case of 88F6281/88F6282/88F6192 A0, * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 - * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and - * Does not have names at this moment (no errata available) + * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are + * reserved regs and does not have names at this moment + * (no errata available) */ writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); for (i = 0; i < BUFLEN; i++) { @@ -271,20 +272,31 @@ static void kw_sysrst_check(void) #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { - char *name = "Unknown"; + char *rev; + u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; + u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; - switch (readl(KW_REG_DEVICE_ID) & 0x03) { - case 1: - name = "88F6192_A0"; + if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + return -1; + } + + switch (revid) { + case 0: + rev = "Z0"; break; case 2: - name = "88F6281_A0"; + rev = "A0"; + break; + case 3: + rev = "A1"; break; default: - printf("SoC: Unsupported Kirkwood\n"); - return -1; + rev = "??"; + break; } - printf("SoC: Kirkwood %s\n", name); + + printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index b3022a3..d28c51a 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -35,6 +35,8 @@ #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) #define SYSRST_CNT_1SEC_VAL (25*1000000) -- 1.7.2.1

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[U-Boot] [PATCH V3] mvsata_ide: adjust port init sequence
by Albert Aribaud 12 Oct '10

12 Oct '10

mvsata_ide_initialize_port(): adjust init sequence (SStatus should be checked only after all writes to SControl) and return success/failure to ide_preinit(). Also, as some tests showed init durations in the hundreds of us, raise the time-out to 01 ms to be on the safe side. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- PATCH HISTORY V1 Initial patch. V2 Fixed wrong placement of comment. Fixed wrong description (was 01 ms, should have been 10). Added Signed-off-by. V3 Replaced return status values with symbolic names. Made error status values negative. Renamed 'tout' to 'timeleft' for clarity. Replaced ternary '?:' operator with '!' and if. Patch was run through checkscript.pl with 0 errors and warnings. drivers/block/mvsata_ide.c | 42 +++++++++++++++++++++++++++++++++--------- 1 files changed, 33 insertions(+), 9 deletions(-) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 077b278..3d6993a 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -91,29 +91,48 @@ struct mvsata_port_registers { #define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003 /* + * Status codes to return to client callers. Currently, callers ignore + * exact value and only care for zero or nonzero, so no need to make this + * public, it is only #define'd for clarity. + * If/when standard negative codes are implemented in U-boot, then these + * #defines should be moved to, or replaced by ones from, the common list + * of status codes. + */ + +#define MVSATA_STATUS_OK 0 +#define MVSATA_STATUS_TIMEOUT -1 + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's * DET back to "no action". */ -static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) +static int mvsata_ide_initialize_port(struct mvsata_port_registers *port) { u32 control; u32 status; - u32 tout = 50; /* wait at most 50 us for SATA reset to complete */ + u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */ + /* Set control IPM to 3 (no low power) and DET to 1 (initialize) */ control = readl(&port->scontrol); control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT; writel(control, &port->scontrol); - while (--tout) { + /* Toggle control DET back to 0 (normal operation) */ + control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; + writel(control, &port->scontrol); + /* wait for status DET to become 3 (device and communication OK) */ + while (--timeleft) { status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK; if (status == MVSATA_SSTATUS_DET_DEVCOMM) break; udelay(1); } - control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE; - writel(control, &port->scontrol); + /* return success or time-out error depending on time left */ + if (!timeleft) + return MVSATA_STATUS_TIMEOUT; + return MVSATA_STATUS_OK; } /* @@ -123,18 +142,23 @@ static void mvsata_ide_initialize_port(struct mvsata_port_registers *port) int ide_preinit(void) { + int status; /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET)); + if (status) + return status; #endif /* Enable ATA port 1 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE1_OFFSET) - mvsata_ide_initialize_port( + status = mvsata_ide_initialize_port( (struct mvsata_port_registers *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET)); + if (status) + return status; #endif - /* return 0 as we always succeed */ - return 0; + /* return success if all ports initializations succeeded */ + return MVSATA_STATUS_OK; } -- 1.7.0.4

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[U-Boot] Testing Data Cache for armv7 (beagleboard)
by chris chriss 12 Oct '10

12 Oct '10

I'm trying to test the cache on my beagle with a snapshot from the git tree today. I tried it out by loading a file from the mmc with dcache off and then dcache on. I didn't see any difference in speed. After reading this commit (http://git.denx.de/?p=u-boot.git;a=commit;h=95c6f6d), I expected to see a performance improvement. This is a capture of how I tested it... <capture> OMAP3 beagleboard.org # mmc init 1 mmc1 is available OMAP3 beagleboard.org # dcache Data (writethrough) Cache is OFF OMAP3 beagleboard.org # fatload mmc 0:1 0x80000000 uImage.bin reading uImage.bin 3852836 bytes read OMAP3 beagleboard.org # dcache on Data (writethrough) Cache is ON OMAP3 beagleboard.org # fatload mmc 0:1 0x80000000 uImage.bin reading uImage.bin 3852836 bytes read OMAP3 beagleboard.org # </capture>

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[U-Boot] [u-boot] MPC8360E ATM Quad OC3 External Phys u-boot patch
by Popa Stefan-R89990 12 Oct '10

12 Oct '10

Hi, I have a fix for MPC8360E ATM Quad OC3 External Phys on u-boot 2010-06. Changed CS4 and CS5 addresses on Local Bus for matching PMC0 and PMC1 addresses. Attached you can find the patch for it. Best regards, Stefan A. POPA Freescale Semiconductor Romania SRL 45, Tudor Vladimirescu Street Tati Business Center Bucharest 050881, Romania Phone: +40 21 3052431 This e-mail, and any associated attachments have been classified as: ( ) Public ( ) Freescale Semiconductor Internal Use Only ( ) Freescale Semiconductor Confidential Proprietary

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[U-Boot] [PATCH 0/1] Add support for the OMAP3 IGEP module
by Enric Balletbo i Serra 12 Oct '10

12 Oct '10

Hello, This is the first version of patch series to add initial support for OMAP3 IGEP module. Please, consider to add in next merge window. Thanks. $ git diff --stat origin/master MAINTAINERS | 1 + MAKEALL | 1 + board/isee/igep0030/Makefile | 49 +++++++++ board/isee/igep0030/config.mk | 34 +++++++ board/isee/igep0030/igep0030.c | 71 +++++++++++++ board/isee/igep0030/igep0030.h | 147 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/igep0030.h | 215 ++++++++++++++++++++++++++++++++++++++++ 8 files changed, 519 insertions(+), 0 deletions(-) Cheers, Enric

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