October 2010 - U-Boot

[U-Boot] [PATCH] boards.cfg: update local documentation
by Mike Frysinger 19 Oct '10

19 Oct '10

The "options" field at the moment is only documented in the changelog which isn't terribly useful to people without git. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- boards.cfg | 14 +++++++++++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/boards.cfg b/boards.cfg index d6c3401..443f9bd 100644 --- a/boards.cfg +++ b/boards.cfg @@ -3,9 +3,7 @@ # # Syntax: # white-space separated list of entries; -# each entry has the following fields: -# -# Targetname Architecture CPU Boardname Vendor SoC +# each entry has the fields documented below. # # Unused fields can be specified as "-", or omitted if they # are the last field on the line. @@ -13,6 +11,16 @@ # Lines starting with '#' are comments. # Blank lines are ignored. # +# The options field takes the form: +# <board config name>[:comma separated config options] +# Each config option has the form (value defaults to "1"): +# option[=value] +# So if you have: +# FOO:HAS_BAR,BAZ=64 +# The file include/configs/FOO.h will be used, and these defines created: +# #define CONFIG_HAS_BAR 1 +# #define CONFIG_BAZ 64 +# # To keep the list sorted, use something like # # :.,$! sort -f -k2,2 -k3,3 -k6,6 -k5,5 -k1,1 -- 1.7.3.1

2 1

[U-Boot] commit "powerpc: Remove warm reset entry point" does not work on mpc83xx
by Joakim Tjernlund 19 Oct '10

19 Oct '10

My board has a problem with this change. I added it manually to my tree and now it wont boot at all(only with BDI2000 connected). It seems like my board uses the warm start vector at all times. Padding with 4 nop's after the _start symbol fixes the problem. It might be due to a somewhat peculiar reset design but I cannot understand why. Does this work for everyone else using 83xx? Jocke

3 8

[U-Boot] [PATCH] logodl: : remove code for yet another corpse
by Wolfgang Denk 19 Oct '10

19 Oct '10

The logodl board has long been unmaintained and left broken. As obviously nobody is interestedin that code any more, we may as well remove it. Signed-off-by: Wolfgang Denk <wd(a)denx.de> Cc: August Hoeraendl <august.hoerandl(a)gmx.at> Cc: Robert Schwebel <r.schwebel(a)pengutronix.de> Cc: Marek Vasut <marek.vasut(a)gmail.com> --- CREDITS | 6 +- board/logodl/Makefile | 51 --- board/logodl/config.mk | 15 - board/logodl/flash.c | 829 ------------------------------------------ board/logodl/logodl.c | 134 ------- board/logodl/lowlevel_init.S | 437 ---------------------- boards.cfg | 1 - include/configs/logodl.h | 299 --------------- 8 files changed, 1 insertions(+), 1771 deletions(-) delete mode 100644 board/logodl/Makefile delete mode 100644 board/logodl/config.mk delete mode 100644 board/logodl/flash.c delete mode 100644 board/logodl/logodl.c delete mode 100644 board/logodl/lowlevel_init.S delete mode 100644 include/configs/logodl.h diff --git a/CREDITS b/CREDITS index 2c3553e..7670af9 100644 --- a/CREDITS +++ b/CREDITS @@ -200,10 +200,6 @@ N: Andreas Heppel E: aheppel(a)sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] -N: August Hoeraendl -E: august.hoerandl(a)gmx.at -D: Support for the logodl board (PXA2xx) - N: Josh Huber E: huber(a)alum.wpi.edu D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. @@ -441,7 +437,7 @@ D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR) N: Robert Schwebel E: r.schwebel(a)pengutronix.de -D: Support for csb226, logodl and innokom boards (PXA2xx) +D: Support for csb226 and innokom boards (PXA2xx) N: Aaron Sells E: sellsa(a)embeddedplanet.com diff --git a/board/logodl/Makefile b/board/logodl/Makefile deleted file mode 100644 index 0795b6b..0000000 --- a/board/logodl/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := logodl.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/logodl/config.mk b/board/logodl/config.mk deleted file mode 100644 index 76c382d..0000000 --- a/board/logodl/config.mk +++ /dev/null @@ -1,15 +0,0 @@ -# -# Linux-Kernel is expected to be at c000'8000, entry c000'8000 -# -# we load ourself to c170'0000, the upper 1 MB of second bank -# -# download areas is c800'0000 -# - -#TEXT_BASE = 0 - -# FIXME: armboot does only work correctly when being compiled -# # for the addresses _after_ relocation to RAM!! Otherwhise the -# # .bss segment is assumed in flash... -# -TEXT_BASE = 0x083E0000 diff --git a/board/logodl/flash.c b/board/logodl/flash.c deleted file mode 100644 index 593943f..0000000 --- a/board/logodl/flash.c +++ /dev/null @@ -1,829 +0,0 @@ -/* - * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * (C) 2003 August Hoeraendl, Logotronic GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef CONFIG_FLASH_16BIT - -#include <common.h> - -#define FLASH_BANK_SIZE 0x1000000 -#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -#define write_word(in, de, da) write_word_amd(in, de, da) -static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t *info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - { - ulong flashbase = 0; - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) - { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) - { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW)0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { - - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect(flash_info_t *info) -{ - FPWV *addr = (FPWV *)(info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW)0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *)(info->start[i]); - info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00800080; /* erase mode */ - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - for (; i<2 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt==0 && i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((FPW*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += sizeof(FPW); - wp += sizeof(FPW); - cnt -= sizeof(FPW); - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - return write_word(info, wp, data); -} - - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *)(info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW)0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW)0x00550055; /* unlock */ - base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c deleted file mode 100644 index 2562ecc..0000000 --- a/board/logodl/logodl.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) 2002 Kyle Harris <kharris(a)nexus-tech.net>, Nexus Technologies, Inc. - * (C) 2002 Marius Groeger <mgroeger(a)sysgo.de>, Sysgo GmbH - * (C) 2003 Robert Schwebel <r.schwebel(a)pengutronix.de>, Pengutronix - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa-regs.h> - -DECLARE_GLOBAL_DATA_PTR; - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_LOGODL; - gd->bd->bi_boot_params = 0x08000100; - gd->bd->bi_baudrate = CONFIG_BAUDRATE; - - (*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */ - (*((volatile short*)0x14000000)) = 0xff; /* power on uart */ - - return 0; -} - - -/** - * dram_init: - setup dynamic RAM - * - * @return: 0 in case of success - */ - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - - -/** - * logodl_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1) - * @param state: switch on (1) or off (0) - */ - -void logodl_set_led(int led, int state) -{ - switch(led) { - - case 0: - if (state==1) { - CONFIG_SYS_LED_A_CR = CONFIG_SYS_LED_A_BIT; - } else if (state==0) { - CONFIG_SYS_LED_A_SR = CONFIG_SYS_LED_A_BIT; - } - break; - - case 1: - if (state==1) { - CONFIG_SYS_LED_B_CR = CONFIG_SYS_LED_B_BIT; - } else if (state==0) { - CONFIG_SYS_LED_B_SR = CONFIG_SYS_LED_B_BIT; - } - break; - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - if (status < -32) status = -1; /* let things compatible */ - /* - switch(status) { - case 1: logodl_set_led(0,1); break; - case 5: logodl_set_led(1,1); break; - case 15: logodl_set_led(2,1); break; - } - */ - logodl_set_led(0, (status & 1)==1); - logodl_set_led(1, (status & 2)==2); - - return; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S deleted file mode 100644 index 9892430..0000000 --- a/board/logodl/lowlevel_init.S +++ /dev/null @@ -1,437 +0,0 @@ -/* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/pxa-regs.h> - -DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE - -/* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -_TEXT_BASE: - .word TEXT_BASE - - -/* - * Memory setup - */ - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - - /* Set up GPIO pins first ----------------------------------------- */ - - ldr r0, =GPSR0 - ldr r1, =CONFIG_SYS_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CONFIG_SYS_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CONFIG_SYS_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CONFIG_SYS_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CONFIG_SYS_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CONFIG_SYS_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CONFIG_SYS_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CONFIG_SYS_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CONFIG_SYS_GPDR2_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CONFIG_SYS_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CONFIG_SYS_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CONFIG_SYS_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CONFIG_SYS_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CONFIG_SYS_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CONFIG_SYS_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CONFIG_SYS_PSSR_VAL - str r1, [r0] - -/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */ -/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ -/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ -/* */ -/* ldr r1, =LED_BLANK */ -/* mov r0, #0xFF */ -/* str r0, [r1] / turn on hex leds */ -/* */ -/*loop: */ -/* */ -/* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ - - - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - -mem_init: - - ldr r1, =MEMC_BASE /* get memory controller base addr. */ - - /* ---------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* ---------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CONFIG_SYS_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CONFIG_SYS_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CONFIG_SYS_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* ---------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CONFIG_SYS_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CONFIG_SYS_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CONFIG_SYS_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CONFIG_SYS_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CONFIG_SYS_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CONFIG_SYS_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CONFIG_SYS_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* ---------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* ---------------------------------------------------------------- */ - - /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */ - adr r3, mem_init /* r0 <- current position of code */ - ldr r2, =mem_init - cmp r3, r2 /* skip init if in place */ - beq initirqs - - - /* ---------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* ---------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r3, =CONFIG_SYS_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 - ldr r4, =0x03ca4000 - orr r4, r4, r3 - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* ---------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* ---------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* Write SXMRS to cause an MRS command to all enabled banks of */ - /* synchronous static memory. Note that SXLCR need not be written */ - /* at this time. */ - - /* FIXME: we use async mode for now */ - - - /* ---------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* ---------------------------------------------------------------- */ - - /* Step 4a: assert MDREFR:K?RUN and configure */ - /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Step 4b: de-assert MDREFR:SLFRSH. */ - - bic r4, r4, #(MDREFR_SLFRSH) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4c: assert MDREFR:E1PIN and E0PIO */ - - orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - - /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ - /* configure but not enable each SDRAM partition pair. */ - - ldr r4, =CONFIG_SYS_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 �sec. */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - - /* There should 9 writes, since the first write doesn't */ - /* trigger a refresh cycle on PXA250. See Intel PXA250 and */ - /* PXA210 Processors Specification Update, */ - /* Jan 2003, Errata #116, page 30. */ - - - ldr r3, =CONFIG_SYS_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - /* Step 4g: Write MDCNFG with enable bits asserted */ - /* (MDCNFG:DEx set to 1). */ - - ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) - str r3, [r1, #MDCNFG_OFFSET] - - /* Step 4h: Write MDMRS. */ - - ldr r2, =CONFIG_SYS_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - - /* We are finished with Intel's memory controller initialisation */ - - /* ---------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* ---------------------------------------------------------------- */ - -initirqs: - - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - - /* ---------------------------------------------------------------- */ - /* Clock initialisation */ - /* ---------------------------------------------------------------- */ - -initclks: - - /* Disable the peripheral clocks, and set the core clock frequency */ - /* (hard-coding at 398.12MHz for now). */ - - /* Turn Off ALL on-chip peripheral clocks for re-configuration */ - /* Note: See label 'ENABLECLKS' for the re-enabling */ - ldr r1, =CKEN - mov r2, #0 - str r2, [r1] - - - /* default value in case no valid rotary switch setting is found */ - ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ - - /* ... and write the core clock config register */ - ldr r1, =CCCR - str r2, [r1] - - /* enable the 32Khz oscillator for RTC and PowerManager */ -/* - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] -*/ - /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ - /* has settled. */ -60: - ldr r2, [r1] - ands r2, r2, #1 - beq 60b - - /* ---------------------------------------------------------------- */ - /* */ - /* ---------------------------------------------------------------- */ - - /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - - /* FIXME */ - -#ifndef DEBUG - /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ - - /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ -#endif - - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ - /* ---------------------------------------------------------------- */ - -endlowlevel_init: - - mov pc, lr diff --git a/boards.cfg b/boards.cfg index 98dfacf..1f0486f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -58,7 +58,6 @@ cradle arm pxa csb226 arm pxa delta arm pxa innokom arm pxa -logodl arm pxa lubbock arm pxa pleb2 arm pxa xaeniax arm pxa diff --git a/include/configs/logodl.h b/include/configs/logodl.h deleted file mode 100644 index 0535ee1..0000000 --- a/include/configs/logodl.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * (C) Copyright 2003 - * Robert Schwebel, Pengutronix, r.schwebel(a)pengutronix.de. - * - * Configuration for the Logotronic DL board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * include/configs/logodl.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ -#define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - /* for timer/console/ethernet */ - -/* we will never enable dcache, because we have to setup MMU first */ -#define CONFIG_SYS_NO_DCACHE - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_PXA_SERIAL -#define CONFIG_FFUART 1 /* we use FFUART */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 19200 -#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_RUN - - -#define CONFIG_BOOTDELAY 3 -/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ -#define CONFIG_BOOTARGS "console=ttyS0,19200" -#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.1.56 -#define CONFIG_SERVERIP 192.168.1.2 -#define CONFIG_BOOTCOMMAND "bootm 0x40000" -#define CONFIG_SHOW_BOOT_PROGRESS - -#define CONFIG_CMDLINE_TAG 1 - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool; this lives below the uppermost 128 KiB which are - * used for the RAM copy of the uboot code - * - */ -#define CONFIG_SYS_MALLOC_LEN (256*1024) - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x08000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0800ffff /* 64 KiB */ - -#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */ - -#define CONFIG_SYS_HZ 1000 - /* RS: the oscillator is actually 3680130?? */ - -#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - /* 0101000001 */ - /* ^^^^^ Memory Speed 99.53 MHz */ - /* ^^ Run Mode Speed = 2x Mem Speed */ - /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ - -#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ - - /* valid baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * SMSC91C111 Network Card - */ -#if 0 -#define CONFIG_NET_MULTI -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */ -#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ -#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ -#undef CONFIG_SHOW_ACTIVITY -#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ -#endif - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of RAM */ -#define PHYS_SDRAM_1 0x08000000 /* SRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (4*1024*1024) /* 4 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE (32*1024*1024) /* 32 MB */ - -#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 /* RAM starts here */ -#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - - -/* - * GPIO settings - * - * GP?? == FOOBAR is 0/1 - */ - -#define _BIT0 0x00000001 -#define _BIT1 0x00000002 -#define _BIT2 0x00000004 -#define _BIT3 0x00000008 - -#define _BIT4 0x00000010 -#define _BIT5 0x00000020 -#define _BIT6 0x00000040 -#define _BIT7 0x00000080 - -#define _BIT8 0x00000100 -#define _BIT9 0x00000200 -#define _BIT10 0x00000400 -#define _BIT11 0x00000800 - -#define _BIT12 0x00001000 -#define _BIT13 0x00002000 -#define _BIT14 0x00004000 -#define _BIT15 0x00008000 - -#define _BIT16 0x00010000 -#define _BIT17 0x00020000 -#define _BIT18 0x00040000 -#define _BIT19 0x00080000 - -#define _BIT20 0x00100000 -#define _BIT21 0x00200000 -#define _BIT22 0x00400000 -#define _BIT23 0x00800000 - -#define _BIT24 0x01000000 -#define _BIT25 0x02000000 -#define _BIT26 0x04000000 -#define _BIT27 0x08000000 - -#define _BIT28 0x10000000 -#define _BIT29 0x20000000 -#define _BIT30 0x40000000 -#define _BIT31 0x80000000 - - -#define CONFIG_SYS_LED_A_BIT (_BIT18) -#define CONFIG_SYS_LED_A_SR GPSR0 -#define CONFIG_SYS_LED_A_CR GPCR0 - -#define CONFIG_SYS_LED_B_BIT (_BIT16) -#define CONFIG_SYS_LED_B_SR GPSR1 -#define CONFIG_SYS_LED_B_CR GPCR1 - - -/* LED A: off, LED B: off */ -#define CONFIG_SYS_GPSR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18) -#define CONFIG_SYS_GPSR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CONFIG_SYS_GPSR2_VAL (_BIT14+_BIT15+_BIT16) - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 - -#define CONFIG_SYS_GPDR0_VAL (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18) -#define CONFIG_SYS_GPDR1_VAL (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25 +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13) -#define CONFIG_SYS_GPDR2_VAL (_BIT14+_BIT15+_BIT16) - -#define CONFIG_SYS_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31) -#define CONFIG_SYS_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31) -#define CONFIG_SYS_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31) -#define CONFIG_SYS_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) -#define CONFIG_SYS_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\ - _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) -#define CONFIG_SYS_GAFR2_U_VAL (_BIT1) - -#define CONFIG_SYS_PSSR_VAL (0x20) - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x123c2980 -#define CONFIG_SYS_MSC1_VAL 0x123c2661 -#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 - - -/* no sdram/pcmcia here */ -#define CONFIG_SYS_MDCNFG_VAL 0x00000000 -#define CONFIG_SYS_MDREFR_VAL 0x00000000 -#define CONFIG_SYS_MDREFR_VAL_100 0x00000000 -#define CONFIG_SYS_MDMRS_VAL 0x00000000 - -/* only SRAM */ -#define SXCNFG_SETTINGS 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ - -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00010504 -#define CONFIG_SYS_MCMEM1_VAL 0x00010504 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00010504 -#define CONFIG_SYS_MCIO0_VAL 0x00004715 -#define CONFIG_SYS_MCIO1_VAL 0x00004715 - - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* FIXME */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) /* Addr of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -#endif /* __CONFIG_H */ -- 1.7.2.3

4 10

[U-Boot] [PATCH] NC650/CP650: remove code for yet another corpse
by Wolfgang Denk 19 Oct '10

19 Oct '10

The NC650 / CP650 boards have long been unmaintained and left broken. As obviously nobody is interested in that code any more, we may as well remove it. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- MAINTAINERS | 1 - board/nc650/Makefile | 45 ---- board/nc650/flash.c | 542 ------------------------------------------ board/nc650/nand.c | 110 --------- board/nc650/nc650.c | 309 ------------------------ board/nc650/u-boot.lds | 126 ---------- board/nc650/u-boot.lds.debug | 125 ---------- boards.cfg | 3 - include/configs/NC650.h | 451 ----------------------------------- 9 files changed, 0 insertions(+), 1712 deletions(-) delete mode 100644 board/nc650/Makefile delete mode 100644 board/nc650/flash.c delete mode 100644 board/nc650/nand.c delete mode 100644 board/nc650/nc650.c delete mode 100644 board/nc650/u-boot.lds delete mode 100644 board/nc650/u-boot.lds.debug delete mode 100644 include/configs/NC650.h diff --git a/MAINTAINERS b/MAINTAINERS index 5108c54..86b6efe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -102,7 +102,6 @@ Wolfgang Denk <wd(a)denx.de> IVMS8_256 MPC860 LANTEC MPC850 LWMON MPC823 - NC650 MPC852 R360MPI MPC823 RMU MPC850 RRvision MPC823 diff --git a/board/nc650/Makefile b/board/nc650/Makefile deleted file mode 100644 index e4006e7..0000000 --- a/board/nc650/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2006 Detlev Zundel, dzu(a)denx.de -# (C) Copyright 2004-2006 -# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o nand.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/nc650/flash.c b/board/nc650/flash.c deleted file mode 100644 index 8a0eab5..0000000 --- a/board/nc650/flash.c +++ /dev/null @@ -1,542 +0,0 @@ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef DEBUG - -#include <common.h> -#include <mpc8xx.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ -#define CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*----------------------------------------------------------------------- - * Protection Flags: - */ -#define FLAG_PROTECT_SET 0x01 -#define FLAG_PROTECT_CLEAR 0x02 - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH8 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#elif FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#else /* FLASH_PORT_WIDTH8 */ -#define FLASH_PORT_WIDTH uchar -#define FLASH_PORT_WIDTHV vu_char -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0; - int i; -#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else - trlx = 0; - - /* We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* For bus frequencies above 50MHz, we want to use relaxed - * timing (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); -#endif - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Remap FLASH according to real size */ -#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); -#else - memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); -#endif - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000); - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F320J3A: - printf ("28F320J3A\n"); - break; - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - FPW value; - - addr[0] = (FPW) 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - -#ifdef FLASH_PORT_WIDTH8 - value = addr[2]; /* device ID */ -#else - value = addr[1]; /* device ID */ -#endif - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { - case (FPW) INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - start = get_timer (0); - last = start; - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - - int i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#elif defined(FLASH_PORT_WIDTH32) - wp = (addr & ~3); - port_width = 4; -#else - wp = addr; - port_width = 1; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer (0); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} diff --git a/board/nc650/nand.c b/board/nc650/nand.c deleted file mode 100644 index 7dca97f..0000000 --- a/board/nc650/nand.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2006 Detlev Zundel, dzu(a)denx.de - * (C) Copyright 2006 DENX Software Engineering - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> - -#if defined(CONFIG_IDS852_REV1) -/* - * hardware specific access to control-lines - */ -static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - this->IO_ADDR_W += 2; - else - this->IO_ADDR_W -= 2; - if ( ctrl & NAND_ALE ) - this->IO_ADDR_W += 1; - else - this->IO_ADDR_W -= 1; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} -#elif defined(CONFIG_IDS852_REV2) -/* - * hardware specific access to control-lines - */ -static void nc650_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - writeb(0, (volatile __u8 *) this->IO_ADDR_W + 0xa); - else - writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8); - if ( ctrl & NAND_ALE ) - writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x9); - else - writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8); - if ( ctrl & NAND_NCE ) - writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0x8); - else - writeb(0, (volatile __u8 *) this->IO_ADDR_W) + 0xc); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} -#else -#error Unknown IDS852 module revision -#endif - -/* - * Board-specific NAND initialization. The following members of the - * argument are board-specific (per include/linux/mtd/nand.h): - * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device - * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device - * - cmd_ctrl: hardwarespecific function for accesing control-lines - * - dev_ready: hardwarespecific function for accesing device ready/busy line - * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must - * only be provided if a hardware ECC is available - * - eccm.ode: mode of ecc, see defines - * - chip_delay: chip dependent delay for transfering data from array to - * read regs (tR) - * - options: various chip options. They can partly be set to inform - * nand_scan about special functionality. See the defines for further - * explanation - * Members with a "?" were not set in the merged testing-NAND branch, - * so they are not set here either. - */ -int board_nand_init(struct nand_chip *nand) -{ - - nand->cmd_ctrl = nc650_hwcontrol; - nand->ecc.mode = NAND_ECC_SOFT; - nand->chip_delay = 12; -/* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/ - return 0; -} -#endif diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c deleted file mode 100644 index 056230d..0000000 --- a/board/nc650/nc650.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2006 Detlev Zundel, dzu(a)denx.de - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <mpc8xx.h> - -/* - * Memory Controller Using - * - * CS0 - Flash memory (0x40000000) - * CS3 - SDRAM (0x00000000} - */ - -/* ------------------------------------------------------------------------- */ - -#define _not_used_ 0xffffffff - -const uint sdram_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, - 0x1ff77c47, - - /* MRS initialization (offset 5) */ - - 0x1ff77c34, 0xefeabc34, 0x1fb57c35, - - /* burst read. (offset 8 in upm RAM) */ - 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* single write. (offset 18 in upm RAM) */ - 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* burst write. (offset 20 in upm RAM) */ - 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* refresh. (offset 30 in upm RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, - _not_used_, _not_used_, _not_used_, _not_used_, - - /* exception. (offset 3c in upm RAM) */ - 0x7ffffc07, _not_used_, _not_used_, _not_used_ -}; - -const uint nand_flash_table[] = { - /* single read. (offset 0 in upm RAM) */ - 0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04, - 0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05, - - /* burst read. (offset 8 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* single write. (offset 18 in upm RAM) */ - 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04, - 0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05, - - /* burst write. (offset 20 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* refresh. (offset 30 in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05, - - /* exception. (offset 3c in upm RAM) */ - 0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05 -}; - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ -#if !defined(CONFIG_CP850) - puts ("Board: NC650"); -#else - puts ("Board: CP850"); -#endif -#if defined(CONFIG_IDS852_REV1) - puts (" with IDS852 rev 1 module\n"); -#elif defined(CONFIG_IDS852_REV2) - puts (" with IDS852 rev 2 module\n"); -#endif - return 0; -} - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size_b0 = 0; - unsigned long reg; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 1 to the SDRAM bank at - * preliminary address - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */ - udelay (200); - memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */ - udelay (200); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - if (size8 < size9) { - size_b0 = size9; - } else { - size_b0 = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay (500); - } - - /* - * Adjust refresh rate depending on SDRAM type, both banks. - * For types > 128 MBit leave it at the current (fast) rate - */ - if ((size_b0 < 0x02000000)) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay (1000); - } - - /* - * Final mapping - */ - - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - udelay (10000); - - /* Configure UPMB for NAND flash access */ - upmconfig (UPMB, (uint *) nand_flash_table, - sizeof (nand_flash_table) / sizeof (uint)); - - memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND; - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - - -#if defined(CONFIG_CP850) - -#define DPRAM_VARNAME "KP850DIP" -#define PARAM_ADDR 0x7C0 -#define NAME_ADDR 0x7F8 -#define BOARD_NAME "KP01" -#define DEFAULT_LB "241111" - -int misc_init_r(void) -{ - int iCompatMode = 0; - char *pParam = NULL; - char *envlb; - - /* - First byte in CPLD read address space signals compatibility mode - 0 - cp850 - 1 - kp852 - */ - pParam = (char*)(CONFIG_SYS_CPLD_BASE); - if( *pParam != 0) - iCompatMode = 1; - - if ( iCompatMode != 0) { - /* - In KP852 compatibility mode we have to write to - DPRAM as early as possible the binary coded - line config and board name. - The line config is derived from the environment - variable DPRAM_VARNAME by converting from ASCII - to binary per character. - */ - if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) { - setenv( DPRAM_VARNAME, DEFAULT_LB); - envlb = DEFAULT_LB; - } - - /* Status string */ - printf("Mode: KP852(LB=%s)\n", envlb); - - /* copy appl init */ - pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR); - while (*envlb) { - *(pParam++) = *(envlb++) - '0'; - } - *pParam = '\0'; - - /* copy board id */ - pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR); - strcpy( pParam, BOARD_NAME); - } else { - puts("Mode: CP850\n"); - } - - return 0; -} -#endif diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds deleted file mode 100644 index e89a9bc..0000000 --- a/board/nc650/u-boot.lds +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug deleted file mode 100644 index 770adf7..0000000 --- a/board/nc650/u-boot.lds.debug +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/boards.cfg b/boards.cfg index 3a965e9..cf2fba7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -244,7 +244,6 @@ TQM866M powerpc mpc8xx tqm8xx tqc TQM885D powerpc mpc8xx tqm8xx tqc AMX860 powerpc mpc8xx amx860 westel AdderII powerpc mpc8xx adder - - Adder:MPC852T -CP850 powerpc mpc8xx nc650 - - NC650:CP850=1,IDS852_REV2=1 IVML24 powerpc mpc8xx ivm - - IVML24:IVML24_16M IVMS8 powerpc mpc8xx ivm - - IVMS8:IVMS8_16M NETTA powerpc mpc8xx netta - - NETTA @@ -603,8 +602,6 @@ IVML24_128 powerpc mpc8xx ivm - - IVML24:IVML24_32M IVML24_256 powerpc mpc8xx ivm - - IVML24:IVML24_64M IVMS8_128 powerpc mpc8xx ivm - - IVMS8:IVMS8_32M IVMS8_256 powerpc mpc8xx ivm - - IVMS8:IVMS8_64M -NC650_Rev1 powerpc mpc8xx nc650 - - NC650:IDS852_REV2=1 -NC650_Rev2 powerpc mpc8xx nc650 - - NC650:IDS852_REV1=1 NETTA2_V2 powerpc mpc8xx netta2 - - NETTA2:NETTA2_VERSION=2 NETTA_6412 powerpc mpc8xx netta - - NETTA:NETTA_6412=1 NETTA_ISDN powerpc mpc8xx netta - - NETTA:NETTA_ISDN=1 diff --git a/include/configs/NC650.h b/include/configs/NC650.h deleted file mode 100644 index df1c1ca..0000000 --- a/include/configs/NC650.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2006, 2007 Detlev Zundel, dzu(a)denx.de - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC852T 1 -#define CONFIG_NC650 1 - -#define CONFIG_SYS_TEXT_BASE 0x40700000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -/* - * 10 MHz - PLL input clock - */ -#define CONFIG_8xx_OSCLK 10000000 - -/* - * 50 MHz - default CPU clock - */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 - -/* - * 15 MHz - CPU minimum clock - */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 - -/* - * 133 MHz - CPU maximum clock - */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 - -#define CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN CONFIG_8xx_OSCLK - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d seconds...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "ids" -#define CONFIG_BOOT_RETRY_TIME 900 -#define CONFIG_BOOT_RETRY_MIN 30 - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_WATCHDOG /* watchdog enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_FEC_ENET 1 /* use FEC ethernet */ -#define FEC_ENET -#define CONFIG_MII -#define CONFIG_SYS_DISCOVER_PHY 1 - - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7f - -/* - * Software (bit-bang) I2C driver configuration - */ -#if defined(CONFIG_IDS852_REV1) - -#define SCL 0x1000 /* PA 3 */ -#define SDA 0x2000 /* PA 2 */ - -#define __I2C_DIR immr->im_ioport.iop_padir -#define __I2C_DAT immr->im_ioport.iop_padat -#define __I2C_PAR immr->im_ioport.iop_papar - -#elif defined(CONFIG_IDS852_REV2) - -#define SCL 0x0002 /* PB 30 */ -#define SDA 0x0001 /* PB 31 */ - -#define __I2C_PAR immr->im_cpm.cp_pbpar -#define __I2C_DIR immr->im_cpm.cp_pbdir -#define __I2C_DAT immr->im_cpm.cp_pbdat - -#endif - -#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ - __I2C_DIR |= (SDA|SCL); } -#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) -#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } -#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } -#define I2C_DELAY { udelay(5); } -#define I2C_ACTIVE { __I2C_DIR |= SDA; } -#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } - -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 -#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x00740000 - -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/* - * NAND flash support - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ - SCCR_DFLCD000 | SCCR_DFALCD00) - - /*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0 and OR0 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ - -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: Default value of OR0 after reset */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) - -/* - * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1 - * rev2 only uses the chipselect - */ -#define CONFIG_SYS_NAND_BASE 0x50000000 -#define CONFIG_SYS_NAND_SIZE 0x04000000 - -#define CONFIG_SYS_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V ) -#define CONFIG_SYS_OR2_PRELIM (((-CONFIG_SYS_NAND_SIZE) & OR_AM_MSK) | OR_BI ) - -/* - * BR3 and OR3 (SDRAM) - */ -#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - - /* - * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM) -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) - -/* - * BR4 and OR4 (CPLD) - */ -#define CONFIG_SYS_CPLD_BASE 0x80000000 /* CPLD */ -#define CONFIG_SYS_CPLD_SIZE 0x10000 /* only 16 used */ - -#define CONFIG_SYS_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_1_CLK) - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR4_PRELIM (((-CONFIG_SYS_CPLD_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_CPLD) - -/* - * BR5 and OR5 (SRAM) - */ -#define CONFIG_SYS_SRAM_BASE 0x60000000 -#define CONFIG_SYS_SRAM_SIZE 0x00080000 - -#define CONFIG_SYS_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ - OR_SCY_15_CLK | OR_EHTR | OR_TRLX) - -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) -#define CONFIG_SYS_OR5_PRELIM (((-CONFIG_SYS_SRAM_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_SRAM) - -#if defined(CONFIG_CP850) -/* - * BR6 and OR6 (DPRAM) - only on CP850 - */ -#define CONFIG_SYS_OR6_PRELIM 0xffff8170 -#define CONFIG_SYS_BR6_PRELIM 0xa0000401 -#define DPRAM_BASE_ADDR 0xa0000000 - -#define CONFIG_MISC_INIT_R 1 -#endif - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 39 - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * MBMR settings for NAND flash - */ - -#define CONFIG_SYS_MBMR_NAND ( MBMR_WLFB_5X ) - -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_SIZE 0x00400000 -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ -#define CONFIG_CMD_MTDPARTS -#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" - -#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ - "4m(cramfs1),1m(cramfs2)," \ - "256k(u-boot),128k(env);" \ - "nc650-nand:4m(jffs1),28m(jffs2)" - -#endif /* __CONFIG_H */ -- 1.7.2.3

1 1

[U-Boot] [PATCH 1/2] Build: PXA: Fix Vpac270 build variants
by Marek Vasut 19 Oct '10

19 Oct '10

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- MAKEALL | 3 --- Makefile | 16 ---------------- board/vpac270/vpac270.c | 2 +- boards.cfg | 3 +++ include/configs/vpac270.h | 12 ++++++------ 5 files changed, 10 insertions(+), 26 deletions(-) diff --git a/MAKEALL b/MAKEALL index 6c71943..59ff847 100755 --- a/MAKEALL +++ b/MAKEALL @@ -339,9 +339,6 @@ LIST_at91=" \ LIST_pxa="$(boards_by_cpu pxa) polaris \ trizepsiv \ - vpac270_nor_128M\ - vpac270_nor_256M\ - vpac270_onenand \ " LIST_ixp="$(boards_by_cpu ixp) diff --git a/Makefile b/Makefile index 25e8fc8..8078d71 100644 --- a/Makefile +++ b/Makefile @@ -1018,22 +1018,6 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv -vpac270_nor_256M_config \ -vpac270_nor_128M_config \ -vpac270_onenand_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring onenand,$@)" ] ; then \ - echo "#define CONFIG_ONENAND_U_BOOT" \ - >>$(obj)include/config.h ; \ - echo "#define CONFIG_256M_U_BOOT" \ - >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring 256M,$@)" ] ; then \ - echo "#define CONFIG_256M_U_BOOT" \ - >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270 - ######################################################################### ## ARM1136 Systems ######################################################################### diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 91d8580..43bbdff 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -66,7 +66,7 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; #endif diff --git a/boards.cfg b/boards.cfg index 5d43f3d..b8365f7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -62,6 +62,9 @@ lubbock arm pxa palmld arm pxa palmtc arm pxa pleb2 arm pxa +vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M +vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M +vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M xaeniax arm pxa xm250 arm pxa zipitz2 arm pxa diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index fc680fc..c9d9c69 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -75,7 +75,7 @@ #undef CONFIG_LCD #define CONFIG_CMD_IDE -#ifdef CONFIG_ONENAND_U_BOOT +#ifdef CONFIG_ONENAND #undef CONFIG_CMD_FLASH #define CONFIG_CMD_ONENAND #else @@ -165,13 +165,13 @@ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ #endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ #else #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ @@ -198,7 +198,7 @@ #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ #endif @@ -206,7 +206,7 @@ #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } #else @@ -308,7 +308,7 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 #else #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 -- 1.7.1

1 1

[U-Boot] [ELF_RELOC] u-boot-arm: elf_reloc branch merged
by Wolfgang Denk 19 Oct '10

19 Oct '10

Hello, this is to let you know that the elf_reloc branch has now been merged into u-boot-arm # master. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Hi there! This is just a note from me, to you, to tell you, the per- son reading this note, that I can't think up any more famous quotes, jokes, nor bizarre stories, so you may as well go home.

1 0

[U-Boot] [PATCH] Support for sending DHCP client options
by Gray Remlin 19 Oct '10

19 Oct '10

Signed-off-by: Gray Remlin <g_remlin(a)rocketmail.com> --- README | 7 ++++++ common/cmd_nvedit.c | 3 ++ net/bootp.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++++++ tools/env/fw_env.c | 4 ++- 4 files changed, 65 insertions(+), 1 deletions(-) diff --git a/README b/README index a52f3bf..90da375 100644 --- a/README +++ b/README @@ -1279,6 +1279,7 @@ The following options need to be configured: CONFIG_BOOTP_NTPSERVER CONFIG_BOOTP_TIMEOFFSET CONFIG_BOOTP_VENDOREX + CONFIG_BOOTP_OPTIONS CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip environment variable, not the BOOTP server. @@ -1299,6 +1300,12 @@ The following options need to be configured: of the "hostname" environment variable is passed as option 12 to the DHCP server. + CONFIG_BOOTP_OPTIONS - The environment is checked for the + supported DHCPv4 client options (prefixed with dhcp_), any + found are sent during a "DHCP Discover" and "DHCP Request". + The DHCP server can use this information to conditionally + tailor it's response. + CONFIG_BOOTP_DHCP_REQUEST_DELAY A 32bit value in microseconds for a delay between diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 3d30c32..2094e8e 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -224,6 +224,9 @@ int _do_env_set (int flag, int argc, char * const argv[]) if (ep) { /* variable exists */ #ifndef CONFIG_ENV_OVERWRITE if ((strcmp (name, "serial#") == 0) || +#if defined(CONFIG_BOOTP_OPTIONS) + (strcmp(name, "dhcp_vendor-class-identifier") == 0) || +#endif /* CONFIG_BOOTP_OPTIONS */ ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp (ep->data,MK_STR(CONFIG_ETHADDR)) != 0) diff --git a/net/bootp.c b/net/bootp.c index 1289e3b..9e687b0 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -68,6 +68,54 @@ extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ #endif +#if defined(CONFIG_BOOTP_OPTIONS) /* check environment for dhcp client options */ + +/* + * The vendor-specifiable options should not be changeable + * unless CONFIG_ENV_OVERWRITE has been defined, however + * user-specifiable options should be changeable regardless + */ +u8 dhcp_options_prep(u8 **ep) +{ + u8 *e = *ep; + char *ptr; + + debug("DHCP Client options start\n"); + + /* vendor-specifiable identification string */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + debug("dhcp_vendor-class-identifier=%s\n",ptr); + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + /* user-specifiable identification string */ + if ((ptr = getenv("dhcp_dhcp-client-identifier"))) { + debug("dhcp_dhcp-client-identifier=%s\n",ptr); + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + /* user-specifiable identification string */ + if ((ptr = getenv("dhcp_user-class"))) { + debug("dhcp_user-class=%s\n",ptr); + *e++ = 77; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + debug("DHCP Client options end\n"); + *ep = e; + return e; +} + +#endif /* CONFIG_BOOTP_OPTIONS */ + #endif static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len) @@ -412,6 +460,10 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R } #endif +#if defined(CONFIG_BOOTP_OPTIONS) + dhcp_options_prep (&e); +#endif + #if defined(CONFIG_BOOTP_VENDOREX) if ((x = dhcp_vendorex_prep (e))) return x - start; diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 8ff7052..ae37d15 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -391,9 +391,11 @@ int fw_env_write(char *name, char *value) */ if (oldval) { /* - * Ethernet Address and serial# can be set only once + * Ethernet Address, vendor DHCP options, + * and serial# can be set only once */ if ((strcmp (name, "ethaddr") == 0) || + (strcmp(name, "dhcp_vendor-class-identifier") == 0) || (strcmp (name, "serial#") == 0)) { fprintf (stderr, "Can't overwrite \"%s\"\n", name); errno = EROFS; --

2 1

[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 19 Oct '10

19 Oct '10

Hi Wolfgang, please pull from u-boot-imx. The following changes since commit cacc342d5aa311673efdc05770cb53246dd41c9f: Merge branch 'master' of git://git.denx.de/u-boot-arm (2010-10-17 20:25:05 +0200) are available in the git repository at: git://git.denx.de/u-boot-imx master Jason Liu (2): MX5: rename mx51 to mx5 MX5: Remove dead code with ENABLE_IMPRECISE_ABORT Magnus Lilja (1): i.MX31: Fix Litekit board to use new ARM relocation support. Stefano Babic (1): MX31: add delay between USB port setup and reset Wolfgang Denk (1): QONG: fix and update board config file arch/arm/cpu/armv7/{mx51 => mx5}/Makefile | 0 arch/arm/cpu/armv7/{mx51 => mx5}/clock.c | 42 ++++++++++---------- arch/arm/cpu/armv7/{mx51 => mx5}/iomux.c | 2 +- arch/arm/cpu/armv7/{mx51 => mx5}/lowlevel_init.S | 14 ------- arch/arm/cpu/armv7/{mx51 => mx5}/soc.c | 28 ++++++++----- arch/arm/cpu/armv7/{mx51 => mx5}/speed.c | 0 arch/arm/cpu/armv7/{mx51 => mx5}/timer.c | 8 ++-- arch/arm/cpu/armv7/{mx51 => mx5}/u-boot.lds | 0 .../asm/{arch-mx51 => arch-mx5}/asm-offsets.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/clock.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/crm_regs.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/imx-regs.h | 0 .../include/asm/{arch-mx51 => arch-mx5}/iomux.h | 8 ++-- .../mx51_pins.h => arch-mx5/mx5x_pins.h} | 6 +- .../asm/{arch-mx51 => arch-mx5}/sys_proto.h | 0 board/freescale/mx51evk/mx51evk.c | 2 +- board/logicpd/imx31_litekit/config.mk | 2 +- board/logicpd/imx31_litekit/imx31_litekit.c | 10 ++++- board/ttcontrol/vision2/vision2.c | 2 +- boards.cfg | 4 +- drivers/usb/host/ehci-mxc.c | 2 + include/configs/imx31_litekit.h | 7 +++ include/configs/mx51evk.h | 4 +- include/configs/qong.h | 32 +++++++-------- include/configs/vision2.h | 4 +- 25 files changed, 90 insertions(+), 87 deletions(-) rename arch/arm/cpu/armv7/{mx51 => mx5}/Makefile (100%) rename arch/arm/cpu/armv7/{mx51 => mx5}/clock.c (85%) rename arch/arm/cpu/armv7/{mx51 => mx5}/iomux.c (99%) rename arch/arm/cpu/armv7/{mx51 => mx5}/lowlevel_init.S (95%) rename arch/arm/cpu/armv7/{mx51 => mx5}/soc.c (81%) rename arch/arm/cpu/armv7/{mx51 => mx5}/speed.c (100%) rename arch/arm/cpu/armv7/{mx51 => mx5}/timer.c (92%) rename arch/arm/cpu/armv7/{mx51 => mx5}/u-boot.lds (100%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/asm-offsets.h (100%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/clock.h (100%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/crm_regs.h (100%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/imx-regs.h (100%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/iomux.h (98%) rename arch/arm/include/asm/{arch-mx51/mx51_pins.h => arch-mx5/mx5x_pins.h} (99%) rename arch/arm/include/asm/{arch-mx51 => arch-mx5}/sys_proto.h (100%) -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

2 1

[U-Boot] [PATCH 1/6] Rename TEXT_BASE to CONFIG_SYS_TEXT_BASE
by Nobuhiro Iwamatsu 19 Oct '10

19 Oct '10

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 07ba68f..415c949 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -29,6 +29,6 @@ STANDALONE_LOAD_ADDR += -EB endif PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__ -PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE) +PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE) LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds -- 1.7.1

1 0

[U-Boot] [PATCH 1/5] sh: Fix warning about uninitialized value of ramdisk_flags
by Nobuhiro Iwamatsu 19 Oct '10

19 Oct '10

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/sh/lib/bootm.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 019e8ec..f38d0b0 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -103,7 +103,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima sh_check_cmd_arg(bootargs, CMD_ARG_RD_DOLOAD, 10); /* Initrd */ if (images->rd_start || images->rd_end) { - unsigned long ramdisk_flags; + unsigned long ramdisk_flags = 0; int val = sh_check_cmd_arg(bootargs, CMD_ARG_RD_PROMPT, 10); if (val == 1) ramdisk_flags |= RD_PROMPT; -- 1.7.1

1 4