July 2009 - U-Boot

[U-Boot] Ping is not working with uboot 1.3.4 on at91sam9263 custom board
by Nirav Rabara 22 Jul '09

22 Jul '09

Hi i have been using custom board with at91sam9263 and U boot 1.3.4, It showing that link is up and down whenever i pluging and plugout the Ethernet cable. But when I try to ping, it showing : host device not active. Whether its a problem with Uboot or something with board?? Your suggestions would be great help for me. -- View this message in context: http://www.nabble.com/Ping-is-not-working-with-uboot-1.3.4-on-at91sam9263-c… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] [PATCH] atmel_df_pow2: standalone to convert dataflashes to pow2
by Mike Frysinger 22 Jul '09

22 Jul '09

Atmel DataFlashes by default operate with pages with 1056 byte pages. They also have a "power of 2" mode where the pages are 1024 bytes in size. The latter mode is required in order to boot with a Blackfin processor, so many people wish to convert their DataFlashes on their development systems to this mode. This standalone application does just that. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- examples/.gitignore | 1 + examples/Makefile | 4 + examples/atmel_df_pow2.c | 206 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+), 0 deletions(-) create mode 100644 examples/atmel_df_pow2.c diff --git a/examples/.gitignore b/examples/.gitignore index 0d1864c..7b783fc 100644 --- a/examples/.gitignore +++ b/examples/.gitignore @@ -1,4 +1,5 @@ /82559_eeprom +/atmel_df_pow2 /hello_world /interrupt /mem_to_mem_idma2intr diff --git a/examples/Makefile b/examples/Makefile index dbcfa92..9f67afd 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -86,6 +86,10 @@ ELF = hello_world SREC = hello_world.srec BIN = hello_world.bin +ELF += atmel_df_pow2 +SREC += atmel_df_pow2.srec +BIN += atmel_df_pow2.bin + ifeq ($(CPU),mpc8xx) ELF += test_burst SREC += test_burst.srec diff --git a/examples/atmel_df_pow2.c b/examples/atmel_df_pow2.c new file mode 100644 index 0000000..e6d02b1 --- /dev/null +++ b/examples/atmel_df_pow2.c @@ -0,0 +1,206 @@ +/* + * atmel_df_pow2.c - convert Atmel Dataflashes to Power of 2 mode + * + * Copyright 2009 Analog Devices Inc. + * + * Licensed under the 2-clause BSD. + */ + +#include <common.h> +#include <exports.h> + +#define CMD_ID 0x9f +#define CMD_STAT 0xd7 +#define CMD_CFG 0x3d + +static int flash_cmd(struct spi_slave *slave, uchar cmd, uchar *buf, int len) +{ + buf[0] = cmd; + return spi_xfer(slave, 8 * len, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END); +} + +static int flash_status(struct spi_slave *slave) +{ + uchar buf[2]; + if (flash_cmd(slave, CMD_STAT, buf, sizeof(buf))) + return -1; + return buf[1]; +} + +static int flash_set_pow2(struct spi_slave *slave) +{ + int ret; + uchar buf[4]; + + buf[1] = 0x2a; + buf[2] = 0x80; + buf[3] = 0xa6; + + ret = flash_cmd(slave, CMD_CFG, buf, sizeof(buf)); + if (ret) + return ret; + + /* wait Tp, or 6 msec */ + udelay(6000x); + + ret = flash_status(slave); + if (ret == -1) + return 1; + + return ret & 0x1 ? 0 : 1; +} + +static int flash_check(struct spi_slave *slave) +{ + int ret; + uchar buf[4]; + + ret = flash_cmd(slave, CMD_ID, buf, sizeof(buf)); + if (ret) + return ret; + + if (buf[1] != 0x1F) { + printf("atmel flash not found (id[0] = %#x)\n", buf[1]); + return 1; + } + + if ((buf[2] >> 5) != 0x1) { + printf("AT45 flash not found (id[0] = %#x)\n", buf[2]); + return 2; + } + + return 0; +} + +static char *getline(void) +{ + static char buffer[100]; + char c; + size_t i; + + i = 0; + while (1) { + buffer[i] = '\0'; + + c = getc(); + + switch (c) { + case '\r': /* Enter/Return key */ + case '\n': + puts("\n"); + return buffer; + + case 0x03: /* ^C - break */ + return NULL; + + case 0x5F: + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + if (i) { + puts("\b \b"); + i--; + } + break; + + default: + /* Ignore control characters */ + if (c < 0x20) + break; + /* Queue up all other characters */ + buffer[i++] = c; + printf("%c", c); + break; + } + } +} + +int atmel_df_pow2(int argc, char *argv[]) +{ + /* Print the ABI version */ + app_startup(argv); + if (XF_VERSION != get_version()) { + printf("Expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %lu\n", get_version()); + printf("Can't run\n\n"); + return 1; + } + + spi_init(); + + while (1) { + struct spi_slave *slave; + char *line, *p; + int bus, cs, status; + + puts("\nenter the [BUS:]CS of the SPI flash: "); + line = getline(); + + /* CTRL+C */ + if (!line) + return 0; + if (line[0] == '\0') + continue; + + bus = cs = simple_strtoul(line, &p, 10); + if (*p) { + if (*p == ':') { + ++p; + cs = simple_strtoul(p, &p, 10); + } + if (*p) { + puts("invalid format, please try again\n"); + continue; + } + } else + bus = 0; + + printf("\ngoing to work with dataflash at %i:%i\n", bus, cs); + + /* use a low speed -- it'll work with all devices, and + * speed here doesn't really matter. + */ + slave = spi_setup_slave(bus, cs, 1000, SPI_MODE_3); + if (!slave) { + puts("unable to setup slave\n"); + continue; + } + + if (spi_claim_bus(slave)) { + spi_free_slave(slave); + continue; + } + + if (flash_check(slave)) { + puts("no flash found\n"); + goto done; + } + + status = flash_status(slave); + if (status == -1) { + puts("unable to read status register\n"); + goto done; + } + if (status & 0x1) { + puts("flash is already in power-of-2 mode!\n"); + goto done; + } + + puts("are you sure you wish to set power-of-2 mode?\n"); + puts("this operation is permanent and irreversible\n"); + printf("enter YES to continue: "); + line = getline(); + if (!line || strcmp(line, "YES")) + goto done; + + if (flash_set_pow2(slave)) { + puts("setting pow2 mode failed\n"); + goto done; + } + + puts("OK!\n"); + + done: + spi_release_bus(slave); + spi_free_slave(slave); + } +} -- 1.6.3.3

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[U-Boot] PATCH 2/2] Add pci/pcie E1000 ethernet support for MPC8544DS and MPC8536 boards
by Roy Zang 22 Jul '09

22 Jul '09

From: Roy Zang <tie-fei.zang(a)freescale.com> Add pci/pcie E1000 ethernet support for MPC8544DS and MPC8536 boards. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- include/configs/MPC8536DS.h | 1 + include/configs/MPC8540ADS.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9e00b89..e23f8f9 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -45,6 +45,7 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5253611..327b342 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -50,6 +50,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ /* * sysclk for MPC85xx -- 1.5.6.5

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[U-Boot] [PATCH v3 4/4] Kirkwood: Sheevaplug: kwimage configuration
by Prafulla Wadaskar 22 Jul '09

22 Jul '09

Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: v2: updated as per review feedback for v1 v3: some white spaces removed board/Marvell/sheevaplug/config.mk | 3 + board/Marvell/sheevaplug/kwbimage.cfg | 162 +++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/sheevaplug/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk index a4ea769..2bd9f79 100644 --- a/board/Marvell/sheevaplug/config.mk +++ b/board/Marvell/sheevaplug/config.mk @@ -23,3 +23,6 @@ # TEXT_BASE = 0x00600000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg new file mode 100644 index 0000000..309f3c4 --- /dev/null +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +0xFFD01410 0x00000099 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +0xFFD01514 0x00000000 # CS[2]n Size, window disabled +0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +0xFFD01494 0x00030000 # DDR ODT Control (Low) +0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +0xFFD0149C 0x0000E803 # CPU ODT Control +0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +0x0 0x0 -- 1.5.3.4

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[U-Boot] [PATCH v2 1/4] tools: mkimage: hdr_size used to facilitate customized support
by Prafulla Wadaskar 22 Jul '09

22 Jul '09

hdr_size variable is initialized at the begining of image creation algorithm instead of reading it each time. This facilitate to use the common code for other image type implementations for ex. kwbimage Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- hdr_size declaration moved at the top tools/mkimage.c | 18 ++++++++---------- 1 files changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 967fe9a..40363a9 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -66,6 +66,7 @@ main (int argc, char **argv) struct stat sbuf; unsigned char *ptr; char *name = ""; + int hdr_size; cmdname = *argv; @@ -250,9 +251,9 @@ NXTARG: ; * * write dummy header, to be fixed later */ - memset (hdr, 0, image_get_header_size ()); - - if (write(ifd, hdr, image_get_header_size ()) != image_get_header_size ()) { + hdr_size = image_get_header_size (); + memset (hdr, 0, hdr_size); + if (write(ifd, hdr, hdr_size) != hdr_size) { fprintf (stderr, "%s: Write error on %s: %s\n", cmdname, imagefile, strerror(errno)); exit (EXIT_FAILURE); @@ -339,14 +340,12 @@ NXTARG: ; hdr = (image_header_t *)ptr; checksum = crc32 (0, - (const char *)(ptr + image_get_header_size ()), - sbuf.st_size - image_get_header_size () - ); - + (const char *)(ptr + hdr_size), + sbuf.st_size - hdr_size); /* Build new header */ image_set_magic (hdr, IH_MAGIC); image_set_time (hdr, sbuf.st_mtime); - image_set_size (hdr, sbuf.st_size - image_get_header_size ()); + image_set_size (hdr, sbuf.st_size - hdr_size); image_set_load (hdr, addr); image_set_ep (hdr, ep); image_set_dcrc (hdr, checksum); @@ -354,10 +353,9 @@ NXTARG: ; image_set_arch (hdr, opt_arch); image_set_type (hdr, opt_type); image_set_comp (hdr, opt_comp); - image_set_name (hdr, name); - checksum = crc32 (0, (const char *)hdr, image_get_header_size ()); + checksum = crc32 (0, (const char *)hdr, hdr_size); image_set_hcrc (hdr, checksum); -- 1.5.3.4

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[U-Boot] [PATCH v2 4/4] Kirkwood: Sheevaplug: kwimage configuration
by Prafulla Wadaskar 22 Jul '09

22 Jul '09

Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: v2: updated as per review feedback for v1 board/Marvell/sheevaplug/config.mk | 3 + board/Marvell/sheevaplug/kwbimage.cfg | 162 +++++++++++++++++++++++++++++++++ 2 files changed, 165 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/sheevaplug/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/config.mk b/board/Marvell/sheevaplug/config.mk index a4ea769..2bd9f79 100644 --- a/board/Marvell/sheevaplug/config.mk +++ b/board/Marvell/sheevaplug/config.mk @@ -23,3 +23,6 @@ # TEXT_BASE = 0x00600000 + +# Kirkwood Boot Image configuration file +KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg new file mode 100644 index 0000000..de12e74 --- /dev/null +++ b/board/Marvell/sheevaplug/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +0xFFD01410 0x00000099 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +0xFFD01514 0x00000000 # CS[2]n Size, window disabled +0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +0xFFD01494 0x00030000 # DDR ODT Control (Low) +0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +0xFFD0149C 0x0000E803 # CPU ODT Control +0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +0x0 0x0 -- 1.5.3.4

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[U-Boot] [PATCH v2 1/4] tools: mkimage: hdr_size used to facilitate customized support
by Prafulla Wadaskar 21 Jul '09

21 Jul '09

hdr_size variable is initialized at the begining of image creation algorithm instead of reading it each time. This facilitate to use the common code for other image type implementations for ex. kwbimage Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- hdr_size declaration moved at the top tools/mkimage.c | 18 ++++++++---------- 1 files changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 967fe9a..40363a9 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -66,6 +66,7 @@ main (int argc, char **argv) struct stat sbuf; unsigned char *ptr; char *name = ""; + int hdr_size; cmdname = *argv; @@ -250,9 +251,9 @@ NXTARG: ; * * write dummy header, to be fixed later */ - memset (hdr, 0, image_get_header_size ()); - - if (write(ifd, hdr, image_get_header_size ()) != image_get_header_size ()) { + hdr_size = image_get_header_size (); + memset (hdr, 0, hdr_size); + if (write(ifd, hdr, hdr_size) != hdr_size) { fprintf (stderr, "%s: Write error on %s: %s\n", cmdname, imagefile, strerror(errno)); exit (EXIT_FAILURE); @@ -339,14 +340,12 @@ NXTARG: ; hdr = (image_header_t *)ptr; checksum = crc32 (0, - (const char *)(ptr + image_get_header_size ()), - sbuf.st_size - image_get_header_size () - ); - + (const char *)(ptr + hdr_size), + sbuf.st_size - hdr_size); /* Build new header */ image_set_magic (hdr, IH_MAGIC); image_set_time (hdr, sbuf.st_mtime); - image_set_size (hdr, sbuf.st_size - image_get_header_size ()); + image_set_size (hdr, sbuf.st_size - hdr_size); image_set_load (hdr, addr); image_set_ep (hdr, ep); image_set_dcrc (hdr, checksum); @@ -354,10 +353,9 @@ NXTARG: ; image_set_arch (hdr, opt_arch); image_set_type (hdr, opt_type); image_set_comp (hdr, opt_comp); - image_set_name (hdr, name); - checksum = crc32 (0, (const char *)hdr, image_get_header_size ()); + checksum = crc32 (0, (const char *)hdr, hdr_size); image_set_hcrc (hdr, checksum); -- 1.5.3.4

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[U-Boot] Pull request - net
by Ben Warren 21 Jul '09

21 Jul '09

Wolfgang, The following changes since commit 1bc1538613d66cef3cbce680fc8d7c3561a0fbd0: Peter Tyser (1): Move examples/ to examples/standalone are available in the git repository at: git://git.denx.de/u-boot-net.git master Alessio Centazzo (1): ppc4xx: Fixed compilation warning in 4xx_enet.c Andreas Pretzsch (1): smc911x: add support for LAN9221 Ben Warren (2): Add warning about upcoming removal of old Ethernet API Convert SMC911X Ethernet driver to CONFIG_NET_MULTI API David Brownell (1): rm9200 ethernet driver: board-specific quirk (csb337) Kim Phillips (1): net: tsec - fix dereferencing type-punned pointer will break strict-aliasing rules warning Kumar Gala (1): uec: Fix compile warning Michael Zaidman (1): DHCP regression on 2009-06 Mike Frysinger (1): net: rename NetRxPkt to NetRxPacket Nobuhiro Iwamatsu (1): sh: sh_eth: Remove garbage from printf Poonam Aggrwal (1): P2020RDB Added support of Vitesse PHYs VSC8641(RGMII) and VSC8221(SGMII) Prafulla Wadaskar (2): net: phy: bugfixes: mv88E61xx multichip addressing support net: Kirkwood_egiga: forced interface speed config support Richard Retanubun (1): MIIPHYBB: Return 0xFFFF if the PHY is not asserting TA. Robin Getz (1): Add DNS support Simon Kagstrom (2): arm: Kirkwood: Fix compiler optimization bug for kwgbe_send arm: Kirkwood: Check the error summary bit for error detection Thomas Dörfler (1): Bugfix: mpc512x_fec MII accesses fail after ethernet transfers board/bf548-ezkit/bf548-ezkit.c | 8 ++ board/cm-bf548/cm-bf548.c | 10 ++ board/freescale/mx31pdk/mx31pdk.c | 10 ++ board/imx31_litekit/imx31_litekit.c | 10 ++ board/imx31_phycore/imx31_phycore.c | 10 ++ board/micronas/vct/ebi_smc911x.c | 22 +++- board/micronas/vct/vct.c | 10 ++ board/omap3/evm/evm.c | 10 ++ board/renesas/ap325rxa/ap325rxa.c | 10 ++ board/renesas/rsk7203/rsk7203.c | 17 +++- common/cmd_net.c | 49 ++++++++ cpu/arm920t/at91rm9200/ether.c | 22 +++- doc/README.dns | 64 +++++++++++ drivers/net/4xx_enet.c | 3 +- drivers/net/Makefile | 2 +- drivers/net/kirkwood_egiga.c | 57 ++++++++-- drivers/net/kirkwood_egiga.h | 1 + drivers/net/mpc512x_fec.c | 13 ++ drivers/net/phy/miiphybb.c | 7 + drivers/net/phy/mv88e61xx.c | 18 ++-- drivers/net/phy/mv88e61xx.h | 2 +- drivers/net/sh_eth.c | 2 +- drivers/net/smc911x.c | 177 ++++++++++++++++------------- drivers/net/smc911x.h | 170 +++++++++++++++------------- drivers/net/tsec.c | 57 +++++++++- include/configs/ap325rxa.h | 7 +- include/configs/bf548-ezkit.h | 7 +- include/configs/cm-bf548.h | 7 +- include/configs/imx31_litekit.h | 7 +- include/configs/imx31_phycore.h | 7 +- include/configs/mx31pdk.h | 7 +- include/configs/omap3_evm.h | 7 +- include/configs/rsk7203.h | 7 +- include/configs/vct.h | 9 +- include/net.h | 9 +- include/netdev.h | 2 + net/Makefile | 7 +- net/bootp.c | 2 +- net/dns.c | 211 +++++++++++++++++++++++++++++++++++ net/dns.h | 39 +++++++ net/eth.c | 2 + net/net.c | 40 ++++++- 42 files changed, 902 insertions(+), 236 deletions(-) create mode 100644 doc/README.dns create mode 100644 net/dns.c create mode 100644 net/dns.h regards, Ben

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[U-Boot] [PATCH v2] 86xx: Report which "bank" of NOR flash we are booting from on MPC8641HPCN
by Kumar Gala 21 Jul '09

21 Jul '09

The MPC8641HPCN board is capable of swizzling the upper address bit of the NOR flash we boot out of which creates the concept of "virtual" banks. This is useful in that we can flash a test of image of u-boot and reset to one of the virtual banks while still maintaining a working image in "bank 0". The PIXIS FPGA exposes registers on LBC which we can use to determine which "bank" we are booting out of (as well as setting which bank to boot out of). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Moved from in8 -> in_8 * used PIXIS_VBOOT instead of magic 0x16 * simplified if() test - k board/freescale/mpc8641hpcn/mpc8641hpcn.c | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 7422e6b..ab7a04c 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -42,10 +42,20 @@ int board_early_init_f(void) int checkboard(void) { - printf ("Board: MPC8641HPCN, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; + + printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + if (vboot & 0x80) + printf ("vBank: %d\n", ((vboot >> 6) & 0x1)); + else + puts ("Promjet\n"); + #ifdef CONFIG_PHYS_64BIT printf (" 36-bit physical address map\n"); #endif -- 1.6.0.6

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[U-Boot] [PATCH] 85xx: Report which "bank" of NOR flash we are booting from on FSL boards
by Kumar Gala 21 Jul '09

21 Jul '09

The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of swizzling the upper address bits of the NOR flash we boot out of which creates the concept of "virtual" banks. This is useful in that we can flash a test of image of u-boot and reset to one of the virtual banks while still maintaining a working image in "bank 0". The PIXIS FPGA exposes registers on LBC which we can use to determine which "bank" we are booting out of (as well as setting which bank to boot out of). Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * This is a merged version of previous patches that covers all the 85xx boards board/freescale/mpc8536ds/mpc8536ds.c | 18 ++++++++++++++++-- board/freescale/mpc8544ds/mpc8544ds.c | 11 +++++++++-- board/freescale/mpc8572ds/mpc8572ds.c | 21 ++++++++++++++++++++- board/freescale/p2020ds/p2020ds.c | 12 +++++++++++- 4 files changed, 56 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 28b27ee..91fb87b 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -60,10 +60,24 @@ int board_early_init_f (void) int checkboard (void) { - printf ("Board: MPC8536DS, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", + u8 vboot; + + puts("Board: MPC8536DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + + printf ("Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), in8(PIXIS_BASE + PIXIS_PVER)); + + vboot = in8(PIXIS_BASE + 0x16); + if ((vboot >> 7) & 0x1) + puts ("Promjet\n"); + else + printf ("vBank: %d\n", ((vboot >> 5) & 0x3)); + return 0; } diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 34bdbad..5a199f7 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -43,15 +43,22 @@ int checkboard (void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + u8 vboot; if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); } - printf ("Board: MPC8544DS, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", + printf ("Board: MPC8544DS, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), in8(PIXIS_BASE + PIXIS_PVER)); + vboot = in8(PIXIS_BASE + 0x16); + if ((vboot >> 7) & 0x1) + printf ("vBank: %d\n", ((vboot >> 6) & 0x1)); + else + puts ("Promjet\n"); + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ ecm->eedr = 0xffffffff; /* Clear ecm errors */ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 4b95617..1d4f9bb 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -42,14 +42,33 @@ long int fixed_sdram(void); int checkboard (void) { + u8 vboot; + puts ("Board: MPC8572DS "); #ifdef CONFIG_PHYS_64BIT puts ("(36-bit addrmap) "); #endif printf ("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), in8(PIXIS_BASE + PIXIS_PVER)); + + vboot = in8(PIXIS_BASE + 0x16); + switch (((vboot >> 6) & 0x3)) { + case 0: + puts ("vBank: 0\n"); + break; + case 1: + puts ("Promjet\n"); + break; + case 2: + puts ("NAND\n"); + break; + case 3: + puts ("vBank: 1\n"); + break; + } + return 0; } diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 293e5a4..292a820 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -47,14 +47,24 @@ phys_size_t fixed_sdram(void); int checkboard(void) { + u8 sw7; + puts("Board: P2020DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif + printf("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), in8(PIXIS_BASE + PIXIS_PVER)); + + sw7 = in8(PIXIS_BASE + 0x2c); + if ((sw7 >> 7) & 0x1) + puts ("Promjet\n"); + else + printf ("vBank: %d\n", ((sw7 >> 4) & 0x3)); + return 0; } -- 1.6.0.6

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