July 2009 - U-Boot

[U-Boot] Please pull u-boot-mpc85xx
by Kumar Gala 23 Jul '09

23 Jul '09

The following changes since commit d4abc757c26c531293f5bbc4262ade44a317eec9: Peter Tyser (1): Move api_examples to examples/api are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Kumar Gala (3): 85xx: Bump up the BOOTMAP to 16M on FSL 85xx boards 85xx: Report which "bank" of NOR flash we are booting from on FSL boards 86xx: Report which "bank" of NOR flash we are booting from on MPC8641HPCN Peter Tyser (6): 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields xes: Remove 8xxx board_add_ram_info() function tqm85xx: Remove board_add_ram_info() 85xx, 86xx: Add common board_add_ram_info() xpedite5200,5370: Use buffered NOR flash writes xpedite5370: Fix I2C GPIO initialization typo Roy Zang (1): 85xx: Add pci/pcie E1000 ethernet support for MPC8544DS and MPC8536 boards board/freescale/mpc8536ds/mpc8536ds.c | 18 +++++- board/freescale/mpc8544ds/mpc8544ds.c | 11 +++- board/freescale/mpc8572ds/mpc8572ds.c | 21 ++++++- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 4 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 19 ++++-- board/freescale/p2020ds/p2020ds.c | 12 +++- board/sbc8641d/sbc8641d.c | 12 ++-- board/tqc/tqm85xx/sdram.c | 33 +--------- board/xes/common/fsl_8xxx_ddr.c | 53 ---------------- board/xes/xpedite5370/xpedite5370.c | 4 +- cpu/mpc86xx/ddr-8641.c | 4 +- cpu/mpc8xxx/ddr/main.c | 43 +------------ cpu/mpc8xxx/ddr/util.c | 96 +++++++++++++++++++++++++++++ include/asm-ppc/immap_86xx.h | 4 +- include/configs/MPC8536DS.h | 5 +- include/configs/MPC8540ADS.h | 4 +- include/configs/MPC8541CDS.h | 4 +- include/configs/MPC8544DS.h | 5 +- include/configs/MPC8548CDS.h | 4 +- include/configs/MPC8555CDS.h | 4 +- include/configs/MPC8560ADS.h | 4 +- include/configs/MPC8568MDS.h | 4 +- include/configs/MPC8569MDS.h | 4 +- include/configs/MPC8572DS.h | 4 +- include/configs/P2020DS.h | 4 +- include/configs/XPEDITE5200.h | 1 + include/configs/XPEDITE5370.h | 1 + 27 files changed, 211 insertions(+), 171 deletions(-)

2 1

[U-Boot] [PATCH] at91cap9adk: fix #ifdef/#endif pairing
by Wolfgang Denk 23 Jul '09

23 Jul '09

The #ifdef/#endif pairing in this file was obviously messed up. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- include/configs/at91cap9adk.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index 526cd60..219eea3 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -123,7 +123,6 @@ /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#endif /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -131,6 +130,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 +#endif /* Ethernet */ #define CONFIG_MACB 1 -- 1.6.0.6

2 2

[U-Boot] arm, kirkwood: added kw_gpio_set_valid() in gpio.h
by Heiko Schocher 23 Jul '09

23 Jul '09

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- This patch needs the patch from: http://lists.denx.de/pipermail/u-boot/2009-July/055854.html first applied. include/asm-arm/arch-kirkwood/gpio.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h index cac58f4..aa880c0 100644 --- a/include/asm-arm/arch-kirkwood/gpio.h +++ b/include/asm-arm/arch-kirkwood/gpio.h @@ -37,6 +37,8 @@ /* * Kirkwood-specific GPIO API */ + +void kw_gpio_set_valid(unsigned pin, int mode); int kw_gpio_is_valid(unsigned pin, int mode); int kw_gpio_direction_input(unsigned pin); int kw_gpio_direction_output(unsigned pin, int value); -- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [PATCH1/2] Kirkwood: add Marvell Kirkwood gpio driver
by Dieter Kiermaier 23 Jul '09

23 Jul '09

Hi again, Here is my first out of 2 patches which adds gpio support to arch/kirkwood. Any suggestions? Cheers, Dieter From fcdea0c7bba3c25a1fb183bbcaf6d1a4ec32a157 Mon Sep 17 00:00:00 2001 From: Dieter Kiermaier <dk-arm-linux(a)gmx.de> Date: Mon, 29 Jun 2009 14:22:13 +0200 Subject: [PATCH] Kirkwood: add Marvell Kirkwood gpio driver Signed-off-by: Dieter Kiermaier <dk-arm-linux(a)gmx.de> --- drivers/gpio/Makefile | 1 + drivers/gpio/kw_gpio.c | 151 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-kirkwood/gpio.h | 51 ++++++++++++ 3 files changed, 203 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/kw_gpio.c create mode 100644 include/asm-arm/arch-kirkwood/gpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index f10144f..acba56c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libgpio.a +COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c new file mode 100644 index 0000000..f49d92c --- /dev/null +++ b/drivers/gpio/kw_gpio.c @@ -0,0 +1,151 @@ +/* + * arch/arm/plat-orion/gpio.c + * + * Marvell Orion SoC GPIO handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. + * Removed orion_gpiochip struct and kernel level irq handling. + * + * Dieter Kiermaier dk-arm-linux(a)gmx.de + */ + +#include <common.h> +#include <asm/bitops.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/gpio.h> + +static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; +static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; + +void __set_direction(unsigned pin, int input) +{ + u32 u; + + u = readl(GPIO_IO_CONF(pin)); + if (input) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_IO_CONF(pin)); + + u = readl(GPIO_IO_CONF(pin)); +} + +void __set_level(unsigned pin, int high) +{ + u32 u; + + u = readl(GPIO_OUT(pin)); + if (high) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_OUT(pin)); +} + +void __set_blinking(unsigned pin, int blink) +{ + u32 u; + + u = readl(GPIO_BLINK_EN(pin)); + if (blink) + u |= 1 << (pin & 31); + else + u &= ~(1 << (pin & 31)); + writel(u, GPIO_BLINK_EN(pin)); +} + +int kw_gpio_is_valid(unsigned pin, int mode) +{ + if (pin < GPIO_MAX) { + if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) + goto err_out; + + if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output)) + goto err_out; + return 0; + } + +err_out: + printf("%s: invalid GPIO %d\n", __func__, pin); + return 1; +} + +void kw_gpio_set_valid(unsigned pin, int mode) +{ + if (mode == 1) + mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; + if (mode & GPIO_INPUT_OK) + __set_bit(pin, gpio_valid_input); + else + __clear_bit(pin, gpio_valid_input); + if (mode & GPIO_OUTPUT_OK) + __set_bit(pin, gpio_valid_output); + else + __clear_bit(pin, gpio_valid_output); +} +/* + * GENERIC_GPIO primitives. + */ +int kw_gpio_direction_input(unsigned pin) +{ + if (!kw_gpio_is_valid(pin, GPIO_INPUT_OK)) + return 1; + + /* Configure GPIO direction. */ + __set_direction(pin, 1); + + return 0; +} + +int kw_gpio_direction_output(unsigned pin, int value) +{ + if (kw_gpio_is_valid(pin, GPIO_OUTPUT_OK) != 0) + { + printf("%s: invalid GPIO %d\n", __func__, pin); + return 1; + } + + __set_blinking(pin, 0); + + /* Configure GPIO output value. */ + __set_level(pin, value); + + /* Configure GPIO direction. */ + __set_direction(pin, 0); + + return 0; +} + +int kw_gpio_get_value(unsigned pin) +{ + int val; + + if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31))) + val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin)); + else + val = readl(GPIO_OUT(pin)); + + return (val >> (pin & 31)) & 1; +} + +void kw_gpio_set_value(unsigned pin, int value) +{ + /* Configure GPIO output value. */ + __set_level(pin, value); +} + +void kw_gpio_set_blink(unsigned pin, int blink) +{ + /* Set output value to zero. */ + __set_level(pin, 0); + + /* Set blinking. */ + __set_blinking(pin, blink); +} diff --git a/include/asm-arm/arch-kirkwood/gpio.h b/include/asm-arm/arch-kirkwood/gpio.h new file mode 100644 index 0000000..688149a --- /dev/null +++ b/include/asm-arm/arch-kirkwood/gpio.h @@ -0,0 +1,51 @@ +/* + * arch/asm-arm/mach-kirkwood/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. + * Removed kernel level irq handling. Took some macros from kernel to + * allow build. + * + * Dieter Kiermaier dk-arm-linux(a)gmx.de + */ + +#ifndef __KIRKWOOD_GPIO_H +#define __KIRKWOOD_GPIO_H + +/* got from kernel include/linux/kernel.h */ +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +/* got from kernel include/linux/bitops.h */ +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) + +#define GPIO_MAX 50 +#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) +#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) + +/* + * Kirkwood-specific GPIO API + */ +int kw_gpio_is_valid(unsigned pin, int mode); +int kw_gpio_direction_input(unsigned pin); +int kw_gpio_direction_output(unsigned pin, int value); +int kw_gpio_get_value(unsigned pin); +void kw_gpio_set_value(unsigned pin, int value); +void kw_gpio_set_blink(unsigned pin, int blink); +void kw_gpio_set_unused(unsigned pin); + +#define GPIO_INPUT_OK (1 << 0) +#define GPIO_OUTPUT_OK (1 << 1) + +#endif -- 1.5.4.3

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[U-Boot] arm, kirkwood: added KW_TWSI_BASE in kirkwood.h
by Heiko Schocher 23 Jul '09

23 Jul '09

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- include/asm-arm/arch-kirkwood/kirkwood.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h index 47679dd..2470efb 100644 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -44,6 +44,7 @@ #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) +#define KW_TWSI_BASE (KW_REGISTER(0x11000)) #define KW_UART0_BASE (KW_REGISTER(0x12000)) #define KW_UART1_BASE (KW_REGISTER(0x12100)) #define KW_MPP_BASE (KW_REGISTER(0x10000)) -- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [PATCH 6/6][repost] Marvell RD6281A Board support
by Prafulla Wadaskar 23 Jul '09

23 Jul '09

This is Marvell's 88F6281_A0 based reference design board This patch is tested for- 1. Boot from DRAM/NAND flash/NFS 2. File transfer using tftp and loadb 3. NAND flash read/write/erase Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Change log: Sorry.. One commit was missing... MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/Marvell/rd6281a/Makefile | 51 ++++++++++ board/Marvell/rd6281a/config.mk | 25 +++++ board/Marvell/rd6281a/rd6281a.c | 179 +++++++++++++++++++++++++++++++++++ board/Marvell/rd6281a/rd6281a.h | 41 ++++++++ include/configs/rd6281a.h | 198 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 499 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/rd6281a/Makefile create mode 100644 board/Marvell/rd6281a/config.mk create mode 100644 board/Marvell/rd6281a/rd6281a.c create mode 100644 board/Marvell/rd6281a/rd6281a.h create mode 100644 include/configs/rd6281a.h diff --git a/MAINTAINERS b/MAINTAINERS index 76268b4..ff587e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -676,6 +676,7 @@ Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> Prafulla Wadaskar <prafulla(a)marvell.com> mv88f6281gtw_ge ARM926EJS (Kirkwood SoC) + rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) Richard Woodruff <r-woodruff2(a)ti.com> diff --git a/MAKEALL b/MAKEALL index 4e1f431..3d7e4da 100755 --- a/MAKEALL +++ b/MAKEALL @@ -521,6 +521,7 @@ LIST_ARM9=" \ omap1610inn \ omap5912osk \ omap730p2 \ + rd6281a \ sbc2410x \ scb9328 \ sheevaplug \ diff --git a/Makefile b/Makefile index b4d8c80..3a011c8 100644 --- a/Makefile +++ b/Makefile @@ -2921,6 +2921,9 @@ omap730p2_cs3boot_config : unconfig fi; @$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap +rd6281a_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood + sbc2410x_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile new file mode 100644 index 0000000..907dd7d --- /dev/null +++ b/board/Marvell/rd6281a/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := rd6281a.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Marvell/rd6281a/config.mk b/board/Marvell/rd6281a/config.mk new file mode 100644 index 0000000..a4ea769 --- /dev/null +++ b/board/Marvell/rd6281a/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +TEXT_BASE = 0x00600000 diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c new file mode 100644 index 0000000..8713a3c --- /dev/null +++ b/board/Marvell/rd6281a/rd6281a.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "rd6281a.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(RD6281A_OE_VAL_LOW, + RD6281A_OE_VAL_HIGH, + RD6281A_OE_LOW, RD6281A_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GPIO, + MPP36_AUDIO_SPDIFI, + MPP37_AUDIO_SPDIFO, + MPP38_GPIO, + MPP39_TDM_SPI_CS0, + MPP40_TDM_SPI_SCK, + MPP41_TDM_SPI_MISO, + MPP42_TDM_SPI_MOSI, + MPP43_TDM_CODEC_INTn, + MPP44_GPIO, + MPP45_TDM_PCLK, + MPP46_TDM_FS, + MPP47_TDM_DRX, + MPP48_TDM_DTX, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + /* + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_RD88F6281; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +int dram_init(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + } + return 0; +} + +void mv_phy_88e1116_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __FUNCTION__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + if (miiphy_read (name, devadr, PHY_BMCR, &reg) != 0) { + printf("Err..(%s) PHY status read failed\n", __FUNCTION__); + return; + } + if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) { + printf("Err..(%s) PHY reset failed\n", __FUNCTION__); + return; + } + + printf("88E1116 Initialized on %s\n", name); +} + +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* configure and initialize switch */ + struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = (1 << 5), + .ports_enabled = 0x3f, + }; + + mv88e61xx_switch_initialize(&swcfg); + + /* configure and initialize PHY */ + mv_phy_88e1116_init("egiga1"); +} diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h new file mode 100644 index 0000000..c978bef --- /dev/null +++ b/board/Marvell/rd6281a/rd6281a.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __RD6281A_H +#define __RD6281A_H + +#define RD6281A_OE_LOW (~(1 << 7)) +#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12)) +#define RD6281A_OE_VAL_LOW (0) +#define RD6281A_OE_VAL_HIGH (1 << 12) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __RD6281A_H */ diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h new file mode 100644 index 0000000..ef16579 --- /dev/null +++ b/include/configs/rd6281a.h @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_RD6281A_H +#define _CONFIG_RD6281A_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nMarvell-RD6281A" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_RD6281A /* Machine type */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \ + "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */ +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */ +#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */ +#define CONFIG_PHY_BASE_ADR 0x0A +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch and PHY */ +#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +#endif /* _CONFIG_RD6281A_H */ -- 1.5.3.3

2 1

[U-Boot] [PATCH] api: Fix broken build on ARM.
by Piotr Ziecik 23 Jul '09

23 Jul '09

This patch fixes broken build introduced by commit 84bf7ca522e94ec402a1264b01971b924b7e268f (api: remove un-needed ifdef CONFIG_API already handle by the Makefile). Signed-off-by: Piotr Ziecik <kosmo(a)semihalf.com> --- api/api_platform-arm.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/api/api_platform-arm.c b/api/api_platform-arm.c index fffaa1e..e65a180 100644 --- a/api/api_platform-arm.c +++ b/api/api_platform-arm.c @@ -53,5 +53,3 @@ int platform_sys_info(struct sys_info *si) return 1; } - -#endif /* CONFIG_API */ -- 1.6.3.1

2 1

[U-Boot] [PATCH] OneNAND IPL: Move u-boot-onenand linker script to common use
by Kyungmin Park 22 Jul '09

22 Jul '09

Use the common OneNAND linker script. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/onenand_ipl/board/apollon/u-boot.onenand.lds b/onenand_ipl/u-boot-onenand.lds similarity index 100% rename from onenand_ipl/board/apollon/u-boot.onenand.lds rename to onenand_ipl/u-boot-onenand.lds

4 7

[U-Boot] Zoom hw reset
by Tom Rix 22 Jul '09

22 Jul '09

For arm/next This patch enables hw resetting of zoom1 and zoom2. This is done through the twl4030 part. Since this part is not currently supported, start an twl4030_i2c device. In testing it was found that I2C was broken on Zoom1 and Zoom2. I2C was fixed by improving the initialization of its sampling clock. The reset changes were run tested on zoom1 and zoom2. The I2C changes were run tested on zoom1, zoom2, beagle and overo. The 400kHz case was run tested on a variant of the zoom1 configuration.

9 43

[U-Boot] [PATCH] ARM Cortex A8: Move OMAP3 specific reset handler
by Minkyu Kang 22 Jul '09

22 Jul '09

Because of the reset_cpu is soc specific, should be move to soc Cc: Dirk Behme <dirk.behme(a)googlemail.com> Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> --- cpu/arm_cortexa8/omap3/Makefile | 1 + cpu/arm_cortexa8/omap3/reset.S | 36 ++++++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/start.S | 14 -------------- 3 files changed, 37 insertions(+), 14 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/reset.S diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index 1fbd0dc..eef165c 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o +SOBJS += reset.o COBJS += board.o COBJS += cache.o diff --git a/cpu/arm_cortexa8/omap3/reset.S b/cpu/arm_cortexa8/omap3/reset.S new file mode 100644 index 0000000..a53c408 --- /dev/null +++ b/cpu/arm_cortexa8/omap3/reset.S @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2009 Samsung Electronics. + * Minkyu Kang <mk7.kang(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.global reset_cpu +reset_cpu: + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PRM_RSTCTRL diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S index 66b4820..6bd6552 100644 --- a/cpu/arm_cortexa8/start.S +++ b/cpu/arm_cortexa8/start.S @@ -500,17 +500,3 @@ finished_inval: @ but we compile with armv5 ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} - - - .align 5 -.global reset_cpu -reset_cpu: - ldr r1, rstctl @ get addr for global reset - @ reg - mov r3, #0x2 @ full reset pll + mpu - str r3, [r1] @ force reset - mov r0, r0 -_loop_forever: - b _loop_forever -rstctl: - .word PRM_RSTCTRL -- 1.5.4.3

4 3