May 2009 - U-Boot

[U-Boot] QUESTION: How do I generate an assembly listing?
by Jonathan Haws 07 May '09

07 May '09

I need to generate an assembly listing that contains all the assembly code generated by the compiler. I have tried putting the standard GCC options in ppc_config.mk, but cannot get the results I am looking for. What I need is a listing file that contains the address (preferably with _start at 0x00000000) and the function name and any assembly code with their respective addresses. Can this easily be done? -- Jonathan R. Haws Electrical Engineering Space Dynamics Laboratory Jonathan.Haws(a)sdl.usu.edu (435)797-4629

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[U-Boot] MII register display
by Jon Smirl 07 May '09

07 May '09

Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly? uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0000) 0. 8 = 0 duplex = half (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved) Definition from Linux: /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ #define BMCR_RESET 0x8000 /* Reset the DP83840 */ uboot> mii dump 0 1 1. (786d) -- PHY status register -- (8000:0000) 1.15 = 0 100BASE-T4 able (4000:4000) 1.14 = 1 100BASE-X full duplex able (2000:2000) 1.13 = 1 100BASE-X half duplex able (1000:1000) 1.12 = 1 10 Mbps full duplex able (0800:0800) 1.11 = 1 10 Mbps half duplex able (0400:0000) 1.10 = 0 100BASE-T2 full duplex able (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able (0100:0000) 1. 8 = 0 extended status (0080:0000) 1. 7 = 0 (reserved) (0040:0040) 1. 6 = 1 MF preamble suppression (0020:0020) 1. 5 = 1 A/N complete (0010:0000) 1. 4 = 0 remote fault (0008:0008) 1. 3 = 1 A/N able (0004:0004) 1. 2 = 1 link status (0002:0000) 1. 1 = 0 jabber detect (0001:0001) 1. 0 = 1 extended capabilities uboot> mii dump 0 2 2. (0022) -- PHY ID 1 register -- (ffff:0022) 2.15- 0 = 34 OUI portion uboot> mii dump 0 3 3. (161a) -- PHY ID 2 register -- (fc00:1400) 3.15-10 = 5 OUI portion (03f0:0210) 3. 9- 4 = 33 manufacturer part number (000f:000a) 3. 3- 0 = 10 manufacturer rev. number uboot> mii dump 0 4 4. (01e1) -- Autonegotiation advertisement register -- (8000:0000) 4.15 = 0 next page able (4000:0000) 4.14 = 0 reserved (2000:0000) 4.13 = 0 remote fault (1000:0000) 4.12 = 0 reserved (0800:0000) 4.11 = 0 asymmetric pause (0400:0000) 4.10 = 0 pause enable (0200:0000) 4. 9 = 0 100BASE-T4 able (0100:0100) 4. 8 = 1 100BASE-TX full duplex able (0080:0080) 4. 7 = 1 100BASE-TX able (0040:0040) 4. 6 = 1 10BASE-T full duplex able (0020:0020) 4. 5 = 1 10BASE-T able (001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3 uboot> mii dump 0 5 5. (c5e1) -- Autonegotiation partner abilities register -- (8000:8000) 5.15 = 1 next page able (4000:4000) 5.14 = 1 acknowledge (2000:0000) 5.13 = 0 remote fault (1000:0000) 5.12 = 0 (reserved) (0800:0000) 5.11 = 0 asymmetric pause able (0400:0400) 5.10 = 1 pause able (0200:0000) 5. 9 = 0 100BASE-T4 able (0100:0100) 5. 8 = 1 100BASE-X full duplex able (0080:0080) 5. 7 = 1 100BASE-TX able (0040:0040) 5. 6 = 1 10BASE-T full duplex able (0020:0020) 5. 5 = 1 10BASE-T able (001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3 uboot> -- Jon Smirl jonsmirl(a)gmail.com

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[U-Boot] About PCI of U-BOOT of CANYONLANDS
by Kazuaki Ichinohe 07 May '09

07 May '09

Hello! I am testing the video display of U-BOOT by using PCI of CANYONLANDS. I added the following lines. #ifdef CONFIG_VIDEO #define CONFIG_BIOSEMU #define CONFIG_ATI_RADEON_FB #define VIDEO_IO_OFFSET 0xD8000000 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VIDEO_LOGO #define CONFIG_CFB_CONSOLE #define CONFIG_SPLASH_SCREEN #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_CMD_BMP #endif /* #ifdef CONFIG_VIDEO */ However, if the memory space of PCI is read, the exception is generated. Do you have any information for PCI of U-BOOT of CANYONLANDS? Regards, Kazuaki Ichinohe.

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[U-Boot] Micrel Switch KS8995M Driver
by Raphael Amorim 07 May '09

07 May '09

Hello all, I need some help here :P I'm trying to add a driver for a KS8995M ethernet switch, I found one at OpenWRT. Has anyone here ever included a driver for this ethernet device on u-boot? Thanks in advance. Raphael Amorim

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[U-Boot] AWARD WINNER!!!
by Kruse, Mary M. 07 May '09

07 May '09

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1 0

[U-Boot] [PATCH] arm: rename timer init callback timer_init
by Jean-Christophe PLAGNIOL-VILLARD 06 May '09

06 May '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- board/armltd/integratorap/integratorap.c | 2 +- board/armltd/integratorcp/integratorcp.c | 2 +- board/atmel/at91cap9adk/at91cap9adk.c | 1 - board/davinci/common/misc.h | 1 - board/m501sk/m501sk.c | 2 - board/netstar/netstar.c | 2 +- board/voiceblue/voiceblue.c | 2 +- cpu/arm1136/mx31/Makefile | 3 +- cpu/arm1136/mx31/{interrupts.c => timer.c} | 3 +- cpu/arm1136/omap24xx/Makefile | 3 +- cpu/arm1136/omap24xx/{interrupts.c => timer.c} | 3 +- cpu/arm1176/s3c64xx/Makefile | 2 +- cpu/arm1176/s3c64xx/{interrupts.c => timer.c} | 2 +- cpu/arm720t/interrupts.c | 46 ++++++++++-------- cpu/arm920t/at91rm9200/Makefile | 2 +- cpu/arm920t/at91rm9200/{interrupts.c => timer.c} | 2 +- cpu/arm920t/imx/Makefile | 4 +- cpu/arm920t/imx/{interrupts.c => timer.c} | 2 +- cpu/arm920t/ks8695/Makefile | 3 +- cpu/arm920t/ks8695/{interrupts.c => timer.c} | 12 ++--- cpu/arm920t/s3c24x0/Makefile | 5 ++- cpu/arm920t/s3c24x0/{interrupts.c => timer.c} | 2 +- cpu/arm925t/Makefile | 5 ++- cpu/arm925t/{interrupts.c => timer.c} | 2 +- cpu/arm926ejs/Makefile | 2 +- cpu/arm926ejs/interrupts.c | 57 ---------------------- cpu/arm_cortexa8/omap3/Makefile | 8 +++- cpu/arm_cortexa8/omap3/{interrupts.c => timer.c} | 3 +- cpu/ixp/Makefile | 6 +-- cpu/ixp/interrupts.c | 55 ++++----------------- cpu/ixp/timer.c | 54 ++++++++++++++++++++ cpu/lh7a40x/interrupts.c | 2 +- cpu/pxa/Makefile | 8 +++- cpu/pxa/{interrupts.c => timer.c} | 7 ++- cpu/s3c44b0/Makefile | 5 ++- cpu/s3c44b0/{interrupts.c => timer.c} | 2 +- cpu/sa1100/Makefile | 4 +- cpu/sa1100/{interrupts.c => timer.c} | 5 +- include/asm-arm/u-boot-arm.h | 3 + include/configs/ixdpg425.h | 1 + include/configs/pdnb3.h | 1 + lib_arm/board.c | 5 ++- 42 files changed, 166 insertions(+), 175 deletions(-) rename cpu/arm1136/mx31/{interrupts.c => timer.c} (97%) rename cpu/arm1136/omap24xx/{interrupts.c => timer.c} (97%) rename cpu/arm1176/s3c64xx/{interrupts.c => timer.c} (99%) rename cpu/arm920t/at91rm9200/{interrupts.c => timer.c} (99%) rename cpu/arm920t/imx/{interrupts.c => timer.c} (99%) rename cpu/arm920t/ks8695/{interrupts.c => timer.c} (93%) rename cpu/arm920t/s3c24x0/{interrupts.c => timer.c} (99%) rename cpu/arm925t/{interrupts.c => timer.c} (99%) delete mode 100644 cpu/arm926ejs/interrupts.c rename cpu/arm_cortexa8/omap3/{interrupts.c => timer.c} (97%) rename cpu/pxa/{interrupts.c => timer.c} (96%) rename cpu/s3c44b0/{interrupts.c => timer.c} (98%) rename cpu/sa1100/{interrupts.c => timer.c} (95%) diff --git a/board/armltd/integratorap/integratorap.c b/board/armltd/integratorap/integratorap.c index 9631967..5ececd6 100644 --- a/board/armltd/integratorap/integratorap.c +++ b/board/armltd/integratorap/integratorap.c @@ -540,7 +540,7 @@ static ulong div_timer = 1; /* Divisor to convert timer reading * - the Integrator/AP timer issues an interrupt * each time it reaches zero */ -int interrupt_init (void) +int timer_init (void) { /* Load timer with initial value */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; diff --git a/board/armltd/integratorcp/integratorcp.c b/board/armltd/integratorcp/integratorcp.c index 72629ce..0d3afd8 100644 --- a/board/armltd/integratorcp/integratorcp.c +++ b/board/armltd/integratorcp/integratorcp.c @@ -163,7 +163,7 @@ static ulong timestamp; /* U-Boot ticks since startup */ /* starts up a counter * - the Integrator/CP timer can be set up to issue an interrupt */ -int interrupt_init (void) +int timer_init (void) { /* Load timer with initial value */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index e8025e7..8f7fd28 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -60,7 +60,6 @@ static void at91cap9_slowclock_hw_init(void) if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) { unsigned i, tmp = at91_sys_read(AT91_SCKCR); if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) { - extern void timer_init(void); timer_init(); tmp |= AT91CAP9_SCKCR_OSC32EN; at91_sys_write(AT91_SCKCR, tmp); diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index 4a57dbb..5d29784 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -22,7 +22,6 @@ #ifndef __MISC_H #define __MISC_H -extern void timer_init(void); extern int eth_hw_init(void); void dv_display_clk_infos(void); diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c index dc5b786..d6881e9 100644 --- a/board/m501sk/m501sk.c +++ b/board/m501sk/m501sk.c @@ -126,8 +126,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; m501sk_gpio_init(); - /* Do interrupt init here, because flash needs timers */ - interrupt_init(); flash_init(); return 0; diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c index ee4f2cd..ffd60bf 100644 --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -48,7 +48,7 @@ int dram_init(void) /* Take the Ethernet controller out of reset and wait * for the EEPROM load to complete. */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before interrupt_init call */ + udelay(10); /* doesn't work before timer_init call */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; udelay(500); diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c index c8dde36..59b3310 100644 --- a/board/voiceblue/voiceblue.c +++ b/board/voiceblue/voiceblue.c @@ -43,7 +43,7 @@ int dram_init(void) /* Take the Ethernet controller out of reset and wait * for the EEPROM load to complete. */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before interrupt_init call */ + udelay(10); /* doesn't work before timer_init call */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; udelay(500); diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index 0e06f0a..1e49e8d 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o generic.o +COBJS += generic.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/timer.c similarity index 97% rename from cpu/arm1136/mx31/interrupts.c rename to cpu/arm1136/mx31/timer.c index ab7202f..29b484e 100644 --- a/cpu/arm1136/mx31/interrupts.c +++ b/cpu/arm1136/mx31/timer.c @@ -89,9 +89,8 @@ static inline unsigned long long us_to_tick(unsigned long long us) } #endif -/* nothing really to do with interrupts, just starts up a counter. */ /* The 32768Hz 32-bit timer overruns in 131072 seconds */ -int interrupt_init (void) +int timer_init (void) { int i; diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile index f9afed7..2a79d9b 100644 --- a/cpu/arm1136/omap24xx/Makefile +++ b/cpu/arm1136/omap24xx/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o SOBJS = start.o +COBJS = timer.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/timer.c similarity index 97% rename from cpu/arm1136/omap24xx/interrupts.c rename to cpu/arm1136/omap24xx/timer.c index 6be1262..aef0b13 100644 --- a/cpu/arm1136/omap24xx/interrupts.c +++ b/cpu/arm1136/omap24xx/timer.c @@ -42,8 +42,7 @@ static ulong timestamp; static ulong lastinc; -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) +int timer_init (void) { int32_t val; diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile index fa4ee3f..4656d9a 100644 --- a/cpu/arm1176/s3c64xx/Makefile +++ b/cpu/arm1176/s3c64xx/Makefile @@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS-y = interrupts.o COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o +COBJS-y += timer.o OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/timer.c similarity index 99% rename from cpu/arm1176/s3c64xx/interrupts.c rename to cpu/arm1176/s3c64xx/timer.c index 83f3806..e3de1dc 100644 --- a/cpu/arm1176/s3c64xx/interrupts.c +++ b/cpu/arm1176/s3c64xx/timer.c @@ -66,7 +66,7 @@ static unsigned long lastdec; /* Monotonic incrementing timer */ static unsigned long long timestamp; -int interrupt_init(void) +int timer_init(void) { s3c64xx_timers *const timers = s3c64xx_get_base_timers(); diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..ff21314 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -110,9 +110,34 @@ static void timer_isr( void *data) { static ulong timestamp; static ulong lastdec; +#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B) int interrupt_init (void) { + int i; + + /* install default interrupt handlers */ + for ( i = 0; i < N_IRQS; i++) { + IRQ_HANDLER[i].m_data = (void *)i; + IRQ_HANDLER[i].m_func = default_isr; + } + + /* configure interrupts for IRQ mode */ + PUT_REG( REG_INTMODE, 0x0); + /* clear any pending interrupts */ + PUT_REG( REG_INTPEND, 0x1FFFFF); + + lastdec = 0; + + /* install interrupt handler for timer */ + IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp; + IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; + + return 0; +} +#endif +int timer_init (void) +{ #if defined(CONFIG_NETARM) /* disable all interrupts */ IRQEN = 0; @@ -137,25 +162,6 @@ int interrupt_init (void) /* set timer 1 counter */ lastdec = IO_TC1D = TIMER_LOAD_VAL; #elif defined(CONFIG_S3C4510B) - int i; - - /* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); - /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); - - lastdec = 0; - - /* install interrupt handler for timer */ - IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp; - IRQ_HANDLER[INT_TIMER0].m_func = timer_isr; - /* configure free running timer 0 */ PUT_REG( REG_TMOD, 0x0); /* Stop timer 0 */ @@ -187,7 +193,7 @@ int interrupt_init (void) PUT32(T0TCR, 1); /* enable timer0 */ #else -#error No interrupt_init() defined for this CPU type +#error No timer_init() defined for this CPU type #endif timestamp = 0; diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index 161ca94..73aeeac 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -31,10 +31,10 @@ COBJS += bcm5221.o COBJS += dm9161.o COBJS += ether.o COBJS += i2c.o -COBJS += interrupts.o COBJS += lxt972.o COBJS += reset.o COBJS += spi.o +COBJS += timer.o COBJS += usb.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/timer.c similarity index 99% rename from cpu/arm920t/at91rm9200/interrupts.c rename to cpu/arm920t/at91rm9200/timer.c index 4c38a9a..235d107 100644 --- a/cpu/arm920t/at91rm9200/interrupts.c +++ b/cpu/arm920t/at91rm9200/timer.c @@ -45,7 +45,7 @@ AT91PS_TC tmr; static ulong timestamp; static ulong lastinc; -int interrupt_init (void) +int timer_init (void) { tmr = AT91C_BASE_TC0; diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile index d3352de..28945e2 100644 --- a/cpu/arm920t/imx/Makefile +++ b/cpu/arm920t/imx/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = generic.o interrupts.o speed.o +COBJS += generic.o +COBJS += speed.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/timer.c similarity index 99% rename from cpu/arm920t/imx/interrupts.c rename to cpu/arm920t/imx/timer.c index ddcfb34..09b4eaf 100644 --- a/cpu/arm920t/imx/interrupts.c +++ b/cpu/arm920t/imx/timer.c @@ -35,7 +35,7 @@ #include <arm920t.h> #include <asm/arch/imx-regs.h> -int interrupt_init (void) +int timer_init (void) { int i; /* setup GP Timer 1 */ diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile index f6b0063..f53fdc2 100644 --- a/cpu/arm920t/ks8695/Makefile +++ b/cpu/arm920t/ks8695/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o SOBJS = lowlevel_init.o +COBJS = timer.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/timer.c similarity index 93% rename from cpu/arm920t/ks8695/interrupts.c rename to cpu/arm920t/ks8695/timer.c index 883d689..22987bc 100644 --- a/cpu/arm920t/ks8695/interrupts.c +++ b/cpu/arm920t/ks8695/timer.c @@ -29,13 +29,13 @@ #define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) #define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) -int timer_inited; ulong timer_ticks; -int interrupt_init (void) +int timer_init (void) { - /* nothing happens here - we don't setup any IRQs */ - return (0); + reset_timer(); + + return 0; } /* @@ -53,7 +53,6 @@ void reset_timer_masked(void) ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); ks8695_write(KS8695_TIMER_CTRL, 0x2); timer_ticks = 0; - timer_inited++; } void reset_timer(void) @@ -87,9 +86,6 @@ void udelay(ulong usec) ulong start = get_timer_masked(); ulong end; - if (!timer_inited) - reset_timer(); - /* Only 1ms resolution :-( */ end = usec / 1000; while (get_timer(start) < end) diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 3afe19c..5d2be2c 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o speed.o usb.o usb_ohci.o +COBJS += speed.o +COBJS += timer.o +COBJS += usb.o +COBJS += usb_ohci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/timer.c similarity index 99% rename from cpu/arm920t/s3c24x0/interrupts.c rename to cpu/arm920t/s3c24x0/timer.c index 11e6804..328c652 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -52,7 +52,7 @@ static inline ulong READ_TIMER(void) static ulong timestamp; static ulong lastdec; -int interrupt_init (void) +int timer_init (void) { S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS(); diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile index 0d4912c..8d0e88f 100644 --- a/cpu/arm925t/Makefile +++ b/cpu/arm925t/Makefile @@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o omap925.o + +COBJS += cpu.o +COBJS += omap925.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/timer.c similarity index 99% rename from cpu/arm925t/interrupts.c rename to cpu/arm925t/timer.c index e5c77f7..9e45031 100644 --- a/cpu/arm925t/interrupts.c +++ b/cpu/arm925t/timer.c @@ -43,7 +43,7 @@ static uint32_t timestamp; static uint32_t lastdec; /* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) +int timer_init (void) { /* Start the decrementer ticking down from 0xffffffff */ __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index d5ac7d3..7701b03 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o +COBJS = cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c deleted file mode 100644 index 7a41f0b..0000000 --- a/cpu/arm926ejs/interrupts.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <arm926ejs.h> - -#ifdef CONFIG_INTEGRATOR - - /* Timer functionality supplied by Integrator board (AP or CP) */ - -#else - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - extern void timer_init(void); - - timer_init(); - - return 0; -} - -#endif /* CONFIG_INTEGRATOR */ diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index b96b3dd..edf5cb2 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o -COBJS := sys_info.o board.o clock.o interrupts.o mem.o syslib.o + +COBJS += board.o +COBJS += clock.o +COBJS += mem.o +COBJS += syslib.o +COBJS += sys_info.o +COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/timer.c similarity index 97% rename from cpu/arm_cortexa8/omap3/interrupts.c rename to cpu/arm_cortexa8/omap3/timer.c index e0b3fbc..5d480b9 100644 --- a/cpu/arm_cortexa8/omap3/interrupts.c +++ b/cpu/arm_cortexa8/omap3/timer.c @@ -41,8 +41,7 @@ static ulong timestamp; static ulong lastinc; static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init(void) +int timer_init(void) { /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile index a673cb1..1403c4f 100644 --- a/cpu/ixp/Makefile +++ b/cpu/ixp/Makefile @@ -26,12 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o + COBJS-y += cpu.o -ifndef CONFIG_USE_IRQ +COBJS-$(CONFIG_USE_IRQ) += interrupts.o COBJS-y += timer.o -else -COBJS-y += interrupts.o -endif SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index ee0129e..a05e439 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -33,14 +33,6 @@ #include <asm/arch/ixp425.h> #include <asm/proc-armv/ptrace.h> -/* - * When interrupts are enabled, use timer 2 for time/delay generation... - */ - -#define FREQ 66666666 -#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) -#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ - struct _irq_handler { void *m_data; void (*m_func)( void *data); @@ -48,8 +40,6 @@ struct _irq_handler { static struct _irq_handler IRQ_HANDLER[N_IRQS]; -static volatile ulong timestamp; - static void default_isr(void *data) { printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", @@ -61,33 +51,20 @@ static int next_irq(void) return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1); } -static void timer_isr(void *data) -{ - unsigned int *pTime = (unsigned int *)data; - - (*pTime)++; - - /* - * Reset IRQ source - */ - *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; -} - -ulong get_timer (ulong base) +void do_irq (struct pt_regs *pt_regs) { - return timestamp - base; -} + int irq = next_irq(); -void reset_timer (void) -{ - timestamp = 0; + IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); } -void do_irq (struct pt_regs *pt_regs) +void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) { - int irq = next_irq(); + if (irq >= N_IRQS || !handle_irq) + return; - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); + IRQ_HANDLER[irq].m_data = data; + IRQ_HANDLER[irq].m_func = handle_irq; } int interrupt_init (void) @@ -95,23 +72,11 @@ int interrupt_init (void) int i; /* install default interrupt handlers */ - for (i = 0; i < N_IRQS; i++) { - IRQ_HANDLER[i].m_data = (void *)i; - IRQ_HANDLER[i].m_func = default_isr; - } - - /* install interrupt handler for timer */ - IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_data = (void *)&timestamp; - IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_func = timer_isr; - - /* setup the Timer counter value */ - *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + for (i = 0; i < N_IRQS; i++) + irq_install_handler(i, default_isr, (void *)i); /* configure interrupts for IRQ mode */ *IXP425_ICLR = 0x00000000; - /* enable timer irq */ - *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); - return (0); } diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c index deb227a..6856149 100644 --- a/cpu/ixp/timer.c +++ b/cpu/ixp/timer.c @@ -32,6 +32,54 @@ #include <common.h> #include <asm/arch/ixp425.h> +#ifdef CONFIG_TIMER_IRQ + +#define FREQ 66666666 +#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ) +#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */ + +/* + * When interrupts are enabled, use timer 2 for time/delay generation... + */ + +static volatile ulong timestamp; + +static void timer_isr(void *data) +{ + unsigned int *pTime = (unsigned int *)data; + + (*pTime)++; + + /* + * Reset IRQ source + */ + *IXP425_OSST = IXP425_OSST_TIMER_2_PEND; +} + +ulong get_timer (ulong base) +{ + return timestamp - base; +} + +void reset_timer (void) +{ + timestamp = 0; +} + +int timer_init (void) +{ + /* install interrupt handler for timer */ + irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp); + + /* setup the Timer counter value */ + *IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE; + + /* enable timer irq */ + *IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ); + + return 0; +} +#else ulong get_timer (ulong base) { return get_timer_masked () - base; @@ -79,3 +127,9 @@ ulong get_timer_masked (void) } return (reload_constant - current); } + +int timer_init(void) +{ + return 0; +} +#endif diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c index 5acfe1a..91ca6a9 100644 --- a/cpu/lh7a40x/interrupts.c +++ b/cpu/lh7a40x/interrupts.c @@ -47,7 +47,7 @@ static inline ulong READ_TIMER(void) static ulong timestamp; static ulong lastdec; -int interrupt_init (void) +int timer_init (void) { lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR; lh7a40x_timer_t* timer = &timers->timer1; diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile index 42903b2..5dc3a52 100644 --- a/cpu/pxa/Makefile +++ b/cpu/pxa/Makefile @@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o usb.o + +COBJS += cpu.o +COBJS += i2c.o +COBJS += pxafb.o +COBJS += serial.o +COBJS += timer.o +COBJS += usb.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/timer.c similarity index 96% rename from cpu/pxa/interrupts.c rename to cpu/pxa/timer.c index 2bc5c50..e2df3a5 100644 --- a/cpu/pxa/interrupts.c +++ b/cpu/pxa/timer.c @@ -56,10 +56,11 @@ static inline unsigned long long us_to_tick(unsigned long long us) return us; } -int interrupt_init (void) +int timer_init (void) { - /* nothing happens here - we don't setup any IRQs */ - return (0); + reset_timer(); + + return 0; } void reset_timer (void) diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile index ae909a6..6da2016 100644 --- a/cpu/s3c44b0/Makefile +++ b/cpu/s3c44b0/Makefile @@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = cache.o cpu.o interrupts.o + +COBJS += cache.o +COBJS += cpu.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/timer.c similarity index 98% rename from cpu/s3c44b0/interrupts.c rename to cpu/s3c44b0/timer.c index eb23e6a..34184ab 100644 --- a/cpu/s3c44b0/interrupts.c +++ b/cpu/s3c44b0/timer.c @@ -40,7 +40,7 @@ static ulong timestamp; static ulong lastdec; -int interrupt_init (void) +int timer_init (void) { TCFG0 = 0x000000E9; TCFG1 = 0x00000004; diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile index fd696f7..28b6682 100644 --- a/cpu/sa1100/Makefile +++ b/cpu/sa1100/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o + +COBJS += cpu.o +COBJS += timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/timer.c similarity index 95% rename from cpu/sa1100/interrupts.c rename to cpu/sa1100/timer.c index 2eff045..3f77e81 100644 --- a/cpu/sa1100/interrupts.c +++ b/cpu/sa1100/timer.c @@ -29,10 +29,9 @@ #include <common.h> #include <SA-1100.h> -int interrupt_init (void) +int timer_init (void) { - /* nothing happens here - we don't setup any IRQs */ - return (0); + return 0; } void reset_timer (void) diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 4ee5a32..32af927 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -59,4 +59,7 @@ void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); +/* cpu/.../timer.c */ +int timer_init (void); + #endif /* _U_BOOT_ARM_H_ */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 75707e5..0c09234 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -55,6 +55,7 @@ */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ +#define CONFIG_TIMER_IRQ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index edaa81b..1255f21 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -51,6 +51,7 @@ * Misc configuration options */ #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ +#define CONFIG_TIMER_IRQ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ diff --git a/lib_arm/board.c b/lib_arm/board.c index 3dfaec0..54a46ae 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -262,8 +262,11 @@ int print_cpuinfo (void); /* test-only */ init_fnc_t *init_sequence[] = { cpu_init, /* basic cpu dependent setup */ - board_init, /* basic board dependent setup */ +#if defined(CONFIG_USE_IRQ) interrupt_init, /* set up exceptions */ +#endif + timer_init, /* initialize timer */ + board_init, /* basic board dependent setup */ env_init, /* initialize environment */ init_baudrate, /* initialze baudrate settings */ serial_init, /* serial communications setup */ -- 1.6.2.1

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[U-Boot] AMCC 405EX Register Definitions
by Jonathan Haws 06 May '09

06 May '09

It is my understanding that the 405EX CPU is not Book-E, however in include/asm-ppc/processor.h line 390, Book-E definitions are used for the 405EX. Is this correct? I am still trying to debug the cause of the AMCC 405EX Trap (see that thread for more info) and found this. I was trying to see if SRR2 is being displayed in the register dump when I get the machine check on my board. >From what I can tell, the 405EX does not have a CSRR0/1, but the SRR2/3 registers have the same functionality. Elsewhere in the code, that is noted and csrr0/1 are defined. Yet, the exception code that is executed, utilizes the Book-E definitions in processor.h. Again I ask, is this correct? It would seem like there should be a compiler directive that determines which definitions to use and define SPRN_CSRR0 to SRR2 and SPRN_CSRR1 to SRR3 and so on for the 34 Book-E definitions defined. Am I correct in my thinking or am I way off? Either way, please let me know. If this is a bug, it should be easily fixed. Thanks! Jonathan -- Jonathan R. Haws Electrical Engineering Space Dynamics Laboratory Jonathan.Haws(a)sdl.usu.edu (435)797-4629

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[U-Boot] Xilinx SPI driver
by Seyyed Mohammad Sajjadi 06 May '09

06 May '09

Hi After searching internet for a good example of using U-boot PPC405 in xilinx FPGAs with only a SPI Flash, and finding nothing, I began writing my own driver. I used a couple of standalone examples besides the linux driver as the base point, and could finally use it. As much as I have tested the system, it is working fine with a m25p64 spi flash. Now I would be happy to share the driver, but haven't done such a thing previously. I am not even much familiar with patch! Is there any document telling the procedure? Besides I have developed board support for suaku V sz410 board, and a simplistic driver for xilinx frame buffer core too (which is not as much tested as the spi driver). Should I submit them too? Regards S. M. Sajjadi

2 1

[U-Boot] SD Card Support
by Raphael Amorim 06 May '09

06 May '09

Hey guys, Is anyone working on adding SD card support to U-Boot? Thanks in advance. Raphael Amorim

2 1

[U-Boot] [PATCH 0/5] Blackfin fixes for 2009.06
by Mike Frysinger 06 May '09

06 May '09

Some random minor bug fixes found during regression testing. Graf Yang (1): Blackfin: bf518f-ezbrd: reset ethernet PHY during init Mike Frysinger (4): Blackfin: recurse with early serial initcode Blackfin: fix booting with older bootroms (no EVT1) Blackfin: avoid get_sclk() with early serial debug Blackfin: bf527-ezkit: fix SPI flash env params blackfin_config.mk | 6 +++- board/bf518f-ezbrd/bf518f-ezbrd.c | 55 ++++++++++++++++++++++++++-- board/bf561-ezkit/u-boot.lds.S | 9 ++++- cpu/blackfin/cpu.c | 10 +++++- cpu/blackfin/initcode.c | 4 ++- cpu/blackfin/serial.h | 10 +++--- include/asm-blackfin/blackfin-config-pre.h | 8 ++++ include/configs/bf527-ezkit.h | 4 +- 8 files changed, 91 insertions(+), 15 deletions(-)

1 5