April 2009 - U-Boot

[U-Boot] [PATCH 1/9] MPC85xx: Add QE clk support for mpc85xx platforms
by Haiying Wang 29 Apr '09

29 Apr '09

Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/speed.c | 13 +++++++++++++ include/asm-ppc/immap_85xx.h | 2 ++ include/e500.h | 1 + 4 files changed, 20 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index ef976a4..b812d88 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,6 +184,10 @@ int checkcpu (void) printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif +#ifdef CONFIG_QE + printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index b0f47e0..16dbe76 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo) uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; +#ifdef CONFIG_QE + u32 qe_ratio; +#endif plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; @@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo) } #endif +#ifdef CONFIG_QE + qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) + >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT; + sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; +#endif + #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; @@ -112,6 +121,10 @@ int get_clocks (void) gd->mem_clk = sys_info.freqDDRBus; gd->lbc_clk = sys_info.freqLocalBus; +#ifdef CONFIG_QE + gd->qe_clk = sys_info.freqQE; + gd->brg_clk = gd->qe_clk / 2; +#endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, * there is no pattern that can be used to determine the frequency, so diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 0810b8e..a4d25cd 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1581,6 +1581,8 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif +#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ diff --git a/include/e500.h b/include/e500.h index 4c5eeb7..84b580d 100644 --- a/include/e500.h +++ b/include/e500.h @@ -18,6 +18,7 @@ typedef struct unsigned long freqSystemBus; unsigned long freqDDRBus; unsigned long freqLocalBus; + unsigned long freqQE; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- 1.6.0.2

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[U-Boot] [SPAM] Dentists Database in the US
by Daryl Dumas 29 Apr '09

29 Apr '09

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[U-Boot] PCI on mpc832x?
by Joakim Tjernlund 29 Apr '09

29 Apr '09

Still trying to wrap my head around PCI and I wonder if I need to do some HW init in u-boot in order to use the PCI controller in Linux? Obviously I need to pass PCI settings in the OF tree, but other than that? Jocke

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[U-Boot] Disable features
by simon polette 29 Apr '09

29 Apr '09

Hi, Is existing a way to globally disable some features such as ethernet or Nand support, instead of doing it for a specific board? More over, I can't disable ethernet on the at91sam9261ek board by simply disable the #define CONFIG_DRIVER_DM9000 in the 'config/at91sam9261ek.h' file so it cause building errors. Thanks for your support, best regards, Simon P.

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[U-Boot] [PATCH] ARM DaVinci: Adding CONFIG options for NAND ALE and CLE
by s-paulraj＠ti.com 29 Apr '09

29 Apr '09

The CLE and ALE for DaVinci DM644x is not the same as DM646x. This patch adds 2 CONFIG_ options to the config.h header files to all the DM6446 based boards. These values are then used by the driver. This has been tested on the DM644x, DM355, DM357 and DM365. Support for the latter 3 will be added soon. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- drivers/mtd/nand/davinci_nand.c | 6 +++--- include/asm-arm/arch-davinci/nand_defs.h | 9 ++++----- include/configs/davinci_dvevm.h | 2 ++ include/configs/davinci_schmoogie.h | 2 ++ include/configs/davinci_sffsdr.h | 2 ++ include/configs/davinci_sonata.h | 2 ++ 6 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index a974667..dcc0f39 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -54,13 +54,13 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c struct nand_chip *this = mtd->priv; u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + IO_ADDR_W &= ~(CONFIG_MASK_ALE | CONFIG_MASK_CLE); if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) - IO_ADDR_W |= MASK_CLE; + IO_ADDR_W |= CONFIG_MASK_CLE; if ( ctrl & NAND_ALE ) - IO_ADDR_W |= MASK_ALE; + IO_ADDR_W |= CONFIG_MASK_ALE; this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; } diff --git a/include/asm-arm/arch-davinci/nand_defs.h b/include/asm-arm/arch-davinci/nand_defs.h index 187d3c3..a2d01b0 100644 --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -28,11 +28,10 @@ #include <asm/arch/hardware.h> -#define MASK_CLE 0x10 -#define MASK_ALE 0x0a - -#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10)) -#define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a)) +#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + \ + CONFIG_MASK_CLE)) +#define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + \ + CONFIG_MASK_ALE)) #define NAND_CE0DATA ((volatile u_int8_t *)CONFIG_SYS_NAND_BASE) typedef struct { diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index fae430b..1fe3e19 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -128,6 +128,8 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_MASK_CLE 0x10 +#define CONFIG_MASK_ALE 0x0a #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 923e477..40df3c3 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -90,6 +90,8 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_MASK_CLE 0x10 +#define CONFIG_MASK_ALE 0x0a #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /*=====================*/ /* Board related stuff */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 73a59db..5d693f8 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -86,6 +86,8 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_MASK_CLE 0x10 +#define CONFIG_MASK_ALE 0x0a #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /* I2C switch definitions for PCA9543 chip */ #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 70d2c7d..6699b3a 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -123,6 +123,8 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define CONFIG_MASK_CLE 0x10 +#define CONFIG_MASK_ALE 0x0a #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) -- 1.6.0.4

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[U-Boot] [PATCH] ARM DaVinci: Adding DM357 Support
by s-paulraj＠ti.com 29 Apr '09

29 Apr '09

Patch adds support for DaVinci DM357. This SOC is very similar to the DM644x. The DM357 EVM has 2 NANDs, one small page NAND and another large page NAND. But the device can only boot of the small page NAND. It does not have NOR support. This patch has been tested on the DM357 EVM. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- Makefile | 3 + include/configs/davinci_dm357_evm.h | 159 +++++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+), 0 deletions(-) create mode 100644 include/configs/davinci_dm357_evm.h diff --git a/Makefile b/Makefile index c52894c..81d6759 100644 --- a/Makefile +++ b/Makefile @@ -2790,6 +2790,9 @@ davinci_sffsdr_config : unconfig davinci_sonata_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci +davinci_dm357_evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dvevm davinci davinci + lpd7a400_config \ lpd7a404_config: unconfig @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x diff --git a/include/configs/davinci_dm357_evm.h b/include/configs/davinci_dm357_evm.h new file mode 100644 index 0000000..f129b67 --- /dev/null +++ b/include/configs/davinci_dm357_evm.h @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/*=======*/ +/* Board */ +/*=======*/ +#define DV_EVM +#define CONFIG_SYS_NAND_SMALLPAGE +#define CONFIG_SYS_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 270000000 /* Arm Clock frequency */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 27000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM644X +/*====================================================*/ +/* definitions for EEPROM on DM357 EVM */ +/*====================================================*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start */ +#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */ +#define DDR_8BANKS /* 8-bank DDR2 (256MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CONFIG_SYS_NS16550_CLK 27000000 /* Input clock */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 10 +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_NAND_DAVINCI +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#ifdef CONFIG_SYS_NAND_SMALLPAGE +#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ +#define CONFIG_ENV_SIZE SZ_16K +#else +#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CONFIG_ENV_SIZE SZ_128K +#endif +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CONFIG_SYS_NAND_BASE 0x02000000 +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MASK_CLE 0x10 +#define CONFIG_MASK_ALE 0x08 +#define CONFIG_ENV_OFFSET 0x0 +#define DEF_BOOTM "" +#endif +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM357 EVM > " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x80700000 +#define CONFIG_VERSION_VARIABLE +#define CONFIG_CMDLINE_EDITING +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- 1.6.0.4

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[U-Boot] [patch u-boot-git 1/2] davinci_nand: cleanup I (minor)
by David Brownell 29 Apr '09

29 Apr '09

From: David Brownell <dbrownell(a)users.sourceforge.net> Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell <dbrownell(a)users.sourceforge.net> --- There are two remaining chipselect issues of note. First, this doesn't present the common "two chipselects per package" chips as one device, like Linux does. Second, the hardware ECC code assumes a specific DaVinci chipselect (with secondary chipselects driven by address lines) ... but e.g. the DM357 EVM uses two distinct hardware chipselects. drivers/mtd/nand/davinci_nand.c | 55 +++++++++++------------------ include/asm-arm/arch-davinci/nand_defs.h | 54 ---------------------------- 2 files changed, 22 insertions(+), 87 deletions(-) --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -49,6 +49,8 @@ extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; +static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; + static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; @@ -115,34 +117,31 @@ static struct nand_ecclayout davinci_nan static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - emifregs emif_addr; int dummy; - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - dummy = emif_addr->NANDF1ECC; - dummy = emif_addr->NANDF2ECC; - dummy = emif_addr->NANDF3ECC; - dummy = emif_addr->NANDF4ECC; + dummy = emif_regs->NANDF1ECC; +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC + dummy = emif_regs->NANDF2ECC; + dummy = emif_regs->NANDF3ECC; + dummy = emif_regs->NANDF4ECC; +#endif - emif_addr->NANDFCR |= (1 << 8); + /* FIXME: only chipselect 0 is supported for now */ + emif_regs->NANDFCR |= 1 << 8; } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - emifregs emif_base_addr; - - emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; if (region == 1) - ecc = emif_base_addr->NANDF1ECC; + ecc = emif_regs->NANDF1ECC; else if (region == 2) - ecc = emif_base_addr->NANDF2ECC; + ecc = emif_regs->NANDF2ECC; else if (region == 3) - ecc = emif_base_addr->NANDF3ECC; + ecc = emif_regs->NANDF3ECC; else if (region == 4) - ecc = emif_base_addr->NANDF4ECC; + ecc = emif_regs->NANDF4ECC; return(ecc); } @@ -369,27 +368,21 @@ static int nand_davinci_correct_data(str static int nand_davinci_dev_ready(struct mtd_info *mtd) { - emifregs emif_addr; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - return(emif_addr->NANDFSR & 0x1); -} - -static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this) -{ - while(!nand_davinci_dev_ready(mtd)) {;} - *NAND_CE0CLE = NAND_STATUS; - return(*NAND_CE0DATA); + return emif_regs->NANDFSR & 0x1; } static void nand_flash_init(void) { + /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! + * Instead, have your board_init() set EMIF timings, based on its + * knowledge of the clocks and what devices are hooked up ... and + * don't even do that unless no UBL handled it. + */ +#ifdef CONFIG_SOC_DM6446 u_int32_t acfg1 = 0x3ffffffc; u_int32_t acfg2 = 0x3ffffffc; u_int32_t acfg3 = 0x3ffffffc; u_int32_t acfg4 = 0x3ffffffc; - emifregs emif_regs; /*------------------------------------------------------------------* * NAND FLASH CHIP TIMEOUT @ 459 MHz * @@ -411,20 +404,17 @@ static void nand_flash_init(void) | (0 << 0 ) /* asyncSize 8-bit bus */ ; - emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - emif_regs->AWCCR |= 0x10000000; emif_regs->AB1CR = acfg1; /* 0x08244128 */; emif_regs->AB2CR = acfg2; emif_regs->AB3CR = acfg3; emif_regs->AB4CR = acfg4; emif_regs->NANDFCR = 0x00000101; +#endif } int board_nand_init(struct nand_chip *nand) { - nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; - nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; nand->chip_delay = 0; nand->select_chip = nand_davinci_select_chip; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT @@ -458,7 +448,6 @@ int board_nand_init(struct nand_chip *na nand->cmd_ctrl = nand_davinci_hwcontrol; nand->dev_ready = nand_davinci_dev_ready; - nand->waitfunc = nand_davinci_waitfunc; nand_flash_init(); --- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -31,60 +31,6 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x0a -#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10)) -#define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a)) -#define NAND_CE0DATA ((volatile u_int8_t *)CONFIG_SYS_NAND_BASE) - -typedef struct { - u_int32_t NRCSR; - u_int32_t AWCCR; - u_int8_t RSVD0[8]; - u_int32_t AB1CR; - u_int32_t AB2CR; - u_int32_t AB3CR; - u_int32_t AB4CR; - u_int8_t RSVD1[32]; - u_int32_t NIRR; - u_int32_t NIMR; - u_int32_t NIMSR; - u_int32_t NIMCR; - u_int8_t RSVD2[16]; - u_int32_t NANDFCR; - u_int32_t NANDFSR; - u_int8_t RSVD3[8]; - u_int32_t NANDF1ECC; - u_int32_t NANDF2ECC; - u_int32_t NANDF3ECC; - u_int32_t NANDF4ECC; - u_int8_t RSVD4[4]; - u_int32_t IODFTECR; - u_int32_t IODFTGCR; - u_int8_t RSVD5[4]; - u_int32_t IODFTMRLR; - u_int32_t IODFTMRMR; - u_int32_t IODFTMRMSBR; - u_int8_t RSVD6[20]; - u_int32_t MODRNR; - u_int8_t RSVD7[76]; - u_int32_t CE0DATA; - u_int32_t CE0ALE; - u_int32_t CE0CLE; - u_int8_t RSVD8[4]; - u_int32_t CE1DATA; - u_int32_t CE1ALE; - u_int32_t CE1CLE; - u_int8_t RSVD9[4]; - u_int32_t CE2DATA; - u_int32_t CE2ALE; - u_int32_t CE2CLE; - u_int8_t RSVD10[4]; - u_int32_t CE3DATA; - u_int32_t CE3ALE; - u_int32_t CE3CLE; -} nand_registers; - -typedef volatile nand_registers *nandregs; - #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 #define NAND_STATUS 0x70

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Re: [U-Boot] [PATCH 1/2] Fix OneNAND ipl to read CONFIG_SYS_MONITOR_LEN
by apgmoorthy 29 Apr '09

29 Apr '09

Hi Scott, >> + if (page < 2 && (onenand_readw(THIS_ONENAND(ONENAND_SPARERAM)) != 0xffff)) >Line length. - Corrected. >> int pagesize = ONENAND_PAGE_SIZE; >> + int nblocks = CONFIG_SYS_MONITOR_LEN / ONENAND_BLOCK_SIZE; >Shouldn't nblocks be rounded up? >> pagesize <<= 1; >> + nblocks = (nblocks + 1) >> 1; >> + } >Hmm, might be clearer to just do this: >if (onenand_readw(THIS_ONENAND(ONENAND_REG_TECHNOLOGY))) { > pagesize = 4096; > pageshift = 12; >} else { > pagesize = 2048; > pageshift = 11; >} >nblocks = (CONFIG_SYS_MONITOR_LEN + pagesize - 1) >> pageshift; - Right , But the above line dosent give the nblocks , used erasesize and erase_shift. >ONENAND_PAGE_SIZE as a constant should go away since it's not always >true. - Removed it. >> + for (; block < nblocks; block++) { >> + for (; page < ONENAND_PAGES_PER_BLOCK; page++) { >> + if (onenand_read_page(block, page, buf + offset, pagesize)) { >> + /* This block is bad. Skip it and read next block */ >> + nblocks++; >> + break; >> + } >> + offset += pagesize; >If you find a bad block marker in the second page of a block, shouldn't >you rewind offset to the beginning of the block? - Correct , have reverted back. >BTW, if we're going to have "onenand_readw" and "onenand_writew" >wrappers, can we make them useful by combining them with THIS_ONENAND? - Corrected , Now onenand_readw/onenand_writew conatins THIS_ONENAND. Please do find the updated patch below. With Regards Moorthy Currently OneNAND initial program loader (ipl) reads only block 0 ie 128KB. However, u-boot image for apollon board is 195KB making the board unbootable with OneNAND. Fix ipl to read CONFIG_SYS_MONITOR_LEN. CONFIG_SYS_MONITOR_LEN macro holds the U-Boot image size. Signed-off-by: Gangheyamoorthy <moorthy.apg(a)samsung.com> Signed-off-by: Rohit Hagargundgi <h.rohit(a)samsung.com> --- diff --git a/onenand_ipl/onenand_boot.c b/onenand_ipl/onenand_boot.c index 86428cc..63995ce 100644 --- a/onenand_ipl/onenand_boot.c +++ b/onenand_ipl/onenand_boot.c @@ -36,7 +36,7 @@ void start_oneboot(void) buf = (uchar *) CONFIG_SYS_LOAD_ADDR; - onenand_read_block0(buf); + onenand_read_block(buf); ((init_fnc_t *)CONFIG_SYS_LOAD_ADDR)(); diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h index c5a722d..412572a 100644 --- a/onenand_ipl/onenand_ipl.h +++ b/onenand_ipl/onenand_ipl.h @@ -31,5 +31,5 @@ #define READ_INTERRUPT() \ onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) -extern int onenand_read_block0(unsigned char *buf); +extern int onenand_read_block(unsigned char *buf); #endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c index 6d04943..7415c7f 100644 --- a/onenand_ipl/onenand_read.c +++ b/onenand_ipl/onenand_read.c @@ -49,20 +49,20 @@ static inline int onenand_read_page(ulong block, ulong page, #endif onenand_writew(onenand_block_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + ONENAND_REG_START_ADDRESS1); onenand_writew(onenand_bufferram_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + ONENAND_REG_START_ADDRESS2); onenand_writew(onenand_sector_address(page), - THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); + ONENAND_REG_START_ADDRESS8); onenand_writew(onenand_buffer_address(), - THIS_ONENAND(ONENAND_REG_START_BUFFER)); + ONENAND_REG_START_BUFFER); - onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); + onenand_writew(ONENAND_INT_CLEAR, ONENAND_REG_INTERRUPT); - onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); + onenand_writew(ONENAND_CMD_READ, ONENAND_REG_COMMAND); #ifndef __HAVE_ARCH_MEMCPY32 p = (unsigned long *) buf; @@ -72,6 +72,10 @@ static inline int onenand_read_page(ulong block, ulong page, while (!(READ_INTERRUPT() & ONENAND_INT_READ)) continue; + /* Check for invalid block mark */ + if (page < 2 && (onenand_readw(ONENAND_SPARERAM) != 0xffff)) + return 1; + #ifdef __HAVE_ARCH_MEMCPY32 /* 32 bytes boundary memory copy */ memcpy32(buf, base, pagesize); @@ -89,25 +93,39 @@ static inline int onenand_read_page(ulong block, ulong page, #define ONENAND_PAGES_PER_BLOCK 64 /** - * onenand_read_block - Read a block data to buf + * onenand_read_block - Read First 'n' consecutive Good blocks holding + * data to buf * @return 0 on success */ -int onenand_read_block0(unsigned char *buf) +int onenand_read_block(unsigned char *buf) { - int page, offset = 0; - int pagesize = ONENAND_PAGE_SIZE; - - /* MLC OneNAND has 4KiB page size */ - if (onenand_readw(THIS_ONENAND(ONENAND_REG_TECHNOLOGY))) - pagesize <<= 1; + int block = 0, page = ONENAND_START_PAGE, offset = 0; + int pagesize = 0, erase_shift =0; + int erasesize = 0, nblocks = 0; + + if(onenand_readw(ONENAND_REG_TECHNOLOGY)) { + pagesize = 4096; /* MLC OneNAND has 4KiB pagesize */ + erase_shift = 18; + } else { + pagesize = 2048; + erase_shift = 17; + } + erasesize = ONENAND_PAGES_PER_BLOCK * pagesize; + nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize -1) >> erase_shift; /* NOTE: you must read page from page 1 of block 0 */ /* read the block page by page*/ - for (page = ONENAND_START_PAGE; - page < ONENAND_PAGES_PER_BLOCK; page++) { - - onenand_read_page(0, page, buf + offset, pagesize); - offset += pagesize; + for (; block < nblocks; block++) { + for (; page < ONENAND_PAGES_PER_BLOCK; page++) { + if (onenand_read_page(block, page, buf + offset, pagesize)) { + /* This block is bad. Skip it and read next block */ + offset -= page * pagesize; + nblocks++; + break; + } + offset += pagesize; + } + page = 0; } return 0;

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[U-Boot] [PATCH] (unicode test) test.c: In function ‘main’:
by Mike Frysinger 28 Apr '09

28 Apr '09

please ignore ... test.c:1: warning: implicit declaration of function ‘foo’ /tmp/ccelkAwh.o: In function `main': test.c:(.text+0x12): undefined reference to `foo' collect2: ld returned 1 exit status moo --- foo | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) create mode 100644 foo diff --git a/foo b/foo new file mode 100644 index 0000000..6ef6f96 --- /dev/null +++ b/foo @@ -0,0 +1,5 @@ +test.c: In function ‘main’: +test.c:1: warning: implicit declaration of function ‘foo’ +/tmp/ccelkAwh.o: In function `main': +test.c:(.text+0x12): undefined reference to `foo' +collect2: ld returned 1 exit status -- 1.6.2.3

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[U-Boot] Uboot NAND SPL make for MX31
by alfred steele 28 Apr '09

28 Apr '09

Hi Magnus and all, Should i do a "mx31pdk_nand_config" instead of the regular "mx31pdk_config" to get the nand boot working on the PDK board. I can make that out from the lowlevel_init.S code, but i am not completely sure though. Thanks.

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