March 2009 - U-Boot

[U-Boot] [PATCH v4] Add support for KMC KZM-ARM11-01 board
by Tomohiro Masubuchi 05 Aug '09

05 Aug '09

Hi, This patch adds support for KMC KZM-ARM11-01. It was rebased to "next" branch. Regards, Tomohiro Signed-off-by: Atsuo Igarashi <atsuo_igarashi(a)tripeaks.co.jp> Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi(a)tripeaks.co.jp> ---- Add support for KMC KZM-ARM11-01 board. MAKEALL | 1 + Makefile | 3 + board/kzm_arm11_01/Makefile | 49 +++++++ board/kzm_arm11_01/config.mk | 1 + board/kzm_arm11_01/kzm_arm11_01.c | 84 +++++++++++ board/kzm_arm11_01/lowlevel_init.S | 281 ++++++++++++++++++++++++++++++++++++ board/kzm_arm11_01/u-boot.lds | 72 +++++++++ include/configs/kzm_arm11_01.h | 184 +++++++++++++++++++++++ 8 files changed, 675 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..22f65ed 100755 --- a/MAKEALL +++ b/MAKEALL @@ -522,6 +522,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + kzm_arm11_01 \ mx31ads \ smdk6400 \ " diff --git a/Makefile b/Makefile index 017e4db..f334c57 100644 --- a/Makefile +++ b/Makefile @@ -2805,6 +2805,9 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +kzm_arm11_01_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 kzm_arm11_01 NULL mx31 + mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 diff --git a/board/kzm_arm11_01/Makefile b/board/kzm_arm11_01/Makefile new file mode 100644 index 0000000..7e2f8ca --- /dev/null +++ b/board/kzm_arm11_01/Makefile @@ -0,0 +1,49 @@ +# +# Derived from mx31ads +# +# Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := kzm_arm11_01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/kzm_arm11_01/config.mk b/board/kzm_arm11_01/config.mk new file mode 100644 index 0000000..d34dc02 --- /dev/null +++ b/board/kzm_arm11_01/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x87f00000 diff --git a/board/kzm_arm11_01/kzm_arm11_01.c b/board/kzm_arm11_01/kzm_arm11_01.c new file mode 100644 index 0000000..ed253d7 --- /dev/null +++ b/board/kzm_arm11_01/kzm_arm11_01.c @@ -0,0 +1,84 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + int i; + + /* CS0 & CS1: Nor Flash */ + /* + * CS0L, CS0A and CS0U values are from the RedBoot sources. + */ + __REG(CSCR_U(0)) = 0x00001801; + __REG(CSCR_L(0)) = 0x45450D01; + __REG(CSCR_A(0)) = 0x00450000; + + __REG(CSCR_U(1)) = 0x00001801; + __REG(CSCR_L(1)) = 0x45450D01; + __REG(CSCR_A(1)) = 0x00450000; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + + /* SPI2 */ + mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); + + gd->bd->bi_arch_number = MACH_TYPE_KZM_ARM11_01;/* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ + + return 0; +} + +int checkboard (void) +{ + printf("Board: KZM-ARM11-01\n"); + return 0; +} diff --git a/board/kzm_arm11_01/lowlevel_init.S b/board/kzm_arm11_01/lowlevel_init.S new file mode 100644 index 0000000..f2032a5 --- /dev/null +++ b/board/kzm_arm11_01/lowlevel_init.S @@ -0,0 +1,281 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +/* RedBoot: AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =0x43F00000 + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =0x53F00000 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =0x43F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] + + ldr r0, =0x53F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =0x43F04000 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =0x00302154 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* RedBoot: M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =0xB8003000 + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =0x00000040 + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* RedBoot: To support 133MHz DDR */ +.macro init_drive_strength + /* + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits + * in SW_PAD_CTL registers + */ + + /* SDCLK */ + ldr r1, =0x43FAC200 + ldr r0, [r1, #0x6C] + bic r0, r0, #(1 << 12) + str r0, [r1, #0x6C] + + /* CAS */ + ldr r0, [r1, #0x70] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x70] + + /* RAS */ + ldr r0, [r1, #0x74] + bic r0, r0, #(1 << 2) + str r0, [r1, #0x74] + + /* CS2 (CSD0) */ + ldr r0, [r1, #0x7C] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x7C] + + /* DQM3 */ + ldr r0, [r1, #0x84] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x84] + + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ +pad_loop: + ldr r0, [r1, #0x88] + bic r0, r0, #(1 << 22) + bic r0, r0, #(1 << 12) + bic r0, r0, #(1 << 2) + str r0, [r1, #0x88] + add r1, r1, #4 + subs r2, r2, #0x1 + bne pad_loop +.endm /* init_drive_strength */ + +/* CPLD on CS4 setup */ +.macro init_cs4 + ldr r0, =WEIM_BASE + ldr r1, =0x00001003 + str r1, [r0, #0x40] + ldr r1, =0x74741B01 + str r1, [r0, #0x44] + ldr r1, =0x00740000 + str r1, [r0, #0x48] +.endm /* init_cs4 */ + +/* LAN on CS5 setup */ +.macro init_cs5 + ldr r0, =WEIM_BASE + ldr r1, =0x00001403 + str r1, [r0, #0x50] + ldr r1, =0x44340D01 + str r1, [r0, #0x54] + ldr r1, =0x00340000 + str r1, [r0, #0x58] +.endm /* init_cs5 */ + +.globl lowlevel_init +lowlevel_init: + + /* Redboot initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + init_cs4 + + /* Image Processing Unit: */ + /* Too early to switch display on? */ + REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ + /* Clock Control Module: */ + REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ + + /* 532-133-66.5 */ + ldr r0, =CCM_BASE + ldr r1, =0xFF872660 + /* PDR0 */ + str r1, [r0, #0x4] + ldreq r1, MPCTL_PARAM_532 + ldrne r1, MPCTL_PARAM_532_27 + /* MPCTL */ + str r1, [r0, #0x10] + + ldreq r1, UPCTL_PARAM_240 + ldrne r1, UPCTL_PARAM_240_27 + /* UPCTL */ + str r1, [r0, #0x14] + /* default CLKO to 1/8 of the ARM core */ + mov r1, #0x000002C0 + add r1, r1, #0x00000006 + /* COSR */ + str r1, [r0, #0x1c] + + /* Default: 1, 4, 12, 1 */ + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x0079d72a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x81000020, 0x00 + REG8 0x80000033, 0xda + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + init_cs5 + + mov pc, lr + +MPCTL_PARAM_532: + .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) +MPCTL_PARAM_532_27: + .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) +UPCTL_PARAM_240: + .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) +UPCTL_PARAM_240_27: + .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/kzm_arm11_01/u-boot.lds b/board/kzm_arm11_01/u-boot.lds new file mode 100644 index 0000000..aa87fcb --- /dev/null +++ b/board/kzm_arm11_01/u-boot.lds @@ -0,0 +1,72 @@ +/* + * Derived from mx31ads + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/arm1136/start.o (.text) + board/kzm_arm11_01/libkzm_arm11_01.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/configs/kzm_arm11_01.h b/include/configs/kzm_arm11_01.h new file mode 100644 index 0000000..72f7b5a --- /dev/null +++ b/include/configs/kzm_arm11_01.h @@ -0,0 +1,184 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * Configuration settings for the KMC KZM-ARM11-01 board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx31-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CONFIG_SYS_MX31_UART1 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SPI +#define CONFIG_CMD_FLASH + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=kzm-arm11/u-boot.bin\0" \ + "kernel=kzm-arm11/uImage\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa007ffff; " \ + "erase ${uboot_addr} 0xa007ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0xb6020300 +#define CONFIG_DRIVER_SMC911X_32_BIT 1 + +/* + * The KZM-ARM11-01 board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the SMC9118 + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs a few hundred milliseconds wait for that after the + * initialization. Which means, at startup, you will not receive answers + * during the first few hundred milliseconds, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* S29GL512N NOR flash has 512 128KiB big sectors. */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */

2 1

[U-Boot] CFI driver and P33 64M flash
by Felix Radensky 04 Aug '09

04 Aug '09

Hi, I'm running U-Boot 1.3.4 on custom 460EX based board, equipped with 64M P33 flash (similar to Intel P30). See http://www.numonyx.com/Documents/Datasheets/314749_P33_Discrete_DS.pdf This flash is comprised internally of two 32M flashes. I have the following declarations in configuration file: #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 518 /* max number of sectors on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ U-Boot identifies this flash as 32M flash. Below is debug output from CFI driver: FLASH: flash detect cfi fwc addr fc000000 cmd f0 f0 8bit x 8 bit fwc addr fc000000 cmd ff ff 8bit x 8 bit fwc addr fc000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fc000010 is= 0 51 fwc addr fc000555 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fc000010 is= 0 51 fwc addr fc000000 cmd f0 f0f0 16bit x 8 bit fwc addr fc000000 cmd ff ffff 16bit x 8 bit fwc addr fc0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fc000020 is= 0051 5151 fwc addr fc000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fc000020 is= 0051 5151 fwc addr fc000000 cmd f0 00f0 16bit x 16 bit fwc addr fc000000 cmd ff 00ff 16bit x 16 bit fwc addr fc0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr fc000020 is= 0051 0051 is= cmd 52(R) addr fc000022 is= 0052 0052 is= cmd 59(Y) addr fc000024 is= 0059 0059 device interface is 1 found port 2 chip 2 port 16 bits chip 16 bits 00 : 51 52 59 01 00 0a 01 00 00 00 00 23 36 85 95 08 QRY........#6... 10 : 09 0a 00 01 01 02 00 19 01 00 06 00 02 03 00 80 ................ 20 : 00 fe 00 00 02 00 00 00 00 ff ff ff ff fc 36 a4 ..............6. fwc addr fc000000 cmd ff 00ff 16bit x 16 bit fwc addr fc000000 cmd 90 0090 16bit x 16 bit fwc addr fc000000 cmd ff 00ff 16bit x 16 bit fwc addr fc0000aa cmd 98 0098 16bit x 16 bit manufacturer is 1 manufacturer id is 0x89 device id is 0x22 device id2 is 0x0 cfi version is 0x3135 size_ratio 1 port 16 bits chip 16 bits found 2 erase regions erase region 0: 0x00800003 erase_region_count = 4 erase_region_size = 32768 erase region 1: 0x020000fe erase_region_count = 255 erase_region_size = 131072 fwc addr fc000000 cmd ff 00ff 16bit x 16 bit 32 MB What should I change in configuration/driver to get all 64M of flash detected ? Thanks a lot. Felix.

4 4

[U-Boot] [PATCH 1/1] LPC2468 support
by Remco Poelstra 18 Jul '09

18 Jul '09

This patch includes the LPC2468 processor from NXP. Included is a working board example. Signed-off-by: Remco Poelstra <remco.poelstra+u-boot(a)duran-audio.com> --- http://www.beryllium.net/~remco/u-boot.diff (144kb)

5 33

[U-Boot] i2c: rework multibus/multiadapter functionality
by Heiko Schocher 18 Jul '09

18 Jul '09

Hello, I want now, because the merge window is open again, restart the the multibus/multiadapter discussion. To have a base for this discusion, I made in the i2c git tree (git://git.denx.de/u-boot-i2c.git) the following new 2 branches: "multibus": Patches from Sergey Kubushyn <ksi(a)koi8.net> posted in the last merge window. see, http://lists.denx.de/pipermail/u-boot/2009-February/047465.html They were discussed, but not accepted ... also some CodingStyle comments, changes in patch hierarchic are not done ... I only synced them to actuall code to have a base for the discussion. "multibus_v2": (I couldn;t post the patches because one of them is bigger than 100k :-( and I cannot split it in 2 patches, because this would break git bisection compatibility. But the patches can be found in git://git.denx.de/u-boot-i2c.git): Based on the i2c_core from Sergeys patches, added the following suggestions from Wolfgang and me: - v2 is bisection compatible - commits are in (hopefully) logical blocks - "cur_adap" added in gd_t: This points allways to the actuall used i2c adapter: - because gd_t is writeable when running in flash, complete multiadapter/multibus functionality is usable, when running in flash - using a pointer brings faster accesses to the i2c_adapter_t struct and saves some bytes here and there (see later). - init from a i2c controller: In the "multibus" branch (also in actual code) all i2c controllers, as a precaution, getting initialized. In the "multibus_v2" branch, a i2c controller gets only initialized if it is used. This is done in i2c_set_bus_num(). Actually, I let the i2c_init_all() in code, but just call in this function i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM). This can be dropped in a second step completely. Also, with this approach, we can easy add in a second step, a i2c_deinit() function in i2c_set_bus_num(), so we can deactivate a no longer used controller. - added "hw_adapnr" in i2c_adapter_t struct: when for example a CPU has more then one i2c controller we can use this variable to differentiate which controller the actual i2c adapter uses. This results in lower codesize and lower sourcecode changes. Example: fsl_i2c driver: (MPC8548CDS only with fsl driver) multibus: [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8548CDS Configuring for MPC8548CDS board... fsl_i2c.c: In function '__i2c_init': fsl_i2c.c:173: warning: assignment discards qualifiers from pointer target type text data bss dec hex filename 222168 17344 27256 266768 41210 ./u-boot multibus_v2: [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8548CDS Configuring for MPC8548CDS board... text data bss dec hex filename 222080 17344 27256 266680 411b8 ./u-boot also the bitbang driver gets better maintainable: Sourcecode changes: multibus: drivers/i2c/soft_i2c.c | 704 ++++++++++++++++++++--------------- multibus_v2: drivers/i2c/soft_i2c.c | 155 +++++--- Codesize bitbang driver: (MPC8548CDS with the following bus topology: * Busses: * * 0: Direct off of FSL_I2C[0] * 1: FSL_I2C[1]->PCA9542(0)->PCA9542(0) * 2: FSL_I2C[1]->PCA9542(0)->PCA9542(1) * 3: FSL_I2C[1]->PCA9542(1) * 4: Direct off of SOFT_I2C[0] * 5: Direct off of SOFT_I2C[1] ) multibus: [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8548CDS Configuring for MPC8548CDS board... fsl_i2c.c: In function '__i2c_init': fsl_i2c.c:173: warning: assignment discards qualifiers from pointer target type text data bss dec hex filename 227092 17864 27256 272212 42754 ./u-boot [hs@pollux u-boot-i2c]$ multibus_v2: [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8548CDS Configuring for MPC8548CDS board... text data bss dec hex filename 225048 17868 27256 270172 41f5c ./u-boot [hs@pollux u-boot-i2c]$ For this I call for all I2C_SDA, I2C_SCL, ... defines, which holds the board specific code, now functions (This is not a must, but I did this as an example see MPC8548CDS). In this functions I use "hw_adapnr" to switch to do the adapter specific gpio settings ... If we look at the "multibus" approach, there, this is not needed but Sourcecode size and Codesize grows with each bitbang adapter ... and if I think for a board with n bitbang adapter (with n > 5) this results in nearly unmaintable source code ... I just write this here because this has to be discussed (and this was a point, which drove the last discussion in chaos). We can now easy compare such a board ... see MPC8548CDS) and discuss on facts, which version we want to have in mainline. - adding a base_addr to i2c_adap_t struct (Did this not yet, but would also a good thing to have, because when I ported for example the ppc_4xx i2c hardware adapter, I saw, that some CPUs have more than one controller, and they just differ in the base addr, so this variable would be a "good to have"). I solved this actually in adding a function in this driver, which returns the base addr depending on hw_adapnr, which is a suboptimal way ... see for an example new ppc_4xx i2c driver: in drivers/i2c/ppc4xx_i2c.c: ppc4xx_get_base () Codesize: for a board with one soft_i2c driver: [hs@pollux u-boot-i2c]$ git checkout master Switched to branch "master" Your branch is ahead of 'origin/master' by 143 commits. [hs@pollux u-boot-i2c]$ ./MAKEALL CPU86 Configuring for CPU86 board... ... booting from 64-bit flash text data bss dec hex filename 146572 22068 24144 192784 2f110 ./u-boot [hs@pollux u-boot-i2c]$ git checkout multibus Switched to branch "multibus" [hs@pollux u-boot-i2c]$ ./MAKEALL CPU86 Configuring for CPU86 board... ... booting from 64-bit flash text data bss dec hex filename 147816 22124 24144 194084 2f624 ./u-boot [hs@pollux u-boot-i2c]$ git checkout multibus_v2 Switched to branch "multibus_v2" [hs@pollux u-boot-i2c]$ ./MAKEALL CPU86 Configuring for CPU86 board... ... booting from 64-bit flash text data bss dec hex filename 147688 22128 24144 193960 2f5a8 ./u-boot [hs@pollux u-boot-i2c]$ for a board with the fsl driver: [hs@pollux u-boot-i2c]$ git checkout master ./MA Switched to branch "master" Your branch is ahead of 'origin/master' by 143 commits. [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8360EMDS Configuring for MPC8360EMDS board... text data bss dec hex filename 203504 11588 26900 241992 3b148 ./u-boot [hs@pollux u-boot-i2c]$ git checkout multibus Switched to branch "multibus" [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8360EMDS Configuring for MPC8360EMDS board... fsl_i2c.c: In function '__i2c_init': fsl_i2c.c:173: warning: assignment discards qualifiers from pointer target type text data bss dec hex filename 204288 11628 26900 242816 3b480 ./u-boot [hs@pollux u-boot-i2c]$ git checkout multibus_v2 Switched to branch "multibus_v2" [hs@pollux u-boot-i2c]$ ./MAKEALL MPC8360EMDS Configuring for MPC8360EMDS board... text data bss dec hex filename 204256 11632 26900 242788 3b464 ./u-boot [hs@pollux u-boot-i2c]$ at last here comes a TODO list what should be done: - add README for the multibus functionality - list of drivers to port: drivbers/i2c: bfin-twi_i2c.c mxc_i2c.c omap1510_i2c.c omap24xx_i2c.c tsi108_i2c.c grep -lr HARD_I2C cpu/ cpu/arm920t/at91rm9200/i2c.c cpu/arm920t/s3c24x0/i2c.c cpu/mpc512x/i2c.c cpu/mpc5xxx/i2c.c cpu/mpc8220/i2c.c cpu/mpc824x/drivers/i2c/i2c.c cpu/mpc8xx/i2c.c cpu/pxa/i2c.c Hope didn;t forget some more ... - test, test, test ... - i2c devices must ported to new multibus functionality. Ideas here are welcome ;-) (They must "know", on which bus they are ...) - In actuall code it is possible to add new i2c busses with the "i2c bus" command (and from code with i2c_mux_ident_muxstring()) This actual is not included in the new code, but that could be done the following way (for the multibus_v2 version, for the approach in "multibus" branch I have no idea how to make this): When running in flash, we just can use the i2c busses defined in CONFIG_SYS_I2C_ADAPTERS (should be okay in the first step. When relocating code, the i2c busses in CONFIG_SYS_I2C_ADAPTERS are converted in a dynamcial list, so we can then easy add new busses to this list. Also we define a "i2c_bus" environment variable, which contains i2c busses, that gets added when relocating. This is needed for the keymile boards. There are a lot of board versions which differ only in the i2c bus topology. With this approach, we can use one u-boot binary for all board versions, just defining the i2c bus topology in the environment ... BTW: This is also a point for using "cur_adap", because the rest of the multibus functionality doesn;t have to be changed ... So, I hope I didn;t forget something ... lets start with the discussion ... bye heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

3 8

[U-Boot] [PATCH 00/30] standardize mac address handling in u-boot (v2)
by Mike Frysinger 16 Jul '09

16 Jul '09

this set of patches aims to standardize the mac address handling in all of u-boot by doing the following: - add helper funcs for working with mac addresses (binary & string) - add format strings from Linux for printf-ing mac addresses - convert all duplicated code to use aforementioned helper funcs - convert all places to get the mac address from the environment - drop the global data instances of bi_enet*addr - document the whole damned thing ive taken pains to make sure the patchset doesnt break along the way (in terms of doing bisection and such). but in general, the interdependency looks something like: - add util funcs - convert net/boards/drivers/cpu/commands from global data to env - convert arch/board.c init to not touch global data - remove global data from all arch headers the ppc steps with load_sernum_ethaddr() are a little hairy due to the spread of code and trying to make sure things don't break bisection. but the other option is to squash all these commits (the common ppc board code as well as each individual board) into one change. doesn't matter to me either way. v2 of the patchset brings these changes: - import updated printf modifiers from the kernel - convert str_enetaddr() to %pM - convert print_IPaddr() to %pI4 - convert board_get_enetaddr() to board specific code - misc fixes/changes based on feedback from people while the new printf code is bigger by about 900bytes, i think we make up most of that by converting str_enetaddr/print_IPaddr users over to it. currently this patch series is maintained in my tree: git://www.denx.de/git/u-boot-blackfin.git macaddr Mike Frysinger (30): vsprintf: pull updates from Linux kernel convert print_IPaddr() to %pI4 net: new utility functions for working with enetaddr's doc/README.enetaddr: document proper MAC usage Blackfin: bfin_mac: force boards to setup the MAC themselves net: get mac address from environment and use eth util funcs bdinfo: get mac address from environment bootvx: get mac address from environment lynxkdi: get mac address from environment nvedit: do not update global bi_enetaddr and do not call eth_set_enetaddr() AmigaOneG3SE/enet: get mac address from environment boards: get mac address from environment drivers/net/: get mac address from environment bcm570x: get mac address from environment cs8900: get mac address from environment sh_eth: get mac address from environment lan91c96/smc91111/smc911x: get mac address from environment cpu/: get mac address from environment npe: get mac address from environment lib_*/board.c: do not initialize bi_enet*addr in global data nx823: get mac address from environment arm: get mac address from environment boards: move board_get_enetaddr() into board-specific init cmc_pu2: get mac address from environment pcs440ep: get mac address from environment and move load_sernum_ethaddr() to board init kup4k/kup4x: rename load_sernum_ethaddr() to kup_load_sernum_ethaddr() tqm8xx: rename load_sernum_ethaddr() to tqc_load_sernum_ethaddr() ppc: mark global bi_enet*addr as legacy drop now unused load_sernum_ethaddr() function remove bi_enet*addr from global data for all arches board/MAI/AmigaOneG3SE/enet.c | 42 +--- board/RPXClassic/RPXClassic.c | 16 +- board/cmc_pu2/load_sernum_ethaddr.c | 18 +- board/etin/debris/debris.c | 10 +- board/keymile/mgcoge/mgcoge.c | 4 +- board/keymile/mgsuvd/mgsuvd.c | 4 +- board/kup/common/load_sernum_ethaddr.c | 2 +- board/kup/kup4k/kup4k.c | 3 + board/kup/kup4x/kup4x.c | 4 +- board/m501sk/m501sk.c | 5 - board/mbx8xx/mbx8xx.c | 14 +- board/mpl/vcma9/cmd_vcma9.c | 11 +- board/muas3001/muas3001.c | 4 +- board/netstal/common/nm_bsp.c | 40 +-- board/nx823/flash.c | 5 +- board/nx823/nx823.c | 41 +-- board/pcs440ep/pcs440ep.c | 31 +-- board/pn62/pn62.c | 24 +- board/sandburst/common/sb_common.c | 4 +- board/sandburst/common/sb_common.h | 1 + board/sandburst/karef/karef.c | 29 ++ board/sandburst/metrobox/metrobox.c | 29 ++ board/siemens/IAD210/IAD210.c | 14 +- board/sixnet/sixnet.c | 11 +- board/tqc/tqm8xx/load_sernum_ethaddr.c | 2 +- board/tqc/tqm8xx/tqm8xx.c | 3 + board/v38b/v38b.c | 12 + board/xilinx/xilinx_enet/emac_adapter.c | 8 +- board/xpedite1k/xpedite1k.c | 51 +++- common/cmd_bdinfo.c | 166 ++++-------- common/cmd_elf.c | 6 +- common/cmd_ide.c | 10 +- common/cmd_nvedit.c | 24 +-- common/lynxkdi.c | 2 +- cpu/arm920t/at91rm9200/ether.c | 8 +- cpu/ixp/npe/npe.c | 36 +-- cpu/mpc512x/cpu.c | 6 +- cpu/mpc5xxx/cpu.c | 6 +- cpu/mpc8260/ether_fcc.c | 4 +- cpu/mpc8260/ether_scc.c | 4 +- cpu/ppc4xx/cpu_init.c | 14 +- disk/part.c | 2 +- doc/README.enetaddr | 97 +++++++ drivers/net/3c589.c | 7 +- drivers/net/4xx_enet.c | 13 +- drivers/net/bcm570x.c | 4 +- drivers/net/bcm570x_lm.h | 2 +- drivers/net/bfin_mac.c | 16 +- drivers/net/bfin_mac.h | 2 +- drivers/net/cs8900.c | 56 +--- drivers/net/dc2114x.c | 9 +- drivers/net/dm9000x.c | 26 +-- drivers/net/enc28j60.c | 4 +- drivers/net/fsl_mcdmafec.c | 11 +- drivers/net/ks8695eth.c | 8 +- drivers/net/lan91c96.c | 75 +---- drivers/net/mcffec.c | 10 +- drivers/net/rtl8019.c | 14 +- drivers/net/rtl8169.c | 2 +- drivers/net/s3c4510b_eth.c | 2 +- drivers/net/s3c4510b_eth.h | 2 +- drivers/net/sh_eth.c | 28 +-- drivers/net/smc91111.c | 72 +---- drivers/net/smc911x.c | 14 +- drivers/net/tigon3.c | 7 +- drivers/net/xilinx_emac.c | 12 +- drivers/net/xilinx_emaclite.c | 11 +- include/asm-arm/u-boot.h | 5 - include/asm-avr32/u-boot.h | 1 - include/asm-blackfin/u-boot.h | 1 - include/asm-i386/u-boot.h | 1 - include/asm-m68k/u-boot.h | 13 - include/asm-microblaze/u-boot.h | 1 - include/asm-mips/u-boot.h | 1 - include/asm-nios/u-boot.h | 1 - include/asm-nios2/u-boot.h | 1 - include/asm-ppc/u-boot.h | 14 +- include/asm-sh/u-boot.h | 1 - include/asm-sparc/u-boot.h | 12 - include/common.h | 9 - include/configs/IAD210.h | 1 + include/configs/MBX860T.h | 2 + include/configs/RPXClassic.h | 1 + include/configs/XPEDITE1K.h | 1 + include/configs/cmc_pu2.h | 1 + include/configs/v38b.h | 1 + include/net.h | 6 +- lib_arm/board.c | 47 +--- lib_blackfin/board.c | 48 +--- lib_generic/vsprintf.c | 479 ++++++++++++++++++++++++------- lib_i386/board.c | 17 -- lib_m68k/board.c | 38 --- lib_microblaze/board.c | 8 - lib_mips/board.c | 8 - lib_nios/board.c | 5 - lib_nios2/board.c | 5 - lib_ppc/board.c | 92 +------ lib_sh/board.c | 10 - lib_sparc/board.c | 19 -- net/bootp.c | 29 +-- net/eth.c | 76 +++-- net/net.c | 30 +-- net/nfs.c | 10 +- net/tftp.c | 10 +- post/cpu/mpc8xx/ether.c | 4 +- 105 files changed, 1055 insertions(+), 1188 deletions(-) create mode 100644 doc/README.enetaddr

5 43

[U-Boot] show_boot_progess @ ppc not working
by Andre Schwarz 09 Jul '09

09 Jul '09

All, can someone tell me why the board specific function "void show_boot_progress(int arg)" is no longer called (at least on MPC5200). Of course this line is present in the board config : #define CONFIG_SHOW_BOOT_PROGRESS 1 What have I missed ? regards, André MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

6 14

[U-Boot] [PATCH 1/2] at91sam9: add watchdog support
by Jean-Christophe PLAGNIOL-VILLARD 18 Jun '09

18 Jun '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- Makefile | 1 + doc/README.at91 | 9 ++++ drivers/serial/atmel_usart.c | 4 +- drivers/watchdog/Makefile | 46 ++++++++++++++++++++ drivers/watchdog/at91sam9_wdt.c | 79 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_wdt.h | 38 ++++++++++++++++ 6 files changed, 176 insertions(+), 1 deletions(-) create mode 100644 drivers/watchdog/Makefile create mode 100644 drivers/watchdog/at91sam9_wdt.c create mode 100644 include/asm-arm/arch-at91/at91_wdt.h diff --git a/Makefile b/Makefile index fcf57f3..3e61417 100644 --- a/Makefile +++ b/Makefile @@ -262,6 +262,7 @@ LIBS += drivers/rtc/librtc.a LIBS += drivers/serial/libserial.a LIBS += drivers/usb/libusb.a LIBS += drivers/video/libvideo.a +LIBS += drivers/watchdog/libwatchdog.a LIBS += common/libcommon.a LIBS += libfdt/libfdt.a LIBS += api/libapi.a diff --git a/doc/README.at91 b/doc/README.at91 index 4e3928a..c883c7c 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -2,6 +2,7 @@ Atmel AT91 Evaluation kits http://atmel.com/dyn/products/tools.asp?family_id=605#1443 +I. Board mapping & boot media ------------------------------------------------------------------------------ AT91SAM9260EK & AT91SAM9XEEK ------------------------------------------------------------------------------ @@ -86,3 +87,11 @@ Environment variables make at91sam9263ek_config - use data flash (spi cs0) (default) make at91sam9263ek_nandflash_config - use nand flash make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) + +II. Watchdog support + + The watchdog wan only be activate once so you need to activate in the + bootloader and in the bootstrap if you use it + + The you can activate with + CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f3b146c..f50552a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <common.h> +#include <watchdog.h> #include <asm/io.h> #include <asm/arch/clk.h> @@ -87,7 +88,8 @@ void serial_puts(const char *s) int serial_getc(void) { - while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) ; + while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) + WATCHDOG_RESET(); return usart3_readl(RHR); } diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile new file mode 100644 index 0000000..200968d --- /dev/null +++ b/drivers/watchdog/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libwatchdog.a + +COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c new file mode 100644 index 0000000..5bb8b77 --- /dev/null +++ b/drivers/watchdog/at91sam9_wdt.c @@ -0,0 +1,79 @@ +/* + * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] + * + * Watchdog driver for Atmel AT91SAM9x processors. + * + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * Copyright (C) 2008 Renaud CERRATO r.cerrato(a)til-technologies.fr + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/* + * The Watchdog Timer Mode Register can be only written to once. If the + * timeout need to be set from U-Boot, be sure that the bootstrap doesn't + * write to this register. Inform Linux to it too + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_wdt.h> + +/* + * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, + * use this to convert a watchdog + * value from/to milliseconds. + */ +#define ms_to_ticks(t) (((t << 8) / 1000) - 1) +#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) + +/* Hardware timeout in seconds */ +#define WDT_HW_TIMEOUT 2 + +/* + * Set the watchdog time interval in 1/256Hz (write-once) + * Counter is 12 bit. + */ +static int at91_wdt_settimeout(unsigned int timeout) +{ + unsigned int reg; + unsigned int mr; + + /* Check if disabled */ + mr = at91_sys_read(AT91_WDT_MR); + if (mr & AT91_WDT_WDDIS) { + printf("sorry, watchdog is disabled\n"); + return -1; + } + + /* + * All counting occurs at SLOW_CLOCK / 128 = 256 Hz + * + * Since WDV is a 12-bit counter, the maximum period is + * 4096 / 256 = 16 seconds. + */ + reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ + /* | AT91_WDT_WDRPROC causes processor reset only */ + | AT91_WDT_WDDBGHLT /* disabled in debug mode */ + | AT91_WDT_WDD /* restart at any time */ + | (timeout & AT91_WDT_WDV); /* timer value */ + at91_sys_write(AT91_WDT_MR, reg); + + return 0; +} + +void hw_watchdog_reset(void) +{ + at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); +} + +void hw_watchdog_init(void) +{ + /* 16 seconds timer, resets enabled */ + at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); +} diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h new file mode 100644 index 0000000..7e18537 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -0,0 +1,38 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] + * + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Watchdog Timer (WDT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_WDT_H +#define AT91_WDT_H + +#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ +#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ +#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ + +#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ +#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ +#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ +#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ +#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ +#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ +#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ +#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ +#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ + +#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ +#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ +#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ + +#endif -- 1.5.6.5

4 9

[U-Boot] Out-of-tree build of API code fails
by Wolfgang Denk 15 Jun '09

15 Jun '09

Dear Rafal, it seems the api_examples/ code fails when building out of tree: -> make O=/work/wd/tmp-ppc PMC440_config Configuring for PMC440 board... -> make O=/work/wd/tmp-ppc all Generating /work/wd/tmp-ppc/include/autoconf.mk.dep Generating /work/wd/tmp-ppc/include/autoconf.mk for dir in tools examples api_examples ; do make -C $dir _depend ; done make[1]: Entering directory `/home/wd/git/u-boot/work/tools' ln -s /home/wd/git/u-boot/work/tools/../common/env_embedded.c /work/wd/tmp-ppc/tools/env_embedded.c ln -s /home/wd/git/u-boot/work/tools/../include/zlib.h /work/wd/tmp-ppc/tools/zlib.h ln -s /home/wd/git/u-boot/work/tools/../lib_generic/crc32.c /work/wd/tmp-ppc/tools/crc32.c ln -s /home/wd/git/u-boot/work/tools/../lib_generic/md5.c /work/wd/tmp-ppc/tools/md5.c ln -s /home/wd/git/u-boot/work/tools/../lib_generic/sha1.c /work/wd/tmp-ppc/tools/sha1.c ln -s /home/wd/git/u-boot/work/tools/../common/image.c /work/wd/tmp-ppc/tools/image.c if [ ! -f /work/wd/tmp-ppc/tools/mkimage.h ] ; then \ ln -s /home/wd/git/u-boot/work/tools/../tools/mkimage.h /work/wd/tmp-ppc/tools/mkimage.h; \ fi if [ ! -f /work/wd/tmp-ppc/tools/fdt_host.h ] ; then \ ln -s /home/wd/git/u-boot/work/tools/../tools/fdt_host.h /work/wd/tmp-ppc/tools/fdt_host.h; \ fi make[1]: Leaving directory `/home/wd/git/u-boot/work/tools' make[1]: Entering directory `/home/wd/git/u-boot/work/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/wd/git/u-boot/work/tools' make[1]: Entering directory `/home/wd/git/u-boot/work/examples' make[1]: Leaving directory `/home/wd/git/u-boot/work/examples' make[1]: Entering directory `/home/wd/git/u-boot/work/examples' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/wd/git/u-boot/work/examples' make[1]: Entering directory `/home/wd/git/u-boot/work/api_examples' make[1]: *** No rule to make target `/work/wd/tmp-ppc/api_examples/.depend', needed by `_depend'. Stop. make[1]: Leaving directory `/home/wd/git/u-boot/work/api_examples' make: *** [depend] Error 2 Could you please have a look? Thanks in advance. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de A Puritan is someone who is deathly afraid that someone, somewhere, is having fun.

2 5

[U-Boot] [PATCH v3] Freescale NFC NAND driver
by John Rigby 04 Jun '09

04 Jun '09

v3: Fixed problem with CFG vs CONFIG_SYS in board/ads5121/ads5121.c v2: Reworked MPC5121 NAND driver. Attempted to address all the problems listed by Scott Wood. Driver is now board independent. Will still need more work to be SOC independent. Driver for the NAND controller on MPC5121. This driver has been tested on ADS5121 rev4 / MPC5121e rev2 only which has the following configuration: 2K page size 8 bit device width This should work on other boards with MPC5121 rev2 silicon with little or no change to the driver. Various vintages of this controller exist on some iMX parts. Getting it to work on an iMX with the same controller version should be fairly easy. More work if it is an iMX with a different version on the controller. This controller treats 2K pages as 4 512 byte pages and the hw ecc is over the combined 512 byte main area and the first 7 bytes of the spare area. The hw ecc is stored in the last 9 bytes of the spare area. This all means the the spare area can not be written separately from the main. This means unmodified JFFS2 will not work. Signed-off-by: John Rigby <jrigby(a)freescale.com> --- board/ads5121/ads5121.c | 16 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_nfc_nand.c | 1105 +++++++++++++++++++++++++++++++++++++++ include/configs/ads5121.h | 38 ++ 4 files changed, 1160 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_nfc_nand.c diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 0610928..bd66e5b 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -24,6 +24,7 @@ #include <common.h> #include <mpc512x.h> #include <asm/bitops.h> +#include <asm/io.h> #include <command.h> #include <asm/processor.h> #include <fdt_support.h> @@ -34,6 +35,7 @@ /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ @@ -312,3 +314,17 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5121_fsl_nfc_board_cs(int chip) +{ + unsigned char *csreg = (unsigned char *)CONFIG_SYS_CPLD_BASE + 0x09; + u8 v; + + v = in_8(csreg); + v |= 0xf; + v &= ~(1<<chip); + + out_8(csreg, v); +} +#endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index b0abe6e..b010b55 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,6 +38,7 @@ endif COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o +COBJS-$(CONFIG_NAND_FSL_NFC) += fsl_nfc_nand.o endif COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/fsl_nfc_nand.c b/drivers/mtd/nand/fsl_nfc_nand.c new file mode 100644 index 0000000..67117fe --- /dev/null +++ b/drivers/mtd/nand/fsl_nfc_nand.c @@ -0,0 +1,1105 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Based on drivers/mtd/nand/mpc5121_nand.c + * which was based on drivers/mtd/nand/mxc_nd.c + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <common.h> +#include <malloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <nand.h> + +#define MIN(x, y) ((x < y) ? x : y) + +static struct fsl_nfc_private { + struct mtd_info mtd; + char spare_only; + char status_req; + u16 col_addr; + int writesize; + int sparesize; + int width; + int chipsel; +} *priv; + +#define IS_2K_PAGE_NAND (priv->writesize == 2048) +#define IS_4K_PAGE_NAND (priv->writesize == 4096) +#define IS_LARGE_PAGE_NAND (priv->writesize > 512) + +#define NFC_REG_BASE ((void *)CONFIG_SYS_NAND_BASE) +/* + * FSL NFC registers Definition + */ +#define NFC_BUF_ADDR (NFC_REG_BASE + 0x1E04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0x1E06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0x1E08) +#define NFC_CONFIG (NFC_REG_BASE + 0x1E0A) +#define NFC_ECC_STATUS1 (NFC_REG_BASE + 0x1E0C) +#define NFC_ECC_STATUS2 (NFC_REG_BASE + 0x1E0E) +#define NFC_SPAS (NFC_REG_BASE + 0x1E10) +#define NFC_WRPROT (NFC_REG_BASE + 0x1E12) +#define NFC_NF_WRPRST (NFC_REG_BASE + 0x1E18) +#define NFC_CONFIG1 (NFC_REG_BASE + 0x1E1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0x1E1C) +#define NFC_UNLOCKSTART_BLKADDR0 (NFC_REG_BASE + 0x1E20) +#define NFC_UNLOCKEND_BLKADDR0 (NFC_REG_BASE + 0x1E22) +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0x1E24) +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0x1E26) +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0x1E28) +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0x1E2A) +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0x1E2C) +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0x1E2E) + +/*! + * Addresses for NFC MAIN RAM BUFFER areas + */ +#define MAIN_AREA(n) (NFC_REG_BASE + (n)*0x200) + +/*! + * Addresses for NFC SPARE BUFFER areas + */ +#define SPARE_LEN 0x40 +#define SPARE_AREA(n) (NFC_REG_BASE + 0x1000 + (n)*SPARE_LEN) + +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_INT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLOCKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#define NFC_ECC_MODE_4 1 +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +#if defined(CONFIG_PPC) +#define NFC_WRITEL(r, v) out_be32(r, v) +#define NFC_WRITEW(r, v) out_be16(r, v) +#define NFC_WRITEB(r, v) out_8(r, v) +#define NFC_READL(r) in_be32(r) +#define NFC_READW(r) in_be16(r) +#define NFC_READB(r) in_8(r) +#elif defined(CONFIG_ARM) +#define NFC_WRITEL(r, v) writel(v, r) +#define NFC_WRITEW(r, v) writew(v, r) +#define NFC_WRITEB(r, v) writeb(r, v) +#define NFC_READL(r) readl(r) +#define NFC_READW(r) readw(r) +#define NFC_READB(r) readb(r) +#endif + + +#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 1; +#endif + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + }, + .oobfree = { + {0, 5} /* byte 5 is factory bad block marker */ + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 36, + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 64, /* actually 72 but only room for 64 */ + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + 71, 72, 73, 74, 75, 76, 77, 78, 79, + 87, 88, 89, 90, 91, 92, 93, 94, 95, + 103, 104, 105, 106, 107, 108, 109, 110, 111, + 119, /* 120, 121, 122, 123, 124, 125, 126, 127, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + {64, 7}, + {80, 7}, + {96, 7}, + {112, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k_218_spare = { + .eccbytes = 64, /* actually 144 but only room for 64 */ + .eccpos = { + /* 18 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, + 33, 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, 50, + 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, + 85, 86, 87, 88, 89, 90, 91, 92, 93, + 94, /* 95, 96, 97, 98, 99, 100, 101, 102, + 111, 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, + 137, 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, 154, + 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 174, 175, 176, 177, 178, 179, 180, + 189, 190, 191, 192, 193, 194, 195, 196, 197, + 198, 199, 200, 201, 202, 203, 204, 205, 206, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {25, 8}, + {51, 8}, + {77, 8}, + {103, 8}, + {129, 8}, + {155, 8}, + {181, 8}, + }, +}; + +/* + * Functions to transfer data to/from spare erea. + */ +static void copy_from_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_fromio(pbuf, SPARE_AREA(i), MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_fromio(pbuf, SPARE_AREA(i), len); +} + +static void copy_to_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_toio(SPARE_AREA(i), pbuf, MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_toio(SPARE_AREA(i), pbuf, len); +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @max_retries number of retry attempts (separated by 1 us) + */ +static void wait_op_done(int max_retries) +{ + + while (1) { + max_retries--; + if (NFC_READW(NFC_CONFIG2) & NFC_INT) + break; + udelay(1); + } + if (max_retries <= 0) + MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n", __FUNCTION__); +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @cmds command for NAND Flash + */ +static void send_cmd(u16 cmd) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(%#x)\n", cmd); + + NFC_WRITEW(NFC_FLASH_CMD, cmd); + NFC_WRITEW(NFC_CONFIG2, NFC_CMD); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @addr address to be written to NFC. + */ +static void send_addr(u16 addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(%#x)\n", addr); + NFC_WRITEW(NFC_FLASH_ADDR, (addr << NFC_FLASH_ADDR_SHIFT)); + + NFC_WRITEW(NFC_CONFIG2, NFC_ADDR); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_prog_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_INPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_read_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_OUTPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + /* NFC buffer 0 is used for device ID output */ + /* Set RBA bits for BUFFER0 */ + val &= ~0x7; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read ID into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_ID); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + u32 save; + u16 ret; + u32 val; + /* Issue status request to NAND device */ + + /* save the main area1 first word, later do recovery */ + save = NFC_READL(MAIN_AREA(1)); + NFC_WRITEL(MAIN_AREA(1), 0); + + /* + * NFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + + /* Select BUFFER1 */ + val = NFC_READW(NFC_BUF_ADDR); + val &= ~0x7; + val |= 1; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read status into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_STATUS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + if (NFC_READW(NFC_CONFIG1) & NFC_BIG) + ret = NFC_READB(MAIN_AREA(1)); + else + ret = NFC_READB(MAIN_AREA(1) + 3); + + NFC_WRITEL(MAIN_AREA(1), save); + return ret; +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int fsl_nfc_dev_ready(struct mtd_info *mtd) +{ + return 1; +} + +static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + return; +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int fsl_nfc_check_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + int is_4bit_ecc = NFC_READW(NFC_CONFIG1) & NFC_ECC_MODE_4; + + ecc_bit_mask = (is_4bit_ecc ? 0x7 : 0xf); + err_limit = (is_4bit_ecc ? 0x4 : 0x8); + + no_subpages = mtd->writesize >> 9; + + ecc_stat = NFC_READW(NFC_ECC_STATUS1); + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) + return -1; + else + ret += err; + ecc_stat >>= 4; + } while (--no_subpages); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte(struct mtd_info *mtd) +{ + void *area_buf; + u_char rv; + + /* Check for status request */ + if (priv->status_req) { + rv = get_dev_status() & 0xff; + return rv; + } + + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + rv = NFC_READB(area_buf + priv->col_addr); + priv->col_addr++; + return rv; +} + +/*! + * This function reads word from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 fsl_nfc_read_word(struct mtd_info *mtd) +{ + u16 rv; + void *area_buf; + + /* If we are accessing the spare region */ + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + /* Update saved column address */ + rv = NFC_READW(area_buf + priv->col_addr); + priv->col_addr += 2; + + return rv; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (priv->status_req) + return (get_dev_status() & 0xff); + + return fsl_nfc_read_word(mtd) & 0xff; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be written to NAND Flash + * @len number of bytes to be written + */ +static void fsl_nfc_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_to_spare(mtd, (char *)buf, len); + return; + } else { + priv->col_addr += len; + memcpy_toio(MAIN_AREA(0), (void *)buf, len); + } +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be read from NAND Flash + * @len number of bytes to be read + */ +static void fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_from_spare(mtd, buf, len); + return; + } else { + priv->col_addr += len; + memcpy_fromio((void *)buf, MAIN_AREA(0), len); + } +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be verified + * @len length of the data to be verified + * + * @return -1 if error else 0 + * + */ +static int fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + void *main_buf = MAIN_AREA(0); + /* check for 32-bit alignment? */ + u32 *p = (u32 *) buf; + u32 v = 0; + + for (; len > 0; len -= 4, main_buf += 4) + v = NFC_READL(main_buf); + if (v != *p++) + return -1; + return 0; +} + +static int fsl_nfc_get_hw_config(struct nand_chip *this) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 rcwh; + int rcwh_romloc; + int rcwh_ps; + int width; + int writesize = 0; + int sparesize = 0; + + /* + * Only support 2K for now. + * Remove this when others are tested and debugged. + */ +#if 1 + if (CONFIG_FSL_NFC_WRITE_SIZE != 2048) { + printf("FSL NFC: " + "%d byte write size flash support is untested\n", + CONFIG_FSL_NFC_WRITE_SIZE); + return -1; + } +#endif + rcwh = NFC_READL((void *)&(im->reset.rcwh)); + width = ((rcwh >> 6) & 0x1) ? 2 : 1; + + if (width != CONFIG_FSL_NFC_WIDTH) { + printf("FSL NFC: Device width mismatch, compiled for %d, " + "reset configuration word width is %d\n", + CONFIG_FSL_NFC_WIDTH, width); + return -1; + } + + if (width == 2) { + this->options |= NAND_BUSWIDTH_16; + this->read_byte = fsl_nfc_read_byte16; + } + + /* + * Decode the rcwh_ps and rcwh_romloc + * bits from reset config word + * to determine write size + */ + rcwh_ps = (rcwh >> 7) & 0x1; + rcwh_romloc = (rcwh >> 21) & 0x3; + switch (rcwh_ps << 2 | rcwh_romloc) { + case 0x0: + case 0x1: + writesize = 512; + sparesize = 16; + break; + case 0x2: + case 0x3: + writesize = 4096; + sparesize = 128; + break; + case 0x4: + case 0x5: + writesize = 2048; + sparesize = 64; + break; + case 0x6: + case 0x7: + writesize = 4096; + sparesize = 218; + break; + } + if (CONFIG_FSL_NFC_WRITE_SIZE != writesize) { + printf("FSL NFC: " + "Device write size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_WRITE_SIZE, writesize); + return -1; + } + if (CONFIG_FSL_NFC_SPARE_SIZE != sparesize) { + printf("FSL NFC: " + "Device spare size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_SPARE_SIZE, sparesize); + return -1; + } + + priv->sparesize = sparesize; + priv->writesize = writesize; + priv->width = width; + return 0; +} + +#ifndef CONFIG_FSL_NFC_BOARD_CS_FUNC +static void fsl_nfc_select_chip(u8 cs) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + val &= ~0x60; + val |= cs << 5; + NFC_WRITEW(NFC_BUF_ADDR, val); +} +#define CONFIG_FSL_NFC_BOARD_CS_FUNC fsl_nfc_select_chip +#endif + + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @mtd MTD structure for the NAND Flash + * @chip val indicating select or deselect + */ +static void fsl_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + /* + * This is different than the linux version. + * Switching between chips is done via + * board_nand_select_device. + * + * Only valid chip numbers here are + * 0 select + * -1 deselect + */ + if (chip < -1 || chip > 0) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + } + + if (chip < 0) { + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_CE)); + return; + } + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_CE)); + + /* + * Turn on appropriate chip. + */ + CONFIG_FSL_NFC_BOARD_CS_FUNC(priv->chipsel); +} + +/* + * Function to perform the address cycles. + */ +static void fsl_nfc_do_addr_cycle(struct mtd_info *mtd, int column, + int page_addr) +{ + struct nand_chip *this = mtd->priv; + u32 page_mask = this->pagemask; + + if (column != -1) { + send_addr(column & 0xff); + /* large page nand needs an extra column addr cycle */ + if (IS_2K_PAGE_NAND) + send_addr((column >> 8) & 0xf); + else if (IS_4K_PAGE_NAND) + send_addr((column >> 8) & 0x1f); + } + if (page_addr != -1) { + do { + send_addr((page_addr & 0xff)); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +} + +/* + * Function to read a page from nand device. + */ +static void read_full_page(struct mtd_info *mtd, int page_addr) +{ + send_cmd(NAND_CMD_READ0); + + fsl_nfc_do_addr_cycle(mtd, 0, page_addr); + + if (IS_LARGE_PAGE_NAND) { + send_cmd(NAND_CMD_READSTART); + send_read_page(0); + } else { + send_read_page(0); + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @mtd MTD structure for the NAND Flash + * @command command for NAND Flash + * @column column offset for the page read + * @page_addr page to be read from NAND Flash + */ +static void fsl_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, + "fsl_nfc_command (cmd = %#x, col = %#x, page = %#x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + priv->status_req = 0; + + /* Reset column address to 0 */ + priv->col_addr = 0; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + priv->status_req = 1; + break; + + case NAND_CMD_READ0: + priv->spare_only = 0; + break; + + case NAND_CMD_READOOB: + priv->col_addr = column; + priv->spare_only = 1; + command = NAND_CMD_READ0; /* only READ0 is valid */ + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) + priv->spare_only = 1; + else + priv->spare_only = 0; + break; + + case NAND_CMD_PAGEPROG: + if (!priv->spare_only) + send_prog_page(0); + else + return; + break; + + case NAND_CMD_ERASE1: + break; + case NAND_CMD_ERASE2: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command); + + fsl_nfc_do_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (IS_LARGE_PAGE_NAND) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART); + /* read for each AREA */ + send_read_page(0); + } else + send_read_page(0); + break; + + case NAND_CMD_READID: + send_read_id(); + break; + } +} + +static int fsl_nfc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + return get_dev_status(); +} + +static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + if (sndcmd) { + read_full_page(mtd, page); + sndcmd = 0; + } + + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return sndcmd; +} + +static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + int read_oob_col = 0; + + send_cmd(NAND_CMD_READ0); + send_cmd(NAND_CMD_SEQIN); + fsl_nfc_do_addr_cycle(mtd, read_oob_col, page); + + /* copy the oob data */ + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); + + send_prog_page(0); + + send_cmd(NAND_CMD_PAGEPROG); + + status = fsl_nfc_wait(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -1; + return 0; +} + +static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + int stat; + + stat = fsl_nfc_check_ecc_status(mtd); + if (stat == -1) { + mtd->ecc_stats.failed++; + printf("FSL NFC: UnCorrectable RS-ECC Error\n"); + } else { + mtd->ecc_stats.corrected += stat; + if (stat) + printf("%d Symbol Correctable RS-ECC Error\n", stat); + } + + memcpy_fromio((void *)buf, MAIN_AREA(0), mtd->writesize); + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +static void fsl_nfc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + memcpy_toio(MAIN_AREA(0), buf, mtd->writesize); + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); +} + + +/* + * Generic flash bbt decriptors + */ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +/* + * These are identical to the generic versions except + * for the offsets. + */ +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + if (chip >= CONFIG_FSL_NFC_CHIPS) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + priv->chipsel = chip; +} + + +int board_nand_init(struct nand_chip *nand) +{ + struct mtd_info *mtd; + + priv = malloc(sizeof(*priv)); + if (!priv) { + printf("FSL NFC: failed to allocate priv structure\n"); + return -1; + } + memset(priv, 0, sizeof(*priv)); + + if (fsl_nfc_get_hw_config(nand) < 0) + return -1; + + mtd = &priv->mtd; + mtd->priv = nand; + + /* 5 us command delay time */ + nand->chip_delay = 5; + + nand->dev_ready = fsl_nfc_dev_ready; + nand->cmdfunc = fsl_nfc_command; + nand->waitfunc = fsl_nfc_wait; + nand->select_chip = fsl_nfc_select_chip; + nand->options = NAND_USE_FLASH_BBT; + if (priv->width == 2) { + nand->options |= NAND_BUSWIDTH_16; + nand->read_byte = fsl_nfc_read_byte16; + } + nand->read_byte = fsl_nfc_read_byte; + nand->read_word = fsl_nfc_read_word; + nand->write_buf = fsl_nfc_write_buf; + nand->read_buf = fsl_nfc_read_buf; + nand->verify_buf = fsl_nfc_verify_buf; + + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_RST)); + + /* Disable interrupt */ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_INT_MSK)); + + if (hardware_ecc) { + nand->ecc.read_page = fsl_nfc_read_page; + nand->ecc.write_page = fsl_nfc_write_page; + nand->ecc.read_oob = fsl_nfc_read_oob; + nand->ecc.write_oob = fsl_nfc_write_oob; + if (IS_2K_PAGE_NAND) + nand->ecc.layout = &nand_hw_eccoob_2k; + else if (IS_4K_PAGE_NAND) + if (priv->sparesize == 128) + nand->ecc.layout = &nand_hw_eccoob_4k; + else + nand->ecc.layout = &nand_hw_eccoob_4k_218_spare; + else + nand->ecc.layout = &nand_hw_eccoob_512; + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = nand->ecc.layout; + nand->ecc.calculate = NULL; + nand->ecc.hwctl = fsl_nfc_enable_hwecc; + nand->ecc.correct = NULL; + nand->ecc.mode = NAND_ECC_HW; + /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */ + nand->ecc.size = 512; + nand->ecc.bytes = 9; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + } else { + nand->ecc.mode = NAND_ECC_SOFT; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_EN)); + } + + NFC_WRITEW(NFC_CONFIG1, NFC_READW(NFC_CONFIG1) & ~NFC_SP_EN); + + + /* Reset NAND */ + nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ + NFC_WRITEW(NFC_CONFIG, NFC_BLS_UNLOCKED); + + /* Blocks to be unlocked */ + NFC_WRITEW(NFC_UNLOCKSTART_BLKADDR0, 0x0); + NFC_WRITEW(NFC_UNLOCKEND_BLKADDR0, 0xffff); + + /* Unlock Block Command for given address range */ + NFC_WRITEW(NFC_WRPROT, NFC_WPC_UNLOCK); + + /* Set sparesize */ + NFC_WRITEW(NFC_SPAS, + (NFC_READW(NFC_SPAS) & 0xff00) | (priv->sparesize/2)); + + /* + * Only use 8bit ecc (aka not 4 bit) if large spare size + */ + if (priv->sparesize == 218) + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_MODE_4)); + else + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) | NFC_ECC_MODE_4)); + + return 0; +} diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 8ec5e9d..d967c2e 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -33,6 +33,7 @@ * * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x4000_0000 - 0x400F_FFFF NFC (1 MB) * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) * 0x8200_0000 - 0x8200_001F CPLD (32 B) * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) @@ -199,6 +200,43 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only) + */ +#define CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0x40000000 +#endif +#define CONFIG_CMD_NAND 1 +/* + * The flash on ADS5121 board is two flash chips in one package + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 +#define CONFIG_NAND_MPC5121 +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS 2 + +#ifndef __ASSEMBLY__ +/* + * ADS board as a custom chip select + */ +extern void ads5121_fsl_nfc_board_cs(int); +#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5121_fsl_nfc_board_cs +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_NAND_FSL_NFC */ + + +/* * CPLD registers area is really only 32 bytes in size, but the smallest possible LP * window is 64KB */ -- 1.5.6.2.255.gbed62

6 8

[U-Boot] [PATCH 1/1] make MODEM SUPPORT generic instead of duplicate it
by Jean-Christophe PLAGNIOL-VILLARD 03 Jun '09

03 Jun '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- common/Makefile | 1 + common/modem.c | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ lib_arm/board.c | 99 -------------------------------------------- lib_ppc/board.c | 97 ------------------------------------------- 4 files changed, 124 insertions(+), 196 deletions(-) create mode 100644 common/modem.c diff --git a/common/Makefile b/common/Makefile index f13cd11..3038e46 100644 --- a/common/Makefile +++ b/common/Makefile @@ -147,6 +147,7 @@ COBJS-y += flash.o COBJS-$(CONFIG_CMD_KGDB) += kgdb.o COBJS-$(CONFIG_LCD) += lcd.o COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o +COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o COBJS-$(CONFIG_UPDATE_TFTP) += update.o COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o diff --git a/common/modem.c b/common/modem.c new file mode 100644 index 0000000..27e164a --- /dev/null +++ b/common/modem.c @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* called from main loop (common/main.c) */ +/* 'inline' - We have to do it fast */ +static inline void mdm_readline(char *buf, int bufsiz) +{ + char c; + char *p; + int n; + + n = 0; + p = buf; + for(;;) { + c = serial_getc(); + + /* dbg("(%c)", c); */ + + switch(c) { + case '\r': + break; + case '\n': + *p = '\0'; + return; + + default: + if(n++ > bufsiz) { + *p = '\0'; + return; /* sanity check */ + } + *p = c; + p++; + break; + } + } +} + +extern void dbg(const char *fmt, ...); +int mdm_init (void) +{ + char env_str[16]; + char *init_str; + int i; + extern char console_buffer[]; + extern void enable_putc(void); + extern int hwflow_onoff(int); + + enable_putc(); /* enable serial_putc() */ + +#ifdef CONFIG_HWFLOW + init_str = getenv("mdm_flow_control"); + if (init_str && (strcmp(init_str, "rts/cts") == 0)) + hwflow_onoff (1); + else + hwflow_onoff(-1); +#endif + + for (i = 1;;i++) { + sprintf(env_str, "mdm_init%d", i); + if ((init_str = getenv(env_str)) != NULL) { + serial_puts(init_str); + serial_puts("\n"); + for(;;) { + mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); + dbg("ini%d: [%s]", i, console_buffer); + + if ((strcmp(console_buffer, "OK") == 0) || + (strcmp(console_buffer, "ERROR") == 0)) { + dbg("ini%d: cmd done", i); + break; + } else /* in case we are originating call ... */ + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini%d: connect", i); + return 0; + } + } + } else + break; /* no init string - stop modem init */ + + udelay(100000); + } + + udelay(100000); + + /* final stage - wait for connect */ + for(;i > 1;) { /* if 'i' > 1 - wait for connection + message from modem */ + mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); + dbg("ini_f: [%s]", console_buffer); + if (strncmp(console_buffer, "CONNECT", 7) == 0) { + dbg("ini_f: connected"); + return 0; + } + } + + return 0; +} diff --git a/lib_arm/board.c b/lib_arm/board.c index 09eaaf2..7d06c0f 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -484,102 +484,3 @@ void hang (void) puts ("### ERROR ### Please RESET the board ###\n"); for (;;); } - -#ifdef CONFIG_MODEM_SUPPORT -static inline void mdm_readline(char *buf, int bufsiz); - -/* called from main loop (common/main.c) */ -extern void dbg(const char *fmt, ...); -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern char console_buffer[]; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); - return 0; - } - } - - return 0; -} - -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - /* dbg("(%c)", c); */ - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} -#endif /* CONFIG_MODEM_SUPPORT */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 3bcfb45..cb23f52 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1220,103 +1220,6 @@ void hang (void) for (;;); } -#ifdef CONFIG_MODEM_SUPPORT -/* called from main loop (common/main.c) */ -/* 'inline' - We have to do it fast */ -static inline void mdm_readline(char *buf, int bufsiz) -{ - char c; - char *p; - int n; - - n = 0; - p = buf; - for(;;) { - c = serial_getc(); - - /* dbg("(%c)", c); */ - - switch(c) { - case '\r': - break; - case '\n': - *p = '\0'; - return; - - default: - if(n++ > bufsiz) { - *p = '\0'; - return; /* sanity check */ - } - *p = c; - p++; - break; - } - } -} - -extern void dbg(const char *fmt, ...); -int mdm_init (void) -{ - char env_str[16]; - char *init_str; - int i; - extern char console_buffer[]; - extern void enable_putc(void); - extern int hwflow_onoff(int); - - enable_putc(); /* enable serial_putc() */ - -#ifdef CONFIG_HWFLOW - init_str = getenv("mdm_flow_control"); - if (init_str && (strcmp(init_str, "rts/cts") == 0)) - hwflow_onoff (1); - else - hwflow_onoff(-1); -#endif - - for (i = 1;;i++) { - sprintf(env_str, "mdm_init%d", i); - if ((init_str = getenv(env_str)) != NULL) { - serial_puts(init_str); - serial_puts("\n"); - for(;;) { - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini%d: [%s]", i, console_buffer); - - if ((strcmp(console_buffer, "OK") == 0) || - (strcmp(console_buffer, "ERROR") == 0)) { - dbg("ini%d: cmd done", i); - break; - } else /* in case we are originating call ... */ - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini%d: connect", i); - return 0; - } - } - } else - break; /* no init string - stop modem init */ - - udelay(100000); - } - - udelay(100000); - - /* final stage - wait for connect */ - for(;i > 1;) { /* if 'i' > 1 - wait for connection - message from modem */ - mdm_readline(console_buffer, CONFIG_SYS_CBSIZE); - dbg("ini_f: [%s]", console_buffer); - if (strncmp(console_buffer, "CONNECT", 7) == 0) { - dbg("ini_f: connected"); - return 0; - } - } - - return 0; -} - -#endif #if 0 /* We could use plain global data, but the resulting code is bigger */ /* -- 1.5.6.5

2 6