February 2009 - U-Boot

[U-Boot] bootvx on MPC8572
by Robert Rzepiela 23 Feb '09

23 Feb '09

Hello I am running u-boot.2009.01 on DS-8572 (whitefin). I use tftpboot to download an elf image (from vxWorks release for the eval) and try to run it with "bootx". After messages about loading text etc etc. the board hangs right after printing "Starting vxWorks at ...". I am using default bootline . Is there something obvious I am missing here or I need to get ready for JTAG ? thanks

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[U-Boot] Doctor Database
by nosendhere＠c-71-62-117-18.hsd1.va.comcast.net 23 Feb '09

23 Feb '09

Practicing Physicians in the USA Lots of Physicians in specialties like Orthopedics, Surgery, Radiology, Dermatology, Neurology, General Practice etc.. you can sort by many different fields like city, state or zip Dramatic cost reduction: $399 {}{}{} Take all 4 items below for F REE when you order *** ** Optometrists <> Visiting Nurses & RN's <> Massage Therapists --> Acupuncturists send email to - : Soto(a)accudoclist.com only during this week ------------------------------------------------------------- Forward email to rrr(a)accudoclist.com to purge you from our records

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[U-Boot] [PATCH] [85xx] Add eTSEC 1/2 IO override control definition
by ksi＠koi8.net 23 Feb '09

23 Feb '09

This adds missing tsec12ioovcr to include/asm-ppc/immap_85xx.h. It was named "res14" (for "reserved") while tsec34ioovcr was properly there. Signed-off-by: Sergey Kubushyn <ksi(a)koi8.net> --- diff -purN u-boot.orig/include/asm-ppc/immap_85xx.h u-boot/include/asm-ppc/immap_85xx.h --- u-boot.orig/include/asm-ppc/immap_85xx.h 2009-02-19 13:39:31.000000000 -0800 +++ u-boot/include/asm-ppc/immap_85xx.h 2009-02-23 10:32:48.000000000 -0800 @@ -1667,7 +1667,11 @@ typedef struct ccsr_gur { uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ +#ifdef CONFIG_MPC8548 + uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */ +#else uint res14; /* 0xe0f28 */ +#endif uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t;

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[U-Boot] [PATCH/next branch] ppc4xx: Don't write the MAC address into the internal SoC registers
by Stefan Roese 23 Feb '09

23 Feb '09

Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/cpu_init.c | 29 +---------------------------- 1 files changed, 1 insertions(+), 28 deletions(-) diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index a8f589a..577d33f 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -321,35 +321,9 @@ cpu_init_f (void) */ int cpu_init_r (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) - bd_t *bd = gd->bd; - unsigned long reg; - uchar enetaddr[6]; #if defined(CONFIG_405GP) uint pvr = get_pvr(); -#endif - - /* - * Write Ethernetaddress into on-chip register - */ - reg = 0x00000000; - eth_getenv_enetaddr("ethaddr", enetaddr); - reg |= enetaddr[0]; /* set high address */ - reg = reg << 8; - reg |= enetaddr[1]; - out32 (EMAC_IAH, reg); - - reg = 0x00000000; - reg |= enetaddr[2]; /* set low address */ - reg = reg << 8; - reg |= enetaddr[3]; - reg = reg << 8; - reg |= enetaddr[4]; - reg = reg << 8; - reg |= enetaddr[5]; - out32 (EMAC_IAL, reg); -#if defined(CONFIG_405GP) /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. @@ -358,7 +332,6 @@ int cpu_init_r (void) mtdcr(ecr, 0x60606000); } #endif /* defined(CONFIG_405GP) */ -#endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ - return (0); + return 0; } -- 1.6.1.3

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[U-Boot] [PATCH] i.MX31: fir imx31_phycore to work after Linux reboot
by Guennadi Liakhovetski 23 Feb '09

23 Feb '09

Upon power on i.MX31 enables most peripheral clocks, Linux disables the ones that it's not using to save power. Until now U-Boot on imx31_phycore didn't enable the I2C clock explicitly, so, after a reboot under Linux, if Linux didn't use I2C, the clock would stay disabled. And U-Boot on imx31_phycore uses an I2C EEPROM for environment data. So, after a reboot U-Boot would be left with its default environment. This patch fixes this problem by enabling the I2C clock explicitly. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- board/imx31_phycore/imx31_phycore.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 4c64cb9..6b78194 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -60,6 +60,9 @@ int board_init (void) mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); + /* start I2C2 clock */ + __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << 28); + gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ -- 1.5.4

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[U-Boot] [PATCH v3] Add 16bpp BMP support
by Mark Jackson 23 Feb '09

23 Feb '09

This patch adds 16bpp BMP support to the common lcd code. Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code. At the moment it's only been tested on the MIMC200 AVR32 board, but extending this to other platforms should be a simple task !! Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- common/lcd.c | 49 +++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 39 insertions(+), 10 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index ae79051..16d6f2a 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -84,7 +84,7 @@ extern void lcd_enable (void); static void *lcd_logo (void); -#if LCD_BPP == LCD_COLOR8 +#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) extern void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); #endif @@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bpix = NBITS(panel_info.vl_bpix); - if ((bpix != 1) && (bpix != 8)) { + if ((bpix != 1) && (bpix != 8) && (bpix != 16)) { printf ("Error: %d bit/pixel mode not supported by U-Boot\n", bpix); return 1; @@ -738,17 +738,46 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x); - for (i = 0; i < height; ++i) { - WATCHDOG_RESET(); - for (j = 0; j < width ; j++) + + switch (bpix) { + case 1: /* pass through */ + case 8: + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width ; j++) #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD) - *(fb++) = *(bmap++); + *(fb++) = *(bmap++); #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) - *(fb++)=255-*(bmap++); + *(fb++)=255-*(bmap++); #endif - bmap += (width - padded_line); - fb -= (width + lcd_line_length); - } + bmap += (width - padded_line); + fb -= (width + lcd_line_length); + } + break; + +#if defined(CONFIG_BMP_16BPP) + case 16: + for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); + for (j = 0; j < width; j++) { +#if defined(CONFIG_ATMEL_LCD_BGR555) + *(fb++) = ((bmap[0] & 0x1f) << 2) | (bmap[1] & 0x03); + *(fb++) = (bmap[0] & 0xe0) | ((bmap[1] & 0x7c) >> 2); + bmap += 2; +#else + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); +#endif + } + bmap += (padded_line - width) * 2; + fb -= (width * 2 + lcd_line_length); + } + break; +#endif /* CONFIG_BMP_16BPP */ + + default: + break; + }; return (0); }

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[U-Boot] [PATCH 1/1 v2] Setup extra MIMC200 chip selects
by Mark Jackson 23 Feb '09

23 Feb '09

Added code to setup the extra Flash and FRAM chip selects as used on the MIMC200 board. V2 moves the init code from the common "cpu.c" file into the board specific setup file. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- board/mimc/mimc200/mimc200.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 8516dcb..423238b 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -29,6 +29,8 @@ #include <asm/arch/hmatrix.h> #include <lcd.h> +#include "../../../cpu/at32ap/hsmc3.h" + #define SM_PM_GCCTRL 0x0060 DECLARE_GLOBAL_DATA_PTR; @@ -98,6 +100,18 @@ int board_early_init_f(void) /* release phys reset */ gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */ + /* setup Data Flash chip select (NCS2) */ + hsmc3_writel(MODE2, 0x20121003); + hsmc3_writel(CYCLE2, 0x000a0009); + hsmc3_writel(PULSE2, 0x0a060806); + hsmc3_writel(SETUP2, 0x00030102); + + /* setup FRAM chip select (NCS3) */ + hsmc3_writel(MODE3, 0x10120001); + hsmc3_writel(CYCLE3, 0x001e001d); + hsmc3_writel(PULSE3, 0x08040704); + hsmc3_writel(SETUP3, 0x02050204); + #if defined(CONFIG_MACB) /* init macb0 pins */ gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */

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[U-Boot] [PATCH 1/1] MIMC200: tidy GCLK init code
by Mark Jackson 23 Feb '09

23 Feb '09

Change the MIMC200 startup code to use the built-in (rather than hard-coded) funtions for setting up gclk outputs. We'll also move the code to the new, more-appropriate board_postclk_init() routine. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- board/mimc/mimc200/mimc200.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index ec83b9d..62c0943 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -30,8 +30,6 @@ #include <asm/arch/portmux.h> #include <lcd.h> -#define SM_PM_GCCTRL 0x0060 - DECLARE_GLOBAL_DATA_PTR; static const struct sdram_config sdram_config = { @@ -83,10 +81,6 @@ int board_early_init_f(void) portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); - /* GCLK0 - 10MHz clock */ - writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); - portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, PORTMUX_FUNC_A, 0); - udelay(5000); /* release phys reset */ @@ -132,6 +126,14 @@ int board_early_init_r(void) return 0; } +int board_postclk_init(void) +{ + /* Use GCLK0 as 10MHz output */ + gclk_enable_output(0, PORTMUX_DRIVE_LOW); + gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000); + return 0; +} + /* SPI chip select control */ #ifdef CONFIG_ATMEL_SPI #include <spi.h>

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[U-Boot] [PATCH v2 0/9] Support for ATEVK1100 evaluation board
by Gunnar Rangoy 23 Feb '09

23 Feb '09

This is a patch series which adds support for the ATEVK1100 evaluation board[1], and the AT32UC3A0xxx[2] microcontrollers used on that board. The patch series is based on avr32/next. Some of these patches has already been submitted and most of the received feedback has been addressed. We would like to thank you for all the received feedback, and say thay we are sorry for the long delay. This microcontroller is similar to the AT32AP700x, which is already supported by U-Boot, and this code is therefore based on that. Patch 1 makes a change which works around a bug in the compiler. Patch 2-7 makes changes to other avr32-code in preparation for support of the new microcontroller. Patch 8 adds support for the AT32UC3A0xxx microcontrollers. Patch 9 adds support for the ATEVK1100 evaluation board. The current revisions of the microcontroller have a bug in the SDRAM-controller, which makes it unreliable to run code from SDRAM. We therefore currently don't use SDRAM, but rather SRAM. Changes since last time: - Merged the two patch-series. - Config option for searching for phy-address. - Config option for limiting macb speed to 10 Mbps. - Changed serial port speed to 115200. - Some cleanups. What works: Loading U-Boot, serial console, loading image over dhcp/tftp, booting image. [1] http://www.atmel.com/dyn/Products/tools_card.asp?tool_id=4114 [2] http://www.atmel.com/products/avr32/uc3/uc3_2.asp?family_id=682

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Re: [U-Boot] U-Boot Digest, Vol 9, Issue 275
by Peter Griffin 23 Feb '09

23 Feb '09

> i'm using u-boot -1.3.0 in MPC8313 evaluation board, it having a NAND , NOR > Flash , u-boot stored in NOR flash. when i do the saveenv , reset command > the u-boot is erased. i'm not able to fix this issue. help me to fix this > issue > On my board this was due to CONFIG_SYS_MONITOR_LEN not being big enough. Peter

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