December 2009 - U-Boot

[U-Boot] [PATCH ARM 4/4] Change s3c24x0 register struct members to lower case
by kevin.morfitt＠fearnside-systems.co.uk 07 Feb '10

07 Feb '10

Changes the names of the s3c24x0 register struct members from upper-case to lower-case. Signed-off-by: Kevin Morfitt <kevin.morfitt(a)fearnside-systems.co.uk> --- checkpatch.pl reports no errors. MAKEALL ARM9 reports no new warnings or errors. Note that this is based on the u-boot-master repository. The versions of s3c24x0_nand.c file are different in the u-boot-samsung, u-boot-nand-flash and u-boot-master repositories. board/mpl/vcma9/vcma9.c | 42 ++-- board/mpl/vcma9/vcma9.h | 20 +- board/samsung/smdk2400/smdk2400.c | 29 +- board/samsung/smdk2410/smdk2410.c | 38 ++- board/sbc2410x/sbc2410x.c | 46 ++-- board/trab/auto_update.c | 1 + board/trab/cmd_trab.c | 36 ++- board/trab/rs485.c | 44 ++- board/trab/trab.c | 71 ++-- board/trab/trab_fkt.c | 159 +++++---- board/trab/tsc2000.c | 38 +- board/trab/tsc2000.h | 112 ++++--- board/trab/vfd.c | 89 +++--- cpu/arm920t/s3c24x0/interrupts.c | 3 +- cpu/arm920t/s3c24x0/speed.c | 8 +- cpu/arm920t/s3c24x0/timer.c | 18 +- cpu/arm920t/s3c24x0/usb.c | 11 +- cpu/arm920t/s3c24x0/usb_ohci.c | 15 +- drivers/i2c/s3c24x0_i2c.c | 102 +++--- drivers/mtd/nand/s3c2410_nand.c | 24 +- drivers/rtc/s3c24x0_rtc.c | 52 ++-- drivers/serial/serial_s3c24x0.c | 26 +- include/asm-arm/arch-s3c24x0/s3c24x0.h | 578 ++++++++++++++++---------------- 23 files changed, 819 insertions(+), 743 deletions(-) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 5401664..73cd260 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -30,6 +30,7 @@ #include <asm/arch/s3c24x0_cpu.h> #include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> #include "vcma9.h" #include "../common/common_util.h" @@ -78,43 +79,44 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x002AAAAA; - gpio->GPBUP = 0x000002BF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x000037F7; - gpio->GPFCON = 0x00000000; - gpio->GPFUP = 0x00000000; - gpio->GPGCON = 0xFFEAFF5A; - gpio->GPGUP = 0x0000F0DC; - gpio->GPHCON = 0x0028AAAA; - gpio->GPHUP = 0x00000656; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); /* setup correct IRQ modes for NIC */ /* rising edge mode */ - gpio->EXTINT2 = (gpio->EXTINT2 & ~(7 << 8)) | (4 << 8); + writel((readl(&gpio->extint2) & ~(7 << 8)) | (4 << 8), &gpio->extint2); /* select USB port 2 to be host or device (fix to host for now) */ - gpio->MISCCR |= 0x08; + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); /* init serial */ gd->baudrate = CONFIG_BAUDRATE; diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index adc7673..0fd34a2 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -41,14 +41,14 @@ static inline void NF_Conf(u16 conf) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCONF = conf; + writel(conf, &nand->nfconf); } static inline void NF_Cmd(u8 cmd) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCMD = cmd; + writel(cmd, &nand->nfcmd); } static inline void NF_CmdW(u8 cmd) @@ -61,7 +61,7 @@ static inline void NF_Addr(u8 addr) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFADDR = addr; + writel(addr, &nand->nfaddr); } static inline void NF_SetCE(NFCE_STATE s) @@ -70,10 +70,10 @@ static inline void NF_SetCE(NFCE_STATE s) switch (s) { case NFCE_LOW: - nand->NFCONF &= ~(1 << 11); + writel(readl(&nand->nfconf) & ~(1 << 11), &nand->nfconf); break; case NFCE_HIGH: - nand->NFCONF |= (1 << 11); + writel(readl(&nand->nfconf) | (1 << 11), &nand->nfconf); break; } } @@ -82,7 +82,7 @@ static inline void NF_WaitRB(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - while (!(nand->NFSTAT & (1 << 0))) + while (!(readl(&nand->nfstat) & (1 << 0))) /* Wait */; } @@ -90,28 +90,28 @@ static inline void NF_Write(u8 data) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFDATA = data; + writeb(data, &nand->nfdata); } static inline u8 NF_Read(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - return (nand->NFDATA); + return readb(&nand->nfdata); } static inline void NF_Init_ECC(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - nand->NFCONF |= (1 << 12); + writel(readl(&nand->nfconf) | (1 << 12), &nand->nfconf); } static inline u32 NF_Read_ECC(void) { struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - return (nand->NFECC); + return readl(&nand->nfecc); } #endif diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index a1b0e0c..8f2da3a 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,30 +48,30 @@ int board_init(void) /* memory and cpu-speed are setup before relocation */ /* change the clock to be 50 MHz 1:1:1 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; - gpio->PECON = 0x0; - gpio->PEUP = 0x0; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); + writel(0x0, &gpio->pecon); + writel(0x0, &gpio->peup); #ifdef CONFIG_HWFLOW /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0xa22; + writel(0xa22, &gpio->pfcon); /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->PFUP = 0x35; + writel(0x35, &gpio->pfup); #else /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->PFCON = 0x22; + writel(0x22, &gpio->pfcon); /* Disable pull-up on Rx and Tx pins */ - gpio->PFUP = 0x5; + writel(0x5, &gpio->pfup); #endif /* CONFIG_HWFLOW */ - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr); /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index e3a4490..7b64408 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -28,6 +28,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -72,36 +73,37 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044555; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FFBA; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x002AFAAA; - gpio->GPHUP = 0x000007FF; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044555, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FFBA, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x002AFAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 548852f..744bd63 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -31,6 +31,7 @@ #include <common.h> #include <netdev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand.h> @@ -80,40 +81,41 @@ int board_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->LOCKTIME = 0xFFFFFF; + writel(0xFFFFFF, &clk_power->locktime); /* configure MPLL */ - clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); + writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV, &clk_power->mpllcon); /* some delay between MPLL and UPLL */ delay(4000); /* configure UPLL */ - clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); + writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV, + &clk_power->upllcon); /* some delay between MPLL and UPLL */ delay(8000); /* set up the I/O ports */ - gpio->GPACON = 0x007FFFFF; - gpio->GPBCON = 0x00044556; - gpio->GPBUP = 0x000007FF; - gpio->GPCCON = 0xAAAAAAAA; - gpio->GPCUP = 0x0000FFFF; - gpio->GPDCON = 0xAAAAAAAA; - gpio->GPDUP = 0x0000FFFF; - gpio->GPECON = 0xAAAAAAAA; - gpio->GPEUP = 0x0000FFFF; - gpio->GPFCON = 0x000055AA; - gpio->GPFUP = 0x000000FF; - gpio->GPGCON = 0xFF95FF3A; - gpio->GPGUP = 0x0000FFFF; - gpio->GPHCON = 0x0016FAAA; - gpio->GPHUP = 0x000007FF; - - gpio->EXTINT0 = 0x22222222; - gpio->EXTINT1 = 0x22222222; - gpio->EXTINT2 = 0x22222222; + writel(0x007FFFFF, &gpio->gpacon); + writel(0x00044556, &gpio->gpbcon); + writel(0x000007FF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x0000FFFF, &gpio->gpeup); + writel(0x000055AA, &gpio->gpfcon); + writel(0x000000FF, &gpio->gpfup); + writel(0xFF95FF3A, &gpio->gpgcon); + writel(0x0000FFFF, &gpio->gpgup); + writel(0x0016FAAA, &gpio->gphcon); + writel(0x000007FF, &gpio->gphup); + + writel(0x22222222, &gpio->extint0); + writel(0x22222222, &gpio->extint1); + writel(0x22222222, &gpio->extint2); /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 4f30c23..27507ec 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -31,6 +31,7 @@ #include <i2c.h> #include <flash.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "trab.h" diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index 2c31d50..5d686fe 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -26,6 +26,7 @@ #include <common.h> #include <command.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <rtc.h> #include <i2c.h> #include "tsc2000.h" @@ -604,28 +605,33 @@ static int adc_read(unsigned int channel) adc_init(); - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; } - result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -642,8 +648,10 @@ static void adc_init(void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon); /* * Wait some time to avoid problem with very first call of @@ -664,10 +672,10 @@ static void led_set(unsigned int state) switch (state) { case 0: /* turn LED off */ - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); break; case 1: /* turn LED on */ - gpio->PADAT &= ~(1 << 12); + writel(readl(&gpio->padat) & ~(1 << 12), &gpio->padat); break; default: break; @@ -693,8 +701,8 @@ static void led_init(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPA12 as output and set to High -> LED off */ - gpio->PACON &= ~(1 << 12); - gpio->PADAT |= (1 << 12); + writel(readl(&gpio->pacon) & ~(1 << 12), &gpio->pacon); + writel(readl(&gpio->padat) | (1 << 12), &gpio->padat); } static void sdelay(unsigned long seconds) diff --git a/board/trab/rs485.c b/board/trab/rs485.c index 79f8cc4..794b197 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "rs485.h" static void rs485_setbrg(void); @@ -51,16 +52,16 @@ static void rs485_setbrg(void) reg = (33000000 / (16 * 38400)) - 1; /* FIFO enable, Tx/Rx FIFO clear */ - uart->UFCON = 0x07; - uart->UMCON = 0x0; + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - uart->ULCON = 0x3; + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - uart->UCON = 0x245; - uart->UBRDIV = reg; + writel(0x245, &uart->ucon); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) ; @@ -70,16 +71,21 @@ static void rs485_cfgio(void) { struct s3c24x0_gpio *const gpio = s3c24x0_get_base_gpio(); - gpio->PFCON &= ~(0x3 << 2); - gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) & ~(0x3 << 2), &gpio->pfcon); + /* configure GPF1 as RXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 2), &gpio->pfcon); - gpio->PFCON &= ~(0x3 << 6); - gpio->PFCON |= (0x2 << 6); /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) &= ~(0x3 << 6), &gpio->pfcon); + /* configure GPF3 as TXD1 */ + writel(readl(&gpio->pfcon) | (0x2 << 6), &gpio->pfcon); - gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */ - gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */ + /* disable pullup on GPF1 */ + writel(readl(&gpio->pfup) | (1 << 1), &gpio->pfup); + /* disable pullup on GPF3 */ + writel(readl(&gpio->pfup) | (1 << 3), &gpio->pfup); - gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */ + /* set GPA11 (RS485_DE) to output */ + writel(readl(&gpio->pacon) & ~(1 << 11), &gpio->pacon); } /* @@ -104,10 +110,10 @@ int rs485_getc(void) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - while (!(uart->UTRSTAT & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */; - return uart->URXH & 0xff; + return readl(&uart->urxh) & 0xff; } /* @@ -117,10 +123,10 @@ void rs485_putc(const char c) { struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR); - while (!(uart->UTRSTAT & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */; - uart->UTXH = c; + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -134,7 +140,7 @@ int rs485_tstc(void) { struct s3c24x0_uart *const uart = s3c24x0_get_base_uart(UART_NR); - return uart->UTRSTAT & 0x1; + return readl(&uart->utrstat) & 0x1; } void rs485_puts(const char *s) @@ -171,9 +177,9 @@ static void set_rs485de(unsigned char rs485de_state) /* This is on PORT A bit 11 */ if (rs485de_state) - gpio->PADAT |= (1 << 11); + writel(readl(&gpio->padat) | (1 << 11), &gpio->padat); else - gpio->PADAT &= ~(1 << 11); + writel(readl(&gpio->padat) & ~(1 << 11), &gpio->padat); } void trab_rs485_enable_tx(void) diff --git a/board/trab/trab.c b/board/trab/trab.c index 80016bc..d339d07 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -27,6 +27,7 @@ #include <netdev.h> #include <malloc.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include <command.h> #include "trab.h" @@ -74,38 +75,38 @@ int board_init() #ifdef CONFIG_TRAB_50MHZ /* change the clock to be 50 MHz 1:1:1 */ /* MDIV:0x5c PDIV:4 SDIV:2 */ - clk_power->MPLLCON = 0x5c042; - clk_power->CLKDIVN = 0; + writel(0x5c042, &clk_power->mpllcon); + writel(0, &clk_power->clkdivn); #else /* change the clock to be 133 MHz 1:2:4 */ /* MDIV:0x7d PDIV:4 SDIV:1 */ - clk_power->MPLLCON = 0x7d041; - clk_power->CLKDIVN = 3; + writel(0x7d041, &clk_power->mpllcon); + writel(3, &clk_power->clkdivn); #endif /* set up the I/O ports */ - gpio->PACON = 0x3ffff; - gpio->PBCON = 0xaaaaaaaa; - gpio->PBUP = 0xffff; + writel(0x3ffff, &gpio->pacon); + writel(0xaaaaaaaa, &gpio->pbcon); + writel(0xffff, &gpio->pbup); /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ /* 00, 10, 10, 10, 10, 10, 10 */ - gpio->PFCON = (2 << 0) | (2 << 2) | (2 << 4) | - (2 << 6) | (2 << 8) | (2 << 10); + writel((2 << 0) | (2 << 2) | (2 << 4) | (2 << 6) | (2 << 8) | (2 << 10), + &gpio->pfcon); #ifdef CONFIG_HWFLOW /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | - (1 << 3) | (1 << 4) | (1 << 5); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5), + &gpio->pfup); #else /* do not pull up RXD0, RXD1, TXD0, TXD1 */ - gpio->PFUP = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), &gpio->pfup); #endif - gpio->PGCON = 0x0; - gpio->PGUP = 0x0; - gpio->OPENCR = 0x0; + writel(0x0, &gpio->pgcon); + writel(0x0, &gpio->pgup); + writel(0x0, &gpio->opencr); /* suppress flicker of the VFDs */ - gpio->MISCCR = 0x40; - gpio->PFCON |= (2 << 12); + writel(0x40, gpio->misccr); + writel(readl(&gpio->pfcon) | (2 << 12), &gpio->pfcon); gd->bd->bi_arch_number = MACH_TYPE_TRAB; @@ -113,8 +114,8 @@ int board_init() gd->bd->bi_boot_params = 0x0c000100; /* Make sure both buzzers are turned off */ - gpio->PDCON |= 0x5400; - gpio->PDDAT &= ~0xE0; + writel(readl(&gpio->pdcon) | 0x5400, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0xE0, &gpio->pddat); #ifdef CONFIG_VFD vfd_init_clocks(); @@ -131,7 +132,7 @@ int board_init() #ifdef CONFIG_DRIVER_S3C24X0_I2C /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; + writel((readl(&gpio->pgcon) & 0x003c00) | 0x003c00, &gpio->pgcon); #endif /* CONFIG_DRIVER_S3C24X0_I2C */ return 0; @@ -328,14 +329,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); } static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); } static void spi_init(void) @@ -345,23 +346,23 @@ static void spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon); CLR_CS_TOUCH(); /* Baudrate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon); /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); wait_transmit_done(); } @@ -369,7 +370,7 @@ static void wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; } @@ -384,13 +385,13 @@ static void tsc2000_write(unsigned int page, unsigned int reg, command |= (page << 11); command |= (reg << 5); - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writel((data & 0xFF00) >> 8, &spi->ch[0].sptdat); wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writel(data & 0x00FF, &spi->ch[0].sptdat); wait_transmit_done(); CLR_CS_TOUCH(); diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index da0c3b1..4708105 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -27,6 +27,7 @@ #include <exports.h> #include <timestamp.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> #include "tsc2000.h" #include "rs485.h" @@ -376,28 +377,33 @@ static int adc_read(unsigned int channel) padc = s3c2400_get_base_adc(); channel &= 0x7; - padc->ADCCON &= ~ADC_STDBM; /* select normal mode */ - padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */ - padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START); + /* select normal mode */ + writel(readl(&padc->adccon) & ~ADC_STDBM, &padc->adccon); + /* clear the channel bits */ + writel(readl(&padc->adccon) & ~(0x7 << 3), &padc->adccon); + writel(readl(&padc->adccon) | ((channel << 3) | ADC_ENABLE_START), + &padc->adccon); while (j--) { - if ((padc->ADCCON & ADC_ENABLE_START) == 0) + if ((readl(&padc->adccon) & ADC_ENABLE_START) == 0) break; udelay(1); } if (j == 0) { printf("%s: ADC timeout\n", __FUNCTION__); - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); return -1; } - result = padc->ADCDAT & 0x3FF; + result = readl(&padc->adcdat) & 0x3FF; - padc->ADCCON |= ADC_STDBM; /* select standby mode */ + /* select standby mode */ + writel(readl(&padc->adccon) | ADC_STDBM, &padc->adccon); debug("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__, - (padc->ADCCON >> 3) & 0x7, result); + (readl(&padc->adccon) >> 3) & 0x7, result); /* * Wait for ADC to be ready for next conversion. This delay value was @@ -414,8 +420,10 @@ static void adc_init(void) padc = s3c2400_get_base_adc(); - padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */ - padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */ + /* clear prescaler bits */ + writel(readl(&padc->adccon) & ~(0xff << 6), &padc->adccon); + /* set prescaler */ + writel(readl(&padc->adccon) | ((65 << 6) | ADC_PRSCEN), &padc->adccon); /* * Wait some time to avoid problem with very first call of @@ -456,10 +464,10 @@ int do_power_switch(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure GPE7 as input */ - gpio->PECON &= ~(0x3 << (2 * 7)); + writel(readl(&gpio->pecon) & ~(0x3 << (2 * 7)), &gpio->pecon); /* signal GPE7 from power switch is low active: 0=on , 1=off */ - result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1; + result = ((readl(&gpio->pedat) & (1 << 7)) == (1 << 7)) ? 0 : 1; print_identifier(); printf("%d\n", result); @@ -522,20 +530,20 @@ int do_vfd_id(void) /* try to red vfd board id from the value defined by pull-ups */ - pcup_old = gpio->PCUP; - pccon_old = gpio->PCCON; + pcup_old = readl(&gpio->pcup); + pccon_old = readl(&gpio->pccon); /* activate GPC0...GPC3 pull-ups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon); udelay(10); /* allow signals to settle */ /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F; - gpio->PCCON = pccon_old; - gpio->PCUP = pcup_old; + writel(pccon_old, &gpio->pccon); + writel(pcup_old, &gpio->pcup); /* print vfd_board_id to console */ print_identifier(); @@ -557,40 +565,42 @@ int do_buzzer(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* set divider for timer 2 */ - timers->TCFG1 &= ~0xF00; - timers->TCFG1 |= 0x300; + writel(readl(&timers->tcfg1) & ~0xF00, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x300, &timers->tcfg1); /* set frequency */ counter = (PCLK / BUZZER_FREQ) >> 9; - timers->ch[2].TCNTB = counter; - timers->ch[2].TCMPB = counter / 2; + writel(counter, &timers->ch[2].tcntb); + writel(counter / 2, &timers->ch[2].tcmpb); if (strcmp(argv[2], "on") == 0) { debug("%s: frequency: %d\n", __FUNCTION__, BUZZER_FREQ); /* configure pin GPD7 as TOUT2 */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x8000; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x8000, &gpio->pdcon); /* start */ - timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) & - ~INVERT2; - timers->TCON = (timers->TCON | START2) & ~UPDATE2; + writel((readl(&timers->tcon) | UPDATE2 | RELOAD2) & ~INVERT2, + &timers->tcon); + writel((readl(&timers->tcon) | START2) & ~UPDATE2, + &timers->tcon); return 0; } else if (strcmp(argv[2], "off") == 0) { /* stop */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon); /* configure GPD7 as output and set to low */ - gpio->PDCON &= ~0xC000; - gpio->PDCON |= 0x4000; - gpio->PDDAT &= ~0x80; + writel(readl(&gpio->pdcon) & ~0xC000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x4000, &gpio->pdcon); + writel(readl(&gpio->pddat) & ~0x80, &gpio->pddat); return 0; } @@ -603,12 +613,12 @@ int do_led(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PC14 and PC15 as output */ - gpio->PCCON &= ~(0xF << 28); - gpio->PCCON |= (0x5 << 28); + writel(readl(&gpio->pccon) & ~(0xF << 28), &gpio->pccon); + writel(readl(&gpio->pccon) | (0x5 << 28), &gpio->pccon); /* configure PD0 and PD4 as output */ - gpio->PDCON &= ~((0x3 << 8) | 0x3); - gpio->PDCON |= ((0x1 << 8) | 0x1); + writel(readl(&gpio->pdcon) & ~((0x3 << 8) | 0x3), &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 8) | 0x1), &gpio->pdcon); switch (simple_strtoul(argv[2], NULL, 10)) { case 0: @@ -616,27 +626,27 @@ int do_led(char **argv) break; case 2: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 14); + writel(readl(&gpio->pcdat) | (1 << 14), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 14); + writel(readl(&gpio->pcdat) & ~(1 << 14), &gpio->pcdat); return 0; case 3: if (strcmp(argv[3], "on") == 0) - gpio->PCDAT |= (1 << 15); + writel(readl(&gpio->pcdat) | (1 << 15), &gpio->pcdat); else - gpio->PCDAT &= ~(1 << 15); + writel(readl(&gpio->pcdat) & ~(1 << 15), &gpio->pcdat); return 0; case 4: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 0); + writel(readl(&gpio->pddat) | (1 << 0), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 0); + writel(readl(&gpio->pddat) & ~(1 << 0), &gpio->pddat); return 0; case 5: if (strcmp(argv[3], "on") == 0) - gpio->PDDAT |= (1 << 4); + writel(readl(&gpio->pddat) | (1 << 4), &gpio->pddat); else - gpio->PDDAT &= ~(1 << 4); + writel(readl(&gpio->pddat) & ~(1 << 4), &gpio->pddat); return 0; default: break; @@ -650,22 +660,24 @@ int do_full_bridge(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* configure PD5 and PD6 as output */ - gpio->PDCON &= ~((0x3 << 5 * 2) | (0x3 << 6 * 2)); - gpio->PDCON |= ((0x1 << 5 * 2) | (0x1 << 6 * 2)); + writel(readl(&gpio->pdcon) & ~((0x3 << 5 * 2) | (0x3 << 6 * 2)), + &gpio->pdcon); + writel(readl(&gpio->pdcon) | ((0x1 << 5 * 2) | (0x1 << 6 * 2)), + &gpio->pdcon); if (strcmp(argv[2], "+") == 0) { - gpio->PDDAT |= (1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) | (1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "-") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT |= (1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) | (1 << 6), &gpio->pddat); return 0; } else if (strcmp(argv[2], "off") == 0) { - gpio->PDDAT &= ~(1 << 5); - gpio->PDDAT &= ~(1 << 6); + writel(readl(&gpio->pddat) & ~(1 << 5), &gpio->pddat); + writel(readl(&gpio->pddat) & ~(1 << 6), &gpio->pddat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -755,15 +767,15 @@ int do_motor(char **argv) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* Configure I/O port */ - gpio->PGCON &= ~(0x3 << 0); - gpio->PGCON |= (0x1 << 0); + writel(readl(&gpio->pgcon) & ~(0x3 << 0), &gpio->pgcon); + writel(readl(&gpio->pgcon) | (0x1 << 0), &gpio->pgcon); if (strcmp(argv[2], "on") == 0) { - gpio->PGDAT &= ~(1 << 0); + writel(readl(&gpio->pgdat) & ~(1 << 0), &gpio->pgdat); return 0; } if (strcmp(argv[2], "off") == 0) { - gpio->PGDAT |= (1 << 0); + writel(readl(&gpio->pgdat) | (1 << 0), &gpio->pgdat); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); @@ -783,36 +795,39 @@ int do_pwm(char **argv) if (strcmp(argv[2], "on") == 0) { /* configure pin GPD8 as TOUT3 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x2 << 8*2); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x2 << 8 * 2), &gpio->pdcon); /* set prescaler for timer 2, 3 and 4 */ - timers->TCFG0 &= ~0xFF00; - timers->TCFG0 |= 0x0F00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* set divider for timer 3 */ - timers->TCFG1 &= ~(0xf << 12); - timers->TCFG1 |= (0x3 << 12); + writel(readl(&timers->tcfg1) & ~(0xF << 12), &timers->tcfg1); + writel(readl(&timers->tcfg1) | (0x3 << 12), &timers->tcfg1); /* set frequency */ counter = (PCLK / PWM_FREQ) >> 9; - timers->ch[3].TCNTB = counter; - timers->ch[3].TCMPB = counter / 2; + writel(counter, &timers->ch[3].tcntb); + writel(counter / 2, &timers->ch[3].tcmpb); /* start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); return 0; } if (strcmp(argv[2], "off") == 0) { /* stop timer */ - timers->TCON &= ~(START2 | RELOAD2); + writel(readl(&timers->tcon) & ~(START2 | RELOAD2), + &timers->tcon); /* configure pin GPD8 as output and set to 0 */ - gpio->PDCON &= ~(0x3 << 8*2); - gpio->PDCON |= (0x1 << 8*2); - gpio->PDDAT &= ~(1 << 8); + writel(readl(&gpio->pdcon) & ~(0x3 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pdcon) | (0x1 << 8 * 2), &gpio->pdcon); + writel(readl(&gpio->pddat) & ~(1 << 8), &gpio->pdcon); return 0; } printf("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index 2855825..c07b4df 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -50,23 +50,23 @@ void tsc2000_spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; - gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; - gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; - gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; + writel((readl(&gpio->pdcon) & 0xF3FFFF) | 0x040000, &gpio->pdcon); + writel((readl(&gpio->pgcon) & 0x0F3FFF) | 0x008000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x0CFFFF) | 0x020000, &gpio->pgcon); + writel((readl(&gpio->pgcon) & 0x03FFFF) | 0x080000, &gpio->pgcon); CLR_CS_TOUCH(); /* Baud-rate ca. 514kHz */ - spi->ch[0].SPPRE = 0x1F; + writel(0x1F, &spi->ch[0].sppre); /* SPI-MOSI holds Level after last bit */ - spi->ch[0].SPPIN = 0x01; + writel(0x01, &spi->ch[0].sppin); /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */ - spi->ch[0].SPCON = 0x1A; + writel(0x1A, &spi->ch[0].spcon); /* Dummy byte ensures clock to be low. */ for (i = 0; i < 10; i++) - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); } @@ -74,7 +74,7 @@ void spi_wait_transmit_done(void) { struct s3c24x0_spi * const spi = s3c24x0_get_base_spi(); - while (!(spi->ch[0].SPSTA & 0x01)) + while (!(readl(&spi->ch[0].spsta) & 0x01)) /* wait until transfer is done */; } @@ -85,13 +85,13 @@ void tsc2000_write(unsigned short reg, unsigned short data) SET_CS_TOUCH(); command = reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0xFF00) >> 8; + writeb((data & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (data & 0x00FF); + writeb(data & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); CLR_CS_TOUCH(); @@ -105,19 +105,19 @@ unsigned short tsc2000_read(unsigned short reg) SET_CS_TOUCH(); command = 0x8000 | reg; - spi->ch[0].SPTDAT = (command & 0xFF00) >> 8; + writel((command & 0xFF00) >> 8, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = (command & 0x00FF); + writel(command & 0x00FF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - spi->ch[0].SPTDAT = 0xFF; + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); - data = spi->ch[0].SPRDAT; - spi->ch[0].SPTDAT = 0xFF; + data = readl(&spi->ch[0].sprdat); + writel(0xFF, &spi->ch[0].sptdat); spi_wait_transmit_done(); CLR_CS_TOUCH(); - return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8); + return (readl(&spi->ch[0].sprdat) & 0x0FF) | (data << 8); } void tsc2000_set_mux(unsigned int channel) diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h index db4b408..3719c2e 100644 --- a/board/trab/tsc2000.h +++ b/board/trab/tsc2000.h @@ -29,45 +29,75 @@ #define _TSC2000_H_ /* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) - -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) - -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) - -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) - -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) - -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) - -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) - -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) - -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) - -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) +#define CON_MUX0 (writel((readl(&gpio->pccon) & 0x0FFFFFCFF) | \ + 0x00000100, &gpio->pccon)) +#define CLR_MUX0 (writel(readl(&gpio->pcdat) & 0x0FFEF, \ + &gpio->pcdat)) +#define SET_MUX0 (writel(readl(&gpio->pcdat) | 0x00010, \ + &gpio->pcdat)) + +#define CON_MUX1 (writel((readl(&gpio->pccon) & 0x0FFFFF3FF) | \ + 0x00000400, &gpio->pccon)) +#define CLR_MUX1 (writel(readl(&gpio->pcdat) & 0x0FFDF, \ + &gpio->pcdat)) +#define SET_MUX1 (writel(readl(&gpio->pcdat) | 0x00020, \ + &gpio->pcdat)) + +#define CON_MUX1_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFFCFFF) | \ + 0x00001000, &gpio->pccon)) +#define CLR_MUX1_ENABLE (writel(readl(&gpio->pcdat) | 0x00040, \ + &gpio->pcdat)) +#define SET_MUX1_ENABLE (writel(readl(&gpio->pcdat) & 0x0FFBF, \ + &gpio->pcdat)) + +#define CON_MUX2_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFF3FFF) | \ + 0x00004000, &gpio->pccon)) +#define CLR_MUX2_ENABLE (writel(readl(&gpio->pcdat) | 0x00080, \ + &gpio->pcdat)) +#define SET_MUX2_ENABLE (writel(readl(&gpio->pcdat) & 0x0FF7F, \ + &gpio->pcdat)) + +#define CON_MUX3_ENABLE (writel((readl(&gpio->pccon) & 0x0FFFCFFFF) | \ + 0x00010000, &gpio->pccon)) +#define CLR_MUX3_ENABLE (writel(readl(&gpio->pcdat) | 0x00100, \ + &gpio->pcdat)) +#define SET_MUX3_ENABLE (writel(readl(&gpio->pcdat) & 0x0FEFF, \ + &gpio->pcdat)) + +#define CON_MUX4_ENABLE (writel((readl(&gpio->pccon) & 0x0FFF3FFFF) | \ + 0x00040000, &gpio->pccon)) +#define CLR_MUX4_ENABLE (writel(readl(&gpio->pcdat) | 0x00200, \ + &gpio->pcdat)) +#define SET_MUX4_ENABLE (writel(readl(&gpio->pcdat) & 0x0FDFF, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_0 (writel((readl(&gpio->pccon) & 0x0FFCFFFFF) | \ + 0x00100000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) & 0x0FBFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_0 (writel(readl(&gpio->pcdat) | 0x00400, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_1 (writel((readl(&gpio->pccon) & 0x0FF3FFFFF) | \ + 0x00400000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) & 0x0F7FF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_1 (writel(readl(&gpio->pcdat) | 0x00800, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_2 (writel((readl(&gpio->pccon) & 0x0FCFFFFFF) | \ + 0x01000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) & 0x0EFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_2 (writel(readl(&gpio->pcdat) | 0x01000, \ + &gpio->pcdat)) + +#define CON_SEL_TEMP_V_3 (writel((readl(&gpio->pccon) & 0x0F3FFFFFF) | \ + 0x04000000, &gpio->pccon)) +#define CLR_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) & 0x0DFFF, \ + &gpio->pcdat)) +#define SET_SEL_TEMP_V_3 (writel(readl(&gpio->pcdat) | 0x02000, \ + &gpio->pcdat)) /* TSC2000 register definition */ #define TSC2000_REG_X ((0 << 11) | (0 << 5)) @@ -130,14 +160,14 @@ static inline void SET_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT &= 0x5FF; + writel(readl(&gpio->pddat) & 0x5FF, &gpio->pddat); } static inline void CLR_CS_TOUCH(void) { struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - gpio->PDDAT |= 0x200; + writel(readl(&gpio->pddat) | 0x200, &gpio->pddat); } #endif /* _TSC2000_H_ */ diff --git a/board/trab/vfd.c b/board/trab/vfd.c index cc7f9d3..ad5b8c2 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -38,6 +38,7 @@ #include <linux/types.h> #include <stdio_dev.h> #include <asm/arch/s3c24x0_cpu.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -414,15 +415,15 @@ int vfd_init_clocks(void) * defined by pull-ups */ /* activate GPC0...GPC3 pullups */ - gpio->PCUP = (gpio->PCUP & 0xFFF0); + writel(readl(&gpio->pcup) & 0xFFF0, &gpio->pcup); /* configure GPC0...GPC3 as inputs */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); + writel(readl(&gpio->pccon) & 0xFFFFFF00, &gpio->pccon); /* allow signals to settle */ /* udelay isn't working yet at this point! */ for (i = 0; i < 10000; i++) __asm__("NOP"); /* read GPC0...GPC3 port pins */ - vfd_board_id = (~gpio->PCDAT) & 0x000F; + vfd_board_id = ~readl(&gpio->pcdat) & 0x000F; VFD_DISABLE; /* activate blank for the vfd */ @@ -434,39 +435,41 @@ int vfd_init_clocks(void) /* Enable 500 Hz timer for fill level sensor to operate * properly */ /* Configure TOUT3 as functional pin, disable pull-up */ - gpio->PDCON &= ~0x30000; - gpio->PDCON |= 0x20000; - gpio->PDUP |= (1 << 8); + writel(readl(&gpio->pdcon) & ~0x30000, &gpio->pdcon); + writel(readl(&gpio->pdcon) | 0x20000, &gpio->pdcon); + writel(readl(&gpio->pdup) | (1 << 8), &gpio->pdup); /* Configure the prescaler */ - timers->TCFG0 &= ~0xff00; - timers->TCFG0 |= 0x0f00; + writel(readl(&timers->tcfg0) & ~0xFF00, &timers->tcfg0); + writel(readl(&timers->tcfg0) | 0x0F00, &timers->tcfg0); /* Select MUX input (divider) for timer3 (1/16) */ - timers->TCFG1 &= ~0xf000; - timers->TCFG1 |= 0x3000; + writel(readl(&timers->tcfg1) & ~0xF000, &timers->tcfg1); + writel(readl(&timers->tcfg1) | 0x3000, &timers->tcfg1); /* Enable autoreload and set the counter and compare * registers to values for the 500 Hz clock * (for a given prescaler (15) and divider (16)): * counter = (66000000 / 500) >> 9; */ - timers->ch[3].TCNTB = 0x101; - timers->ch[3].TCMPB = 0x101 / 2; + writel(0x101, &timers->ch[3].tcntb); + writel(0x101 / 2, &timers->ch[3].tcmpb); /* Start timer */ - timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3; - timers->TCON = (timers->TCON | START3) & ~UPDATE3; + writel((readl(&timers->tcon) | UPDATE3 | RELOAD3) & ~INVERT3, + &timers->tcon); + writel((readl(&timers->tcon) | START3) & ~UPDATE3, + &timers->tcon); } #endif /* If old board revision, then use vm-signal as cpld-clock */ - lcd->LCDCON2 = 0x00FFC000; - lcd->LCDCON3 = 0x0007FF00; - lcd->LCDCON4 = 0x00000000; - lcd->LCDCON5 = 0x00000400; - lcd->LCDCON1 = 0x00000B75; + writel(0x00FFC000, &lcd->lcdcon2); + writel(0x0007FF00, &lcd->lcdcon3); + writel(0x00000000, &lcd->lcdcon4); + writel(0x00000400, &lcd->lcdcon5); + writel(0x00000B75, &lcd->lcdcon1); /* VM (GPD1) is used as clock for the CPLD */ - gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008; + writel((readl(&gpio->pdcon) & 0xFFFFFFF3) | 0x00000008, &gpio->pdcon); return 0; } @@ -536,46 +539,46 @@ int drv_vfd_init(void) * see manual S3C2400 */ /* Stopp LCD-Controller */ - lcd->LCDCON1 = 0x00000000; + writel(0x00000000, &lcd->lcdcon1); /* frame buffer startadr */ - lcd->LCDSADDR1 = gd->fb_base >> 1; + writel(gd->fb_base >> 1, &lcd->lcdsaddr1); /* frame buffer endadr */ - lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; - lcd->LCDSADDR3 = ((256 / 4)); - lcd->LCDCON2 = 0x000DC000; + writel((gd->fb_base + FRAME_BUF_SIZE) >> 1, &lcd->lcdsaddr2); + writel(256 / 4, &lcd->lcdsaddr3); + writel(0x000DC000, &lcd->lcdcon2); if (gd->vfd_type == VFD_TYPE_MN11236) - lcd->LCDCON2 = 37 << 14; /* MN11236: 38 lines */ + writel(37 << 14, &lcd->lcdcon2); /* MN11236: 38 lines */ else - lcd->LCDCON2 = 55 << 14; /* T119C: 56 lines */ - lcd->LCDCON3 = 0x0051000A; - lcd->LCDCON4 = 0x00000001; + writel(55 << 14, &lcd->lcdcon2); /* T119C: 56 lines */ + writel(0x0051000A, &lcd->lcdcon3); + writel(0x00000001, &lcd->lcdcon4); if (gd->vfd_type && vfd_inv_data) - lcd->LCDCON5 = 0x000004C0; + writel(0x000004C0, &lcd->lcdcon5); else - lcd->LCDCON5 = 0x00000440; + writel(0x00000440, &lcd->lcdcon5); /* Port pins as LCD output */ - gpio->PCCON = (gpio->PCCON & 0xFFFFFF00) | 0x000000AA; - gpio->PDCON = (gpio->PDCON & 0xFFFFFF03) | 0x000000A8; + writel((readl(&gpio->pccon) & 0xFFFFFF00) | 0x000000AA, &gpio->pccon); + writel((readl(&gpio->pdcon) & 0xFFFFFF03) | 0x000000A8, &gpio->pdcon); /* Synchronize VFD enable with LCD controller to avoid flicker */ /* Start LCD-Controller */ - lcd->LCDCON1 = 0x00000B75; - while ((lcd->LCDCON5 & 0x180000) != 0x100000) + writel(0x00000B75, &lcd->lcdcon1); + while ((readl(&lcd->lcdcon5) & 0x180000) != 0x100000) /* Wait for end of VSYNC */; /* Wait for next HSYNC */ - while ((lcd->LCDCON5 & 0x060000) != 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) == 0x040000) + while ((readl(&lcd->lcdcon5) & 0x060000) == 0x040000) ; - while ((lcd->LCDCON5 & 0x060000) != 0x000000) + while ((readl(&lcd->lcdcon5) & 0x060000) != 0x000000) ; if (gd->vfd_type) VFD_ENABLE; - debug("LCDSADDR1: %lX\n", lcd->LCDSADDR1); - debug("LCDSADDR2: %lX\n", lcd->LCDSADDR2); - debug("LCDSADDR3: %lX\n", lcd->LCDSADDR3); + debug("LCDSADDR1: %lX\n", readl(&lcd->lcdsaddr1)); + debug("LCDSADDR2: %lX\n", readl(&lcd->lcdsaddr2)); + debug("LCDSADDR3: %lX\n", readl(&lcd->lcdsaddr3)); return 0; } @@ -589,8 +592,8 @@ void disable_vfd(void) struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); VFD_DISABLE; - gpio->PDCON &= ~0xC; - gpio->PDUP &= ~0x2; + writel(readl(&gpio->pdcon) & ~0xC, &gpio->pdcon); + writel(readl(&gpio->pdup) & ~0x2, &gpio->pdup); } /************************************************************************/ diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 879fda6..5d7b05e 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -33,10 +33,11 @@ #include <asm/arch/s3c24x0_cpu.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> void do_irq (struct pt_regs *pt_regs) { struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt(); - u_int32_t intpnd = readl(&irq->INTPND); + u_int32_t intpnd = readl(&irq->intpnd); } diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index b13283a..58e8865 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg) ulong r, m, p, s; if (pllreg == MPLL) - r = readl(&clk_power->MPLLCON); + r = readl(&clk_power->mpllcon); else if (pllreg == UPLL) - r = readl(&clk_power->UPLLCON); + r = readl(&clk_power->upllcon); else hang(); @@ -78,7 +78,7 @@ ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); + return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK(); } /* return PCLK frequency */ @@ -86,7 +86,7 @@ ulong get_PCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK(); + return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK(); } /* return UCLK frequency */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 7d47354..9fcfec2 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); - return readl(&timers->TCNTO4) & 0xffff; + return readl(&timers->tcnto4) & 0xffff; } static ulong timestamp; @@ -56,7 +56,7 @@ int timer_init(void) /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ - writel(0x0f00, &timers->TCFG0); + writel(0x0f00, &timers->tcfg0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 @@ -68,13 +68,13 @@ int timer_init(void) } /* load value for 10 ms timeout */ lastdec = timer_load_val; - writel(timer_load_val, &timers->TCNTB4); + writel(timer_load_val, &timers->tcntb4); /* auto load, manual update of Timer 4 */ - tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; - writel(tmr, &timers->TCON); + tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; + writel(tmr, &timers->tcon); /* auto load, start Timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; - writel(tmr, &timers->TCON); + writel(tmr, &timers->tcon); timestamp = 0; return (0); @@ -206,13 +206,13 @@ void reset_cpu(ulong ignored) watchdog = s3c24x0_get_base_watchdog(); /* Disable watchdog */ - writel(0x0000, &watchdog->WTCON); + writel(0x0000, &watchdog->wtcon); /* Initialize watchdog timer count register */ - writel(0x0001, &watchdog->WTCNT); + writel(0x0001, &watchdog->wtcnt); /* Enable watchdog timer; assert reset at timer timeout */ - writel(0x0021, &watchdog->WTCON); + writel(0x0021, &watchdog->wtcon); while (1) /* loop forever and wait for reset to happen */; diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index e468ed0..2033965 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -39,14 +39,15 @@ int usb_cpu_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON); + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ - writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR); + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); return 0; } @@ -55,14 +56,14 @@ int usb_cpu_stop(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); /* may not want to do this */ - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } int usb_cpu_init_fail(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 5aa8d64..4799610 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -1666,13 +1666,14 @@ int usb_lowlevel_init(void) * Set the 48 MHz UPLL clocking. Values are taken from * "PLL value selection guide", 6-23, s3c2400_UM.pdf. */ - clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2); - gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */ + writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon); + /* 1 = use pads related USB for USB host */ + writel(readl(&gpio->misccr) | 0x8, &gpio->misccr); /* * Enable USB host clock. */ - clk_power->CLKCON |= (1 << 4); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); memset(&gohci, 0, sizeof(struct ohci)); memset(&urb_priv, 0, sizeof(struct urb_priv)); @@ -1709,7 +1710,8 @@ int usb_lowlevel_init(void) if (hc_reset(&gohci) < 0) { hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; } @@ -1722,7 +1724,8 @@ int usb_lowlevel_init(void) err("can't start usb-%s", gohci.slot_name); hc_release_ohci(&gohci); /* Initialization failed */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), + &clk_power->clkcon); return -1; } #ifdef DEBUG @@ -1748,7 +1751,7 @@ int usb_lowlevel_stop(void) /* call hc_release_ohci() here ? */ hc_reset(&gohci); /* may not want to do this */ - clk_power->CLKCON &= ~(1 << 4); + writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon); return 0; } diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index e6c0083..4e43344 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -58,10 +58,10 @@ static int get_i2c_sda(void) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - return (readl(&gpio->GPEDAT) & 0x8000) >> 15; + return (readl(&gpio->gpedat) & 0x8000) >> 15; #endif #ifdef CONFIG_S3C2400 - return (readl(&gpio->PGDAT) & 0x0020) >> 5; + return (readl(&gpio->pgdat) & 0x0020) >> 5; #endif } @@ -70,10 +70,10 @@ static void set_i2c_scl(int x) struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); #ifdef CONFIG_S3C2410 - writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT); + writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat); #endif #ifdef CONFIG_S3C2400 - writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT); + writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); #endif } @@ -83,26 +83,26 @@ static int wait_for_xfer(void) int i; i = I2C_TIMEOUT * 10000; - while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) { + while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { udelay(100); i--; } - return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; + return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; } static int is_ack(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK); + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); } static void read_write_byte(void) { struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c(); - writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON); + writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } void i2c_init(int speed, int slaveadd) @@ -115,30 +115,30 @@ void i2c_init(int speed, int slaveadd) /* wait for some time to give previous transfer a chance to finish */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) && I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || get_i2c_sda() == 0) { + if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || get_i2c_sda() == 0) { #ifdef CONFIG_S3C2410 - ulong old_gpecon = readl(&gpio->GPECON); + ulong old_gpecon = readl(&gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - ulong old_gpecon = readl(&gpio->PGCON); + ulong old_gpecon = readl(&gpio->pgcon); #endif /* bus still busy probably by (most) previously interrupted transfer */ #ifdef CONFIG_S3C2410 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ - writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000, - &gpio->GPECON); + writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, + &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ - writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000, - &gpio->PGCON); + writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, + &gpio->pgcon); #endif /* toggle I2CSCL until bus idle */ @@ -157,10 +157,10 @@ void i2c_init(int speed, int slaveadd) /* restore pin functions */ #ifdef CONFIG_S3C2410 - writel(old_gpecon, &gpio->GPECON); + writel(old_gpecon, &gpio->gpecon); #endif #ifdef CONFIG_S3C2400 - writel(old_gpecon, &gpio->PGCON); + writel(old_gpecon, &gpio->pgcon); #endif } @@ -176,13 +176,13 @@ void i2c_init(int speed, int slaveadd) /* set prescaler, divisor according to freq, also set * ACKGEN, IRQ */ - writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON); + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); /* init to SLAVE REVEIVE and set slaveaddr */ - writel(0, &i2c->IICSTAT); - writel(slaveadd, &i2c->IICADD); + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } @@ -211,47 +211,47 @@ int i2c_transfer(unsigned char cmd_type, /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; - while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) { + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { udelay(1000); i--; } - if (readl(&i2c->IICSTAT) & I2CSTAT_BSY) + if (readl(&i2c->iicstat) & I2CSTAT_BSY) return I2C_NOK_TOUT; - writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) | 0x80, &i2c->iiccon); result = I2C_OK; switch (cmd_type) { case I2C_WRITE: if (addr && addr_len) { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < addr_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); i++; } i = 0; while ((i < data_len) && (result == I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } } else { - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* send START */ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->IICSTAT); + &i2c->iicstat); i = 0; while ((i < data_len) && (result = I2C_OK)) { result = wait_for_xfer(); - writel(data[i], &i2c->IICDS); + writel(data[i], &i2c->iicds); read_write_byte(); i++; } @@ -261,42 +261,42 @@ int i2c_transfer(unsigned char cmd_type, result = wait_for_xfer(); /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break; case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer(); if (is_ack()) { i = 0; while ((i < addr_len) && (result == I2C_OK)) { - writel(addr[i], &i2c->IICDS); + writel(addr[i], &i2c->iicds); read_write_byte(); result = wait_for_xfer(); i++; } - writel(chip, &i2c->IICDS); + writel(chip, &i2c->iicds); /* resend START */ writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->IICSTAT); + I2C_START_STOP, &i2c->iicstat); read_write_byte(); result = wait_for_xfer(); i = 0; while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) - & ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) + & ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -304,11 +304,11 @@ int i2c_transfer(unsigned char cmd_type, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); - writel(chip, &i2c->IICDS); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->IICSTAT) | I2C_START_STOP, - &i2c->IICSTAT); + writel(readl(&i2c->iicstat) | I2C_START_STOP, + &i2c->iicstat); result = wait_for_xfer(); if (is_ack()) { @@ -316,11 +316,11 @@ int i2c_transfer(unsigned char cmd_type, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - writel(readl(&i2c->IICCON) & - ~0x80, &i2c->IICCON); + writel(readl(&i2c->iiccon) & + ~0x80, &i2c->iiccon); read_write_byte(); result = wait_for_xfer(); - data[i] = readl(&i2c->IICDS); + data[i] = readl(&i2c->iicds); i++; } } else { @@ -329,7 +329,7 @@ int i2c_transfer(unsigned char cmd_type, } /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT); + writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); read_write_byte(); break; diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index a27d47e..ccc771f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -69,11 +69,11 @@ static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) chip->IO_ADDR_W = (void *)IO_ADDR_W; if (ctrl & NAND_NCE) - writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) & ~S3C2410_NFCONF_nFCE, + &nand->nfconf); else - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE, - &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_nFCE, + &nand->nfconf); } if (cmd != NAND_CMD_NONE) @@ -84,7 +84,7 @@ static int s3c2410_dev_ready(struct mtd_info *mtd) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "dev_ready\n"); - return readl(&nand->NFSTAT) & 0x01; + return readl(&nand->nfstat) & 0x01; } #ifdef CONFIG_S3C2410_NAND_HWECC @@ -92,16 +92,16 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode); - writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF); + writel(readl(&nand->nfconf) | S3C2410_NFCONF_INITECC, &nand->nfconf); } static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { struct s3c2410_nand *nand = s3c2410_get_base_nand(); - ecc_code[0] = readb(&nand->NFECC); - ecc_code[1] = readb(&nand->NFECC + 1); - ecc_code[2] = readb(&nand->NFECC + 2); + ecc_code[0] = readb(&nand->nfecc); + ecc_code[1] = readb(&nand->nfecc + 1); + ecc_code[2] = readb(&nand->nfecc + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,7 +130,7 @@ int board_nand_init(struct nand_chip *nand) debugX(1, "board_nand_init()\n"); - writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON); + writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon); /* initialize hardware */ twrph0 = 3; @@ -141,10 +141,10 @@ int board_nand_init(struct nand_chip *nand) cfg |= S3C2410_NFCONF_TACLS(tacls - 1); cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); - writel(cfg, &nand_reg->NFCONF); + writel(cfg, &nand_reg->nfconf); /* initialize nand_chip data structure */ - nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->nfdata; nand->select_chip = NULL; diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 04de5ca..7f02f05 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -49,11 +49,11 @@ static inline void SetRTC_Access(RTC_ACCESS a) switch (a) { case RTC_ENABLE: - writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); break; case RTC_DISABLE: - writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON); + writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); break; } } @@ -71,23 +71,23 @@ int rtc_get(struct rtc_time *tmp) /* read RTC registers */ do { - sec = readb(&rtc->BCDSEC); - min = readb(&rtc->BCDMIN); - hour = readb(&rtc->BCDHOUR); - mday = readb(&rtc->BCDDATE); - wday = readb(&rtc->BCDDAY); - mon = readb(&rtc->BCDMON); - year = readb(&rtc->BCDYEAR); - } while (sec != readb(&rtc->BCDSEC)); + sec = readb(&rtc->bcdsec); + min = readb(&rtc->bcdmin); + hour = readb(&rtc->bcdhour); + mday = readb(&rtc->bcddate); + wday = readb(&rtc->bcdday); + mon = readb(&rtc->bcdmon); + year = readb(&rtc->bcdyear); + } while (sec != readb(&rtc->bcdsec)); /* read ALARM registers */ - a_sec = readb(&rtc->ALMSEC); - a_min = readb(&rtc->ALMMIN); - a_hour = readb(&rtc->ALMHOUR); - a_date = readb(&rtc->ALMDATE); - a_mon = readb(&rtc->ALMMON); - a_year = readb(&rtc->ALMYEAR); - a_armed = readb(&rtc->RTCALM); + a_sec = readb(&rtc->almsec); + a_min = readb(&rtc->almmin); + a_hour = readb(&rtc->almhour); + a_date = readb(&rtc->almdate); + a_mon = readb(&rtc->almmon); + a_year = readb(&rtc->almyear); + a_armed = readb(&rtc->rtcalm); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -145,13 +145,13 @@ int rtc_set(struct rtc_time *tmp) SetRTC_Access(RTC_ENABLE); /* write RTC registers */ - writeb(sec, &rtc->BCDSEC); - writeb(min, &rtc->BCDMIN); - writeb(hour, &rtc->BCDHOUR); - writeb(mday, &rtc->BCDDATE); - writeb(wday, &rtc->BCDDAY); - writeb(mon, &rtc->BCDMON); - writeb(year, &rtc->BCDYEAR); + writeb(sec, &rtc->bcdsec); + writeb(min, &rtc->bcdmin); + writeb(hour, &rtc->bcdhour); + writeb(mday, &rtc->bcddate); + writeb(wday, &rtc->bcdday); + writeb(mon, &rtc->bcdmon); + writeb(year, &rtc->bcdyear); /* disable access to RTC registers */ SetRTC_Access(RTC_DISABLE); @@ -163,8 +163,8 @@ void rtc_reset(void) { struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON); - writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON); + writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); + writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); } #endif diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 5dd4dd8..a613229 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -100,7 +100,7 @@ void _serial_setbrg(const int dev_index) /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - writel(reg, &uart->UBRDIV); + writel(reg, &uart->ubrdiv); for (i = 0; i < 100; i++) /* Delay */ ; } @@ -130,26 +130,26 @@ static int serial_init_dev(const int dev_index) #endif /* FIFO enable, Tx/Rx FIFO clear */ - writel(0x07, &uart->UFCON); - writel(0x0, &uart->UMCON); + writel(0x07, &uart->ufcon); + writel(0x0, &uart->umcon); /* Normal,No parity,1 stop,8 bit */ - writel(0x3, &uart->ULCON); + writel(0x3, &uart->ulcon); /* * tx=level,rx=edge,disable timeout int.,enable rx error int., * normal,interrupt or polling */ - writel(0x245, &uart->UCON); + writel(0x245, &uart->ucon); #ifdef CONFIG_HWFLOW - writel(0x1, &uart->UMCON); /* RTS up */ + writel(0x1, &uart->umcon); /* RTS up */ #endif /* FIXME: This is sooooooooooooooooooo ugly */ #if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) /* we need auto hw flow control on the gsm and gps port */ if (dev_index == 0 || dev_index == 1) - writel(0x10, &uart->UMCON); + writel(0x10, &uart->umcon); #endif _serial_setbrg(dev_index); @@ -175,10 +175,10 @@ int _serial_getc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - while (!(readl(&uart->UTRSTAT) & 0x1)) + while (!(readl(&uart->utrstat) & 0x1)) /* wait for character to arrive */ ; - return readb(&uart->URXH) & 0xff; + return readb(&uart->urxh) & 0xff; } #if defined(CONFIG_SERIAL_MULTI) @@ -236,15 +236,15 @@ void _serial_putc(const char c, const int dev_index) return; #endif - while (!(readl(&uart->UTRSTAT) & 0x2)) + while (!(readl(&uart->utrstat) & 0x2)) /* wait for room in the tx FIFO */ ; #ifdef CONFIG_HWFLOW - while (hwflow && !(readl(&uart->UMSTAT) & 0x1)) + while (hwflow && !(readl(&uart->umstat) & 0x1)) /* Wait for CTS up */ ; #endif - writeb(c, &uart->UTXH); + writeb(c, &uart->utxh); /* If \n, also do \r */ if (c == '\n') @@ -271,7 +271,7 @@ int _serial_tstc(const int dev_index) { struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index); - return readl(&uart->UTRSTAT) & 0x1; + return readl(&uart->utrstat) & 0x1; } #if defined(CONFIG_SERIAL_MULTI) diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h index 15f53dd..3481dd6 100644 --- a/include/asm-arm/arch-s3c24x0/s3c24x0.h +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -33,12 +33,12 @@ /* Memory controller (see manual chapter 5) */ struct s3c24x0_memctl { - u32 BWSCON; - u32 BANKCON[8]; - u32 REFRESH; - u32 BANKSIZE; - u32 MRSRB6; - u32 MRSRB7; + u32 bwscon; + u32 bankcon[8]; + u32 refresh; + u32 banksize; + u32 mrsrb6; + u32 mrsrb7; }; @@ -72,34 +72,34 @@ struct s3c24x0_usb_host { /* INTERRUPT (see manual chapter 14) */ struct s3c24x0_interrupt { - u32 SRCPND; - u32 INTMOD; - u32 INTMSK; - u32 PRIORITY; - u32 INTPND; - u32 INTOFFSET; + u32 srcpnd; + u32 intmod; + u32 intmsk; + u32 priority; + u32 intpnd; + u32 intoffset; #ifdef CONFIG_S3C2410 - u32 SUBSRCPND; - u32 INTSUBMSK; + u32 subsrcpnd; + u32 intsubmsk; #endif }; /* DMAS (see manual chapter 8) */ struct s3c24x0_dma { - u32 DISRC; + u32 disrc; #ifdef CONFIG_S3C2410 - u32 DISRCC; + u32 disrcc; #endif - u32 DIDST; + u32 didst; #ifdef CONFIG_S3C2410 - u32 DIDSTC; + u32 didstc; #endif - u32 DCON; - u32 DSTAT; - u32 DCSRC; - u32 DCDST; - u32 DMASKTRIG; + u32 dcon; + u32 dstat; + u32 dcsrc; + u32 dcdst; + u32 dmasktrig; #ifdef CONFIG_S3C2400 u32 res[1]; #endif @@ -116,90 +116,90 @@ struct s3c24x0_dmas { /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ /* (see S3C2410 manual chapter 7) */ struct s3c24x0_clock_power { - u32 LOCKTIME; - u32 MPLLCON; - u32 UPLLCON; - u32 CLKCON; - u32 CLKSLOW; - u32 CLKDIVN; + u32 locktime; + u32 mpllcon; + u32 upllcon; + u32 clkcon; + u32 clkslow; + u32 clkdivn; }; /* LCD CONTROLLER (see manual chapter 15) */ struct s3c24x0_lcd { - u32 LCDCON1; - u32 LCDCON2; - u32 LCDCON3; - u32 LCDCON4; - u32 LCDCON5; - u32 LCDSADDR1; - u32 LCDSADDR2; - u32 LCDSADDR3; - u32 REDLUT; - u32 GREENLUT; - u32 BLUELUT; + u32 lcdcon1; + u32 lcdcon2; + u32 lcdcon3; + u32 lcdcon4; + u32 lcdcon5; + u32 lcdsaddr1; + u32 lcdsaddr2; + u32 lcdsaddr3; + u32 redlut; + u32 greenlut; + u32 bluelut; u32 res[8]; - u32 DITHMODE; - u32 TPAL; + u32 dithmode; + u32 tpal; #ifdef CONFIG_S3C2410 - u32 LCDINTPND; - u32 LCDSRCPND; - u32 LCDINTMSK; - u32 LPCSEL; + u32 lcdintpnd; + u32 lcdsrcpnd; + u32 lcdintmsk; + u32 lpcsel; #endif }; /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { - u32 NFCONF; - u32 NFCMD; - u32 NFADDR; - u32 NFDATA; - u32 NFSTAT; - u32 NFECC; + u32 nfconf; + u32 nfcmd; + u32 nfaddr; + u32 nfdata; + u32 nfstat; + u32 nfecc; }; /* UART (see manual chapter 11) */ struct s3c24x0_uart { - u32 ULCON; - u32 UCON; - u32 UFCON; - u32 UMCON; - u32 UTRSTAT; - u32 UERSTAT; - u32 UFSTAT; - u32 UMSTAT; + u32 ulcon; + u32 ucon; + u32 ufcon; + u32 umcon; + u32 utrstat; + u32 uerstat; + u32 ufstat; + u32 umstat; #ifdef __BIG_ENDIAN u8 res1[3]; - u8 UTXH; + u8 utxh; u8 res2[3]; - u8 URXH; + u8 urxh; #else /* Little Endian */ - u8 UTXH; + u8 utxh; u8 res1[3]; - u8 URXH; + u8 urxh; u8 res2[3]; #endif - u32 UBRDIV; + u32 ubrdiv; }; /* PWM TIMER (see manual chapter 10) */ struct s3c24x0_timer { - u32 TCNTB; - u32 TCMPB; - u32 TCNTO; + u32 tcntb; + u32 tcmpb; + u32 tcnto; }; struct s3c24x0_timers { - u32 TCFG0; - u32 TCFG1; - u32 TCON; + u32 tcfg0; + u32 tcfg1; + u32 tcon; struct s3c24x0_timer ch[4]; - u32 TCNTB4; - u32 TCNTO4; + u32 tcntb4; + u32 tcnto4; }; @@ -207,9 +207,9 @@ struct s3c24x0_timers { struct s3c24x0_usb_dev_fifos { #ifdef __BIG_ENDIAN u8 res[3]; - u8 EP_FIFO_REG; + u8 ep_fifo_reg; #else /* little endian */ - u8 EP_FIFO_REG; + u8 ep_fifo_reg; u8 res[3]; #endif }; @@ -217,29 +217,29 @@ struct s3c24x0_usb_dev_fifos { struct s3c24x0_usb_dev_dmas { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res2[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res3[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res4[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res5[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res6[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; #else /* little endian */ - u8 EP_DMA_CON; + u8 ep_dma_con; u8 res1[3]; - u8 EP_DMA_UNIT; + u8 ep_dma_unit; u8 res2[3]; - u8 EP_DMA_FIFO; + u8 ep_dma_fifo; u8 res3[3]; - u8 EP_DMA_TTC_L; + u8 ep_dma_ttc_l; u8 res4[3]; - u8 EP_DMA_TTC_M; + u8 ep_dma_ttc_m; u8 res5[3]; - u8 EP_DMA_TTC_H; + u8 ep_dma_ttc_h; u8 res6[3]; #endif }; @@ -247,69 +247,69 @@ struct s3c24x0_usb_dev_dmas { struct s3c24x0_usb_device { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res2[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res3[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res4[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res5[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res6[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res7[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res8[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res9[3]; - u8 INDEX_REG; + u8 index_reg; u8 res10[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res11[3]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res12[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res13[7]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res14[3]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res15[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res16[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; #else /* little endian */ - u8 FUNC_ADDR_REG; + u8 func_addr_reg; u8 res1[3]; - u8 PWR_REG; + u8 pwr_reg; u8 res2[3]; - u8 EP_INT_REG; + u8 ep_int_reg; u8 res3[15]; - u8 USB_INT_REG; + u8 usb_int_reg; u8 res4[3]; - u8 EP_INT_EN_REG; + u8 ep_int_en_reg; u8 res5[15]; - u8 USB_INT_EN_REG; + u8 usb_int_en_reg; u8 res6[3]; - u8 FRAME_NUM1_REG; + u8 frame_num1_reg; u8 res7[3]; - u8 FRAME_NUM2_REG; + u8 frame_num2_reg; u8 res8[3]; - u8 INDEX_REG; + u8 index_reg; u8 res9[7]; - u8 MAXP_REG; + u8 maxp_reg; u8 res10[7]; - u8 EP0_CSR_IN_CSR1_REG; + u8 ep0_csr_in_csr1_reg; u8 res11[3]; - u8 IN_CSR2_REG; + u8 in_csr2_reg; u8 res12[3]; - u8 OUT_CSR1_REG; + u8 out_csr1_reg; u8 res13[7]; - u8 OUT_CSR2_REG; + u8 out_csr2_reg; u8 res14[3]; - u8 OUT_FIFO_CNT1_REG; + u8 out_fifo_cnt1_reg; u8 res15[3]; - u8 OUT_FIFO_CNT2_REG; + u8 out_fifo_cnt2_reg; u8 res16[3]; #endif /* __BIG_ENDIAN */ struct s3c24x0_usb_dev_fifos fifo[5]; @@ -319,18 +319,18 @@ struct s3c24x0_usb_device { /* WATCH DOG TIMER (see manual chapter 18) */ struct s3c24x0_watchdog { - u32 WTCON; - u32 WTDAT; - u32 WTCNT; + u32 wtcon; + u32 wtdat; + u32 wtcnt; }; /* IIC (see manual chapter 20) */ struct s3c24x0_i2c { - u32 IICCON; - u32 IICSTAT; - u32 IICADD; - u32 IICDS; + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; }; @@ -338,25 +338,25 @@ struct s3c24x0_i2c { struct s3c24x0_i2s { #ifdef __BIG_ENDIAN u16 res1; - u16 IISCON; + u16 iiscon; u16 res2; - u16 IISMOD; + u16 iismod; u16 res3; - u16 IISPSR; + u16 iispsr; u16 res4; - u16 IISFCON; + u16 iisfcon; u16 res5; - u16 IISFIFO; + u16 iisfifo; #else /* little endian */ - u16 IISCON; + u16 iiscon; u16 res1; - u16 IISMOD; + u16 iismod; u16 res2; - u16 IISPSR; + u16 iispsr; u16 res3; - u16 IISFCON; + u16 iisfcon; u16 res4; - u16 IISFIFO; + u16 iisfifo; u16 res5; #endif }; @@ -365,87 +365,87 @@ struct s3c24x0_i2s { /* I/O PORT (see manual chapter 9) */ struct s3c24x0_gpio { #ifdef CONFIG_S3C2400 - u32 PACON; - u32 PADAT; + u32 pacon; + u32 padat; - u32 PBCON; - u32 PBDAT; - u32 PBUP; + u32 pbcon; + u32 pbdat; + u32 pbup; - u32 PCCON; - u32 PCDAT; - u32 PCUP; + u32 pccon; + u32 pcdat; + u32 pcup; - u32 PDCON; - u32 PDDAT; - u32 PDUP; + u32 pdcon; + u32 pddat; + u32 pdup; - u32 PECON; - u32 PEDAT; - u32 PEUP; + u32 pecon; + u32 pedat; + u32 peup; - u32 PFCON; - u32 PFDAT; - u32 PFUP; + u32 pfcon; + u32 pfdat; + u32 pfup; - u32 PGCON; - u32 PGDAT; - u32 PGUP; + u32 pgcon; + u32 pgdat; + u32 pgup; - u32 OPENCR; + u32 opencr; - u32 MISCCR; - u32 EXTINT; + u32 misccr; + u32 extint; #endif #ifdef CONFIG_S3C2410 - u32 GPACON; - u32 GPADAT; + u32 gpacon; + u32 gpadat; u32 res1[2]; - u32 GPBCON; - u32 GPBDAT; - u32 GPBUP; + u32 gpbcon; + u32 gpbdat; + u32 gpbup; u32 res2; - u32 GPCCON; - u32 GPCDAT; - u32 GPCUP; + u32 gpccon; + u32 gpcdat; + u32 gpcup; u32 res3; - u32 GPDCON; - u32 GPDDAT; - u32 GPDUP; + u32 gpdcon; + u32 gpddat; + u32 gpdup; u32 res4; - u32 GPECON; - u32 GPEDAT; - u32 GPEUP; + u32 gpecon; + u32 gpedat; + u32 gpeup; u32 res5; - u32 GPFCON; - u32 GPFDAT; - u32 GPFUP; + u32 gpfcon; + u32 gpfdat; + u32 gpfup; u32 res6; - u32 GPGCON; - u32 GPGDAT; - u32 GPGUP; + u32 gpgcon; + u32 gpgdat; + u32 gpgup; u32 res7; - u32 GPHCON; - u32 GPHDAT; - u32 GPHUP; + u32 gphcon; + u32 gphdat; + u32 gphup; u32 res8; - u32 MISCCR; - u32 DCLKCON; - u32 EXTINT0; - u32 EXTINT1; - u32 EXTINT2; - u32 EINTFLT0; - u32 EINTFLT1; - u32 EINTFLT2; - u32 EINTFLT3; - u32 EINTMASK; - u32 EINTPEND; - u32 GSTATUS0; - u32 GSTATUS1; - u32 GSTATUS2; - u32 GSTATUS3; - u32 GSTATUS4; + u32 misccr; + u32 dclkcon; + u32 extint0; + u32 extint1; + u32 extint2; + u32 eintflt0; + u32 eintflt1; + u32 eintflt2; + u32 eintflt3; + u32 eintmask; + u32 eintpend; + u32 gstatus0; + u32 gstatus1; + u32 gstatus2; + u32 gstatus3; + u32 gstatus4; #endif }; @@ -454,74 +454,74 @@ struct s3c24x0_gpio { struct s3c24x0_rtc { #ifdef __BIG_ENDIAN u8 res1[67]; - u8 RTCCON; + u8 rtccon; u8 res2[3]; - u8 TICNT; + u8 ticnt; u8 res3[11]; - u8 RTCALM; + u8 rtcalm; u8 res4[3]; - u8 ALMSEC; + u8 almsec; u8 res5[3]; - u8 ALMMIN; + u8 almmin; u8 res6[3]; - u8 ALMHOUR; + u8 almhour; u8 res7[3]; - u8 ALMDATE; + u8 almdate; u8 res8[3]; - u8 ALMMON; + u8 almmon; u8 res9[3]; - u8 ALMYEAR; + u8 almyear; u8 res10[3]; - u8 RTCRST; + u8 rtcrst; u8 res11[3]; - u8 BCDSEC; + u8 bcdsec; u8 res12[3]; - u8 BCDMIN; + u8 bcdmin; u8 res13[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res14[3]; - u8 BCDDATE; + u8 bcddate; u8 res15[3]; - u8 BCDDAY; + u8 bcdday; u8 res16[3]; - u8 BCDMON; + u8 bcdmon; u8 res17[3]; - u8 BCDYEAR; + u8 bcdyear; #else /* little endian */ u8 res0[64]; - u8 RTCCON; + u8 rtccon; u8 res1[3]; - u8 TICNT; + u8 ticnt; u8 res2[11]; - u8 RTCALM; + u8 rtcalm; u8 res3[3]; - u8 ALMSEC; + u8 almsec; u8 res4[3]; - u8 ALMMIN; + u8 almmin; u8 res5[3]; - u8 ALMHOUR; + u8 almhour; u8 res6[3]; - u8 ALMDATE; + u8 almdate; u8 res7[3]; - u8 ALMMON; + u8 almmon; u8 res8[3]; - u8 ALMYEAR; + u8 almyear; u8 res9[3]; - u8 RTCRST; + u8 rtcrst; u8 res10[3]; - u8 BCDSEC; + u8 bcdsec; u8 res11[3]; - u8 BCDMIN; + u8 bcdmin; u8 res12[3]; - u8 BCDHOUR; + u8 bcdhour; u8 res13[3]; - u8 BCDDATE; + u8 bcddate; u8 res14[3]; - u8 BCDDAY; + u8 bcdday; u8 res15[3]; - u8 BCDMON; + u8 bcdmon; u8 res16[3]; - u8 BCDYEAR; + u8 bcdyear; u8 res17[3]; #endif }; @@ -529,34 +529,34 @@ struct s3c24x0_rtc { /* ADC (see manual chapter 16) */ struct s3c2400_adc { - u32 ADCCON; - u32 ADCDAT; + u32 adccon; + u32 adcdat; }; /* ADC (see manual chapter 16) */ struct s3c2410_adc { - u32 ADCCON; - u32 ADCTSC; - u32 ADCDLY; - u32 ADCDAT0; - u32 ADCDAT1; + u32 adccon; + u32 adctsc; + u32 adcdly; + u32 adcdat0; + u32 adcdat1; }; /* SPI (see manual chapter 22) */ struct s3c24x0_spi_channel { - u8 SPCON; + u8 spcon; u8 res1[3]; - u8 SPSTA; + u8 spsta; u8 res2[3]; - u8 SPPIN; + u8 sppin; u8 res3[3]; - u8 SPPRE; + u8 sppre; u8 res4[3]; - u8 SPTDAT; + u8 sptdat; u8 res5[3]; - u8 SPRDAT; + u8 sprdat; u8 res6[3]; u8 res7[16]; }; @@ -570,53 +570,53 @@ struct s3c24x0_spi { struct s3c2400_mmc { #ifdef __BIG_ENDIAN u8 res1[3]; - u8 MMCON; + u8 mmcon; u8 res2[3]; - u8 MMCRR; + u8 mmcrr; u8 res3[3]; - u8 MMFCON; + u8 mmfcon; u8 res4[3]; - u8 MMSTA; + u8 mmsta; u16 res5; - u16 MMFSTA; + u16 mmfsta; u8 res6[3]; - u8 MMPRE; + u8 mmpre; u16 res7; - u16 MMLEN; + u16 mmlen; u8 res8[3]; - u8 MMCR7; - u32 MMRSP[4]; + u8 mmcr7; + u32 mmrsp[4]; u8 res9[3]; - u8 MMCMD0; - u32 MMCMD1; + u8 mmcmd0; + u32 mmcmd1; u16 res10; - u16 MMCR16; + u16 mmcr16; u8 res11[3]; - u8 MMDAT; + u8 mmdat; #else - u8 MMCON; + u8 mmcon; u8 res1[3]; - u8 MMCRR; + u8 mmcrr; u8 res2[3]; - u8 MMFCON; + u8 mmfcon; u8 res3[3]; - u8 MMSTA; + u8 mmsta; u8 res4[3]; - u16 MMFSTA; + u16 mmfsta; u16 res5; - u8 MMPRE; + u8 mmpre; u8 res6[3]; - u16 MMLEN; + u16 mmlen; u16 res7; - u8 MMCR7; + u8 mmcr7; u8 res8[3]; - u32 MMRSP[4]; - u8 MMCMD0; + u32 mmrsp[4]; + u8 mmcmd0; u8 res9[3]; - u32 MMCMD1; - u16 MMCR16; + u32 mmcmd1; + u16 mmcr16; u16 res10; - u8 MMDAT; + u8 mmdat; u8 res11[3]; #endif }; @@ -624,29 +624,29 @@ struct s3c2400_mmc { /* SD INTERFACE (see S3C2410 manual chapter 19) */ struct s3c2410_sdi { - u32 SDICON; - u32 SDIPRE; - u32 SDICARG; - u32 SDICCON; - u32 SDICSTA; - u32 SDIRSP0; - u32 SDIRSP1; - u32 SDIRSP2; - u32 SDIRSP3; - u32 SDIDTIMER; - u32 SDIBSIZE; - u32 SDIDCON; - u32 SDIDCNT; - u32 SDIDSTA; - u32 SDIFSTA; + u32 sdicon; + u32 sdipre; + u32 sdicarg; + u32 sdiccon; + u32 sdicsta; + u32 sdirsp0; + u32 sdirsp1; + u32 sdirsp2; + u32 sdirsp3; + u32 sdidtimer; + u32 sdibsize; + u32 sdidcon; + u32 sdidcnt; + u32 sdidsta; + u32 sdifsta; #ifdef __BIG_ENDIAN u8 res[3]; - u8 SDIDAT; + u8 sdidat; #else - u8 SDIDAT; + u8 sdidat; u8 res[3]; #endif - u32 SDIIMSK; + u32 sdiimsk; }; #endif /*__S3C24X0_H__*/ -- 1.6.0.6

4 15

[U-Boot] [patch 0/2] Some more USB-OHCI bugfixes [V2]
by Remy Bohmer 01 Feb '10

01 Feb '10

This is version 2 of these series! Only patch 1 of 2 has changed, some pedantic Coding Style issues updated that were not detected by Linux/scripts/checkpatch.pl. The USB OHCI init procedure sets the maximum message length the wrong way. A max of 64 bits should not be done by writing '64' in maxpacketsize, but '3'. While fixing this problem it turned out that there is more wrong here in this code it turned out that the wrong bits were checked to determine if the pipe was of type PIPE_INTERRUPT. This series fixes those errors also. I made it 2 seperate patches. The 1st of this series is fully tested and correct on at least the AT91SAM9261 cores. The 2nd patch, however, is created by search-for-the-same-errors-and-replace. I am not able to test that patch, I do not have the boards, so that needs to be done by others or by review. It is clear that code there is buggy in the first place. These patches require my previous series called 'Improve stability USB memory sticks for the common OHCI USB layer.' to be applied before this series. So they should apply on the u-boot-usb git tree. --> git://git.denx.de/u-boot-usb.git I want to mention also, that everytime I look deeper into this code, I find new bugs. It appears that several parts of this code is written with interrupt handling in mind, while we have no interrupt handling at all. Assumptions are done that a interrupt handler does things asynchronous, causing long loops that have no real use at all... So, no guarantees that _all_ problems are solved by now... --

4 8

[U-Boot] [PATCH v3] TI: DaVinci: Updating EMAC driver for DM365, DM646x and DA8XX
by Nick Thompson 01 Feb '10

01 Feb '10

The EMAC IP on DM365, DM646x and DA830 is slightly different from that on DM644x. This change updates the DaVinci EMAC driver so that EMAC becomes operational on SOCs with EMAC v2. Signed-off-by: Nick Thompson <nick.thompson(a)ge.com> --- v2 was messed up, these changes are relative to the original patch CHANGES: Move ;'s from the end of all empty while loops to next line. Gig enable function has no ifdefs on body. Gig enable doesn't change the ET1011C PHY SYSCLK reg as this is board specific (to the DM6467 HD EVM). All struct register overlay accesses now use writel/readl. MDIO startup delay is not specific to emac_v2. Fixed some over-long lines and bad indents. UNCHANGED: Gig enable called whenever phy link is checked since link may have dropped out and come back. I can't test if removing these calls is acceptable. Legacy register definitions are uppercase - new definitions are lowercase. drivers/net/davinci_emac.c | 266 +++++++++++++++++++----------- include/asm-arm/arch-davinci/emac_defs.h | 59 ++++++- 2 files changed, 226 insertions(+), 99 deletions(-) diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fa8cee4..02bbb8c 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -42,10 +42,17 @@ #include <miiphy.h> #include <malloc.h> #include <asm/arch/emac_defs.h> +#include <asm/io.h> unsigned int emac_dbg = 0; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) +#ifdef DAVINCI_EMAC_GIG_ENABLE +#define emac_gigabit_enable() davinci_eth_gigabit_enable() +#else +#define emac_gigabit_enable() /* no gigabit to enable */ +#endif + static void davinci_eth_mdio_enable(void); static int gen_init_phy(int phy_addr); @@ -99,12 +106,14 @@ static void davinci_eth_mdio_enable(void) clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - adap_mdio->CONTROL = (clkdiv & 0xff) | - MDIO_CONTROL_ENABLE | - MDIO_CONTROL_FAULT | - MDIO_CONTROL_FAULT_ENABLE; + writel((clkdiv & 0xff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->CONTROL); - while (adap_mdio->CONTROL & MDIO_CONTROL_IDLE) {;} + while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) + ; } /* @@ -119,7 +128,8 @@ static int davinci_eth_phy_detect(void) active_phy_addr = 0xff; - if ((phy_act_state = adap_mdio->ALIVE) == 0) + phy_act_state = readl(&adap_mdio->ALIVE) & EMAC_MDIO_PHY_MASK; + if (phy_act_state == 0) return(0); /* No active PHYs */ debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); @@ -144,15 +154,18 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) { int tmp; - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; - adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | - MDIO_USERACCESS0_WRITE_READ | - ((reg_num & 0x1f) << 21) | - ((phy_addr & 0x1f) << 16); + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16), + &adap_mdio->USERACCESS0); /* Wait for command to complete */ - while ((tmp = adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) {;} + while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) + ; if (tmp & MDIO_USERACCESS0_ACK) { *data = tmp & 0xffff; @@ -167,16 +180,19 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) { - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; - adap_mdio->USERACCESS0 = MDIO_USERACCESS0_GO | - MDIO_USERACCESS0_WRITE_WRITE | - ((reg_num & 0x1f) << 21) | - ((phy_addr & 0x1f) << 16) | - (data & 0xffff); + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff), + &adap_mdio->USERACCESS0); /* Wait for command to complete */ - while (adap_mdio->USERACCESS0 & MDIO_USERACCESS0_GO) {;} + while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) + ; return(1); } @@ -245,9 +261,24 @@ static int davinci_mii_phy_write(char *devname, unsigned char addr, unsigned cha { return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); } - #endif +static void __attribute__((unused)) davinci_eth_gigabit_enable(void) +{ + u_int16_t data; + + if (davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, 0, &data)) { + if (data & (1 << 6)) { /* speed selection MSB */ + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(EMAC_MACCONTROL_GIGFORCE | + EMAC_MACCONTROL_GIGABIT_ENABLE, + &adap_emac->MACCONTROL); + } + } +} /* Eth device open */ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) @@ -255,64 +286,73 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) dv_reg_p addr; u_int32_t clkdiv, cnt; volatile emac_desc *rx_desc; + unsigned long mac_hi; + unsigned long mac_lo; debug_emac("+ emac_open\n"); /* Reset EMAC module and disable interrupts in wrapper */ - adap_emac->SOFTRESET = 1; - while (adap_emac->SOFTRESET != 0) {;} - adap_ewrap->EWCTL = 0; + writel(1, &adap_emac->SOFTRESET); + while (readl(&adap_emac->SOFTRESET) != 0) + ; +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); + while (readl(&adap_ewrap->softrst) != 0) + ; +#else + writel(0, &adap_ewrap->EWCTL); for (cnt = 0; cnt < 5; cnt++) { - clkdiv = adap_ewrap->EWCTL; + clkdiv = readl(&adap_ewrap->EWCTL); } +#endif rx_desc = emac_rx_desc; - adap_emac->TXCONTROL = 0x01; - adap_emac->RXCONTROL = 0x01; + writel(1, &adap_emac->TXCONTROL); + writel(1, &adap_emac->RXCONTROL); /* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */ /* Using channel 0 only - other channels are disabled */ - adap_emac->MACINDEX = 0; - adap_emac->MACADDRHI = - (davinci_eth_mac_addr[3] << 24) | - (davinci_eth_mac_addr[2] << 16) | - (davinci_eth_mac_addr[1] << 8) | - (davinci_eth_mac_addr[0]); - adap_emac->MACADDRLO = - (davinci_eth_mac_addr[5] << 8) | - (davinci_eth_mac_addr[4]); - - adap_emac->MACHASH1 = 0; - adap_emac->MACHASH2 = 0; + writel(0, &adap_emac->MACINDEX); + mac_hi = (davinci_eth_mac_addr[3] << 24) | + (davinci_eth_mac_addr[2] << 16) | + (davinci_eth_mac_addr[1] << 8) | + (davinci_eth_mac_addr[0]); + mac_lo = (davinci_eth_mac_addr[5] << 8) | + (davinci_eth_mac_addr[4]); + + writel(mac_hi, &adap_emac->MACADDRHI); +#if defined(DAVINCI_EMAC_VERSION2) + writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, + &adap_emac->MACADDRLO); +#else + writel(mac_lo, &adap_emac->MACADDRLO); +#endif + + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); /* Set source MAC address - REQUIRED */ - adap_emac->MACSRCADDRHI = - (davinci_eth_mac_addr[3] << 24) | - (davinci_eth_mac_addr[2] << 16) | - (davinci_eth_mac_addr[1] << 8) | - (davinci_eth_mac_addr[0]); - adap_emac->MACSRCADDRLO = - (davinci_eth_mac_addr[4] << 8) | - (davinci_eth_mac_addr[5]); + writel(mac_hi, &adap_emac->MACSRCADDRHI); + writel(mac_lo, &adap_emac->MACSRCADDRLO); /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; for(cnt = 0; cnt < 16; cnt++) - *addr++ = 0; + writel(0, addr++); addr = &adap_emac->RX0HDP; for(cnt = 0; cnt < 16; cnt++) - *addr++ = 0; + writel(0, addr++); /* Clear Statistics (do this before setting MacControl register) */ addr = &adap_emac->RXGOODFRAMES; for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) - *addr++ = 0; + writel(0, addr++); /* No multicast addressing */ - adap_emac->MACHASH1 = 0; - adap_emac->MACHASH2 = 0; + writel(0, &adap_emac->MACHASH1); + writel(0, &adap_emac->MACHASH2); /* Create RX queue and set receive process in place */ emac_rx_active_head = emac_rx_desc; @@ -324,34 +364,52 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) rx_desc++; } - /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ + /* Finalize the rx desc list */ rx_desc--; rx_desc->next = 0; emac_rx_active_tail = rx_desc; emac_rx_queue_active = 1; /* Enable TX/RX */ - adap_emac->RXMAXLEN = EMAC_MAX_ETHERNET_PKT_SIZE; - adap_emac->RXBUFFEROFFSET = 0; + writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); + writel(0, &adap_emac->RXBUFFEROFFSET); - /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ - adap_emac->RXMBPENABLE = EMAC_RXMBPENABLE_RXBROADEN; + /* + * No fancy configs - Use this for promiscous debug + * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE + */ + writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); /* Enable ch 0 only */ - adap_emac->RXUNICASTSET = 0x01; + writel(1, &adap_emac->RXUNICASTSET); /* Enable MII interface and Full duplex mode */ - adap_emac->MACCONTROL = (EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE); +#ifdef CONFIG_SOC_DA8XX + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE | + EMAC_MACCONTROL_RMIISPEED_100), + &adap_emac->MACCONTROL); +#else + writel((EMAC_MACCONTROL_MIIEN_ENABLE | + EMAC_MACCONTROL_FULLDUPLEX_ENABLE), + &adap_emac->MACCONTROL); +#endif /* Init MDIO & get link state */ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; - adap_mdio->CONTROL = ((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT); + writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, + &adap_mdio->CONTROL); + + /* We need to wait for MDIO to start */ + udelay(1000); if (!phy.get_link_speed(active_phy_addr)) return(0); + emac_gigabit_enable(); + /* Start receive process */ - adap_emac->RX0HDP = (u_int32_t)emac_rx_desc; + writel((u_int32_t)emac_rx_desc, &adap_emac->RX0HDP); debug_emac("- emac_open\n"); @@ -368,34 +426,42 @@ static void davinci_eth_ch_teardown(int ch) if (ch == EMAC_CH_TX) { /* Init TX channel teardown */ - adap_emac->TXTEARDOWN = 1; - for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->TX0CP) { - /* Wait here for Tx teardown completion interrupt to occur - * Note: A task delay can be called here to pend rather than - * occupying CPU cycles - anyway it has been found that teardown - * takes very few cpu cycles and does not affect functionality */ - dly--; - udelay(1); - if (dly == 0) + writel(1, &adap_emac->TXTEARDOWN); + do { + /* + * Wait here for Tx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) break; - } - adap_emac->TX0CP = cnt; - adap_emac->TX0HDP = 0; + cnt = readl(&adap_emac->TX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->TX0CP); + writel(0, &adap_emac->TX0HDP); } else { /* Init RX channel teardown */ - adap_emac->RXTEARDOWN = 1; - for(cnt = 0; cnt != 0xfffffffc; cnt = adap_emac->RX0CP) { - /* Wait here for Rx teardown completion interrupt to occur - * Note: A task delay can be called here to pend rather than - * occupying CPU cycles - anyway it has been found that teardown - * takes very few cpu cycles and does not affect functionality */ - dly--; - udelay(1); - if (dly == 0) + writel(1, &adap_emac->RXTEARDOWN); + do { + /* + * Wait here for Rx teardown completion interrupt to + * occur. Note: A task delay can be called here to pend + * rather than occupying CPU cycles - anyway it has + * been found that teardown takes very few cpu cycles + * and does not affect functionality + */ + dly--; + udelay(1); + if (dly == 0) break; - } - adap_emac->RX0CP = cnt; - adap_emac->RX0HDP = 0; + cnt = readl(&adap_emac->RX0CP); + } while (cnt != 0xfffffffc); + writel(cnt, &adap_emac->RX0CP); + writel(0, &adap_emac->RX0HDP); } debug_emac("- emac_ch_teardown\n"); @@ -410,8 +476,12 @@ static void davinci_eth_close(struct eth_device *dev) davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ /* Reset EMAC module and disable interrupts in wrapper */ - adap_emac->SOFTRESET = 1; - adap_ewrap->EWCTL = 0; + writel(1, &adap_emac->SOFTRESET); +#if defined(DAVINCI_EMAC_VERSION2) + writel(1, &adap_ewrap->softrst); +#else + writel(0, &adap_ewrap->EWCTL); +#endif debug_emac("- emac_close\n"); } @@ -435,6 +505,8 @@ static int davinci_eth_send_packet (struct eth_device *dev, return (ret_status); } + emac_gigabit_enable(); + /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { length = EMAC_MIN_ETHERNET_PKT_SIZE; @@ -449,7 +521,7 @@ static int davinci_eth_send_packet (struct eth_device *dev, EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); /* Send the packet */ - adap_emac->TX0HDP = (unsigned int) emac_tx_desc; + writel((unsigned long)emac_tx_desc, &adap_emac->TX0HDP); /* Wait for packet to complete or link down */ while (1) { @@ -457,7 +529,10 @@ static int davinci_eth_send_packet (struct eth_device *dev, davinci_eth_ch_teardown (EMAC_CH_TX); return (ret_status); } - if (adap_emac->TXINTSTATRAW & 0x01) { + + emac_gigabit_enable(); + + if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { ret_status = length; break; } @@ -490,15 +565,15 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } /* Ack received packet descriptor */ - adap_emac->RX0CP = (unsigned int) rx_curr_desc; + writel((unsigned long)rx_curr_desc, &adap_emac->RX0CP); curr_desc = rx_curr_desc; emac_rx_active_head = (volatile emac_desc *) rx_curr_desc->next; if (status & EMAC_CPPI_EOQ_BIT) { if (emac_rx_active_head) { - adap_emac->RX0HDP = - (unsigned int) emac_rx_active_head; + writel((unsigned long)emac_rx_active_head, + &adap_emac->RX0HDP); } else { emac_rx_queue_active = 0; printf ("INFO:emac_rcv_packet: RX Queue not active\n"); @@ -515,8 +590,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc; if (emac_rx_queue_active != 0) { - adap_emac->RX0HDP = - (unsigned int) emac_rx_active_head; + writel((unsigned long)emac_rx_active_head, + &adap_emac->RX0HDP); printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); emac_rx_queue_active = 1; } @@ -526,7 +601,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) tail_desc->next = (unsigned int) curr_desc; status = tail_desc->pkt_flag_len; if (status & EMAC_CPPI_EOQ_BIT) { - adap_emac->RX0HDP = (unsigned int) curr_desc; + writel((unsigned long)curr_desc, + &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT; tail_desc->pkt_flag_len = status; } @@ -566,7 +642,7 @@ int davinci_emac_initialize(void) davinci_eth_mdio_enable(); for (i = 0; i < 256; i++) { - if (adap_mdio->ALIVE) + if (readl(&adap_mdio->ALIVE)) break; udelay(10); } diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index 96bc80e..e313263 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -43,6 +43,13 @@ #define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) #define EMAC_WRAPPER_RAM_ADDR (0x01d08000) #define EMAC_MDIO_BASE_ADDR (0x01d0b000) +#define DAVINCI_EMAC_VERSION2 +#elif defined(CONFIG_SOC_DA8XX) +#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE +#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE +#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE +#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE +#define DAVINCI_EMAC_VERSION2 #else #define EMAC_BASE_ADDR (0x01c80000) #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) @@ -51,6 +58,11 @@ #endif #ifdef CONFIG_SOC_DM646X +#define DAVINCI_EMAC_VERSION2 +#define DAVINCI_EMAC_GIG_ENABLE +#endif + +#ifdef CONFIG_SOC_DM646X /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 76500000 /* MDIO clock output frequency */ @@ -60,6 +72,11 @@ #define EMAC_MDIO_BUS_FREQ 121500000 /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ +#elif defined(CONFIG_SOC_DA8XX) +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ #else /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ @@ -128,6 +145,10 @@ typedef volatile struct _emac_desc #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) #define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) #define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MAC_ADDR_MATCH (1 << 19) +#define EMAC_MAC_ADDR_IS_VALID (1 << 20) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) @@ -283,10 +304,40 @@ typedef struct { /* EMAC Wrapper Registers Structure */ typedef struct { -#if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365) - dv_reg IDVER; - dv_reg SOFTRST; - dv_reg EMCTRL; +#ifdef DAVINCI_EMAC_VERSION2 + dv_reg idver; + dv_reg softrst; + dv_reg emctrl; + dv_reg c0rxthreshen; + dv_reg c0rxen; + dv_reg c0txen; + dv_reg c0miscen; + dv_reg c1rxthreshen; + dv_reg c1rxen; + dv_reg c1txen; + dv_reg c1miscen; + dv_reg c2rxthreshen; + dv_reg c2rxen; + dv_reg c2txen; + dv_reg c2miscen; + dv_reg c0rxthreshstat; + dv_reg c0rxstat; + dv_reg c0txstat; + dv_reg c0miscstat; + dv_reg c1rxthreshstat; + dv_reg c1rxstat; + dv_reg c1txstat; + dv_reg c1miscstat; + dv_reg c2rxthreshstat; + dv_reg c2rxstat; + dv_reg c2txstat; + dv_reg c2miscstat; + dv_reg c0rximax; + dv_reg c0tximax; + dv_reg c1rximax; + dv_reg c1tximax; + dv_reg c2rximax; + dv_reg c2tximax; #else u_int8_t RSVD0[4100]; dv_reg EWCTL; -- 1.6.3.3

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[U-Boot] [PATCH] macb: Fix mii_phy_read and mii_phy_write functions
by Semih Hazar 01 Feb '10

01 Feb '10

Enabling CONFIG_CMD_MII in AVR32 boards was not possible due to compile errors. This patch fixes miiphy_read and miiphy_write functions and registers them properly. Signed-off-by: Semih Hazar <semih.hazar(a)indefia.com> --- drivers/net/macb.c | 110 +++++++++++++++------------------------------------ 1 files changed, 33 insertions(+), 77 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 6de0a04..c74bee5 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -42,6 +42,7 @@ #include <net.h> #include <netdev.h> #include <malloc.h> +#include <miiphy.h> #include <linux/mii.h> #include <asm/io.h> @@ -164,6 +165,36 @@ static u16 macb_mdio_read(struct macb_device *macb, u8 reg) return MACB_BFEXT(DATA, frame); } +#if defined(CONFIG_CMD_MII) + +int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if ( macb->phy_addr != phy_adr ) + return -1; + + *value = macb_mdio_read(macb, reg); + + return 0; +} + +int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct macb_device *macb = to_macb(dev); + + if ( macb->phy_addr != phy_adr ) + return -1; + + macb_mdio_write(macb, reg, value); + + return 0; +} +#endif + + #if defined(CONFIG_CMD_NET) static int macb_send(struct eth_device *netdev, volatile void *packet, @@ -540,84 +571,9 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) eth_register(netdev); - return 0; -} - -#endif - #if defined(CONFIG_CMD_MII) - -int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - int iflag; - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl |= MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(&macb, EMACB_MAN, frame); - - do { - netstat = macb_readl(&macb, EMACB_NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - frame = macb_readl(&macb, EMACB_MAN); - *value = MACB_BFEXT(DATA, frame); - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - return 0; -} - -int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - int iflag; - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl |= MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(&macb, EMACB_MAN, frame); - - do { - netstat = macb_readl(&macb, EMACB_NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - iflag = disable_interrupts(); - netctl = macb_readl(&macb, EMACB_NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(&macb, EMACB_NCR, netctl); - if (iflag) - enable_interrupts(); - + miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); +#endif return 0; } -- 1.5.4.3

2 1

[U-Boot] [PATCH 1/5] tsec: Clean up Broadcom PHY status parsing
by Peter Tyser 27 Jan '10

27 Jan '10

- Remove unnecessary printing "Enet starting in <speed>/<duplex>" This same information is already printed during normal ethernet operation in the form "Speed: 1000, full duplex". - Add a check for link before determining link speed and duplex If there is no link, speed/duplex don't matter. This also removes the annoying and unneeded "Auto-neg error, defaulting to 10BT/HD" message that occurs when no link is detected. - Whitespace and line > 80 characters cleanup Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- drivers/net/tsec.c | 77 +++++++++++++++++++++++----------------------------- 1 files changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d8b6619..1038285 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -487,50 +487,41 @@ uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv) */ uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv) { + /* If there is no link, speed and duplex don't matter */ + if (!priv->link) + return 0; - switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){ - - case 1: - printf("Enet starting in 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; - - case 2: - printf("Enet starting in 10BT/FD\n"); - priv->duplexity = 1; - priv->speed = 10; - break; - - case 3: - printf("Enet starting in 100BT/HD\n"); - priv->duplexity = 0; - priv->speed = 100; - break; - - case 5: - printf("Enet starting in 100BT/FD\n"); - priv->duplexity = 1; - priv->speed = 100; - break; - - case 6: - printf("Enet starting in 1000BT/HD\n"); - priv->duplexity = 0; - priv->speed = 1000; - break; - - case 7: - printf("Enet starting in 1000BT/FD\n"); - priv->duplexity = 1; - priv->speed = 1000; - break; - - default: - printf("Auto-neg error, defaulting to 10BT/HD\n"); - priv->duplexity = 0; - priv->speed = 10; - break; + switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> + MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { + case 1: + priv->duplexity = 0; + priv->speed = 10; + break; + case 2: + priv->duplexity = 1; + priv->speed = 10; + break; + case 3: + priv->duplexity = 0; + priv->speed = 100; + break; + case 5: + priv->duplexity = 1; + priv->speed = 100; + break; + case 6: + priv->duplexity = 0; + priv->speed = 1000; + break; + case 7: + priv->duplexity = 1; + priv->speed = 1000; + break; + default: + printf("Auto-neg error, defaulting to 10BT/HD\n"); + priv->duplexity = 0; + priv->speed = 10; + break; } return 0; -- 1.6.2.1

2 7

[U-Boot] [PATCH] tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode
by Peter Tyser 27 Jan '10

27 Jan '10

In SGMII mode the link between a processor's internal TBI PHY and an external PHY should always be 1000Mbps, full duplex. Also, the SGMII interface between an internal TBI PHY and external PHY does not support in-band auto-negotation. Previously, when configured for SGMII mode a TBI PHY would attempt to restart auto-negotation during initializtion. This auto-negotation between a TBI PHY and external PHY would fail and result in unusable ethernet operation. Forcing the TBI PHY and and external PHY to link at 1000Mbps full duplex in SGMII mode resolves this issue of auto-negotation failing. Note that 10Mbps and 100Mbps operation is still possible on the external side of the external PHY even when SGMII is operating at 1000Mbps. The SGMII interface still operates at 1000Mbps, but each byte of data is repeated 100 or 10 times for 10/100Mbps and the external PHY handles converting this data stream into proper 10/100Mbps signalling. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- In-band SGMII auto-negotiation doesn't work according to a lengthy discussion with a Freescale FAE and the AN3869 SGMII appnote. XES's MPC8572 and MPC8640 boards need this patch in order to use ethernet. These boards generally use SGMII to connect to an BCM5482S PHY which has an external gigabit-capable copper or fiber interface. Some of Freescale's reference platforms have an SGMII riser card - any idea how those function when using auto-negotiation? Do they function? Are the really using SGMII, or are they using 1000 Base-X? Some of the info in the manuals is misleading/confusing so any comments are more than welcome from Freescalers:) Thanks, Peter drivers/net/tsec.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3f74118..cff5d38 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -276,12 +276,13 @@ uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) | TBIANA_FULL_DUPLEX \ ) +/* Force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ #define TBICR_SETTINGS ( \ TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { -- 1.6.2.1

2 3

[U-Boot] [PATCH] NetStar: Disable CONFIG_CMD_JFFS2
by Ladislav Michl 26 Jan '10

26 Jan '10

Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- include/configs/netstar.h | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 7bddf24..e37a378 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -151,7 +151,6 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_LOADB #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NAND @@ -160,8 +159,6 @@ #define CONFIG_CMD_RUN -#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ - /* * BOOTP options */

3 2

[U-Boot] [PATCH] NetStar: Remove debug junk leaked into eeprom utility
by Ladislav Michl 26 Jan '10

26 Jan '10

Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/netstar/eeprom.c | 8 +-- board/netstar/eeprom_start.S | 190 +++--------------------------------------- 2 files changed, 14 insertions(+), 184 deletions(-) rewrite board/netstar/eeprom_start.S (94%) diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index 1366457..adb01b9 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -22,8 +22,6 @@ * Some code shamelessly stolen back from Robin Getz. */ -#define DEBUG - #include <common.h> #include <exports.h> #include <timestamp.h> @@ -142,8 +140,6 @@ static int parse_element(char *s, unsigned char *buf, int len) return cnt; } -extern int crcek(void); - int eeprom(int argc, char *argv[]) { int i, len, ret; @@ -161,8 +157,6 @@ int eeprom(int argc, char *argv[]) return 1; } - return crcek(); - if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; @@ -176,7 +170,7 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { - printf("VoiceBlue EEPROM writer\n"); + printf("NetStar EEPROM writer\n"); printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); return 0; diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S index 1306485..3609382 100644 --- a/board/netstar/eeprom_start.S +++ b/board/netstar/eeprom_start.S @@ -8,170 +8,6 @@ */ .globl _start -_start: b eeprom - -#include "crcek.h" - -/** - * do_crc32 - calculate CRC32 of given buffer - * r0 - crc - * r1 - pointer to buffer - * r2 - buffer len - */ - .macro do_crc32 - ldr r5, FFFFFFFF - eor r0, r0, r5 - adr r3, CRC32_TABLE -1: - ldrb r4, [r1], #1 - eor r4, r4, r0 - and r4, r4, #0xff - ldr r4, [r3, r4, lsl#2] - eor r0, r4, r0, lsr#8 - subs r2, r2, #0x1 - bne 1b - eor r0, r0, r5 - .endm - - .macro crcuj, offset, size - ldr r1, \offset - ldr r2, [r1] - cmp r2, #0 @ no data, no problem - beq 2f - mov r7, #1 - tst r2, #3 @ unaligned size - bne 2f - mov r7, #2 - ldr r0, \size - cmp r2, r0 @ bogus size - bhi 2f - mov r7, #3 - add r1, r1, #4 - mov r0, #0 - do_crc32 - ldr r1, [r1] -2: - cmp r0, r1 - .endm - - .macro wait, reg - mov \reg, #0x1000 -3: - subs \reg, \reg, #0x1 - bne 3b - - .endm -.text -.globl crcek -crcek: - mov r6, #0 -@ crcuj _LOADER1_OFFSET, _LOADER_SIZE -@ bne crc1_bad -@ orr r6, r6, #1 -crc1_bad: - crcuj _LOADER2_OFFSET, _LOADER_SIZE - bne crc2_bad - orr r6, r6, #2 -crc2_bad: -@ mov r0, r6 - mov pc, lr - ldr r3, _LOADER1_OFFSET - ldr r4, _LOADER2_OFFSET - tst r6, #3 - beq one_is_bad @ one of them (or both) has bad crc - ldr r1, [r3, #4] - ldr r2, [r4, #4] - cmp r1, r2 @ boot 2nd loader if versions differ - beq boot_1st - b boot_2nd -one_is_bad: - tst r6, #1 - bne boot_1st - tst r6, #2 - bne boot_2nd -@ We are doomed, so let user know. - ldr r0, GPIO_BASE @ configure GPIO pins - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] -blink_loop: - mov r1, #0x08 - strh r1, [r0, #0x04] - wait r3 - mov r1, #0x10 - strh r1, [r0, #0x04] - wait r3 - b blink_loop -boot_1st: - add pc, r3, #8 -boot_2nd: - add pc, r4, #8 - -_LOADER_SIZE: - .word LOADER_SIZE - 8 @ minus size and crc32 -_LOADER1_OFFSET: - .word LOADER1_OFFSET -_LOADER2_OFFSET: - .word LOADER2_OFFSET - -FFFFFFFF: - .word 0xffffffff -CRC32_TABLE: - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b - .word 0x2d02ef8d - -GPIO_BASE: - .word 0xfffce000 -GPIO_DIRECTION: - .word 0x0000ffe7 +_start: b eeprom .end

2 3

[U-Boot] [PATCH] NetStar: make crcit utility more readable.
by Ladislav Michl 26 Jan '10

26 Jan '10

Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/netstar/crcit.c | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c index e0cea9b..0eef41a 100644 --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -56,13 +56,14 @@ static int do_crc(char *path, unsigned version) fprintf(stderr, "File too large\n"); return EXIT_FAILURE; } - size = (size + 3) & ~3; /* round up to 4 bytes */ - data[0] = size + 4; /* add size of version field */ + size = (size + 3) & ~3; /* round up to 4 bytes */ + size += 4; /* add size of version field */ + data[0] = size; data[1] = version; - data[2 + (size >> 2)] = crc32(0, (unsigned char *)(data + 1), data[0]); + data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size); close(fd); - if (write(STDOUT_FILENO, data, size + 3*4) == -1) { + if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) { perror("Error writing file"); return EXIT_FAILURE; } -- 1.5.3.8

2 1

[U-Boot] [RFC PATCH] add ability to handle compressed images to imxtract
by Wolfgang Wegner 26 Jan '10

26 Jan '10

imxtract currently can not handle compressed images. This patch adds handling for bzip2 and zip compression. In both cases, a destination address has to be specified for extraction. Signed-off-by: Wolfgang Wegner <w.wegner(a)astro-kom.de> --- common/cmd_ximg.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 77 insertions(+), 5 deletions(-) diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 5593b2d..e6eb336 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -31,8 +31,20 @@ #include <common.h> #include <command.h> #include <image.h> +#include <watchdog.h> +#include <u-boot/zlib.h> +#if defined(CONFIG_BZIP2) +#include <bzlib.h> +#endif #include <asm/byteorder.h> +/* there is no prototype in zlib.h */ +int gunzip (void *, int, unsigned char *, unsigned long *); + +#ifndef CFG_XIMG_LEN +#define CFG_XIMG_LEN 0x800000 /* use 8MByte as default max gunzip size */ +#endif + int do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -50,6 +62,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) const void *fit_data; size_t fit_len; #endif + uint unc_len = CFG_XIMG_LEN; + uint8_t comp; verify = getenv_yesno ("verify"); @@ -92,8 +106,9 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - if (image_get_comp (hdr) != IH_COMP_NONE) { - printf("Wrong Compression Type for %s command\n", + comp = image_get_comp (hdr); + if ((comp != IH_COMP_NONE) && (argc < 4)) { + printf("Must specify load address for %s command with compressed image\n", cmdtp->name); return 1; } @@ -138,8 +153,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } - if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)) { - printf("Wrong Compression Type for %s command\n", + if ((fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)) && (argc < 4)) { + printf("Must specify load address for %s command with compressed image\n", cmdtp->name); return 1; } @@ -158,6 +173,11 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } + if (fit_image_get_comp (fit_hdr, noffset, &comp)) { + puts ("Could not find script subimage compression type\n"); + return 1; + } + data = (ulong)fit_data; len = (ulong)fit_len; break; @@ -168,7 +188,59 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (argc > 3) { - memcpy((char *) dest, (char *) data, len); + switch (comp) { + case IH_COMP_NONE: +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *) dest; + void *from = (void *)data; + + printf (" Loading part %d ... ", part); + + while (l > 0) { + size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove ((char *) dest, (char *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + break; + case IH_COMP_GZIP: + printf (" Uncompressing part %d (len %d) ... ", part, len); + if (gunzip ((void *) dest, unc_len, + (uchar *) data, &len) != 0) { + puts ("GUNZIP ERROR - image not loaded\n"); + return 1; + } + break; +#if defined(CONFIG_BZIP2) + case IH_COMP_BZIP2: + printf (" Uncompressing part %d ... ", part); + /* + * If we've got less than 4 MB of malloc() space, + * use slower decompression algorithm which requires + * at most 2300 KB of memory. + */ + i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load), + &unc_len, (char *)data, len, + CFG_MALLOC_LEN < (4096 * 1024), 0); + if (i != BZ_OK) { + printf ("BUNZIP2 ERROR %d - image not loaded\n", i); + return 1; + } + break; +#endif /* CONFIG_BZIP2 */ + default: + printf ("Unimplemented compression type %d\n", comp); + return 1; + } + puts ("OK\n"); } sprintf(pbuf, "%8lx", data); -- 1.5.6.5

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