December 2009 - U-Boot

[U-Boot] Regarding MPC8640D second core initialization
by Thirumalai 03 Dec '09

03 Dec '09

Hi denx, I am using 2009-06 u-boot for MPC8640D based board. i just want to know whether the second core of MPC8640D is kicked off automatically or will it required by the user to kick. Also if am enabling the CONFIG_MP macro and CONFIG_NUM_CPUS as 2, then the reset command of the target is not working(means board is getting hanged). I have mentioned the value of CONFIG_SYS_SCRATCH_VA as 0xf5000000. Kindly suggest me what might be the error. Thank you, T.

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[U-Boot] NE2000 driver issues and extensions
by Rutger Hofman 03 Dec '09

03 Dec '09

On our new, custom BlackFin board (see http://www.rfidguardian.org) we have an Asix AX88796B Ethernet chip. This chip is NE2000-compatible according to the manufacturer. When porting this driver to our board, and extending it for extra commands (DP_RESET in software and then some, attempt to read the MAC address from an EEPROM), I met a few issues with the ne2000 controller: bug 1) when a corrupted packet arrives, the driver attempts to detect this by doing a sanity check on the packet length in uboot_push_packet_len(). If the length check fails, this function returns and the caller continues as if nothing happened, reading rcv_hdr[1] as the location for the next packet. But this header will probably also be corrupt, so the management of receive pages becomes nonsensical. Proposed fix: a) check rcv_hdr[0], the receive status byte; if != 0x01, then the packet is corrupt; b) check the length; if it exceeds PKTSIZE_ALIGN, the packet is corrupt; c) if the packet is corrupt, advance the next-packet-pointer to the following location, irrespective of the pointer in the header. This will discard the corrupt packet and keep the received pages consistent bug 2) dp83902a_RxEvent() caches a pointer to the next-page-to-be read, then calls uboot_push_packet_len(), which calls upper layers via NetReceive(). If the upper layers want, they can call dp83902a_start() -- which happens e.g. when a tftp-ed file doesn't exist. dp83902a_start() resets the receive page pointers to the initial state. But when NetReceive() returns, the modified pointers into the receive pages are ignored. The BNDRY pointer is set to the cached next pointer, which has no relation to the current state. Proposed fix: a) dp83902a_start() sets a bit in the driver state. This bit cleared before the driver upcalls to NetReceive(); if the bit is set after NetReceive() returned, the driver knows that the receive page pointers are reset. In that case, it doesn't touch the receive page pointers any more. Another issue: Extension 1) our chip has an x16 bus. I extended the driver to support 16-bit data read/writes, following the implementation in eCos (where the ne2000 driver originates). Issue: the endianness in the eCos driver appears wrong to me -- NE2000 is little-endian itself, so the driver must convert between NE2000's little-endianness and the endianness of the host. The eCos driver appears to assume a big-endian host in all cases. I plan to also report this on the eCos mailing lists. Rutger

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[U-Boot] [PATCH v2 1/2] NET: Move MDIO regs out of TSEC Space
by Sandeep Gopalpet 03 Dec '09

03 Dec '09

Moved the mdio regs out of the tsec structure,and provided different offsets for tsec base and mdio base so that provision for etsec2.0 can be provided. This patch helps in providing the support for etsec2.0 In etsec2.0, the MDIO register space and the etsec reg space are different. Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into platform specific files. Signed-off-by: Sandeep Gopalpet <sandeep.kumar(a)freescale.com> --- drivers/net/tsec.c | 20 +++++++++--------- include/asm-ppc/immap_83xx.h | 9 ++++++++ include/asm-ppc/immap_85xx.h | 10 +++++++++ include/asm-ppc/immap_86xx.h | 9 ++++++++ include/tsec.h | 43 +++++++++++++++++++---------------------- 5 files changed, 58 insertions(+), 33 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5c3d261..2ad033e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -83,7 +83,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -136,6 +136,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -222,7 +223,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -245,7 +246,7 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) { uint value; @@ -290,11 +291,11 @@ static void tsec_configure_serdes(struct tsec_private *priv) { /* Access TBI PHY registers at given TSEC register offset as opposed to the * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -306,12 +307,11 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -739,7 +739,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -1772,7 +1772,7 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index c60a7d2..57b1a72 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -868,4 +868,13 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) + +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC_SIZE 0x01000 + +#define CONFIG_SYS_MDIO1_OFFSET 0x24520 +#define MDIO_OFFSET 0x01000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 4194295..ad3910c 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1932,4 +1932,14 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +/* TSEC and MDIO OFFSETS */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC_SIZE 0x01000 + +#define CONFIG_SYS_MDIO1_OFFSET 0x24520 +#define MDIO_OFFSET 0x01000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index fdfc654..80e7ecd 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1298,4 +1298,13 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC_SIZE 0x01000 + +#define CONFIG_SYS_MDIO1_OFFSET 0x24520 +#define MDIO_OFFSET 0x01000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_86xx__*/ diff --git a/include/tsec.h b/include/tsec.h index 0ac3034..2b9c9c3 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao(a)motorola.com) * author Andy Fleming @@ -20,22 +20,11 @@ #include <net.h> #include <config.h> -#ifndef CONFIG_SYS_TSEC1_OFFSET - #define CONFIG_SYS_TSEC1_OFFSET (0x24000) -#endif - -#define TSEC_SIZE 0x01000 - -/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ - || defined(CONFIG_MPC83xx) - #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#endif - #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET ), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS \ @@ -44,7 +33,8 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR + (num -1)*MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -461,6 +451,16 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; +typedef struct tsec_mdio +{ + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ +} tsec_mdio_t; + typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -526,12 +526,7 @@ typedef struct tsec uint res51c; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ + uint resmdio[6]; uint res538; @@ -571,7 +566,8 @@ typedef struct tsec struct tsec_private { volatile tsec_t *regs; - volatile tsec_t *phyregs; + volatile tsec_mdio_t *phyregs; + volatile tsec_mdio_t *phyregs_sgmii; struct phy_info *phyinfo; uint phyaddr; u32 flags; @@ -630,7 +626,8 @@ struct phy_info { struct tsec_info_struct { tsec_t *regs; - tsec_t *miiregs; + tsec_mdio_t *miiregs; + tsec_mdio_t *miiregs_sgmii; char *devname; unsigned int phyaddr; u32 flags; -- 1.5.2.2

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[U-Boot] [PATCH v2] Fix build failure in examples/standalone
by Sanjeev Premi 03 Dec '09

03 Dec '09

Some versions of 'make' do not handle trailing white-spaces properly. Trailing spaces in ELF causes a 'fake' source to be added to the variable COBJS; leading to build failure (listed below). The problem was found with GNU Make 3.80. Using text-function 'strip' as a workaround for the problem. make[1]: Entering directory `/home/sanjeev/u-boot/examples/standalone' arm-none-linux-gnueabi-gcc -g -Os -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanjeev/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/codesourcery/2009q1- 203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/include -pipe -DCONFIG_ ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-interwork -march=armv5 -Wall -Wstrict-prototypes -fno-stack-protector -g -Os -fno-common -ff ixed-r8 -msoft-float -D__KERNEL__ -DTEXT_BASE=0x80e80000 -I/home/sanje ev/u-boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/co desourcery/2009q1-203/bin/../lib/gcc/arm-none-linux-gnueabi/4.3.3/includ e -pipe -DCONFIG_ARM -D__ARM__ -marm -mabi=aapcs-linux -mno-thumb-inte rwork -march=armv5 -I.. -Bstatic -T u-boot.lds -Ttext 0x80e80000 -o .c arm-none-linux-gnueabi-gcc: no input files make[1]: *** [.c] Error 1 make[1]: Leaving directory `/home/sanjeev/u-boot/examples/standalone' make: *** [examples/standalone] Error 2 premi # Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- examples/standalone/Makefile | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 5e2f2bc..c02ce43 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -38,7 +38,13 @@ ELF-mpc8260 += mem_to_mem_idma2intr ELF-ppc += sched ELF-oxc += eepro100_eeprom -ELF := $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)) +# +# Some versions of make do not handle trailing white spaces properly; +# leading to build failures. The problem was found with GNU Make 3.80. +# Using 'strip' as a workaround for the problem. +# +ElF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU))) + SREC = $(addsuffix .srec,$(ELF)) BIN = $(addsuffix .bin,$(ELF)) -- 1.6.2.2

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[U-Boot] omap3: Is lowlevel_init() ever called?
by Premi, Sanjeev 03 Dec '09

03 Dec '09

Hi all, I have been trying to debug 'strange' clock settings in the omap3evm; that would surface quite infrequently. However, today I was able to get them regularly. Symptom: the MPU clock is set at 381MHz instead of expected 500MHz. Tracing back from prcm_init() to s_init() to lowlevel_init() and cpu_init_crit() I feel that lowlevel_init() is being skipped at together. In the patch below, I am updating a flag on very beginning of s_init() and later printing in print_cpuinfo(). To exclude any other (possible) foul-play by stray pointer, I initialized this flag to 11 and expect it to be 55 after s_init() is called. But the value remains 11 - when printed in print_cpuinfo(). Also, CONFIG_SKIP_LOWLEVEL_INIT is not defined in omap3_evm_config. Though I am at 2009.08, I did not see any differences in start.S that could have an apparent effect. Am I missing something completely? Best regards, Sanjeev diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 939ed6c..5dfd8f3 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -42,6 +42,8 @@ extern omap3_sysinfo sysinfo; extern u32 is_mem_sdr(void); +int s_init_flag=11; + /****************************************************************************** * Routine: delay * Description: spinning delay to use before udelay works @@ -193,6 +195,8 @@ void s_init(void) { int in_sdram = is_running_in_sdram(); + s_init_flag=55; + watchdog_init(); try_unlock_memory(); diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/cpu/arm_cortexa8/omap3/lowlevel_init.S index 73063ec..d83dd53 100644 --- a/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -174,7 +174,11 @@ lowlevel_init: ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ mov ip, lr /* save link reg across call */ + nop + nop bl s_init /* go setup pll, mux, memory */ + nop + nop ldr ip, [sp] /* restore save ip */ mov lr, ip /* restore link reg */ diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 2fb6c10..2f29032 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -31,6 +31,8 @@ #include <asm/arch/sys_proto.h> #include <i2c.h> +extern int s_init_flag; + extern omap3_sysinfo sysinfo; static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; @@ -414,6 +416,8 @@ int print_cpuinfo (void) cpu_s, sec_s, rev_s[get_cpu_rev()], (cpu_family == CPU_AM35XX) ? "" : " CPU-OPP2"); + printf ("s_init_flag = %d\n", s_init_flag); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ ====================================== U-Boot 2009.08-00047-gd5ef5fe-dirty (Nov 30 2009 - 23:15:59) OMAP3430/3530-GP ES3.1, CPU-OPP2 L3-165MHz s_init_flag = 11 OMAP3 EVM board + LPDDR/NAND DRAM: 128 MB NAND: 256 MiB In: serial Out: serial Err: serial Die ID #609200040000000004032d460c01201a Net: smc911x-0 Hit any key to stop autoboot: 0 OMAP3_EVM # OMAP3_EVM # OMAP3_EVM #

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[U-Boot] [PATCH v2] Davinci: Configurable NAND chip selects
by Nick Thompson 03 Dec '09

03 Dec '09

Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- This config item is already used on many other platforms so is not a new config item as such. This change should not result in any functional changes to current davinci boards. They all seem to use CS2 as this was the only chip select supported by the driver. da830evm however uses CS3, so a configurable driver is required. Changes from previous version: Made dummy reads more obvious. Allow for indexing into ECC1 result registers. Correct ECC clear dummy read to account for new CONFIG setting Applies to: u-boot-ti drivers/mtd/nand/davinci_nand.c | 25 +++++++++++-------------- include/asm-arm/arch-davinci/emif_defs.h | 14 ++++++++++---- include/configs/davinci_dm355evm.h | 1 + include/configs/davinci_dm355leopard.h | 1 + include/configs/davinci_dm365evm.h | 1 + include/configs/davinci_dm6467evm.h | 1 + include/configs/davinci_dvevm.h | 1 + include/configs/davinci_schmoogie.h | 1 + include/configs/davinci_sffsdr.h | 1 + include/configs/davinci_sonata.h | 1 + diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index eabaf3e..612846f 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -82,26 +82,20 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - int dummy; + u_int32_t val; - dummy = emif_regs->NANDF1ECC; + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); - /* FIXME: only chipselect 0 is supported for now */ - emif_regs->NANDFCR |= 1 << 8; + val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + writel(val, &emif_regs->NANDFCR); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - if (region == 1) - ecc = emif_regs->NANDF1ECC; - else if (region == 2) - ecc = emif_regs->NANDF2ECC; - else if (region == 3) - ecc = emif_regs->NANDF3ECC; - else if (region == 4) - ecc = emif_regs->NANDF4ECC; + ecc = readl(&(emif_regs->NANDFECC[region - 1])); return(ecc); } @@ -214,8 +208,11 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) * Start a new ECC calculation for reading or writing 512 bytes * of data. */ - val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12); - emif_regs->NANDFCR = val; + val = readl(&emif_regs->NANDFCR); + val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_START; + writel(val, &emif_regs->NANDFCR); break; case NAND_ECC_READSYN: val = emif_regs->NAND4BITECC1; diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index c91e30c..d67292f 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -51,10 +51,7 @@ typedef struct { dv_reg NANDFCR; dv_reg NANDFSR; u_int8_t RSVD1[8]; - dv_reg NANDF1ECC; - dv_reg NANDF2ECC; - dv_reg NANDF3ECC; - dv_reg NANDF4ECC; + dv_reg NANDFECC[4]; u_int8_t RSVD2[60]; dv_reg NAND4BITECCLOAD; dv_reg NAND4BITECC1; @@ -68,4 +65,13 @@ typedef struct { } emif_registers; typedef emif_registers *emifregs; + +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) + +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) + +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) + #endif diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index ea40df0..07914a3 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -66,6 +66,7 @@ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index 5db720e..54b153d 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -65,6 +65,7 @@ /* NAND */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_HW_ECC diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 53a105b..5a510e6 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -74,6 +74,7 @@ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 6617941..dce0411 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -75,6 +75,7 @@ #define CONFIG_SYS_NO_FLASH #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_IS_IN_NAND #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index b045e80..ff2c845 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -114,6 +114,7 @@ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 9384cdd..299ec25 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -83,6 +83,7 @@ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 71d48fb..6c1d303 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -78,6 +78,7 @@ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 9138b2b..203bd18 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -114,6 +114,7 @@ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */

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[U-Boot] [PATCH] Davinci: Table driven pinmux configuration
by Nick Thompson 03 Dec '09

03 Dec '09

Davinci: Table driven pinmux configuration Add code to allow pinmux_config tables to be grouped and configured as a single resource. This removes multiple calls to the pinmux configuration code from board_init and allows pinmuxes to be individually configured and added by data manipulation only. All related #ifdefs can the be removed from board_init code and since the compiler optimises away statics, #ifdefs can be reduced in the data definitions as well. Signed-off-by: Nick Thompson <nick.thompson(a)gefanuc.com> --- Applies to u-boot-ti: board/davinci/common/misc.c | 31 +++++++++++++++++++++++++++++++ board/davinci/common/misc.h | 13 +++++++++++++ 2 files changed, 44 insertions(+), 0 deletions(-) diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 9fab76f..25ca326 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -155,3 +155,34 @@ int davinci_configure_pin_mux(const struct pinmux_config *pins, return 0; } + +/* + * Configure multiple pinmux resources. + * + * Takes an pinmux_resource array of pinmux_config and pin counts: + * + * const struct pinmux_resource pinmuxes[] = { + * PINMUX_ITEM(uart_pins), + * PINMUX_ITEM(i2c_pins), + * }; + * + * The number of items in the array must be passed (ARRAY_SIZE can provide + * this value conveniently). + * + * Each item entry is configured in the defined order. If configuration + * of any item fails, -1 is returned and none of the following items are + * configured. On success, 0 is returned. + */ +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + const int n_items) +{ + int i; + + for (i = 0; i < n_items; i++) { + if (davinci_configure_pin_mux(item[i].pins, + item[i].n_pins) != 0) + return -1; + } + + return 0; +} diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h index f6d8b1b..329c369 100644 --- a/board/davinci/common/misc.h +++ b/board/davinci/common/misc.h @@ -34,8 +34,21 @@ struct pinmux_config { unsigned char field; /* field number */ }; +/* pin table definition */ +struct pinmux_resource { + const struct pinmux_config *pins; + const int n_pins; +}; + +#define PINMUX_ITEM(item) { \ + .pins = item, \ + .n_pins = ARRAY_SIZE(item) \ + } + int dvevm_read_mac_address(uint8_t *buf); void dv_configure_mac_address(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + int n_items); #endif /* __MISC_H */

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[U-Boot] [PATCH v2] ppc: Added macro to test for specific SVR revision
by Kumar Gala 03 Dec '09

03 Dec '09

Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Removed extra whitespace per Wolfgang feedback * Fixed up commit message include/asm-ppc/processor.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f61778f..c6da411 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -992,6 +992,9 @@ #endif #endif +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + /* * SVR_SOC_VER() Version Values */ -- 1.6.0.6

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[U-Boot] [PATCH v2] Remove entirely superfluous preprocessor tests from some cmd_*.c files.
by Robert P. J. Day 02 Dec '09

02 Dec '09

A small number of common/cmd_*.c files contain preprocessor tests that are apparently superfluous since those same tests are used in the Makefile to control the compilation of those files. Those tests are clearly redundant as long as they surround the entirety of the source in those files. Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- revision of earlier patch, dropping change to cmd_license.c since that's already been submitted. there *are* at least a couple more files like this but they'll require slightly different tweaking so i'm doing those separately. diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 0dfa336..1202258 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -27,8 +27,6 @@ #include <common.h> #include <command.h> -#if defined(CONFIG_CMD_CACHE) - static int on_off (const char *); int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -108,5 +106,3 @@ U_BOOT_CMD( "[on, off]\n" " - enable or disable data (writethrough) cache" ); - -#endif diff --git a/common/cmd_mgdisk.c b/common/cmd_mgdisk.c index aadc335..3ba62f6 100644 --- a/common/cmd_mgdisk.c +++ b/common/cmd_mgdisk.c @@ -24,8 +24,6 @@ #include <common.h> #include <command.h> -#if defined (CONFIG_CMD_MG_DISK) - #include <mg_disk.h> int do_mg_disk_cmd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -72,5 +70,3 @@ U_BOOT_CMD( " - sector read : mgd readsec [sector] [to] [counts]\n" " - sector write : mgd writesec [from] [sector] [counts]" ); - -#endif ======================================================================== Robert P. J. Day Waterloo, Ontario, CANADA Linux Consulting, Training and Kernel Pedantry. Web page: http://crashcourse.ca Twitter: http://twitter.com/rpjday ========================================================================

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[U-Boot] [PATCH] ppc: Added macro to test for specific SVR revision
by Kumar Gala 02 Dec '09

02 Dec '09

Various SoC errata are specific to a given revision of silicon this gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-ppc/processor.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f61778f..cda9210 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -992,6 +992,10 @@ #endif #endif +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + + /* * SVR_SOC_VER() Version Values */ -- 1.6.0.6

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