December 2009 - U-Boot

[U-Boot] [PATCH] bdinfo: Don't print IP or MAC addresses on boards without network support
by Stefan Roese 23 Dec '09

23 Dec '09

Signed-off-by: Stefan Roese <sr(a)denx.de> --- common/cmd_bdinfo.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 11c1547..03ed594 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -93,6 +93,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_str ("pevfreq", strmhz(buf, bd->bi_pevfreq)); #endif +#ifdef CONFIG_CMD_NET print_eth(0); #if defined(CONFIG_HAS_ETH1) print_eth(1); @@ -114,6 +115,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed)); #endif printf ("IP addr = %pI4\n", &bd->bi_ip_addr); +#endif /* CONFIG_CMD_NET */ printf ("baudrate = %6ld bps\n", bd->bi_baudrate ); return 0; } @@ -130,8 +132,10 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); +#ifdef CONFIG_CMD_NET print_eth(0); printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif printf ("baudrate = %ld bps\n", bd->bi_baudrate); return 0; @@ -288,8 +292,10 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num("flashsize", (ulong)bd->bi_flashsize); print_num("flashoffset", (ulong)bd->bi_flashoffset); +#ifdef CONFIG_CMD_NET print_eth(0); printf("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif printf("baudrate = %d bps\n", bd->bi_baudrate); return 0; @@ -308,8 +314,10 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); +#ifdef CONFIG_CMD_NET print_eth(0); printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif printf ("baudrate = %d bps\n", bd->bi_baudrate); return 0; -- 1.6.6.rc4

2 1

[U-Boot] about ram test in u-boot
by IaMaPlAyEr 23 Dec '09

23 Dec '09

Hi, maybe this question not greatly related with u-boot. when I read the wiki of u-boot: http://www.denx.de/wiki/view/DULG/UBootCrashAfterRelocation I noticed this: Standard memory tests are not effective in identifying this type of problem because they do not cause stressful cache burst read/write operations. We have a board, the ram works fine before, but recently, we need to change the ram for the lack of the original chip. After I read the datasheet of original chip, I found the parameter tRCD is wrong! In code, tRCD is set to 10ns, but in datasheet, the minimal tRCD is 15ns. I know in u-boot, there is a command name mtest, it is a simple RAM test. it test fine in two tRCD condition. I also try memtester 10 loops, also fine! Could somebody give me some advice to determine which value of tRCD is better? thanks. here is the memtester log: [root@root]# ./memtester 31M 10 memtester version 4.1.2 (32-bit) Copyright (C) 2009 Charles Cazabon. Licensed under the GNU General Public License version 2 (only). pagesize is 4096 pagesizemask is 0xfffff000 want 31MB (32505856 bytes) got 31MB (32505856 bytes), trying mlock ...locked. Loop 1---10: Stuck Address : ok Random Value : ok Compare XOR : ok Compare SUB : ok Compare MUL : ok Compare DIV : ok Compare OR : ok Compare AND : ok Sequential Increment: ok Solid Bits : ok Block Sequential : ok Checkerboard : ok Bit Spread : ok Bit Flip : ok Walking Ones : ok Walking Zeroes : ok -- -- Sincerely, HaveF

2 1

[U-Boot] [PATCH V3 1/3] Initial support for Marvell Orion5x SoC
by Albert Aribaud 23 Dec '09

23 Dec '09

This patch adds support for the Marvell Orion5x SoC. It has no use alone, and must be followed by a patch to add Orion5x support for serial, then support for the ED Mini V2, an Orion5x-based product from LaCie. Signed-off-by: Albert Aribaud <albert.aribaud(a)free.fr> --- V1 of the patch was monolithic V2 contains a number of fixes as a result of the V1 review, and notably: - is split in three patches : orion, serial, edmini; - has been checkpatch'ed, with only 6 errors, in patch 1/3, all 6 errors being false positives. V3 contains yet several fixes as a result of the V2 review, and notably: - removes most of the GPIO and MPP programming support; - adds low level init and removes CONFIG_SKIP_LOW_LEVEL_INIT. cpu/arm926ejs/orion5x/Makefile | 51 ++++++ cpu/arm926ejs/orion5x/cpu.c | 258 ++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 61 +++++++ cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++++++++ include/asm-arm/arch-orion5x/cpu.h | 205 ++++++++++++++++++++++++ include/asm-arm/arch-orion5x/mv88f5182.h | 40 +++++ include/asm-arm/arch-orion5x/orion5x.h | 65 ++++++++ 7 files changed, 861 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile new file mode 100644 index 0000000..5386379 --- /dev/null +++ b/cpu/arm926ejs/orion5x/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) 2009 Albert ARIBAUD <albrt.aribaud(a)free.fr> +# +# Based on original Kirkwood support which is +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = cpu.o +COBJS-y += dram.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c new file mode 100644 index 0000000..deebf24 --- /dev/null +++ b/cpu/arm926ejs/orion5x/cpu.c @@ -0,0 +1,258 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/cache.h> +#include <u-boot/md5.h> +#include <asm/arch/orion5x.h> +#include <hush.h> + +#define BUFLEN 16 + +void reset_cpu(unsigned long ignored) +{ + struct orion5x_cpu_registers *cpureg = + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE; + + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) + ; +} + +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val > 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return 0x0000ffff & j; +} + +/* + * orion5x_config_adr_windows - Configure address Windows + * + * There are 8 address windows supported by Orion5x Soc to addess different + * devices. Each window can be configured for size, BAR and remap addr + * Below configuration is standard for most of the cases + * + * If remap function not used, remap_lo must be set as base + * + * Reference Documentation: + * Mbus-L to Mbus Bridge Registers Configuration. + * (Sec 25.1 and 25.3 of Datasheet) + */ +int orion5x_config_adr_windows(void) +{ + struct orion5x_win_registers *winregs = + (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE; + + /* Window 0: PCIE MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM, + ORION5X_WIN_ENABLE), &winregs[0].ctrl); + writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo); + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi); + + /* Window 1: PCIE IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO, + ORION5X_WIN_ENABLE), &winregs[1].ctrl); + writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo); + writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi); + + /* Window 2: PCI MEM address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM, + ORION5X_WIN_ENABLE), &winregs[2].ctrl); + writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base); + + /* Window 3: PCI IO address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO, + ORION5X_WIN_ENABLE), &winregs[3].ctrl); + writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base); + + /* Window 4: DEV_CS0 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0, + ORION5X_WIN_ENABLE), &winregs[4].ctrl); + writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base); + + /* Window 5: DEV_CS1 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1, + ORION5X_WIN_ENABLE), &winregs[5].ctrl); + writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base); + + /* Window 6: DEV_CS2 address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2, + ORION5X_WIN_ENABLE), &winregs[6].ctrl); + writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base); + + /* Window 7: BOOT Memory address space */ + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM, + ORION5X_WIN_ENABLE), &winregs[7].ctrl); + writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base); + + return 0; +} + +/* + * Orion5x identification is done through PCIE space. + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) +u32 orion5x_device_id(void) +{ + return readl(PCIE_DEV_ID_OFF) >> 16; +} + +u32 orion5x_device_rev(void) +{ + return readl(PCIE_DEV_REV_OFF) & 0xff; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) + +int print_cpuinfo(void) +{ + char dev_str[] = "0x0000"; + char rev_str[] = "0x00"; + char *dev_name = NULL; + char *rev_name = NULL; + + u32 dev = orion5x_device_id(); + u32 rev = orion5x_device_rev(); + + if (dev == MV88F5181_DEV_ID) { + dev_name = "MV88F5181"; + if (rev == MV88F5181_REV_B1) + rev_name = "B1"; + else if (rev == MV88F5181L_REV_A1) { + dev_name = "MV88F5181L"; + rev_name = "A1"; + } else if (rev == MV88F5181L_REV_A0) { + dev_name = "MV88F5181L"; + rev_name = "A0"; + } + } else if (dev == MV88F5182_DEV_ID) { + dev_name = "MV88F5182"; + if (rev == MV88F5182_REV_A2) + rev_name = "A2"; + } else if (dev == MV88F5281_DEV_ID) { + dev_name = "MV88F5281"; + if (rev == MV88F5281_REV_D2) + rev_name = "D2"; + else if (rev == MV88F5281_REV_D1) + rev_name = "D1"; + else if (rev == MV88F5281_REV_D0) + rev_name = "D0"; + } else if (dev == MV88F6183_DEV_ID) { + dev_name = "MV88F6183"; + if (rev == MV88F6183_REV_B0) + rev_name = "B0"; + } + if (dev_name == NULL) { + sprintf(dev_str, "0x%04x", dev); + dev_name = dev_str; + } + if (rev_name == NULL) { + sprintf(rev_str, "0x%02x", rev); + rev_name = rev_str; + } + + printf("SoC: Orion5x %s-%s\n", dev_name, rev_name); + + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + /* Enable and invalidate L2 cache in write through mode */ + invalidate_l2_cache(); + + orion5x_config_adr_windows(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + u32 temp; + + /*CPU streaming & write allocate */ + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 28); /* disable wr alloc */ + writefr_extra_feature_reg(temp); + + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 29); /* streaming disabled */ + writefr_extra_feature_reg(temp); + + /* L2Cache settings */ + temp = readfr_extra_feature_reg(); + /* Disable L2C pre fetch - Set bit 24 */ + temp |= (1 << 24); + /* enable L2C - Set bit 22 */ + temp |= (1 << 22); + writefr_extra_feature_reg(temp); + + icache_enable(); + /* Change reset vector to address 0x0 */ + temp = get_cr(); + set_cr(temp & ~CR_V); + + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c new file mode 100644 index 0000000..ba6dd91 --- /dev/null +++ b/cpu/arm926ejs/orion5x/dram.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <config.h> +#include <asm/arch/orion5x.h> + +#define ORION5X_REG_CPUCS_WIN_BAR(x) (ORION5X_REGISTER(0x1500) + (x * 0x08)) +#define ORION5X_REG_CPUCS_WIN_SZ(x) (ORION5X_REGISTER(0x1504) + (x * 0x08)) +/* + * orion5x_sdram_bar - reads SDRAM Base Address Register + */ +u32 orion5x_sdram_bar(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank)); + return result; +} + +/* + * orion5x_sdram_bs - reads SDRAM Bank size + */ +u32 orion5x_sdram_bs(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + result = 0xff000000 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank)); + result += 0x01000000; + return result; +} diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c new file mode 100644 index 0000000..4ee80cc --- /dev/null +++ b/cpu/arm926ejs/orion5x/timer.c @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/arch/orion5x.h> + +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ + +/* Timer reload and current value registers */ +struct orion5x_tmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct orion5x_tmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct orion5x_tmr_val tmr[2]; + u32 wdt_reload; + u32 wdt_val; +}; + +struct orion5x_tmr_registers *orion5x_tmr_regs = + (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE; + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl) +#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload) +#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val) + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* + * ARM Timer\Watchdog Reload Register + * CNTMR_RELOAD_REG (TRR) + */ +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* + * ARM Timer\Watchdog Register + * CNTMR_VAL_REG (TVRG) + */ +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff + +static inline ulong read_timer(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)) + / (CONFIG_SYS_TCLK / 1000); +} + +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = read_timer(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = read_timer(); + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +static inline ulong uboot_cntr_val(void) +{ + return readl(CNTMR_VAL_REG(UBOOT_CNTR)); +} + +void udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = uboot_cntr_val(); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (uboot_cntr_val() < current) + ; + while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val()) + ; + } else { + while (uboot_cntr_val() > (current - delayticks)) + ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + unsigned int cntmrctrl; + + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + cntmrctrl = readl(CNTMR_CTRL_REG); + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); + writel(cntmrctrl, CNTMR_CTRL_REG); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h new file mode 100644 index 0000000..706c9c0 --- /dev/null +++ b/include/asm-arm/arch-orion5x/cpu.h @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirorion5x_ood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ORION5X_CPU_H +#define _ORION5X_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) + +#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum orion5x_cpu_winen { + ORION5X_WIN_DISABLE, + ORION5X_WIN_ENABLE +}; + +enum orion5x_cpu_target { + ORION5X_TARGET_DRAM = 0, + ORION5X_TARGET_DEVICE = 1, + ORION5X_TARGET_PCI = 3, + ORION5X_TARGET_PCIE = 4, + ORION5X_TARGET_SASRAM = 9 +}; + +enum orion5x_cpu_attrib { + ORION5X_ATTR_DRAM_CS0 = 0x0e, + ORION5X_ATTR_DRAM_CS1 = 0x0d, + ORION5X_ATTR_DRAM_CS2 = 0x0b, + ORION5X_ATTR_DRAM_CS3 = 0x07, + ORION5X_ATTR_PCI_MEM = 0x59, + ORION5X_ATTR_PCI_IO = 0x51, + ORION5X_ATTR_PCIE_MEM = 0x59, + ORION5X_ATTR_PCIE_IO = 0x51, + ORION5X_ATTR_SASRAM = 0x00, + ORION5X_ATTR_DEV_CS0 = 0x1e, + ORION5X_ATTR_DEV_CS1 = 0x1d, + ORION5X_ATTR_DEV_CS2 = 0x1b, + ORION5X_ATTR_BOOTROM = 0x0f +}; + +/* + * Default Device Address MAP BAR values + */ +#define ORION5X_DEFADR_PCIE_MEM 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCIE_IO 0xf0000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000 +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0 +#define ORION5X_DEFSZ_PCIE_IO (64*1024) + +#define ORION5X_DEFADR_PCI_MEM 0x98000000 +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024) + +#define ORION5X_DEFADR_PCI_IO 0xf0100000 +#define ORION5X_DEFSZ_PCI_IO (64*1024) + +#define ORION5X_DEFADR_DEV_CS0 0xfa000000 +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024) + +#define ORION5X_DEFADR_DEV_CS1 0xf8000000 +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024) + +#define ORION5X_DEFADR_DEV_CS2 0xfa800000 +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024) + +#define ORION5X_DEFADR_BOOTROM 0xFFF80000 +#define ORION5X_DEFSZ_BOOTROM (512*1024) + +/* + * PCIE registers are used for SoC device ID and revision + */ +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) + +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +/* + * read feroceon core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * AHB to Mbus Bridge Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + * Note: only windows 0 and 1 have remap capability. + */ +struct orion5x_win_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Source: 88F5182 User Manual, Appendix A, section A.4 + */ +struct orion5x_cpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ +}; + +/* + * GPIO Registers + * Source: 88F5182 User Manual, Appendix A, section A.17 + */ +struct orion5x_gpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 int_cause; + u32 int_mask; + u32 int_level_mask; +}; + +/* + * functions + */ +void reset_cpu(unsigned long ignored); +u32 orion5x_device_id(void); +u32 orion5x_device_rev(void); +unsigned int orion5x_sdram_bar(enum memory_bank bank); +unsigned int orion5x_sdram_bs(enum memory_bank bank); +int orion5x_config_adr_windows(void); +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); +#endif /* __ASSEMBLY__ */ +#endif /* _ORION5X_CPU_H */ diff --git a/include/asm-arm/arch-orion5x/mv88f5182.h b/include/asm-arm/arch-orion5x/mv88f5182.h new file mode 100644 index 0000000..b16b23f --- /dev/null +++ b/include/asm-arm/arch-orion5x/mv88f5182.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood 88F6182 support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Header file for Feroceon CPU core 88F5182 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_88F5182_H +#define _CONFIG_88F5182_H + +/* SOC specific definations */ +#define F88F5182_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_88F5182_H */ diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h new file mode 100644 index 0000000..7b8ed65 --- /dev/null +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud(a)free.fr> + * + * Based on original Kirkwood support which is + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * Header file for Marvell's Orion SoC with Feroceon CPU core. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ORION5X_H +#define _ASM_ARCH_ORION5X_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined(CONFIG_FEROCEON) +#include <asm/arch/cpu.h> + +/* SOC specific definations */ +#define ORION5X_REGISTER(x) (ORION5X_REGS_PHY_BASE + x) + +/* Documented registers */ +#define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000)) +#define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000)) +#define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100)) +#define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000)) +#define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100)) +#define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000)) +#define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100)) +#define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300)) +#define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000)) +#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000)) +#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000)) +#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000)) +#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000)) + +#if defined(CONFIG_88F5182) +#include <asm/arch/mv88f5182.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_FEROCEON */ +#endif /* _ASM_ARCH_ORION5X_H */ -- 1.6.4.4

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[U-Boot] [PATCH V2 0/3] Support for Marvell Orion5x SoC and LaCie ED Mini V2 board
by Albert Aribaud 23 Dec '09

23 Dec '09

This series of patches is the second attempt at introducing support for the Marvell Orion5x SoC and the LaCie ED Mini V2 board. Initial support includes only serial port and Flash. Additional support will be added as Marvell devices (e.g. egiga) are made common to kirkwood and orion5x. All comments to the first attempt have been taken into account. The Linux checkpatch.pl script has been run on all three patches. The first patch has six errors and zero warnings, and all errors are false positives triggered by colons in 'asm volatile' statements. The second and third patches have zero errors and zero warnings. Albert Aribaud (3): Initial support for Marvell Orion5x SoC Add Orion5x support to 16550 serial device driver Add support for the LaCie ED Mini V2 board MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/LaCie/edminiv2/Makefile | 54 +++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 134 +++++++++++++ board/LaCie/edminiv2/edminiv2.h | 43 ++++ cpu/arm926ejs/orion5x/Makefile | 52 +++++ cpu/arm926ejs/orion5x/cpu.c | 332 ++++++++++++++++++++++++++++++++ cpu/arm926ejs/orion5x/dram.c | 61 ++++++ cpu/arm926ejs/orion5x/mpp.c | 89 +++++++++ cpu/arm926ejs/orion5x/timer.c | 175 +++++++++++++++++ drivers/serial/serial.c | 3 + include/asm-arm/arch-orion5x/88f5182.h | 40 ++++ include/asm-arm/arch-orion5x/cpu.h | 213 ++++++++++++++++++++ include/asm-arm/arch-orion5x/gpio.h | 52 +++++ include/asm-arm/arch-orion5x/mpp.h | 122 ++++++++++++ include/asm-arm/arch-orion5x/orion5x.h | 67 +++++++ include/configs/edminiv2.h | 143 ++++++++++++++ 19 files changed, 1615 insertions(+), 0 deletions(-) create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 board/LaCie/edminiv2/edminiv2.h create mode 100644 cpu/arm926ejs/orion5x/Makefile create mode 100644 cpu/arm926ejs/orion5x/cpu.c create mode 100644 cpu/arm926ejs/orion5x/dram.c create mode 100644 cpu/arm926ejs/orion5x/mpp.c create mode 100644 cpu/arm926ejs/orion5x/timer.c create mode 100644 include/asm-arm/arch-orion5x/88f5182.h create mode 100644 include/asm-arm/arch-orion5x/cpu.h create mode 100644 include/asm-arm/arch-orion5x/gpio.h create mode 100644 include/asm-arm/arch-orion5x/mpp.h create mode 100644 include/asm-arm/arch-orion5x/orion5x.h create mode 100644 include/configs/edminiv2.h

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[U-Boot] [PATCH] ppc: Don't use getenv_IPaddr() systems without network support
by Stefan Roese 23 Dec '09

23 Dec '09

This patch disables the usage of getenv_IPaddr() in lib_ppc/board.c on systems that don't have network support enabled. This fixes the following compilation problem: ./MAKEALL DP405 Configuring for DP405 board... lib_ppc/libppc.a(board.o): In function `board_init_r': /home/stefan/git/u-boot/u-boot/lib_ppc/board.c:858: undefined reference to `getenv_IPaddr' Signed-off-by: Stefan Roese <sr(a)denx.de> --- lib_ppc/board.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index dd22f99..c1fbaa5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -852,10 +852,10 @@ void board_init_r (gd_t *id, ulong dest_addr) #ifdef CONFIG_HAS_ETH5 eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); #endif -#endif /* CONFIG_CMD_NET */ /* IP Address */ bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); +#endif /* CONFIG_CMD_NET */ WATCHDOG_RESET (); -- 1.6.6.rc4

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[U-Boot] [PATCH 1/5] usb: musb: make sure the register layout is packed
by Mike Frysinger 22 Dec '09

22 Dec '09

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/usb/musb/musb_core.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index f9da3f0..5e01b98 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -97,7 +97,7 @@ struct musb_regs { u8 rxhubaddr; u8 rxhubport; } tar[16]; -} __attribute__((aligned(32))); +} __attribute__((packed, aligned(32))); /* * MUSB Register bits -- 1.6.5.5

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[U-Boot] BUG_ON() uses macro unlikely(), which isn't defined
by Matthias Kaehlcke 22 Dec '09

22 Dec '09

include/common.h defines the BUG_ON macro: #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) this macro isn't defined in common.h or its includes i'd submit a patch to fix this, but i wonder what kind of fix is preferred: a) eliminate the use of 'unlikely' in BUG_ON b) define likely() and unlikely() in common.h c) define likely() and unlikely() elsewhere d) ? best regards -- Matthias Kaehlcke Embedded Linux Developer Barcelona C treats you like a consenting adult. Pascal treats you like a naughty child. Ada treats you like a criminal (Bruce Powel Douglass) .''`. using free software / Debian GNU/Linux | http://debian.org : :' : `. `'` gpg --keyserver pgp.mit.edu --recv-keys 47D8E5D4 `-

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[U-Boot] [PATCH 0/4 v7] DA8xx: USB support
by Ajay Kumar Gupta 22 Dec '09

22 Dec '09

Hi, These patch set have been refreshed and created against mainline master branch. Changes from v6: Added missing drivers/usb/musb/da8xx.c/h files. Regards, Ajay Ajay Kumar Gupta (4): DA830: Add pinmux for USB0_DRVVBUS DA8xx: Add GPIO register definitions DA8xx: Add MUSB host support DA830: Add usb config board/davinci/da830evm/da830evm.c | 8 ++ drivers/usb/musb/Makefile | 1 + drivers/usb/musb/da8xx.c | 139 ++++++++++++++++++++++++++++++ drivers/usb/musb/da8xx.h | 103 ++++++++++++++++++++++ include/asm-arm/arch-davinci/gpio_defs.h | 14 +++ include/configs/da830evm.h | 38 +++++++- include/usb.h | 2 +- 7 files changed, 299 insertions(+), 6 deletions(-) create mode 100644 drivers/usb/musb/da8xx.c create mode 100644 drivers/usb/musb/da8xx.h

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[U-Boot] [PATCH] ppc/p4080: Add Corenet Platform Cache (CPC) registers
by Kumar Gala 22 Dec '09

22 Dec '09

From: Becky Bruce <beckyb(a)kernel.crashing.org> Signed-off-by: Becky Bruce <beckyb(a)kernel.crashing.org> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-ppc/immap_85xx.h | 74 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 74 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 43b3a2c..176a381 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1562,6 +1562,77 @@ typedef struct par_io { u8 res[8]; } par_io_t; +#ifdef CONFIG_SYS_FSL_CPC +/* + * Define a single offset that is the start of all the CPC register + * blocks - if there is more than one CPC, we expect these to be + * contiguous 4k regions + */ + +typedef struct cpc_corenet { + u32 cpccsr0; /* Config/status reg */ +#define CPC_CSR0_CE 0x80000000 /* Cache Enable */ +#define CPC_CSR0_PE 0x40000000 /* Enable ECC */ +#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ +#define CPC_CSR0_WT 0x00080000 /* Write-through mode */ +#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ +#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ + u32 res1; + u32 cpccfg0; /* Configuration register */ +#define CPC_CFG0_SZ_MASK 0x00003fff +#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) +#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) +#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) + u32 res2; + u32 cpcewcr0; /* External Write reg 0 */ + u32 cpcewabr0; /* External write base reg 0 */ + u32 res3[2]; + u32 cpcewcr1; /* External Write reg 1 */ + u32 cpcewabr1; /* External write base reg 1 */ + u32 res4[54]; + u32 cpcsrcr1; /* SRAM control reg 1 */ +#define CPC_SRCR1_SRBARU_MASK 0x0000ffff +#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ + & CPC_SRCR1_SRBARU_MASK) + u32 cpcsrcr0; /* SRAM control reg 0 */ +#define CPC_SRCR0_SRBARL_MASK 0xffff8000 +#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) +#define CPC_SRCR0_INTLVEN 0x00000100 +#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 +#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 +#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 +#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 +#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 +#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a +#define CPC_SRCR0_SRAMEN 0x00000001 + u32 res5[62]; + struct { + u32 id; /* partition ID */ + u32 res; + u32 alloc; /* partition allocation */ + u32 way; /* partition way */ + } partition_regs[16]; + u32 res6[704]; + u32 cpcerrinjhi; /* Error injection high */ + u32 cpcerrinjlo; /* Error injection lo */ + u32 cpcerrinjctl; /* Error injection control */ + u32 res7[5]; + u32 cpccaptdatahi; /* capture data high */ + u32 cpccaptdatalo; /* capture data low */ + u32 cpcaptecc; /* capture ECC */ + u32 res8[5]; + u32 cpcerrdet; /* error detect */ + u32 cpcerrdis; /* error disable */ +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ + u32 cpcerrinten; /* errir interrupt enable */ + u32 cpcerrattr; /* error attribute */ + u32 cpcerreaddr; /* error extended address */ + u32 cpcerraddr; /* error address */ + u32 cpcerrctl; /* error control */ + u32 res9[105]; /* pad out to 4k */ +} cpc_corenet_t; +#endif /* CONFIG_SYS_FSL_CPC */ + /* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { @@ -1937,6 +2008,7 @@ enum { #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 @@ -1974,6 +2046,8 @@ enum { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_CPC_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ -- 1.6.0.6

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