January 2009 - U-Boot

Re: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals andmodules enable functions.
by Hugo Villeneuve 17 Feb '09

17 Feb '09

> From: u-boot-bounces(a)lists.denx.de on behalf of Hugo Villeneuve > Sent: Fri 11/21/2008 2:35 PM > To: u-boot(a)lists.denx.de > Subject: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals > andmodules enable functions. > > Taken all the duplicated code for enabling common modules and apply > software workarounds from the board specific code into common > functions. Also added comments explaining the workarounds > (from TI errata documents) and replaced some numerical bit numbers > with more meaningful defines. > > Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> > --- > board/davinci/common/psc.c | 65 ++++++++++++++++++++++++++ > +++++++++ board/davinci/common/psc.h | 3 ++ > board/davinci/dvevm/dvevm.c | 35 +++++-------------- > board/davinci/schmoogie/schmoogie.c | 37 +++++-------------- > board/davinci/sffsdr/sffsdr.c | 31 +++-------------- > board/davinci/sonata/sonata.c | 35 +++++-------------- > 6 files changed, 101 insertions(+), 105 deletions(-) I sent this patch two months ago but I didn´t receive feedback... Hugo V. > diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c > index d538d51..28e2a4b 100644 > --- a/board/davinci/common/psc.c > +++ b/board/davinci/common/psc.c > @@ -26,6 +26,14 @@ > #include <common.h> > #include <asm/arch/hardware.h> > > +#define PINMUX0_EMACEN (1 << 31) > +#define PINMUX0_AECS5 (1 << 11) > +#define PINMUX0_AECS4 (1 << 10) > + > +#define PINMUX1_I2C (1 << 7) > +#define PINMUX1_UART1 (1 << 1) > +#define PINMUX1_UART0 (1 << 0) > + > /* > * The DM6446 includes two separate power domains: "Always On" and > "DSP". The > * "Always On" power domain is always on when the chip is on. The > "Always On" @@ -115,3 +123,60 @@ void dsp_on(void) > REG(PSC_GBLCTL) &= ~0x1f; > } > #endif /* CONFIG_SYS_USE_DSPLINK */ > + > +void davinci_enable_uart0(void) > +{ > + lpsc_on(DAVINCI_LPSC_UART0); > + > + /* Bringup UART0 out of reset */ > + REG(UART0_PWREMU_MGMT) = 0x0000e003; > + > + /* Enable UART0 MUX lines */ > + REG(PINMUX1) |= PINMUX1_UART0; > +} > + > +#ifdef CONFIG_DRIVER_TI_EMAC > +void davinci_enable_emac(void) > +{ > + lpsc_on(DAVINCI_LPSC_EMAC); > + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); > + lpsc_on(DAVINCI_LPSC_MDIO); > + > + /* Enable GIO3.3V cells used for EMAC */ > + REG(VDD3P3V_PWDN) = 0; > + > + /* Enable EMAC. */ > + REG(PINMUX0) |= PINMUX0_EMACEN; > +} > +#endif > + > +void davinci_enable_i2c(void) > +{ > + lpsc_on(DAVINCI_LPSC_I2C); > + > + /* Enable I2C pin Mux */ > + REG(PINMUX1) |= PINMUX1_I2C; > +} > + > +void davinci_errata_workarounds(void) > +{ > + /* > + * Workaround for TMS320DM6446 errata 1.3.22: > + * PSC: PTSTAT Register Does Not Clear After Warm/Maximum > Reset > + * Revision(s) Affected: 1.3 and earlier > + */ > + REG(PSC_SILVER_BULLET) = 0; > + > + /* > + * Set the PR_OLD_COUNT bits in the Bus Burst Priority > Register (PBBPR) > + * as suggested in TMS320DM6446 errata 2.1.2: > + * > + * On DM6446 Silicon Revision 2.1 and earlier, under certain > conditions > + * low priority modules can occupy the bus and prevent high > priority > + * modules like the VPSS from getting the required DDR2 > throughput. > + * A hex value of 0x20 should provide a good ARM (cache > enabled) > + * performance and still allow good utilization by the VPSS > or other > + * modules. > + */ > + REG(VBPR) = 0x20; > +} > diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h > index 6ab2575..b18a185 100644 > --- a/board/davinci/common/psc.h > +++ b/board/davinci/common/psc.h > @@ -24,5 +24,8 @@ > > void lpsc_on(unsigned int id); > void dsp_on(void); > +void davinci_enable_uart0(void); > +void davinci_enable_emac(void); > +void davinci_enable_i2c(void); > > #endif /* __PSC_H */ > diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c > index abf60b3..f740124 100644 > --- a/board/davinci/dvevm/dvevm.c > +++ b/board/davinci/dvevm/dvevm.c > @@ -27,7 +27,6 @@ > #include <common.h> > #include <i2c.h> > #include <asm/arch/hardware.h> > -#include <asm/arch/emac_defs.h> > #include "../common/psc.h" > #include "../common/misc.h" > > @@ -41,16 +40,13 @@ int board_init(void) > /* address of boot parameters */ > gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; > > - /* Workaround for TMS320DM6446 errata 1.3.22 */ > - REG(PSC_SILVER_BULLET) = 0; > + /* Configure AEMIF pins (although this should be configured > at boot time > + * with pull-up/pull-down resistors) */ > + REG(PINMUX0) = 0x00000c1f; > + > + davinci_errata_workarounds(); > > /* Power on required peripherals */ > - lpsc_on(DAVINCI_LPSC_EMAC); > - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); > - lpsc_on(DAVINCI_LPSC_MDIO); > - lpsc_on(DAVINCI_LPSC_I2C); > - lpsc_on(DAVINCI_LPSC_UART0); > - lpsc_on(DAVINCI_LPSC_TIMER1); > lpsc_on(DAVINCI_LPSC_GPIO); > > #if !defined(CONFIG_SYS_USE_DSPLINK) > @@ -58,24 +54,11 @@ int board_init(void) > dsp_on(); > #endif /* CONFIG_SYS_USE_DSPLINK */ > > - /* Bringup UART0 out of reset */ > - REG(UART0_PWREMU_MGMT) = 0x0000e003; > - > - /* Enable GIO3.3V cells used for EMAC */ > - REG(VDD3P3V_PWDN) = 0; > - > - /* Enable UART0 MUX lines */ > - REG(PINMUX1) |= 1; > - > - /* Enable EMAC and AEMIF pins */ > - REG(PINMUX0) = 0x80000c1f; > - > - /* Enable I2C pin Mux */ > - REG(PINMUX1) |= (1 << 7); > - > - /* Set the Bus Priority Register to appropriate value */ > - REG(VBPR) = 0x20; > + davinci_enable_uart0(); > + davinci_enable_emac(); > + davinci_enable_i2c(); > > + lpsc_on(DAVINCI_LPSC_TIMER1); > timer_init(); > > return(0); > diff --git a/board/davinci/schmoogie/schmoogie.c > b/board/davinci/schmoogie/schmoogie.c index 3504a2e..433769a 100644 > --- a/board/davinci/schmoogie/schmoogie.c > +++ b/board/davinci/schmoogie/schmoogie.c > @@ -27,7 +27,6 @@ > #include <common.h> > #include <i2c.h> > #include <asm/arch/hardware.h> > -#include <asm/arch/emac_defs.h> > #include "../common/psc.h" > #include "../common/misc.h" > > @@ -41,16 +40,13 @@ int board_init(void) > /* address of boot parameters */ > gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; > > - /* Workaround for TMS320DM6446 errata 1.3.22 */ > - REG(PSC_SILVER_BULLET) = 0; > + /* Configure AEMIF pins (although this should be configured > at boot time > + * with pull-up/pull-down resistors) */ > + REG(PINMUX0) = 0x00000c1f; > + > + davinci_errata_workarounds(); > > /* Power on required peripherals */ > - lpsc_on(DAVINCI_LPSC_EMAC); > - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); > - lpsc_on(DAVINCI_LPSC_MDIO); > - lpsc_on(DAVINCI_LPSC_I2C); > - lpsc_on(DAVINCI_LPSC_UART0); > - lpsc_on(DAVINCI_LPSC_TIMER1); > lpsc_on(DAVINCI_LPSC_GPIO); > > #if !defined(CONFIG_SYS_USE_DSPLINK) > @@ -58,24 +54,11 @@ int board_init(void) > dsp_on(); > #endif /* CONFIG_SYS_USE_DSPLINK */ > > - /* Bringup UART0 out of reset */ > - REG(UART0_PWREMU_MGMT) = 0x0000e003; > - > - /* Enable GIO3.3V cells used for EMAC */ > - REG(VDD3P3V_PWDN) = 0; > - > - /* Enable UART0 MUX lines */ > - REG(PINMUX1) |= 1; > - > - /* Enable EMAC and AEMIF pins */ > - REG(PINMUX0) = 0x80000c1f; > - > - /* Enable I2C pin Mux */ > - REG(PINMUX1) |= (1 << 7); > - > - /* Set the Bus Priority Register to appropriate value */ > - REG(VBPR) = 0x20; > + davinci_enable_uart0(); > + davinci_enable_emac(); > + davinci_enable_i2c(); > > + lpsc_on(DAVINCI_LPSC_TIMER1); > timer_init(); > > return(0); > @@ -87,7 +70,7 @@ int misc_init_r(void) > int i = 0; > > /* Set serial number from UID chip */ > - u_int8_t crc_tbl[256] = { > + const u_int8_t crc_tbl[256] = { > 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, > 0x83, 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41, > 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, > 0x1e, diff --git a/board/davinci/sffsdr/sffsdr.c > b/board/davinci/sffsdr/sffsdr.c index 9296d7b..e76f86d 100644 > --- a/board/davinci/sffsdr/sffsdr.c > +++ b/board/davinci/sffsdr/sffsdr.c > @@ -30,7 +30,6 @@ > #include <common.h> > #include <i2c.h> > #include <asm/arch/hardware.h> > -#include <asm/arch/emac_defs.h> > #include "../common/psc.h" > #include "../common/misc.h" > > @@ -51,16 +50,9 @@ int board_init(void) > /* address of boot parameters */ > gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; > > - /* Workaround for TMS320DM6446 errata 1.3.22 */ > - REG(PSC_SILVER_BULLET) = 0; > + davinci_errata_workarounds(); > > /* Power on required peripherals */ > - lpsc_on(DAVINCI_LPSC_EMAC); > - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); > - lpsc_on(DAVINCI_LPSC_MDIO); > - lpsc_on(DAVINCI_LPSC_I2C); > - lpsc_on(DAVINCI_LPSC_UART0); > - lpsc_on(DAVINCI_LPSC_TIMER1); > lpsc_on(DAVINCI_LPSC_GPIO); > > #if !defined(CONFIG_SYS_USE_DSPLINK) > @@ -68,24 +60,11 @@ int board_init(void) > dsp_on(); > #endif /* CONFIG_SYS_USE_DSPLINK */ > > - /* Bringup UART0 out of reset */ > - REG(UART0_PWREMU_MGMT) = 0x0000e003; > - > - /* Enable GIO3.3V cells used for EMAC */ > - REG(VDD3P3V_PWDN) = 0; > - > - /* Enable UART0 MUX lines */ > - REG(PINMUX1) |= 1; > - > - /* Enable EMAC and AEMIF pins */ > - REG(PINMUX0) = 0x80000c1f; > - > - /* Enable I2C pin Mux */ > - REG(PINMUX1) |= (1 << 7); > - > - /* Set the Bus Priority Register to appropriate value */ > - REG(VBPR) = 0x20; > + davinci_enable_uart0(); > + davinci_enable_emac(); > + davinci_enable_i2c(); > > + lpsc_on(DAVINCI_LPSC_TIMER1); > timer_init(); > > return(0); > diff --git a/board/davinci/sonata/sonata.c > b/board/davinci/sonata/sonata.c index 6de9356..d56b443 100644 > --- a/board/davinci/sonata/sonata.c > +++ b/board/davinci/sonata/sonata.c > @@ -26,7 +26,6 @@ > > #include <common.h> > #include <asm/arch/hardware.h> > -#include <asm/arch/emac_defs.h> > #include "../common/psc.h" > #include "../common/misc.h" > > @@ -40,16 +39,13 @@ int board_init(void) > /* address of boot parameters */ > gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; > > - /* Workaround for TMS320DM6446 errata 1.3.22 */ > - REG(PSC_SILVER_BULLET) = 0; > + /* Configure AEMIF pins (although this should be configured > at boot time > + * with pull-up/pull-down resistors) */ > + REG(PINMUX0) = 0x00000c1f; > + > + davinci_errata_workarounds(); > > /* Power on required peripherals */ > - lpsc_on(DAVINCI_LPSC_EMAC); > - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); > - lpsc_on(DAVINCI_LPSC_MDIO); > - lpsc_on(DAVINCI_LPSC_I2C); > - lpsc_on(DAVINCI_LPSC_UART0); > - lpsc_on(DAVINCI_LPSC_TIMER1); > lpsc_on(DAVINCI_LPSC_GPIO); > > #if !defined(CONFIG_SYS_USE_DSPLINK) > @@ -57,24 +53,11 @@ int board_init(void) > dsp_on(); > #endif /* CONFIG_SYS_USE_DSPLINK */ > > - /* Bringup UART0 out of reset */ > - REG(UART0_PWREMU_MGMT) = 0x0000e003; > - > - /* Enable GIO3.3V cells used for EMAC */ > - REG(VDD3P3V_PWDN) = 0; > - > - /* Enable UART0 MUX lines */ > - REG(PINMUX1) |= 1; > - > - /* Enable EMAC and AEMIF pins */ > - REG(PINMUX0) = 0x80000c1f; > - > - /* Enable I2C pin Mux */ > - REG(PINMUX1) |= (1 << 7); > - > - /* Set the Bus Priority Register to appropriate value */ > - REG(VBPR) = 0x20; > + davinci_enable_uart0(); > + davinci_enable_emac(); > + davinci_enable_i2c(); > > + lpsc_on(DAVINCI_LPSC_TIMER1); > timer_init(); > > return(0); > -- > 1.5.4.5 > > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > > --------------- Hugo Villeneuve www.hugovil.com ---------------

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[U-Boot] [PATCH] Create configuration option for restricted ns16550 functions
by Ron Madrid 12 Feb '09

12 Feb '09

This patch will create a configuration option for a minimum configuration for the ns16550 serial driver at drivers/serial/ns16550.c which will exclude all functions with exception of NS16550_putc and NS16550_init. This will be used primarily to save space and remove unused code from builds in which space is limited. Signed-off-by: Ron Madrid <ron_madrid(a)sbcglobal.net> --- drivers/serial/ns16550.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93c2243..3e2a3c2 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -39,6 +39,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) #endif } +#ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit (NS16550_t com_port, int baud_divisor) { com_port->ier = 0x00; @@ -53,6 +54,7 @@ void NS16550_reinit (NS16550_t com_port, int baud_divisor) com_port->dlm = (baud_divisor >> 8) & 0xff; com_port->lcr = LCRVAL; } +#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ void NS16550_putc (NS16550_t com_port, char c) { @@ -60,6 +62,7 @@ void NS16550_putc (NS16550_t com_port, char c) com_port->thr = c; } +#ifndef CONFIG_NS16550_MIN_FUNCTIONS char NS16550_getc (NS16550_t com_port) { while ((com_port->lsr & LSR_DR) == 0) { @@ -75,5 +78,5 @@ int NS16550_tstc (NS16550_t com_port) { return ((com_port->lsr & LSR_DR) != 0); } - +#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ #endif -- 1.5.5.1

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[U-Boot] [PATCH 00/27] Blackfin updates for 2009.03 (part 2)
by Mike Frysinger 12 Feb '09

12 Feb '09

A few more simple bug fixes, but now we get some fun stuff too: - major cleanup of the Blackfin on-chip MAC driver - new driver for Blackfin on-chip NAND controller - new driver for Blackfin on-chip ATAPI controller - new driver for Blackfin on-chip SDIO controller - improve cache performance - improve dma memcpy performance Cliff Cai (1): Blackfin: add driver for on-chip MMC/SD controller Mike Frysinger (25): Blackfin: bfin_mac: force board_get_enetaddr() usage Blackfin: bfin_mac: set MDCDIV based on SCLK Blackfin: bfin_mac: cleanup MII/PHY functions Blackfin: bfin_mac: respect CONFIG_PHY_{ADDR,CLOCK_FREQ} Blackfin: bfin_mac: use common debug() Blackfin: bfin_mac: convert CONFIG_BFIN_MAC_RMII to CONFIG_RMII Blackfin: bfin_mac: cleanup pointer/casts for aliasing issues Blackfin: only build post code when CONFIG_POST Blackfin: add driver for on-chip SPI controller Blackfin: dont check baud if it wont actually get used Blackfin: enable --gc-sections Blackfin: cache core/system clock values Blackfin: setup bi_enetaddr for single nets Blackfin: rewrite cache handling functions Blackfin: dma_memcpy(): fix random failures Blackfin: only flag L1 instruction for DMA memcpy Blackfin: use 8/16/32 bit transfer widths in dma_memcpy() Blackfin: fix up EBIU defines Blackfin: build with -mno-fdpic Blackfin: add driver for on-chip NAND controller Blackfin: add port I bits Blackfin: update asm-blackfin/posix_types.h to latest Linux version Blackfin: set default CONFIG_ENV_SPI_CS based on bootrom Blackfin: output booting source when booting Blackfin: add port muxing for BF51x SPI Sonic Zhang (1): Blackfin: add driver for on-chip ATAPI controller blackfin_config.mk | 5 +- board/bf537-stamp/spi_flash.c | 20 +- cpu/blackfin/Makefile | 1 + cpu/blackfin/cache.S | 118 ++- cpu/blackfin/initcode.c | 6 +- drivers/block/Makefile | 1 + drivers/block/pata_bfin.c | 1201 ++++++++++++++++++++++++++ drivers/block/pata_bfin.h | 173 ++++ drivers/mmc/Makefile | 1 + drivers/mmc/bfin_sdh.c | 546 ++++++++++++ drivers/mmc/bfin_sdh.h | 59 ++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/bfin_nand.c | 376 ++++++++ drivers/net/bfin_mac.c | 404 +++++----- drivers/net/bfin_mac.h | 31 +- drivers/spi/Makefile | 1 + drivers/spi/bfin_spi.c | 343 ++++++++ include/asm-blackfin/blackfin-config-post.h | 5 + include/asm-blackfin/blackfin-config-pre.h | 22 + include/asm-blackfin/blackfin_local.h | 20 +- include/asm-blackfin/mach-bf548/ports.h | 20 +- include/asm-blackfin/mach-common/bits/ebiu.h | 4 +- include/asm-blackfin/mach-common/bits/pata.h | 220 +++++ include/asm-blackfin/mach-common/bits/sdh.h | 122 +++ include/asm-blackfin/mmc.h | 1 + include/asm-blackfin/posix_types.h | 20 +- include/common.h | 2 +- lib_blackfin/Makefile | 4 +- lib_blackfin/board.c | 92 +-- lib_blackfin/cache.c | 18 +- lib_blackfin/clocks.c | 77 ++ lib_blackfin/post.c | 4 - lib_blackfin/string.c | 38 +- lib_blackfin/tests.c | 3 - 34 files changed, 3545 insertions(+), 414 deletions(-) create mode 100644 drivers/block/pata_bfin.c create mode 100644 drivers/block/pata_bfin.h create mode 100644 drivers/mmc/bfin_sdh.c create mode 100644 drivers/mmc/bfin_sdh.h create mode 100644 drivers/mtd/nand/bfin_nand.c create mode 100644 drivers/spi/bfin_spi.c create mode 100644 include/asm-blackfin/mach-common/bits/pata.h create mode 100644 include/asm-blackfin/mach-common/bits/sdh.h create mode 100644 include/asm-blackfin/mmc.h create mode 100644 lib_blackfin/clocks.c

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[U-Boot] [PATCH 00/40] Blackfin updates for 2009.03
by Mike Frysinger 12 Feb '09

12 Feb '09

Nothing terribly interesting here. Normal smatterings of bug fixes and minor updates as we fold the external Blackfin fork back into mainline. Everything can be found in the "next" branch of the Blackfin git tree: git://www.denx.de/git/u-boot-blackfin.git next Mike Frysinger (40): Blackfin: add defines to describe active bootrom behavior Blackfin: add bit defines for DDR parts Blackfin: convert CMD_LINE_ADDR to CONFIG_LINUX_CMDLINE_{ADDR,SIZE} Blackfin: set more sane default board config values Blackfin: rename bootm.c to boot.c Blackfin: abort dma_memcpy() for L1 scratchpad Blackfin: split cache handling out of dma_memcpy() Blackfin: minimize time cache is turned off when replacing cplb entries Blackfin: pass --bmode/--initcode when creating ldr Blackfin: dont generate ldrs with --force Blackfin: fix dcache handling when doing dma memcpy's Blackfin: bfin_mac: update port muxing Blackfin: do not init i2c in Blackfin board init Blackfin: implement general support for CONFIG_STATUS_LED Blackfin: respect/check CONFIG_SYS_GBL_DATA_SIZE Blackfin: respect CONFIG_SYS_MONITOR_LEN for default flash protection Blackfin: overhaul i2c driver Blackfin: bf533-ezkit: shuffle flash defines a little Blackfin: drop dead/wrong debug code in initdram() Blackfin: bf537-stamp nand: fix more style errors in previous commit Blackfin: tighten up post memory coding style Blackfin: resurrect BF533-STAMP video splash driver Blackfin: punt unused BF533-STAMP definitions Blackfin: set default boot SPI CS for BF538/BF539 Blackfin: use common memcpy routine during init Blackfin: respect CONFIG_CLKIN_HALF Blackfin: add portmuxing for UARTs on the BF51x Blackfin: just set SP register directly during init Blackfin: clarify relocation comment during init Blackfin: pass RETX to Linux Blackfin: handle new anomalies with reset Blackfin: support console-over-JTAG Blackfin: allow serial console to be disabled Blackfin: update on-chip ROM API Blackfin: implement real write support for OTP Blackfin: bootldr: implement BF53x/BF56x LDR loader smc91111_eeprom: move board-specific init into SMC91111_EEPROM_INIT() Blackfin: bf533-stamp: rewrite resource swap logic Blackfin: convert old boards to use COBJS-y Makefile style Blackfin: fixup misc warnings such as printf's and missing casts Makefile | 2 +- blackfin_config.mk | 4 + board/bf533-ezkit/Makefile | 8 +- board/bf533-ezkit/bf533-ezkit.c | 23 +- board/bf533-ezkit/flash-defines.h | 4 +- board/bf533-ezkit/flash.c | 10 +- board/bf533-stamp/Makefile | 12 +- board/bf533-stamp/bf533-stamp.c | 50 +-- board/bf533-stamp/bf533-stamp.h | 3 - board/bf533-stamp/video.c | 167 +++++++++ board/bf533-stamp/video.h | 25 ++ board/bf537-stamp/Makefile | 10 +- board/bf537-stamp/bf537-stamp.c | 14 +- board/bf537-stamp/nand.c | 9 +- board/bf537-stamp/post-memory.c | 23 +- board/bf537-stamp/spi_flash.c | 8 +- board/bf561-ezkit/Makefile | 8 +- board/bf561-ezkit/bf561-ezkit.c | 14 +- common/cmd_bootldr.c | 135 +++++++- common/cmd_cplbinfo.c | 4 +- common/cmd_otp.c | 163 +++++++--- common/devices.c | 3 + cpu/blackfin/Makefile | 9 +- cpu/blackfin/cache.S | 4 +- cpu/blackfin/cpu.c | 6 + cpu/blackfin/i2c.c | 428 ----------------------- cpu/blackfin/initcode.c | 2 +- cpu/blackfin/jtag-console.c | 125 +++++++ cpu/blackfin/reset.c | 20 +- cpu/blackfin/serial.c | 4 + cpu/blackfin/serial.h | 15 +- cpu/blackfin/start.S | 41 +-- cpu/blackfin/traps.c | 52 +-- drivers/i2c/Makefile | 1 + drivers/i2c/bfin-twi_i2c.c | 285 +++++++++++++++ drivers/net/bfin_mac.c | 47 ++- examples/smc91111_eeprom.c | 15 +- include/asm-blackfin/blackfin-config-post.h | 84 ++++- include/asm-blackfin/blackfin_local.h | 2 +- include/asm-blackfin/mach-common/bits/bootrom.h | 72 +++-- include/asm-blackfin/mach-common/bits/ebiu.h | 21 +- include/asm-blackfin/mach-common/bits/otp.h | 21 +- include/configs/bf533-ezkit.h | 2 +- include/configs/bf533-stamp.h | 2 +- include/configs/bf537-stamp.h | 43 +-- include/devices.h | 3 + include/status_led.h | 3 + lib_blackfin/Makefile | 2 +- lib_blackfin/board.c | 37 +- lib_blackfin/boot.c | 63 ++++ lib_blackfin/bootm.c | 56 --- lib_blackfin/string.c | 45 ++- 52 files changed, 1326 insertions(+), 883 deletions(-) create mode 100644 board/bf533-stamp/video.c create mode 100644 board/bf533-stamp/video.h delete mode 100644 cpu/blackfin/i2c.c create mode 100644 cpu/blackfin/jtag-console.c create mode 100644 drivers/i2c/bfin-twi_i2c.c create mode 100644 lib_blackfin/boot.c delete mode 100644 lib_blackfin/bootm.c

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[U-Boot] [PATCH]V3 NAND_SPL support for phycore imx31
by Maxim Artamonov 11 Feb '09

11 Feb '09

V3 NAND_SPL support for phycore imx31 This patch is applied on U-Boot v2008.10 release. Changelog: * Added infinitive loop for ecc-error cases; * Correct to code-style; * Was changed mx31_nand_data_output function for support 2-k NAND page chips (Magnus Lilja proposal); * Was changed name of CFG_NAND_PAGE_COUNT by CFG_NAND_PAGES_PER_BLOCK; > V2 NAND_SPL support for phycore imx31 > > Changelog: > > * Added bad block verify & skip; > * Correct to code-style; > * Added few comments; >> V1 nand booting support (SPL) for phyCORE-i.MX31 >> >> This patch allows Phytec phyCORE-i.MX31 based >> system to boot from embed NAND-flash memory. >> It not add support for NAND cmd and/or driver >> for U-BOOT, it is only SPL for U-BOOT. For NAND >> support in U-BOOT I give refer to Magnus Lilja's >> aug/2008 patch series for PDK/Litekit boards. >> ("[U-Boot] [PATCH v3 4/6] i.MX31: Add i.MX31 >> NAND Flash Controller driver."; MID 1219998982- >> 21289-5-git-send-email-lilja.magnus(a)gmail.com) >> >> Some note: by default, Phytec phyCORE-i.MX31 >> board (pcm-037 on pcm-970) is not suitable >> for nand-bootloading, because of SW5 switchers >> block haven't appropriate modes(8-bit, 2k page >> or 16-bit, 512B page) for BOOTPINS[4:0] and >> nand-flash(8-bit mode, 512B page) contemporary. >> There is require to make RESOLDER for really >> nand-booting either BOOTPIN state or JN1/2 and >> RN41/42. >> >> This nand-spl work with 8-bit, 512B page size nand-flash. Signed-off-by: Maxim Artamonov <scn1874 at yandex.ru> --- MAKEALL | 1 + Makefile | 9 ++- board/imx31_phycore/config.mk | 10 ++ board/imx31_phycore/lowlevel_init.S | 27 ++++- board/imx31_phycore/u-boot-nand.lds | 62 ++++++++++ cpu/arm1136/start.S | 36 ++++-- include/asm-arm/arch-mx31/mx31-regs.h | 96 +++++++++++++++ include/configs/imx31_phycore.h | 33 +++++ nand_spl/board/imx31_phycore/Makefile | 95 +++++++++++++++ nand_spl/board/imx31_phycore/config.mk | 33 +++++ nand_spl/board/imx31_phycore/u-boot.lds | 65 ++++++++++ nand_spl/nand_boot_mx31.c | 200 +++++++++++++++++++++++++++++++ 12 files changed, 656 insertions(+), 11 deletions(-) create mode 100644 board/imx31_phycore/u-boot-nand.lds create mode 100644 nand_spl/board/imx31_phycore/Makefile create mode 100644 nand_spl/board/imx31_phycore/config.mk create mode 100644 nand_spl/board/imx31_phycore/u-boot.lds create mode 100644 nand_spl/nand_boot_mx31.c diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..1f639a8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -522,6 +522,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + imx31_phycore_nand \ mx31ads \ smdk6400 \ " diff --git a/Makefile b/Makefile index 58b8331..7519dfe 100644 --- a/Makefile +++ b/Makefile @@ -353,7 +353,7 @@ $(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin + cat $(obj)nand_spl/u-boot-spl-aligned.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all @@ -2805,6 +2805,13 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +imx31_phycore_nand_config : unconfig + @mkdir -p $(obj)include $(obj)board/imx31_phycore + @mkdir -p $(obj)nand_spl/board/imx31_phycore + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a imx31_phycore arm arm1136 imx31_phycore NULL mx31 + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk index d34dc02..412defc 100644 --- a/board/imx31_phycore/config.mk +++ b/board/imx31_phycore/config.mk @@ -1 +1,11 @@ +# +# (C) Copyright 2008 +# was changed by Maxim Artamonov, <scn1874 at yandex.ru> +# + +ifndef CONFIG_NAND_SPL TEXT_BASE = 0x87f00000 +else +TEXT_BASE = 0x87ec0000 +endif + diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S index c5d6eb0..afae317 100644 --- a/board/imx31_phycore/lowlevel_init.S +++ b/board/imx31_phycore/lowlevel_init.S @@ -1,5 +1,7 @@ /* - * + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> * * See file CREDITS for list of people who contributed to this @@ -43,6 +45,20 @@ bcs 1b .endm +#ifdef CONFIG_NAND_SPL +/* somewhat macro to reduce bin size for CONFIG_NAND_SPL*/ +.macro FILLREGS begreg, val, count, step + ldr r2, =\begreg + ldr r3, =\val + ldr r4, =\count +2: + str r3, [r2] + add r2, r2, #\step + subs r4, r4, #1 + bcs 2b +.endm +#endif + .globl lowlevel_init lowlevel_init: @@ -60,10 +76,18 @@ lowlevel_init: REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) +#ifdef CONFIG_NAND_SPL + FILLREGS 0x43FAC26C, 0, 0x3, 0x4 +#else REG 0x43FAC26C, 0 /* SDCLK */ REG 0x43FAC270, 0 /* CAS */ REG 0x43FAC274, 0 /* RAS */ +#endif /* CONFIG_NAND_SPL */ REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ + +#ifdef CONFIG_NAND_SPL + FILLREGS 0x43FAC284, 0, 0x17, 0x4 +#else REG 0x43FAC284, 0 /* DQM3 */ REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ REG 0x43FAC28C, 0 @@ -87,6 +111,7 @@ lowlevel_init: REG 0x43FAC2D4, 0 REG 0x43FAC2D8, 0 REG 0x43FAC2DC, 0 +#endif /* CONFIG_NAND_SPL */ REG 0xB8001010, 0x00000004 REG 0xB8001004, 0x006ac73a REG 0xB8001000, 0x92100000 diff --git a/board/imx31_phycore/u-boot-nand.lds b/board/imx31_phycore/u-boot-nand.lds new file mode 100644 index 0000000..bd09a8d --- /dev/null +++ b/board/imx31_phycore/u-boot-nand.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 51b664d..596efe9 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -1,6 +1,9 @@ /* * armboot - Startup Code for OMP2420/ARM1136 CPU-core * + * + * Copyright (c) 2008 Maxim Artamonov, <scn1874 at yandex.ru> + * * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> * * Copyright (c) 2001 Marius Gr�ger <mag(a)sysgo.de> @@ -32,6 +35,15 @@ #include <version.h> .globl _start _start: b reset +#ifdef CONFIG_NAND_SPL + nop + nop + nop + nop + nop + nop + nop +#else #ifdef CONFIG_ONENAND_IPL ldr pc, _hang ldr pc, _hang @@ -68,6 +80,7 @@ _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ .global _end_vect _end_vect: @@ -156,9 +169,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) beq stack_setup -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ ldr r2, _armboot_start ldr r3, _bss_start @@ -175,7 +188,7 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined (CONFIG_NAND_SPL) sub sp, r0, #128 /* leave 32 words for abort-stack */ #else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ @@ -184,14 +197,14 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ -#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_ONENAND_IPL || CONFIG_NAND_SPL*/ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 @@ -200,12 +213,15 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot +#ifdef CONFIG_NAND_SPL +_start_armboot: .word nand_boot +#else #ifdef CONFIG_ONENAND_IPL _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot -#endif - +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ /* ************************************************************************* @@ -244,7 +260,7 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) /* ************************************************************************* * @@ -357,11 +373,12 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ /* * exception handlers */ +#ifndef CONFIG_NAND_SPL #ifdef CONFIG_ONENAND_IPL .align 5 do_hang: @@ -436,3 +453,4 @@ arm1136_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller #endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_NAND_SPL*/ diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index b04a718..78825f5 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -168,4 +168,100 @@ #define CS5_BASE 0xB6000000 #define PCMCIA_MEM_BASE 0xC0000000 +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00))) +#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04))) +#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06))) +#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08))) +#define NFC_CONFIG (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A))) +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C))) +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E))) +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10))) +#define NFC_WRPROT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12))) +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14))) +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16))) +#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18))) +#define NFC_CONFIG1 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A))) +#define NFC_CONFIG2 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C))) + +/* + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x200) +#define MAIN_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x400) +#define MAIN_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x600) + +/* + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x800) +#define SPARE_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x810) +#define SPARE_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x820) +#define SPARE_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x830) + +/* + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/* + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/* + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/* + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data + * Output operation + */ +#define NFC_OUTPUT 0x8 + +/* + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/* + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read + * Status operation + */ +#define NFC_STATUS 0x20 + +/* + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)CCM_RCSR)) +#define NFMS_BIT 30 + #endif /* __ASM_ARCH_MX31_REGS_H */ + diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1540203..44ffaf3 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * * (C) Copyright 2004 * Texas Instruments. * Richard Woodruff <r-woodruff2(a)ti.com> @@ -34,6 +37,11 @@ #define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -172,6 +180,31 @@ #define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ +/*----------------------------------------------------------------------- + * NAND flash + */ + +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 + +/* + * Because of small buffer size of NFC in iMX31, SPL has to fit into 2kB. + */ + +/*CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must be align to full pages*/ +#define CFG_NAND_U_BOOT_OFFS 0x800 +#define CFG_NAND_U_BOOT_SIZE 0x30000 +#define CFG_NAND_U_BOOT_DST 0x87f00000 /* Load big U-Boot to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start big U-Boot from */ +#define CFG_NAND_SPL_DST CFG_NAND_U_BOOT_DST-0x40000 /* Relocate NAND_SPL to this adress*/ + +#define CFG_NAND_PAGE_SIZE 0x200 +#define CFG_NAND_BLOCK_SIZE 0x4000 +#define CFG_NAND_PAGES_PER_BLOCK 0x20 +/*for NAND_SPL*/ +#define CFG_NAND_CHIP_SIZE 0x4000000 + /* * JFFS2 partitions */ diff --git a/nand_spl/board/imx31_phycore/Makefile b/nand_spl/board/imx31_phycore/Makefile new file mode 100644 index 0000000..0aabea3 --- /dev/null +++ b/nand_spl/board/imx31_phycore/Makefile @@ -0,0 +1,95 @@ +# +# (C) Copyright 2008 +# Maxim Artamonov, <scn1874 at yandex.ru> +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o lowlevel_init.o +COBJS = nand_boot_mx31.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-aligned.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-aligned.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/cpu/arm1136/start.S $@ + +# from board directory +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/board/imx31_phycore/lowlevel_init.S $@ + +# from nand_spl directory +$(obj)nand_boot_mx31.c: + @rm -f $@ + @ln -s $(TOPDIR)/nand_spl/nand_boot_mx31.c $@ + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/imx31_phycore/config.mk b/nand_spl/board/imx31_phycore/config.mk new file mode 100644 index 0000000..4c271c5 --- /dev/null +++ b/nand_spl/board/imx31_phycore/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2008 +# Maxim Artamonov, <scn1874 at yandex.ru> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# phyCORE-i.MX31 - PHYTEC’s phyCORE Single Board Computer module + +# TEXT_BASE for SPL: = CFG_NAND_U_BOOT_DST-0x40000 is set in board/imx31_phycore/config.mk + +# PAD_TO used to generate a 2kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 2048 +PAD_TO := $(shell expr $$[$(TEXT_BASE) + 2048]) + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/nand_spl/board/imx31_phycore/u-boot.lds b/nand_spl/board/imx31_phycore/u-boot.lds new file mode 100644 index 0000000..d25abf8 --- /dev/null +++ b/nand_spl/board/imx31_phycore/u-boot.lds @@ -0,0 +1,65 @@ +/* + * + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + lowlevel_init.o (.text) + nand_boot_mx31.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c new file mode 100644 index 0000000..be22d18 --- /dev/null +++ b/nand_spl/nand_boot_mx31.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <nand.h> +#include <asm-arm/arch/mx31-regs.h> + +static void mx31_wait_ready(void) +{ + while (1) { + if (NFC_CONFIG2 & NFC_INT) { + NFC_CONFIG2 = NFC_CONFIG2 & (~NFC_INT);/* int flag reset */ + break; + } + } +} + +static void mx31_nand_init(void) +{ + /* unlocking RAM Buff */ + NFC_CONFIG = 0x2; + + /* hardware ECC checking and correct */ + NFC_CONFIG1 = NFC_ECC_EN; +} + +static void mx31_nand_command(unsigned short command) +{ + NFC_FLASH_CMD = command; + NFC_CONFIG2 = NFC_CMD; + mx31_wait_ready(); +} + +static void mx31_nand_page_address(unsigned int page_address) +{ + unsigned int page_count; + + NFC_FLASH_ADDR = 0x00; + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + + /* code only for 2kb flash */ + if (CFG_NAND_PAGE_SIZE == 0x800){ + NFC_FLASH_ADDR = 0x00; + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + }; + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; + + if (page_address <= page_count){ + page_count--;/* transform 0x01000000 to 0x00ffffff */ + do { + NFC_FLASH_ADDR = (unsigned short)(page_address & 0xff); + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + page_address = page_address >> 8; + page_count = page_count >> 8; + } while (page_count); + } +} + +static void mx31_nand_data_output(void) +{ + int i; + + /* + * The NAND controller requires four output commands for + * large page devices. + */ + for (i = 0; i < (CFG_NAND_PAGE_SIZE / 512); i++) { + NFC_CONFIG1 = NFC_ECC_EN; + NFC_BUF_ADDR = i; /* read in i:th buffer */ + NFC_CONFIG2 = NFC_OUTPUT; + mx31_wait_ready(); + } +} + +static int mx31_nand_check_ecc(void) +{ + unsigned short ecc_status_registr; + + ecc_status_registr = NFC_ECC_STATUS_RESULT; + + if (ecc_status_registr != 0) + return 1;/* error */ + return 0; +} + +static int mx31_read_page(unsigned int page_address, unsigned char *buf) +{ + int i; + volatile u32 *p1, *p2, a; + + mx31_nand_init (); + NFC_BUF_ADDR = 0; /* read in first 0 buffer */ + mx31_nand_command (NAND_CMD_READ0); + mx31_nand_page_address (page_address); + + if (CFG_NAND_CHIP_SIZE >= 0x08000000) + mx31_nand_command (NAND_CMD_READSTART); + + mx31_nand_data_output ();/* fill the main buffer 0 */ + + if (mx31_nand_check_ecc ()) + while (1) { + /* hang-loop in case of ecc-error */ + } + + p1 = (u32 *)MAIN_AREA0; + p2 = (u32 *)buf; + + /* main copy loop from NAND-buffer to SDRAM memory */ + for (i=0; i < (CFG_NAND_PAGE_SIZE / 4); i++) { + *p2 = *p1; + p1++; + p2++; + } + + p1 = (u32 *)SPARE_AREA0; + + /* it is hardware specific code for 8-bit 512 B NAND-flash spare area */ + p1++; + a = *p1; + a = (a & 0x0000ff00) >> 8; + + if (a != 0xff) /* bad block marker verify */ + return 1;/* potential bad block */ + + return 0; +} + +static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) +{ + int i, bb; + + mx31_nand_init (); + + /* convert from to page number */ + from = from / CFG_NAND_PAGE_SIZE; + + i = 0; + + while (i < (size/CFG_NAND_PAGE_SIZE)) { + + if ((from*CFG_NAND_PAGE_SIZE) >= CFG_NAND_CHIP_SIZE) + return 2;/* memory segment violation */ + + bb = mx31_read_page (from, buf); + + /* checking first page of each block */ + /* if this page has bb marker, then skip whole block */ + if ((!(from % CFG_NAND_PAGES_PER_BLOCK)) && bb) { + from = from + CFG_NAND_PAGES_PER_BLOCK; + } + else { + i++; + from++; + buf = buf + CFG_NAND_PAGE_SIZE; + } + } + return 0; +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + /* CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must */ + /* be align to full pages */ + nand_load (CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, \ + (uchar *)CFG_NAND_U_BOOT_DST); + + uboot = (void *)CFG_NAND_U_BOOT_START; + uboot (); +} -- 1.5.2.4

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[U-Boot] u-boot for ARM
by Amandeep Bhullar 11 Feb '09

11 Feb '09

Hello All, I have an Atmel AT91SAM9263 evaluation board with an arm926ejs based processor. I want to configure U-boot for this and want to have a USB device boot option available too. Though the U-boot will be in NAND Flash but i want the board to boot from a USB device like a USB Flash drive etc. I was reading the README and it talks about configuring a large number of options. Where do I define these options? In which file? if i just give the command $ make arm926ejs_config if comes with a message make: *** No rule to make target 'arm926ejs_config'. Stop. Can anybody help me in how to obtain a .bin file for my processor that i can load in NANDFlash and use this U-boot. Many Thanks Aman.

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[U-Boot] [PATCH] USB: Remove LUN number from CDB
by Abraham, Thomas 10 Feb '09

10 Feb '09

The LUN number is not part of the Command Descriptor Block (CDB) for scsi inquiry, request sense, test unit ready, read capacity and read10 commands. This patch removes the LUN number information from the CDB. Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> --- u-boot-usb/common/usb_storage.c.orig 2008-10-28 17:08:45.000000000 +0530 +++ u-boot-usb/common/usb_storage.c 2008-10-28 17:09:12.000000000 +0530 @@ -827,7 +827,6 @@ static int usb_inquiry(ccb *srb,struct u do { memset(&srb->cmd[0],0,12); srb->cmd[0]=SCSI_INQUIRY; - srb->cmd[1]=srb->lun<<5; srb->cmd[4]=36; srb->datalen=36; srb->cmdlen=12; @@ -851,7 +850,6 @@ static int usb_request_sense(ccb *srb,st ptr=(char *)srb->pdata; memset(&srb->cmd[0],0,12); srb->cmd[0]=SCSI_REQ_SENSE; - srb->cmd[1]=srb->lun<<5; srb->cmd[4]=18; srb->datalen=18; srb->pdata = &srb->sense_buf[0]; @@ -869,7 +867,6 @@ static int usb_test_unit_ready(ccb *srb, do { memset(&srb->cmd[0],0,12); srb->cmd[0]=SCSI_TST_U_RDY; - srb->cmd[1]=srb->lun<<5; srb->datalen=0; srb->cmdlen=12; if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { @@ -889,7 +886,6 @@ static int usb_read_capacity(ccb *srb,st do { memset(&srb->cmd[0],0,12); srb->cmd[0]=SCSI_RD_CAPAC; - srb->cmd[1]=srb->lun<<5; srb->datalen=8; srb->cmdlen=12; if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { @@ -904,7 +900,6 @@ static int usb_read_10(ccb *srb,struct u { memset(&srb->cmd[0],0,12); srb->cmd[0]=SCSI_READ10; - srb->cmd[1]=srb->lun<<5; srb->cmd[2]=((unsigned char) (start>>24))&0xff; srb->cmd[3]=((unsigned char) (start>>16))&0xff; srb->cmd[4]=((unsigned char) (start>>8))&0xff;

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[U-Boot] [PATCH v3 0/6] i.MX31: Add NAND support and new PDK board.
by Magnus Lilja 10 Feb '09

10 Feb '09

Hi again This series of patches adds support for the NAND flash controller in the i.MX31 device and also introduces the Freescale i.MX31 PDK board. Changes since v2: - Added doc/README.mx31 (contains MC13783 SPI config documentation) - Split the PDK patch into two patches, the first introduces the board without NAND support, the second adds NAND support. - Re-ordered the series so the NAND patches are placed last - mx31_nand.c has been updated w.r.t. coding style. - There are still issues with the NAND driver (i.e. not all comments from Scott Wood have been taken care of yet). Therefore I suspect that the NAND driver is not ready for inclusion yet, the other patches should be OK. The patches are based on the current main U-boot git repo (as of Friday morning). Changes since v1: - Moved PDK board to boards/freescale/mx31pdk - Moved mxc_nd.c to driver/mtd/nand/mx31_nand.c - Moved contents of mxc_nd.h to mx31-regs.h - Cleaned up the mx31pdk.h config file after comments from this list - CONFIG_CMD_IMLS is still #undef'd but a comment is added in the config file about that. - A new patch has been inserted into the series, it makes the MC13783 SPI bus and chip select configurable. The patches are based on the current main U-boot git repo. Original intro for this series of patches: At the moment, the patch series does not add support for booting from NAND. This means that the PDK board support assumes that some other entity configures the SDRAM and loads U-boot into RAM (e.g. another bootloader or a JTAG debugger). Support for NAND boot is in progress and will be submitted later. The NAND driver is based on Freescale's Linux driver from their BSP. I've cleaned it up a bit and made the (minor) modifications necessary for U-boot. Perhaps the driver should be cleaned up even more, there are some CONFIG_MTD_MXC_* leftovers in the driver. I have tested the driver on the Litekit (small page NAND) and on the PDK (large page NAND) by having the U-boot environment placed in NAND. Regards, Magnus

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[U-Boot] [PATCH 1/3] 85xx: Use BR_ADDR macro for NAND chipselects
by Kumar Gala 10 Feb '09

10 Feb '09

Use the new BR_ADDR macro to properly setup the address field of the localbus chipselects used by NAND. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/configs/MPC8536DS.h | 8 ++++---- include/configs/MPC8572DS.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 48a8cf2..1209a05 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -257,7 +257,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -274,20 +274,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c8acc80..8e4eb10 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -276,7 +276,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -293,20 +293,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ -- 1.5.6.6

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[U-Boot] [patch V3] [0/3] U-Boot Firetux board support (PNX8181)
by Jürgen Schöw 10 Feb '09

10 Feb '09

Hi U-Boot mailling list, This patchset adds a new ARM board with the NXP PNX8181 cpu to u-boot. The PNX8181 is an ARM926ej with an internal DSP (mostly used for Audio processing and VOIP codecs) and a baseband processor (used for DECT). The chip also features dual ethernet, digital to analog interface, spi, i2c and other SOC peripherals. These boards have been build by NXP Semiconductors GmbH, Nuremberg, Germany and are now build by DSPG Technologies GmbH, Nuremberg, Germany. Signed-off-by: Jürgen Schöw <js(a)emlix.com> Signed-off-by: Sebastian Hess <sh(a)emlix.com> Signed-off-by: Matthias Mwenzel <nxp(a)mazzoo.de> Signed-off-by: Dirk Hörner <dirk.hoerner(a)dspg.com> Signed-off-by: Andreas Weißel <andreas.weissel(a)dspg.com> --- It took quite some time to rework the patchset to match your requierments. In this 3rd patchset the folling changes have been done: - separate the network driver and move to drivers/net/ - use new network API - make network driver independ from board - use CONFIG_NET_MULTI-style API - initialize network driver with board_eth_init() - move board files to vendor directory dspg - implement a gpio driver for the gpio A pins - separate board detection - use deferent function for each hardware revision - create a led driver - move timer functions to SOC specific directory Complete stats: MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 7 + board/dspg/firetux/Makefile | 59 ++++ board/dspg/firetux/boardrevision.c | 299 ++++++++++++++++ board/dspg/firetux/config.mk | 44 +++ board/dspg/firetux/firetux.c | 413 ++++++++++++++++++++++ board/dspg/firetux/firetux.h | 144 ++++++++ board/dspg/firetux/gpio.c | 134 ++++++++ board/dspg/firetux/led.c | 169 +++++++++ board/dspg/firetux/lowlevel_init.S | 404 ++++++++++++++++++++++ board/dspg/firetux/memsetup.S | 381 +++++++++++++++++++++ board/dspg/firetux/nand.c | 68 ++++ board/dspg/firetux/relocate.S | 252 ++++++++++++++ board/dspg/firetux/u-boot.lds | 57 +++ cpu/arm926ejs/pnx8181/Makefile | 45 +++ cpu/arm926ejs/pnx8181/timer.c | 141 ++++++++ drivers/i2c/Makefile | 1 + drivers/i2c/pnx8181_i2c.c | 304 +++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/ip3912.c | 659 ++++++++++++++++++++++++++++++++++++ drivers/net/ip3912.h | 174 ++++++++++ include/configs/firetux.h | 454 +++++++++++++++++++++++++ 23 files changed, 4215 insertions(+), 0 deletions(-) Regards Jürgen Schöw -- Dipl.-Ing. Jürgen Schöw, emlix GmbH, http://www.emlix.com, mailto:js@emlix.com Fon +49 551 30664-0, Fax -11, Bahnhofsallee 1b, 37081 Göttingen, Germany Geschäftsführung: Dr. Uwe Kracke, Dr. Cord Seele, Ust-IdNr.: DE 205 198 055 Sitz der Gesellschaft: Göttingen, Amtsgericht Göttingen HR B 3160 emlix - your embedded linux partner

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