September 2008 - U-Boot

[U-Boot] [PATCH] Add simple IP/UDP fragmentation support
by Josh Boyer 28 Oct '08

28 Oct '08

From: Frank Haverkamp <haver(a)vnet.ibm.com> http://tools.ietf.org/html/rfc2348 describes the TFTP block size option which allows larger packtes than the 512 byte default. This reduces the number of TFTP ACKs significantly and improves performance. To get the most benefit out of the tftp block size option the support of defragementation of IP/UDP packet is helpful. The current implemenation should work even with packets received out of order. To enable the large packet size the user should set "tftp_block_size" so a value like 16352. We experimented with different packet sizes and found that more than those 16KiB do not contribute much to the performance anymore. Therefor I limited the defragmentation buffer to 16KiB no too waste memory. Signed-off-by: Frank Haverkamp <haver(a)vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer(a)linux.vnet.ibm.com> --- include/net.h | 17 ++++++ net/net.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++-------- net/tftp.c | 22 ++++++++ net/tftp.h | 10 +++ 4 files changed, 185 insertions(+), 20 deletions(-) --- u-boot.git.orig/include/net.h +++ u-boot.git/include/net.h @@ -200,6 +200,13 @@ typedef struct { ushort udp_xsum; /* Checksum */ } IP_t; +#define IP_OFFS 0x1FFF /* ip offset *= 8 */ +#define IP_OFFS_SHIFT 3 /* in 8 byte steps */ +#define IP_FLAGS 0xE000 /* first 3 bits */ +#define IP_FLAGS_RES 0x8000 /* reserved */ +#define IP_FLAGS_DFRAG 0x4000 /* don't fragments */ +#define IP_FLAGS_MFRAG 0x2000 /* more fragments */ + #define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8) #define IP_HDR_SIZE (sizeof (IP_t)) @@ -282,6 +289,16 @@ typedef struct icmphdr { #define PKTSIZE_ALIGN 1536 /*#define PKTSIZE 608*/ + /* + * IP/UDP Fragmentation support + * See: http://en.wikipedia.org/wiki/IPv4#Fragmentation_and_reassembly + * MAX possible UDP packet size is 64 KiB, if there is memory available. + */ +#define NET_ETH_MTU 1500 +#define NET_FRAG_BUF_SIZE (16 * 1024) /* MAX is 64 KiB */ +#define NET_UDP_FRAG_SIZE (NET_ETH_MTU - IP_HDR_SIZE_NO_UDP) /* 1480 */ +#define NET_FRAG_BUF_USED (NET_FRAG_BUF_SIZE / NET_UDP_FRAG_SIZE + 1) + /* * Maximum receive ring size; that is, the number of packets * we can buffer before overflow happens. Basically, this just --- u-boot.git.orig/net/net.c +++ u-boot.git/net/net.c @@ -192,6 +192,15 @@ volatile uchar PktBuf[(PKTBUFSRX+1) * PK volatile uchar *NetRxPackets[PKTBUFSRX]; /* Receive packets */ +/* Packet fragmentation support */ +static uint16_t ip_id = 0; /* sequence number */ +static uint16_t udp_len = 0; +static uint16_t udp_src = 0; +static uint16_t udp_dst = 0; +static int max_idx = 0; +static uchar NetFragBuf[NET_FRAG_BUF_SIZE]; +static char NetFragBufUsed[NET_FRAG_BUF_USED] = { 0, }; + static rxhand_f *packetHandler; /* Current RX packet handler */ static thand_f *timeHandler; /* Current timeout handler */ static ulong timeStart; /* Time base value */ @@ -288,6 +297,13 @@ NetLoop(proto_t protocol) { bd_t *bd = gd->bd; + /* Packet fragmentation support */ + ip_id = udp_len = udp_src = udp_dst = max_idx = 0; + memset(NetFragBuf, 0xFF, sizeof(NetFragBuf)); + memset(NetFragBufUsed, 0, sizeof(NetFragBufUsed)); + printf("NetFragBuf @ %08x max tftp_block_size=%d udp_frag_size=%d\n", + NetFragBuf, TFTP_BLOCK_SIZE_MAX, NET_UDP_FRAG_SIZE); + #ifdef CONFIG_NET_MULTI NetRestarted = 0; NetDevExists = 0; @@ -1150,6 +1166,39 @@ static void CDPStart(void) } #endif +#ifdef CONFIG_UDP_CHECKSUM +/* + * @sumptr: Points to UDP data + * @sumlen: Size of UDP data + * @xsum: UDP checksum across IP source, destination address, protocol and size + * + * Returns 0 when checksum is correct and 1 if it is not. + */ +static int udp_checksum(ushort *sumptr, ushort sumlen, ulong xsum) +{ + while (sumlen > 1) { + ushort sumdata; + + sumdata = *sumptr++; + xsum += ntohs(sumdata); + sumlen -= 2; + } + if (sumlen > 0) { + ushort sumdata; + + sumdata = *(unsigned char *) sumptr; + sumdata = (sumdata << 8) & 0xff00; + xsum += sumdata; + } + while ((xsum >> 16) != 0) { + xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff); + } + if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) + return 1; + + return 0; +} +#endif /* CONFIG_UDP_CHECKSUM */ void NetReceive(volatile uchar * inpkt, int len) @@ -1164,6 +1213,7 @@ NetReceive(volatile uchar * inpkt, int l int iscdp; #endif ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid; + uint32_t off; /* ip_off for fragmentation */ #ifdef ET_DEBUG printf("packet received\n"); @@ -1404,9 +1454,11 @@ NetReceive(volatile uchar * inpkt, int l if ((ip->ip_hl_v & 0xf0) != 0x40) { return; } +#if 0 /* Obsolete after adding the fragmentation support */ if (ip->ip_off & htons(0x1fff)) { /* Can't deal w/ fragments */ return; } +#endif /* can't deal with headers > 20 bytes */ if ((ip->ip_hl_v & 0x0f) > 0x05) { return; @@ -1422,6 +1474,88 @@ NetReceive(volatile uchar * inpkt, int l #endif return; } + + /* + * Fragmentation support. We need to check the ip_id + * and if all fragments were received correctly. + */ + off = (ntohs(ip->ip_off) & IP_OFFS) << IP_OFFS_SHIFT; + if ((off != 0) || (ip->ip_off & htons(IP_FLAGS_MFRAG))) { + int size, idx, complete; + char *start; + + /* New fragmented packet arrived, clear data. */ + if (ntohs(ip->ip_id) != ip_id) { + ip_id = ntohs(ip->ip_id); + memset(NetFragBufUsed, 0, sizeof(NetFragBufUsed)); + udp_len = udp_src = udp_dst = max_idx = 0; + } + + idx = off / NET_UDP_FRAG_SIZE; + + /* Packet does not fit into IP/UDP fragmentation buf */ + if (idx >= NET_FRAG_BUF_USED) { + return; + } + + NetFragBufUsed[idx] = 1; + + /* Copy the UDP hdr with the data for 1st + fragment, else copy just payload */ + if (off == 0) { + udp_len = ntohs(ip->udp_len); + udp_src = ntohs(ip->udp_src); + udp_dst = ntohs(ip->udp_dst); + } + size = ntohs(ip->ip_len) - IP_HDR_SIZE_NO_UDP; + start = (char *)ip + IP_HDR_SIZE_NO_UDP; + memcpy(NetFragBuf + off, start, size); + + /* + * When last fragement has been received we + * know the number of fragments we expect. If + * all have arrived we process the packet. + */ + if (((off != 0) && !(ip->ip_off & htons(IP_FLAGS_MFRAG)))) + max_idx = idx; + + if (max_idx == 0) + return; + + complete = 1; + for (idx = 0; idx < max_idx; idx++) { + if (NetFragBufUsed[idx] == 0) { + complete = 0; + break; + } + } + if (!complete) + return; +#ifdef CONFIG_UDP_CHECKSUM + if (ip->udp_xsum != 0) { + ulong xsum = ip->ip_p; + uint16_t *sumptr; + + xsum += udp_len; + xsum += (ntohl(ip->ip_src) >> 16) & 0xffff; + xsum += (ntohl(ip->ip_src) >> 0) & 0xffff; + xsum += (ntohl(ip->ip_dst) >> 16) & 0xffff; + xsum += (ntohl(ip->ip_dst) >> 0) & 0xffff; + sumptr = (ushort *)NetFragBuf; + + if (udp_checksum(sumptr, udp_len, xsum)) { + putc('U'); + return; + } + } +#endif /* CONFIG_UDP_CHECKSUM */ + (*packetHandler)(NetFragBuf + 8, + udp_dst, + udp_src, + udp_len - 8); + return; + } + /* * watch for ICMP host redirects * @@ -1502,26 +1636,8 @@ NetReceive(volatile uchar * inpkt, int l sumlen = ntohs(ip->udp_len); sumptr = (ushort *) &(ip->udp_src); - while (sumlen > 1) { - ushort sumdata; - - sumdata = *sumptr++; - xsum += ntohs(sumdata); - sumlen -= 2; - } - if (sumlen > 0) { - ushort sumdata; - - sumdata = *(unsigned char *) sumptr; - sumdata = (sumdata << 8) & 0xff00; - xsum += sumdata; - } - while ((xsum >> 16) != 0) { - xsum = (xsum & 0x0000ffff) + ((xsum >> 16) & 0x0000ffff); - } - if ((xsum != 0x00000000) && (xsum != 0x0000ffff)) { - printf(" UDP wrong checksum %08lx %08x\n", - xsum, ntohs(ip->udp_xsum)); + if (udp_checksum(sumptr, sumlen, xsum)) { + putc('U'); return; } } --- u-boot.git.orig/net/tftp.c +++ u-boot.git/net/tftp.c @@ -456,6 +456,7 @@ TftpTimeout (void) void TftpStart (void) { + char *s, *err; #ifdef CONFIG_TFTP_PORT char *ep; /* Environment pointer */ #endif @@ -518,6 +519,27 @@ TftpStart (void) puts ("Loading: *\b"); + /* Get alternate tftp_block_size */ + if ((s = getenv("tftp_block_size")) != NULL) { + err = NULL; + + TftpBlkSizeOption = simple_strtoul(s, &err, 10); + if (*err) { + printf("ERR: \"tftp_block_size\" is not a number\n"); + TftpBlkSizeOption = TFTP_BLOCK_SIZE; + } + /* + * Reject values which require extensive handling. + * block size of 1428 octets (Ethernet MTU, less + * the TFTP, UDP and IP header lengths). + */ + if (TftpBlkSizeOption > TFTP_BLOCK_SIZE_MAX) { + printf("ERR: tftp_block_sizes larger than %d not " + "supported\n", TFTP_BLOCK_SIZE_MAX); + TftpBlkSizeOption = TFTP_BLOCK_SIZE; + } + } + NetSetTimeout (TIMEOUT * CFG_HZ, TftpTimeout); NetSetHandler (TftpHandler); --- u-boot.git.orig/net/tftp.h +++ u-boot.git/net/tftp.h @@ -8,11 +8,21 @@ #ifndef __TFTP_H__ #define __TFTP_H__ +#include <net.h> + /**********************************************************************/ /* * Global functions and variables. */ +/* + * Maximum TFTP block size bound to max size of fragmented IP/UDP + * packets minus TFTP and UDP/IP overhead. TFTP overhead is 2 byte + * opcode and 2 byte block-number. + */ +#define TFTP_BLOCK_SIZE_MAX (NET_FRAG_BUF_SIZE - sizeof(IP_t) - 4) + + /* tftp.c */ extern void TftpStart (void); /* Begin TFTP get */

4 7

[U-Boot] [RFC][PATCH 2b/3] New i386 board (includes code relocation)
by Graeme Russ 28 Oct '08

28 Oct '08

Split to meet mailing list size limit Initial addition of eNET files - builds clean but will not run until additional i386 code changes are made Signed-off-by: Graeme Russ <graeme.russ(a)gmail.com> -- diff --git a/board/eNET/fpga.c b/board/eNET/fpga.c new file mode 100644 index 0000000..a3e4677 --- /dev/null +++ b/board/eNET/fpga.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2002 + * Wolfgang Grandegger, DENX Software Engineering, wg(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <command.h> +#include <linux/ctype.h> +#include <asm/ic/sc520.h> +#include <asm/ic/ssi.h> +#include <watchdog.h> +#include <asm/io.h> + +#include "fpga.h" + +static u8 fpga_init(void); +static u8 fpga_write(void *buf, size_t bsize); +static u8 fpga_finalise(void); +static void fpga_close(void); + + +int fpga_load(int devnum, void *buf, size_t bsize ) +{ + u8 ret = FPGA_SUCCESS; + + WATCHDOG_RESET(); + + ret = fpga_init(); + + if (ret == FPGA_SUCCESS) { + ret = fpga_write(buf, bsize); + } + + if (ret == FPGA_SUCCESS) { + ret = fpga_finalise(); + } + + fpga_close(); + + WATCHDOG_RESET(); + + return ret; +} + + +static u8 fpga_init(void) +{ + u8 ret = FPGA_FAIL_INIT; + u16 state = 0x0000; + + /* + * Drop then raise the FPGA's program bit + */ + writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_CLR); + udelay(CFG_FPGA_PROGRAM_BIT_DROP_TIME * 1000); + writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_SET); + + reset_timer(); + + while (get_timer(0) < CFG_FPGA_MAX_INIT_TIME) { + /* + * Check if the FPGA has raised its initialized bit + */ + state = readw(CFG_FPGA_PIO_DATA); + + if (state & CFG_FPGA_INIT_PIO_BIT) { + ret = FPGA_SUCCESS; + goto Done; + } + + udelay (10); + } + +Done: + return ret; +} + + +static u8 fpga_write(void *buf, size_t bsize) +{ + u8 *ptr = (u8 *) buf; + + /* + * Stream the buffer to the FPGA using the SSI + */ + ssi_set_interface(CFG_FPGA_SSI_DATA_RATE, 0, 0, 0); + + /* + * TODO: Can ssi_tx_byte() fail (port busy)? + */ + while (bsize--) + ssi_tx_byte (*ptr); + + return FPGA_SUCCESS; +} + + +static u8 fpga_finalise(void) +{ + u8 ret = FPGA_FAIL_FINALISE; + u16 state = 0x0000; + + reset_timer(); + + while (get_timer(0) < CFG_FPGA_MAX_FINALISE_TIME) { + state = readw(CFG_FPGA_PIO_DATA); + + if (state & CFG_FPGA_DONE_PIO_BIT) { + ret = FPGA_SUCCESS; + goto Done; + } + + udelay (10); + } + +Done: + return ret; +} + +static void fpga_close(void) +{ + u16 dirs = readw(CFG_FPGA_PIO_DIRECTION); + + /* + * Set the program pin of the FPGA to be an input (high impedance) + */ + dirs &= ~CFG_FPGA_PROGRAM_PIO_BIT; + + writew(dirs, CFG_FPGA_PIO_DIRECTION); +} diff --git a/board/eNET/fpga.h b/board/eNET/fpga.h new file mode 100644 index 0000000..a4db321 --- /dev/null +++ b/board/eNET/fpga.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ(a)gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _FPGA_H_ +#define _FPGA_H_ + +#define FPGA_SUCCESS 0 +#define FPGA_FAIL_INIT 1 +#define FPGA_FAIL_FINALISE 2 +#define FPGA_FAIL_START 3 + + + +int fpga_load( int devnum, void *buf, size_t bsize ); + +#endif /* _FPGA_H_ */ diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h new file mode 100644 index 0000000..eab612c --- /dev/null +++ b/board/eNET/hardware.h @@ -0,0 +1,13 @@ +/* + * hardware.h + * + * Created on: 17/09/2008 + * Author: graeme + */ + +#ifndef HARDWARE_H_ +#define HARDWARE_H_ + +#include "hardware_defs.h" + +#endif /* HARDWARE_H_ */ diff --git a/board/eNET/hardware_defs.h b/board/eNET/hardware_defs.h new file mode 100644 index 0000000..2ffa008 --- /dev/null +++ b/board/eNET/hardware_defs.h @@ -0,0 +1,19 @@ +/* + * hardware.h + * + * Created on: 11/09/2008 + * Author: graeme + */ + +#ifndef HARDWARE_DEFS_H_ +#define HARDWARE_DEFS_H_ + +#define LED_LATCH_ADDRESS 0x1002 +#define LED_RUN_BITMASK 0x01 +#define LED_1_BITMASK 0x02 +#define LED_2_BITMASK 0x04 +#define LED_RX_BITMASK 0x08 +#define LED_TX_BITMASK 0x10 +#define LED_ERR_BITMASK 0x20 + +#endif /* HARDWARE_H_ */ diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds new file mode 100644 index 0000000..7855c0b --- /dev/null +++ b/board/eNET/u-boot.lds @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2002 + * Daniel Engstrï¿½m, Omicron Ceti AB, daniel(a)omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ + . = 0x38040000; /* Where bootcode in the flash is mapped */ + .text : { *(.text); } + + . = ALIGN(4); + .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } + + _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + + . = 0x03FF0000; /* Ram data segment to use */ + _i386boot_romdata_dest = ABSOLUTE(.); + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } + _i386boot_romdata_start = LOADADDR(.data); + + . = ALIGN(4); + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + _i386boot_cmd_start = LOADADDR(.u_boot_cmd); + + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd); + + . = ALIGN(4); + _i386boot_bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } + _i386boot_bss_size = SIZEOF(.bss); + + /* 16bit realmode trampoline code */ + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) } + + _i386boot_realmode = LOADADDR(.realmode); + _i386boot_realmode_size = SIZEOF(.realmode); + + /* 16bit BIOS emulation code (just enough to boot Linux) */ + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + + _i386boot_bios = LOADADDR(.bios); + _i386boot_bios_size = SIZEOF(.bios); + + /* The load addresses below assumes that the flash + * will be mapped so that 0x387f0000 == 0xffff0000 + * at reset time + * + * The fe00 and ff00 offsets of the start32 and start16 + * segments are arbitrary, the just have to be mapped + * at reset and the code have to fit. + * The fff0 offset of reset is important, however. + */ + + . = 0xfffffe00; + .start32 : AT (0x3807fe00) { *(.start32); } + + . = 0xf800; + .start16 : AT (0x3807f800) { *(.start16); } + + . = 0xfff0; + .reset : AT (0x3807fff0) { *(.reset); } + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) ); +} diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 640b255..a5724b6 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -32,7 +32,7 @@ #include <config.h> #include <pci.h> #ifdef CONFIG_SC520_SSI -#include <ssi.h> +#include <asm/ic/ssi.h> #endif #include <asm/io.h> #include <asm/pci.h> diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c index d99af26..047d3aa 100644 --- a/examples/82559_eeprom.c +++ b/examples/82559_eeprom.c @@ -19,7 +19,7 @@ */ #define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */ -#define _LINUX_STRING_H_ /* avoid unnecessary str/mem functions */ +/* #define _LINUX_STRING_H_ */ /* avoid unnecessary str/mem functions */ #include <common.h> #include <exports.h> diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index 0f7e7a5..2da01ea 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -312,7 +312,10 @@ extern int sc520_pci_ints[]; void init_sc520(void); unsigned long init_sc520_dram(void); + +#ifdef CONFIG_PCI void pci_sc520_init(struct pci_controller *hose); int pci_sc520_set_irq(int pci_pin, int irq); +#endif #endif diff --git a/include/asm-i386/ic/sc520_defs.h b/include/asm-i386/ic/sc520_defs.h new file mode 100644 index 0000000..c8f6311 --- /dev/null +++ b/include/asm-i386/ic/sc520_defs.h @@ -0,0 +1,1489 @@ +/* + * sc520_defs.h + * + * Created on: 17/09/2008 + * Author: graeme + */ + +#ifndef _ASM_IC_SC520_DEFS_H_ +#define _ASM_IC_SC520_DEFS_H_ + +/* Memory mapped configuration registers, MMCR */ +#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ +#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ +#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ +#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ +#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ +#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ +#define SC520_ECCCTL 0x0020 /* ECC Control Register */ +#define SC520_ECCSTA 0x0021 /* ECC Status Register */ +#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ +#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ +#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ +#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ +#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ +#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ +#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ +#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ +#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ +#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ +#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ +#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ +#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ +#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ +#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ +#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ +#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ +#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ +#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ +#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ +#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ +#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ +#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ +#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ +#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ +#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ +#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ +#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ +#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ +#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ +#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ +#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ +#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ +#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ +#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ +#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ +#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ +#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ +#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ +#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ +#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ +#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ +#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ +#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ +#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ +#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ +#define SC520_CLKSEL 0x0c26 /* Clock Select */ +#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ +#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ +#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ +#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ +#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ +#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ +#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ +#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ +#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ +#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ +#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ +#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ +#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ +#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ +#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ +#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ +#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ +#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ +#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ +#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ +#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ +#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ +#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ +#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ +#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ +#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ +#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ +#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ +#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ +#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ +#define SC520_SSICTL 0x0cd0 /* SSI Control */ +#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ +#define SC520_SSICMD 0x0cd2 /* SSI Command */ +#define SC520_SSISTA 0x0cd3 /* SSI Status */ +#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ +#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ +#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ +#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ +#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ +#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ +#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ +#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ +#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ +#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ +#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ +#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ +#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ +#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ +#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ +#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ +#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ +#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ +#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ +#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ +#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ +#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ +#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ +#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ +#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ +#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ +#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ +#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ +#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ +#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ +#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ +#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ +#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ +#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ +#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ +#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ +#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ +#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ +#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ +#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ +#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ +#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ +#define SC520_RESSTA 0x0d74 /* Reset Status Register */ +#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ +#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ +#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ +#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ +#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ +#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ +#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ +#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ +#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ +#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ +#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ +#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ +#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ +#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ +#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ +#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ +#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ +#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ +#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ +#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ +#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ +#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ +#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ +#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ +#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ +#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ +#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ +#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ +#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ +#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ + +/* MMCR Register bits (not all of them :) ) */ + +/* SSI Stuff */ +#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ +#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ +#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ +#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ +#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ +#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ +#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ +#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ + +#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ +#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ +#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ +#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ + +#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ +#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ +#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ +#define SSISTA_BSY 0x02 /* SSI Busy */ +#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ + + +/* BITS for SC520_ADDDECCTL: */ +#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ +#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ +#define RTC_DIS 0x04 /* RTC Disable */ +#define UART2_DIS 0x02 /* UART2 Disable */ +#define UART1_DIS 0x01 /* UART1 Disable */ + +/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ +#define SC520_REG_ADDR 0x00000cf8 +#define SC520_REG_DATA 0x00000cfc + + +#define SC520_ISA_MEM_PHYS 0x00000000 +#define SC520_ISA_MEM_BUS 0x00000000 +#define SC520_ISA_MEM_SIZE 0x01000000 + +#define SC520_ISA_IO_PHYS 0x00000000 +#define SC520_ISA_IO_BUS 0x00000000 +#define SC520_ISA_IO_SIZE 0x00001000 + +/* PCI I/O space from 0x1000 to 0xdfff + * (make 0xe000-0xfdff available for stuff like PCCard boot) */ +#define SC520_PCI_IO_PHYS 0x00001000 +#define SC520_PCI_IO_BUS 0x00001000 +#define SC520_PCI_IO_SIZE 0x0000d000 + +/* system memory from 0x00000000 to 0x0fffffff */ +#define SC520_PCI_MEMORY_PHYS 0x00000000 +#define SC520_PCI_MEMORY_BUS 0x00000000 +#define SC520_PCI_MEMORY_SIZE 0x10000000 + +/* PCI bus memory from 0x10000000 to 0x26ffffff + * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ +#define SC520_PCI_MEM_PHYS 0x10000000 +#define SC520_PCI_MEM_BUS 0x10000000 +#define SC520_PCI_MEM_SIZE 0x17000000 + +/* 0x28000000 - 0x3fffffff is used by the flash banks */ + +/* 0x40000000 - 0xffffffff is not adressable by the SC520 */ + +/* priority numbers used for interrupt channel mappings */ +#define SC520_IRQ_DISABLED 0 +#define SC520_IRQ0 1 +#define SC520_IRQ1 2 +#define SC520_IRQ2 4 /* same as IRQ9 */ +#define SC520_IRQ3 11 +#define SC520_IRQ4 12 +#define SC520_IRQ5 13 +#define SC520_IRQ6 21 +#define SC520_IRQ7 22 +#define SC520_IRQ8 3 +#define SC520_IRQ9 4 +#define SC520_IRQ10 5 +#define SC520_IRQ11 6 +#define SC520_IRQ12 7 +#define SC520_IRQ13 8 +#define SC520_IRQ14 9 +#define SC520_IRQ15 10 + + +/* pin number used for PCI interrupt mappings */ +#define SC520_PCI_INTA 0 +#define SC520_PCI_INTB 1 +#define SC520_PCI_INTC 2 +#define SC520_PCI_INTD 3 +#define SC520_PCI_GPIRQ0 4 +#define SC520_PCI_GPIRQ1 5 +#define SC520_PCI_GPIRQ2 6 +#define SC520_PCI_GPIRQ3 7 +#define SC520_PCI_GPIRQ4 8 +#define SC520_PCI_GPIRQ5 9 +#define SC520_PCI_GPIRQ6 10 +#define SC520_PCI_GPIRQ7 11 +#define SC520_PCI_GPIRQ8 12 +#define SC520_PCI_GPIRQ9 13 +#define SC520_PCI_GPIRQ10 14 + + + +/* PIC I/O mapped registers */ + +#define MPICIR 0x20 /* Master PIC Interrupt Request Register */ +#define MPICISR 0x20 /* Master PIC In-Service Register */ +#define MPICICW1 0x20 /* Master PIC Initialization Control Word 1 Register */ +#define MPICOCW2 0x20 /* Master PIC Operation Control Word 2 Register */ +#define MPICOCW3 0x20 /* Master PIC Operation Control Word 3 Register */ + +#define MPICICW2 0x21 /* Master PIC Initialization Control Word 2 Register */ +#define MPICICW3 0x21 /* Master PIC Initialization Control Word 3 Register */ +#define MPICICW4 0x21 /* Master PIC Initialization Control Word 4 Register */ +#define MPICINTMSK 0x21 /* Master PIC Interrupt Mask Register */ + +#define S2PICIR 0x24 /* Slave 2 PIC Interrupt Request Register */ +#define S2PICISR 0x24 /* Slave 2 PIC In-Service Register */ +#define S2PICICW1 0x24 /* Slave 2 PIC Initialization Control Word 1 Register */ +#define S2PICOCW2 0x24 /* Slave 2 PIC Operation Control Word 2 Register */ +#define S2PICOCW3 0x24 /* Slave 2 PIC Operation Control Word 3 Register */ + +#define S2PICICW2 0x25 /* Slave 2 PIC Initialization Control Word 2 Register */ +#define S2PICICW3 0x25 /* Slave 2 PIC Initialization Control Word 3 Register */ +#define S2PICICW4 0x25 /* Slave 2 PIC Initialization Control Word 4 Register */ +#define S2PICINTMSK 0x25 /* Slave 2 PIC Interrupt Mask Register */ + +#define S1PICIR 0xa0 /* Slave 1 PIC Interrupt Request Register */ +#define S1PICISR 0xa0 /* Slave 1 PIC In-Service Register */ +#define S1PICICW1 0xa0 /* Slave 1 PIC Initialization Control Word 1 Register */ +#define S1PICOCW2 0xa0 /* Slave 1 PIC Operation Control Word 2 Register */ +#define S1PICOCW3 0xa0 /* Slave 1 PIC Operation Control Word 3 Register */ + +#define S1PICICW2 0xa1 /* Slave 1 PIC Initialization Control Word 2 Register */ +#define S1PICICW3 0xa1 /* Slave 1 PIC Initialization Control Word 3 Register */ +#define S1PICICW4 0xa1 /* Slave 1 PIC Initialization Control Word 4 Register */ +#define S1PICINTMSK 0xa1 /* Slave 1 PIC Interrupt Mask Register */ + +/* +Programmable Interrupt Controller Register Bit Definitions +*/ + +/* Interrupt Control Register Bit Definitions */ + +#define NMI_DONE 0x80 /* NMI Routine Done */ +#define NMI_ENB 0x40 /* Master NMI Done */ +#define S2_GINT_MODE 0x04 /* Slave 2 PIC Global Interrupt Mode Enable */ +#define S1_GINT_MODE 0x02 /* Slave 1 PIC Global Interrupt Mode Enable */ +#define M_GINT_MODE 0x01 /* Master PIC Global Interrupt Mode Enable */ + +/* Master , SLAVEs 1&2 PIC Interrupt Mode Register Bit Definitions */ + +#define CH7_INT_MODE 0x80 /* PIC Channel 7 Interrupt Mode 0-edge 1-level */ +#define CH6_INT_MODE 0x40 /* PIC Channel 6 Interrupt Mode 0-edge 1-level */ +#define CH5_INT_MODE 0x20 /* PIC Channel 5 Interrupt Mode 0-edge 1-level */ +#define CH4_INT_MODE 0x10 /* PIC Channel 4 Interrupt Mode 0-edge 1-level */ +#define CH3_INT_MODE 0x08 /* PIC Channel 3 Interrupt Mode 0-edge 1-level */ +#define CH2_INT_MODE 0x04 /* PIC Channel 2 Interrupt Mode 0-edge 1-level */ +#define CH1_INT_MODE 0x02 /* PIC Channel 1 Interrupt Mode 0-edge 1-level */ +#define CH0_INT_MODE 0x01 /* PIC Channel 0 Interrupt Mode 0-edge 1-level */ + +/* Software Interrupt 16-1 Control Register Bit Definitions */ + +#define SW_P16_TRIG 0x8000 /* Directly Trigger Priority Level P16 0-don't assert int, 1-assert int*/ +#define SW_P15_TRIG 0x4000 /* Directly Trigger Priority Level P15 */ +#define SW_P14_TRIG 0x2000 /* Directly Trigger Priority Level P14 */ +#define SW_P13_TRIG 0x1000 /* Directly Trigger Priority Level P13 */ +#define SW_P12_TRIG 0x0800 /* Directly Trigger Priority Level P12 */ +#define SW_P11_TRIG 0x0400 /* Directly Trigger Priority Level P11 */ +#define SW_P10_TRIG 0x0200 /* Directly Trigger Priority Level P10 */ +#define SW_P9_TRIG 0x0100 /* Directly Trigger Priority Level P9 */ +#define SW_P8_TRIG 0x0080 /* Directly Trigger Priority Level P8 */ +#define SW_P7_TRIG 0x0040 /* Directly Trigger Priority Level P7 */ +#define SW_P6_TRIG 0x0020 /* Directly Trigger Priority Level P6 */ +#define SW_P5_TRIG 0x0010 /* Directly Trigger Priority Level P5 */ +#define SW_P4_TRIG 0x0008 /* Directly Trigger Priority Level P4 */ +#define SW_P3_TRIG 0x0004 /* Directly Trigger Priority Level P3 */ +#define SW_P2_TRIG 0x0002 /* Directly Trigger Priority Level P2 */ +#define SW_P1_TRIG 0x0001 /* Directly Trigger Priority Level P1 */ + +/* Software Interrupt 22-17/NMI Control Register Bit Defintions */ + +#define NMI_TRIG 0x0040 /* Software NMI Source */ +#define SW_P22_TRIG 0x0020 /* Directly Trigger Priority Level P22 */ +#define SW_P21_TRIG 0x0010 /* Directly Trigger Priority Level P21 */ +#define SW_P20_TRIG 0x0008 /* Directly Trigger Priority Level P20 */ +#define SW_P19_TRIG 0x0004 /* Directly Trigger Priority Level P19 */ +#define SW_P18_TRIG 0x0002 /* Directly Trigger Priority Level P18 */ +#define SW_P17_TRIG 0x0001 /* Directly Trigger Priority Level P17 */ + +/* Interrupt Pin Polarity Register Bit Definitions */ + +#define INTD_POL 0x8000 /* PCI Interrupt Request /INTD Polarity */ +#define INTC_POL 0x4000 /* PCI Interrupt Request /INTC Polarity */ +#define INTB_POL 0x2000 /* PCI Interrupt Request /INTB Polarity */ +#define INTA_POL 0x1000 /* PCI Interrupt Request /INTA Polarity */ + +#define GPINT10_POL 0x0400 /* General-Purpose Interrupt Request GPIRQ10 Polarity 0 - high to low, 1 low to high */ +#define GPINT9_POL 0x0200 /* General-Purpose Interrupt Request GPIRQ9 Polarity 0 - high to low, 1 low to high */ +#define GPINT8_POL 0x0100 /* General-Purpose Interrupt Request GPIRQ8 Polarity 0 - high to low, 1 low to high */ +#define GPINT7_POL 0x0080 /* General-Purpose Interrupt Request GPIRQ7 Polarity 0 - high to low, 1 low to high */ +#define GPINT6_POL 0x0040 /* General-Purpose Interrupt Request GPIRQ6 Polarity 0 - high to low, 1 low to high */ +#define GPINT5_POL 0x0020 /* General-Purpose Interrupt Request GPIRQ5 Polarity 0 - high to low, 1 low to high */ +#define GPINT4_POL 0x0010 /* General-Purpose Interrupt Request GPIRQ4 Polarity 0 - high to low, 1 low to high */ +#define GPINT3_POL 0x0008 /* General-Purpose Interrupt Request GPIRQ3 Polarity 0 - high to low, 1 low to high */ +#define GPINT2_POL 0x0004 /* General-Purpose Interrupt Request GPIRQ2 Polarity 0 - high to low, 1 low to high */ +#define GPINT1_POL 0x0002 /* General-Purpose Interrupt Request GPIRQ1 Polarity 0 - high to low, 1 low to high */ +#define GPINT0_POL 0x0001 /* General-Purpose Interrupt Request GPIRQ0 Polarity 0 - high to low, 1 low to high */ + +/* PCI Host Bridge Interrupt Mapping Register Bit Definitions */ + +#define PCI_NMI_ENB 0x0010 /* PCI Host Bridge NMI Enable */ + +#define PCI_IRQ_MAP_P0 0x0000 /* PCI Host Bridge Interrupt Mapping: Disable PCI interrupt from reaching PIC */ +#define PCI_IRQ_MAP_P1 0x0001 /* PCI Host Bridge Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/ +#define PCI_IRQ_MAP_P2 0x0002 /* PCI Host Bridge Interrupt Mapping: Priority P2 (Master PIC IR1)*/ +#define PCI_IRQ_MAP_P3 0x0003 /* PCI Host Bridge Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/ +#define PCI_IRQ_MAP_P4 0x0004 /* PCI Host Bridge Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/ +#define PCI_IRQ_MAP_P5 0x0005 /* PCI Host Bridge Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/ +#define PCI_IRQ_MAP_P6 0x0006 /* PCI Host Bridge Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/ +#define PCI_IRQ_MAP_P7 0x0007 /* PCI Host Bridge Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/ +#define PCI_IRQ_MAP_P8 0x0008 /* PCI Host Bridge Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/ +#define PCI_IRQ_MAP_P9 0x0009 /* PCI Host Bridge Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/ +#define PCI_IRQ_MAP_P10 0x000a /* PCI Host Bridge Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/ +#define PCI_IRQ_MAP_P11 0x000b /* PCI Host Bridge Interrupt Mapping: Priority P11 (Master PIC IR3)*/ +#define PCI_IRQ_MAP_P12 0x000c /* PCI Host Bridge Interrupt Mapping: Priority P12 (Master PIC IR4)*/ +#define PCI_IRQ_MAP_P13 0x000d /* PCI Host Bridge Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/ +#define PCI_IRQ_MAP_P14 0x000e /* PCI Host Bridge Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/ +#define PCI_IRQ_MAP_P15 0x000f /* PCI Host Bridge Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/ +#define PCI_IRQ_MAP_P16 0x0010 /* PCI Host Bridge Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/ +#define PCI_IRQ_MAP_P17 0x0011 /* PCI Host Bridge Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/ +#define PCI_IRQ_MAP_P18 0x0012 /* PCI Host Bridge Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/ +#define PCI_IRQ_MAP_P19 0x0013 /* PCI Host Bridge Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/ +#define PCI_IRQ_MAP_P20 0x0014 /* PCI Host Bridge Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/ +#define PCI_IRQ_MAP_P21 0x0015 /* PCI Host Bridge Interrupt Mapping: Priority P21 (Master PIC IR6)*/ +#define PCI_IRQ_MAP_P22 0x0016 /* PCI Host Bridge Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */ +#define PCI_IRQ_MAP_DA 0x0017 /* PCI Host Bridge Interrupt Mapping: disable internal-interrupt from reaching PIC*/ +#define PCI_IRQ_MAP_NMI 0x001F /* PCI Host Bridge Interrupt Mapping: NMI Source*/ + +/* ECC Interrupt Mapping Register Bit Definitions */ + +#define ECC_NMI_ENB 0x0100 /* ECC NMI Enable */ + +#define ECC_IRQ_MAP_P0 0x0000 /* SDRAM ECC Interrupt Mapping: Disable PCI interrupt from reaching PIC */ +#define ECC_IRQ_MAP_P1 0x0001 /* SDRAM ECC Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/ +#define ECC_IRQ_MAP_P2 0x0002 /* SDRAM ECC Interrupt Mapping: Priority P2 (Master PIC IR1)*/ +#define ECC_IRQ_MAP_P3 0x0003 /* SDRAM ECC Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/ +#define ECC_IRQ_MAP_P4 0x0004 /* SDRAM ECC Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/ +#define ECC_IRQ_MAP_P5 0x0005 /* SDRAM ECC Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/ +#define ECC_IRQ_MAP_P6 0x0006 /* SDRAM ECC Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/ +#define ECC_IRQ_MAP_P7 0x0007 /* SDRAM ECC Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/ +#define ECC_IRQ_MAP_P8 0x0008 /* SDRAM ECC Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/ +#define ECC_IRQ_MAP_P9 0x0009 /* SDRAM ECC Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/ +#define ECC_IRQ_MAP_P10 0x000a /* SDRAM ECC Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/ +#define ECC_IRQ_MAP_P11 0x000b /* SDRAM ECC Interrupt Mapping: Priority P11 (Master PIC IR3)*/ +#define ECC_IRQ_MAP_P12 0x000c /* SDRAM ECC Interrupt Mapping: Priority P12 (Master PIC IR4)*/ +#define ECC_IRQ_MAP_P13 0x000d /* SDRAM ECC Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/ +#define ECC_IRQ_MAP_P14 0x000e /* SDRAM ECC Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/ +#define ECC_IRQ_MAP_P15 0x000f /* SDRAM ECC Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/ +#define ECC_IRQ_MAP_P16 0x0010 /* SDRAM ECC Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/ +#define ECC_IRQ_MAP_P17 0x0011 /* SDRAM ECC Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/ +#define ECC_IRQ_MAP_P18 0x0012 /* SDRAM ECC Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/ +#define ECC_IRQ_MAP_P19 0x0013 /* SDRAM ECC Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/ +#define ECC_IRQ_MAP_P20 0x0014 /* SDRAM ECC Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/ +#define ECC_IRQ_MAP_P21 0x0015 /* SDRAM ECC Interrupt Mapping: Priority P21 (Master PIC IR6)*/ +#define ECC_IRQ_MAP_P22 0x0016 /* SDRAM ECC Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */ +#define ECC_IRQ_MAP_DA 0x0017 /* SDRAM ECC Interrupt Mapping: disable internal-interrupt from reaching PIC*/ + +/* Interrupt Mappings for GP TIMER 0 +GP TImer 1 +GP Timer 2 +PIT0 +PIT1 +PIT2 +UART 1 +UART 2 +PCI A +PCI B +PCI C +PCI D +DMA Buffer Chaining +SSI +WDT +RTC +Write-Protection Violation +AMDebug JTAG RX/TX +Floating Point Error +GPIRQ0 - QPIRQ10 +*/ + +#define INT_MAP_P0 0x0000 /* Interrupt Mapping: Disable PCI interrupt from reaching PIC */ +#define INT_MAP_P1 0x0001 /* Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/ +#define INT_MAP_P2 0x0002 /* Interrupt Mapping: Priority P2 (Master PIC IR1)*/ +#define INT_MAP_P3 0x0003 /* Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/ +#define INT_MAP_P4 0x0004 /* Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/ +#define INT_MAP_P5 0x0005 /* Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/ +#define INT_MAP_P6 0x0006 /* Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/ +#define INT_MAP_P7 0x0007 /* Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/ +#define INT_MAP_P8 0x0008 /* Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/ +#define INT_MAP_P9 0x0009 /* Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/ +#define INT_MAP_P10 0x000a /* Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/ +#define INT_MAP_P11 0x000b /* Interrupt Mapping: Priority P11 (Master PIC IR3)*/ +#define INT_MAP_P12 0x000c /* Interrupt Mapping: Priority P12 (Master PIC IR4)*/ +#define INT_MAP_P13 0x000d /* Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/ +#define INT_MAP_P14 0x000e /* Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/ +#define INT_MAP_P15 0x000f /* Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/ +#define INT_MAP_P16 0x0010 /* Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/ +#define INT_MAP_P17 0x0011 /* Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/ +#define INT_MAP_P18 0x0012 /* Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/ +#define INT_MAP_P19 0x0013 /* Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/ +#define INT_MAP_P20 0x0014 /* Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/ +#define INT_MAP_P21 0x0015 /* Interrupt Mapping: Priority P21 (Master PIC IR6)*/ +#define INT_MAP_P22 0x0016 /* Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */ +#define INT_MAP_DA 0x0017 /* Interrupt Mapping: disable internal-interrupt from reaching PIC*/ +#define INT_MAP_NMI 0x001F /* Interrupt Mapping: NMI Source*/ + +/* Master, SLAVE 1,2 PIC Interrupt Request Register Bit Definitions */ + +#define IR7 0x80 /* Interrupt Request 7 */ +#define IR6 0x40 /* Interrupt Request 6 */ +#define IR5 0x20 /* Interrupt Request 5 */ +#define IR4 0x10 /* Interrupt Request 4 */ +#define IR3 0x08 /* Interrupt Request 3 */ +#define IR2 0x04 /* Interrupt Request 2 */ +#define IR1 0x02 /* Interrupt Request 1 */ +#define IR0 0x01 /* Interrupt Request 0 */ + +/* Master, SLAVE 1,2 PIC In-Service Register Bit Definitions */ + +#define IS7 0x80 /* Interrupt Request 7 In-Service */ +#define IS6 0x40 /* Interrupt Request 6 In-Service */ +#define IS5 0x20 /* Interrupt Request 5 In-Service */ +#define IS4 0x10 /* Interrupt Request 4 In-Service */ +#define IS3 0x08 /* Interrupt Request 3 In-Service */ +#define IS2 0x04 /* Interrupt Request 2 In-Service */ +#define IS1 0x02 /* Interrupt Request 1 In-Service */ +#define IS0 0x01 /* Interrupt Request 0 In-Service */ + +/* Master PIC Initilization Control Word 1 Register Bit Definitions */ + +#define SLCT_ICW1 0x10 /* Select ICW1 */ +#define LTIM 0x08 /* Level-Triggered Interrupt Mode */ +#define ADI 0x04 /* Address Interval */ +#define SNGL 0x02 /* Single PIC */ +#define IC4 0x01 /* Initilization Control Word 4 */ + +/* Master PIC Operation Control Word 2 Register Bit Definitions */ + +#define R_SL_EOI_RAEOIC 0x00 /* Interrupt Request EOI and Priority Rotation Controls: Rotate in auto EOI mode (clear)*/ +#define R_SL_EOI_NEOI 0x20 /* Interrupt Request EOI and Priority Rotation Controls: Non-specific EOI */ +#define R_SL_EOI_NOP 0x40 /* Interrupt Request EOI and Priority Rotation Controls: NOP */ +#define R_SL_EOI_SEOI 0x60 /* Interrupt Request EOI and Priority Rotation Controls: Specific EOI */ +#define R_SL_EOI_RAEOIS 0x80 /* Interrupt Request EOI and Priority Rotation Controls: Rotate in auto EOI mode (set)*/ +#define R_SL_EOI_RONEOI 0xA0 /* Interrupt Request EOI and Priority Rotation Controls: Rotate on non-specific EOI command */ +#define R_SL_EOI_SPC 0xC0 /* Interrupt Request EOI and Priority Rotation Controls: Set Priority Command */ +#define R_SL_EOI_ROEOIC 0xE0 /* Interrupt Request EOI and Priority Rotation Controls: Rotate on specific EOI command */ + +#define IS_OCW3 0x08 /* Access is OCW3 */ + +#define LS_IR0 0x00 /* Specific EOI Level Select: IR0 */ +#define LS_IR1 0x01 /* Specific EOI Level Select: IR1 */ +#define LS_IR2 0x02 /* Specific EOI Level Select: IR2 */ +#define LS_IR3 0x03 /* Specific EOI Level Select: IR3 */ +#define LS_IR4 0x04 /* Specific EOI Level Select: IR4 */ +#define LS_IR5 0x05 /* Specific EOI Level Select: IR5 */ +#define LS_IR6 0x06 /* Specific EOI Level Select: IR6 */ +#define LS_IR7 0x07 /* Specific EOI Level Select: IR7 */ + +/* Master PIC Operation Control Word 3 */ + +#define ESMMSMM_NOP 0x00 /* Special Mask Mode: NOP */ +#define ESMMSMM_RSM 0x40 /* Special Mask Mode: Reset Special mask */ +#define ESMMSMM_SSM 0x60 /* Special Mask Mode: Set Special mask */ + +#define P 0x04 /* PIC Poll Command */ + +#define RRRIS_NC 0x00 /* Status Register Select: No change from last state */ +#define RRRIS_MPICIR 0x02 /* Status Register Select: Next Port 0020h read returns MPICIR register contents */ +#define RRRIS_MPICISR 0x03 /* Status Register Select: Next Port 0020h read returns MPICISR register contents */ + +/* Master PIC Intialization Control Word 2 Register Masks */ + +#define T7_T3 0xF8 /* Bits 7-3 of Base Interrupt Vector Number for this PIC */ +#define A10_A8 0x07 /* A10-A8 of Interrupt Vector */ + +/* Master PIC Intilization Control Word 3 Register Bit Definitions */ + +#define S7 0x80 /* Channel 7 Slave Cascade Select */ +#define S6 0x40 /* Channel 6 Slave Cascade Select */ +#define S5 0x20 /* Channel 5 Slave Cascade Select */ +#define S4 0x10 /* Channel 4 Slave Cascade Select */ +#define S3 0x08 /* Channel 3 Slave Cascade Select */ +#define S2 0x04 /* Channel 2 Slave Cascade Select */ +#define S1 0x02 /* Channel 1 Slave Cascade Select */ +#define S0 0x01 /* Channel 0 Slave Cascade Select */ + +/* Master PIC Initilization Control Word 4 Register Bit Definitions */ + +#define SFNM 0x10 /* Special Fully Nested Mode Enable */ +#define BUFMS_NBM 0x00 /* Buffered Mode and Master/Slave Select: Non-buffered mode */ +#define BUFMS_BMS 0x08 /* Buffered Mode and Master/Slave Select: Buffered Mode/slave */ +#define BUFMS_BMM 0x0C /* Buffered Mode and Master/Slave Select: Buffered mode/master */ + +#define AEOI 0x02 /* Automatic EOI Mode */ +#define PM 0x01 /* Microprocessor Mode */ + +/* Master, SLAVE 1,2 PIC Interrupt Mask Register Bit Definitions */ + +#define IM7 0x80 /* IR7 Mask */ +#define IM6 0x40 /* IR6 Mask */ +#define IM5 0x20 /* IR5 Mask */ +#define IM4 0x10 /* IR4 Mask */ +#define IM3 0x08 /* IR3 Mask */ +#define IM2 0x04 /* IR2 Mask */ +#define IM1 0x02 /* IR1 Mask */ +#define IM0 0x01 /* IR0 Mask */ + +/* other SLAVE1 and SLAVE2 PIC definitions have already been previously defined + just use the name of the bit as specified in the Register set manual */ + +/* Slave 1 PIC Initilization Control Word 3 Register Masks */ + +#define ID2_ID0 0x07 /* Slave 1 PIC ID 2-0 */ + +/********************************************** +* Reset Generation Registers * +**********************************************/ + +/* MMCR Registers */ + +#define OFFS_SYSINFO 0x0D70 /* System Board Information Register */ +#define OFFS_RESCFG 0x0D72 /* Reset Configuration Register */ +#define OFFS_RESSTA 0x0D74 /* Reset Status Register */ + +#define SYSINFO (MMCR + OFFS_SYSINFO) /* System Board Information Register */ +#define RESCFG (MMCR + OFFS_RESCFG) /* Reset Configuration Register */ +#define RESSTA (MMCR + OFFS_RESSTA) /* Reset Status Register */ + +/* I/O Mapped Registers */ + +#define SCPDATA 0x60 /* SCP DATA Port */ +#define SCPCMD 0x64 /* SCP Command Port */ +#define SYSCTLA 0x92 /* System Control Port A */ +#define FPUERRCLR 0xF0 /* FPU Error Interrupt Clear */ + +/* +Reset Generation Register Bit Definitions +*/ + +/* System Board Information Register Masks */ + +#define RST_ID 0xFF /* Reset Latched Input Data */ + +/* Reset Configuration Register Bit Definitions */ + +#define ICE_ON_RST 0x08 /* Enter AMDebug Mode on Next Reset */ +#define PRG_RST_ENB 0x04 /* Programmable Reset Enable */ +#define GP_RST 0x02 /* Software GP Bus Reset */ +#define SYS_RST 0x01 /* Software System Reset */ + +/* Reset Status Register Bit Definitions */ + +#define SCP_RST_DET 0x40 /* SCP Reset Detect */ +#define ICE_HRST_DET 0x20 /* AMDebug Utiliity Hard Reset Detect */ +#define ICE_SRST_DET 0x10 /* AMDebug Utility Sytem Reset Detect */ +#define WDT_RST_DET 0x08 /* WDT Reset Detect */ +#define SD_RST_DET 0x04 /* CPU Shutdown Reset Detect */ +#define PRGRST_DET 0x02 /* PRGRESET Detect */ +#define PWRGOOD_DET 0x01 /* POWERGOOD Reset Detect */ + +/* SCP Data Port Register Masks */ + +#define SCP_DATA 0xFF /* System Control Processor Data */ + +/* SCP Data Port Register Bit Definitions */ + +#define A20_GATE 0x02 /* A20 Gate Data */ +#define CPU_RST 0x01 /* CPU Reset Control */ + +/* SCP Command Port Register Masks */ + +#define SCP_CMD 0xFF /* SCP Command */ + +/* System Control Port A Register Bit Definitions */ + +#define A20G_CTL 0x02 /* A20 Gate Control */ +/* CPU_RST - Alternate CPU Core Reset Control, already defined */ + +/* Floating Point Error Interrupt Clear Register Mask */ + +#define FPUERR_RST 0xFF /* Clear FPU Error Interrupt Request */ + +/********************************** +* GP Bus DMA Controller Registers * +**********************************/ + +/* GP-DMA MMCR Registers */ + +#define OFFS_GPDMACTL 0x0D80 /* GP-DMa Control Register */ +#define OFFS_GPDMAMMIO 0x0D81 /* GP-DMA Memory-Mapped I/O Register */ +#define OFFS_GPDMAEXTCHMAPA 0x0D82 /* GP-DMA Resource Channel Map A */ +#define OFFS_GPDMAEXTCHMAPB 0x0D84 /* GP-DMA Resource Channel Map B */ +#define OFFS_GPDMAEXTPG0 0x0D86 /* GP-DMA Channel 0 Extended Page */ +#define OFFS_GPDMAEXTPG1 0x0D87 /* GP-DMA Channel 1 Extended Page */ +#define OFFS_GPDMAEXTPG2 0x0D88 /* GP-DMA Channel 2 Extended Page */ +#define OFFS_GPDMAEXTPG3 0x0D89 /* GP-DMA Channel 3 Extended Page */ +#define OFFS_GPDMAEXTPG5 0x0D8a /* GP-DMA Channel 5 Extended Page */ +#define OFFS_GPDMAEXTPG6 0x0D8b /* GP-DMA Channel 6 Extended Page */ +#define OFFS_GPDMAEXTPG7 0x0D8c /* GP-DMA Channel 7 Extended Page */ +#define OFFS_GPDMAEXTTC3 0x0D90 /* GP-DMA Channel 3 Extender Transfer count */ +#define OFFS_GPDMAEXTTC5 0x0D91 /* GP-DMA Channel 5 Extender Transfer count */ +#define OFFS_GPDMAEXTTC6 0x0D92 /* GP-DMA Channel 6 Extender Transfer count */ +#define OFFS_GPDMAEXTTC7 0x0D93 /* GP-DMA Channel 7 Extender Transfer count */ +#define OFFS_GPDMABCCTL 0x0D98 /* Buffer Chaining Control */ +#define OFFS_GPDMABCSTA 0x0D99 /* Buffer Chaining Status */ +#define OFFS_GPDMABSINTENB 0x0D9A /* Buffer Chaining Interrupt Enable */ +#define OFFS_GPDMABCVAL 0x0D9B /* Buffer Chaining Valid */ +#define OFFS_GPDMANXTADDL3 0x0DA0 /* GP-DMA Channel 3 Next Address Low */ +#define OFFS_GPDMANXTADDH3 0x0DA2 /* GP-DMA Channel 3 Next Address High */ +#define OFFS_GPDMANXTADDL5 0x0DA4 /* GP-DMA Channel 5 Next Address Low */ +#define OFFS_GPDMANXTADDH5 0x0DA6 /* GP-DMA Channel 5 Next Address High */ +#define OFFS_GPDMANXTADDL6 0x0DA8 /* GP-DMA Channel 6 Next Address Low */ +#define OFFS_GPDMANXTADDH6 0x0DAA /* GP-DMA Channel 6 Next Address High */ +#define OFFS_GPDMANXTADDL7 0x0DAC /* GP-DMA Channel 7 Next Address Low */ +#define OFFS_GPDMANXTADDH7 0x0DAE /* GP-DMA Channel 7 Next Address High */ +#define OFFS_GPDMANXTTCL3 0x0DB0 /* GP-DMA Channel 3 Next Transfer Count Low */ +#define OFFS_GPDMANXTTCH3 0x0DB2 /* GP-DMA Channel 3 Next Transfer Count High */ +#define OFFS_GPDMANXTTCL5 0x0DB4 /* GP-DMA Channel 5 Next Transfer Count Low */ +#define OFFS_GPDMANXTTCH5 0x0DB6 /* GP-DMA Channel 5 Next Transfer Count High */ +#define OFFS_GPDMANXTTCL6 0x0DB8 /* GP-DMA Channel 6 Next Transfer Count Low */ +#define OFFS_GPDMANXTTCH6 0x0DBA /* GP-DMA Channel 6 Next Transfer Count High */ +#define OFFS_GPDMANXTTCL7 0x0DBC /* GP-DMA Channel 7 Next Transfer Count Low */ +#define OFFS_GPDMANXTTCH7 0x0DBE /* GP-DMA Channel 7 Next Transfer Count High */ + +#define GPDMACTL (MMCR + OFFS_GPDMACTL) /* GP-DMa Control Register */ +#define GPDMAMMIO (MMCR + OFFS_GPDMAMMIO) /* GP-DMA Memory-Mapped I/O Register */ +#define GPDMAEXTCHMAPA (MMCR + OFFS_GPDMAEXTCHMAPA)/* GP-DMA Resource Channel Map A */ +#define GPDMAEXTCHMAPB (MMCR + OFFS_GPDMAEXTCHMAPB)/* GP-DMA Resource Channel Map B */ +#define GPDMAEXTPG0 (MMCR + OFFS_GPDMAEXTPG0) /* GP-DMA Channel 0 Extended Page */ +#define GPDMAEXTPG1 (MMCR + OFFS_GPDMAEXTPG1) /* GP-DMA Channel 1 Extended Page */ +#define GPDMAEXTPG2 (MMCR + OFFS_GPDMAEXTPG2) /* GP-DMA Channel 2 Extended Page */ +#define GPDMAEXTPG3 (MMCR + OFFS_GPDMAEXTPG3) /* GP-DMA Channel 3 Extended Page */ +#define GPDMAEXTPG5 (MMCR + OFFS_GPDMAEXTPG5) /* GP-DMA Channel 5 Extended Page */ +#define GPDMAEXTPG6 (MMCR + OFFS_GPDMAEXTPG6) /* GP-DMA Channel 6 Extended Page */ +#define GPDMAEXTPG7 (MMCR + OFFS_GPDMAEXTPG7) /* GP-DMA Channel 7 Extended Page */ +#define GPDMAEXTTC3 (MMCR + OFFS_GPDMAEXTTC3) /* GP-DMA Channel 3 Extender Transfer count */ +#define GPDMAEXTTC5 (MMCR + OFFS_GPDMAEXTTC5) /* GP-DMA Channel 5 Extender Transfer count */ +#define GPDMAEXTTC6 (MMCR + OFFS_GPDMAEXTTC6) /* GP-DMA Channel 6 Extender Transfer count */ +#define GPDMAEXTTC7 (MMCR + OFFS_GPDMAEXTTC7) /* GP-DMA Channel 7 Extender Transfer count */ +#define GPDMABCCTL (MMCR + OFFS_GPDMABCCTL) /* Buffer Chaining Control */ +#define GPDMABCSTA (MMCR + OFFS_GPDMABCSTA) /* Buffer Chaining Status */ +#define GPDMABSINTENB (MMCR + OFFS_GPDMABSINTENB) /* Buffer Chaining Interrupt Enable */ +#define GPDMABCVAL (MMCR + OFFS_GPDMABCVAL) /* Buffer Chaining Valid */ +#define GPDMANXTADDL3 (MMCR + OFFS_GPDMANXTADDL3) /* GP-DMA Channel 3 Next Address Low */ +#define GPDMANXTADDH3 (MMCR + OFFS_GPDMANXTADDH3) /* GP-DMA Channel 3 Next Address High */ +#define GPDMANXTADDL5 (MMCR + OFFS_GPDMANXTADDL5) /* GP-DMA Channel 5 Next Address Low */ +#define GPDMANXTADDH5 (MMCR + OFFS_GPDMANXTADDH5) /* GP-DMA Channel 5 Next Address High */ +#define GPDMANXTADDL6 (MMCR + OFFS_GPDMANXTADDL6) /* GP-DMA Channel 6 Next Address Low */ +#define GPDMANXTADDH6 (MMCR + OFFS_GPDMANXTADDH6) /* GP-DMA Channel 6 Next Address High */ +#define GPDMANXTADDL7 (MMCR + OFFS_GPDMANXTADDL7) /* GP-DMA Channel 7 Next Address Low */ +#define GPDMANXTADDH7 (MMCR + OFFS_GPDMANXTADDH7) /* GP-DMA Channel 7 Next Address High */ +#define GPDMANXTTCL3 (MMCR + OFFS_GPDMANXTTCL3) /* GP-DMA Channel 3 Next Transfer Count Low */ +#define GPDMANXTTCH3 (MMCR + OFFS_GPDMANXTTCH3) /* GP-DMA Channel 3 Next Transfer Count High */ +#define GPDMANXTTCL5 (MMCR + OFFS_GPDMANXTTCL5) /* GP-DMA Channel 5 Next Transfer Count Low */ +#define GPDMANXTTCH5 (MMCR + OFFS_GPDMANXTTCH5) /* GP-DMA Channel 5 Next Transfer Count High */ +#define GPDMANXTTCL6 (MMCR + OFFS_GPDMANXTTCL6) /* GP-DMA Channel 6 Next Transfer Count Low */ +#define GPDMANXTTCH6 (MMCR + OFFS_GPDMANXTTCH6) /* GP-DMA Channel 6 Next Transfer Count High */ +#define GPDMANXTTCL7 (MMCR + OFFS_GPDMANXTTCL7) /* GP-DMA Channel 7 Next Transfer Count Low */ +#define GPDMANXTTCH7 (MMCR + OFFS_GPDMANXTTCH7) /* GP-DMA Channel 7 Next Transfer Count High */ + +/* GP-DMA Direct-Mapped Registers */ + +#define GPDMA0MAR 0x0000 /* Slave DMA Channel 0 Memory Address */ +#define GPDMA0TC 0x0001 /* Slave DMA Channel 0 Transfer Count */ +#define GPDMA1MAR 0x0002 /* Slave DMA Channel 1 Memory Address */ +#define GPDMA1TC 0x0003 /* Slave DMA Channel 1 Transfer Count */ +#define GPDMA2MAR 0x0004 /* Slave DMA Channel 2 Memory Address */ +#define GPDMA2TC 0x0005 /* Slave DMA Channel 2 Transfer Count */ +#define GPDMA3MAR 0x0006 /* Slave DMA Channel 3 Memory Address */ +#define GPDMA3TC 0x0007 /* Slave DMA Channel 3 Transfer Count */ +#define SLDMASTA 0x0008 /* Slave DMA Channel 0-3 Status */ +#define SLDMACTL 0x0008 /* Slave DMA Channel 0-3 Control */ +#define SLDMASWREQ 0x0009 /* Slave Software DRQ(n) Request */ +#define SLDMAMSK 0x000A /* Slave DMA Channel 0-3 Mask */ +#define SLDMAMODE 0x000B /* Slave DMA Channel 0-3 Mode */ +#define SLDMACBP 0x000C /* Slave DMA Clear Byte Pointer */ +#define SLDMARST 0x000D /* Slave DMA Controller Reset */ +#define SLDMATMP 0x000D /* Slave DMA Controller Temporary */ +#define SLDMAMSKRST 0x000E /* Slave DMA Mask Reset */ +#define SLDMAGENMSK 0x000F /* Slave DMA General Mask */ +#define GPDMAGR0 0x0080 /* General 0 */ +#define GPDMA2PG 0x0081 /* Slave DMA Channel 2 Page */ +#define GPDMA3PG 0x0082 /* Slave DMA Channel 3 Page */ +#define GPDMA1PG 0x0083 /* Slave DMA Channel 1 Page */ +#define GPDMAGR1 0x0084 /* General 1 */ +#define GPDMAGR2 0x0085 /* General 2 */ +#define GPDMAGR3 0x0086 /* General 3 */ +#define GPDMA0PG 0x0087 /* Slave DMA Channel 0 Page */ +#define GPDMAGR4 0x0088 /* General 4 */ +#define GPDMA6PG 0x0089 /* Master DMA Channel 6 Page */ +#define GPDMA7PG 0x008a /* Master DMA Channel 7 Page */ +#define GPDMA5PG 0x008b /* Master DMA Channel 5 Page */ +#define GPDMAGR5 0x008c /* General 5 */ +#define GPDMAGR6 0x008d /* General 6 */ +#define GPDMAGR7 0x008e /* General 7 */ +#define GPDMAGR8 0x008f /* General 8 */ +#define GPDMA4MAR 0x00c0 /* Master DMA Channel 4 Memory Address */ +#define GPDMA4TC 0x00c2 /* Master DMA Channel 4 Transfer Count */ +#define GPDMA5MAR 0x00c4 /* Master DMA Channel 5 Memory Address */ +#define GPDMA5TC 0x00c6 /* Master DMA Channel 5 Transfer Count */ +#define GPDMA6MAR 0x00c8 /* Master DMA Channel 6 Memory Address */ +#define GPDMA6TC 0x00cc /* Master DMA Channel 6 Transfer Count */ +#define GPDMA7MAR 0x00ce /* Master DMA Channel 7 Memory Address */ +#define GPDMA7TC 0x00c2 /* Master DMA Channel 7 Transfer Count */ +#define MSTDMASTA 0x00d0 /* Master DMA Channel 4-7 Status */ +#define MSTDMACTL 0x00d0 /* Master DMA Channel 4-7 Control */ +#define MSTDMASWREQ 0x00d2 /* Master Software DRQ(n) Request */ +#define MSTDMAMSK 0x00d4 /* Master DMA Channel 4-7 Mask */ +#define MSTDMAMODE 0x00d6 /* Master DMA Channel 4-7 mode */ +#define MSTDMACBP 0x00d8 /* Master DMA Clear Byte Pointer */ +#define MSTDMARST 0x00da /* Master DMA Controller Reset */ +#define MSTDMATMP 0x00da /* Master DMA Temporary */ +#define MSTDMAMSKRST 0x00dc /* Master DMA Mask Reset */ +#define MSTDMAGENMSK 0x00de /* Master DMA General Mask */ + +/* +GP Bus DMA Controller Register Bit Definitions +*/ + +/* GP-DMA Control Register Bit Definitions */ + +#define CH7_ALT_SIZE 0x80 /* Alternate Size for Channel 7 */ +#define CH6_ALT_SIZE 0x40 /* Alternate Size for Channel 6 */ +#define CH5_ALT_SIZE 0x20 /* Alternate Size for Channel 5 */ +#define CH3_ALT_SIZE 0x10 /* Alternate Size for Channel 3 */ + +#define CLK_MODE_4MHZ 0x00 /* Clock Mode: GP Bus Controller at 4Mhz */ +#define CLK_MODE_8MHZ 0x04 /* Clock Mode: GP Bus Controller at 8Mhz */ +#define CLK_MODE_16MHZ 0x08 /* Clock Mode: GP Bus Controller at 16Mhz */ + +#define ENH_MODE_ENB 0x01 /* Enhanced Mode Enable */ + +/* GP-DMA Memory-Mapped I/O Register Bit Definitions */ + +#define DMA7_MMAP 0x80 /* Memory-Mapped Device for DMA Channel 7 */ +#define DMA6_MMAP 0x40 /* Memory-Mapped Device for DMA Channel 6 */ +#define DMA5_MMAP 0x20 /* Memory-Mapped Device for DMA Channel 5 */ +#define DMA3_MMAP 0x08 /* Memory-Mapped Device for DMA Channel 3 */ +#define DMA2_MMAP 0x04 /* Memory-Mapped Device for DMA Channel 2 */ +#define DMA1_MMAP 0x02 /* Memory-Mapped Device for DMA Channel 1 */ +#define DMA0_MMAP 0x01 /* Memory-Mapped Device for DMA Channel 0 */ + +/* GP-DMA Resource Channel Map A Register Bit Definitions */ + +#define GPDRQ3_CHSEL_0 0x0000 /* GPDRQ3 Channel Mapping: Channel 0 */ +#define GPDRQ3_CHSEL_1 0x1000 /* GPDRQ3 Channel Mapping: Channel 1 */ +#define GPDRQ3_CHSEL_2 0x2000 /* GPDRQ3 Channel Mapping: Channel 2 */ +#define GPDRQ3_CHSEL_3 0x3000 /* GPDRQ3 Channel Mapping: Channel 3 */ +#define GPDRQ3_CHSEL_5 0x5000 /* GPDRQ3 Channel Mapping: Channel 5 */ +#define GPDRQ3_CHSEL_6 0x6000 /* GPDRQ3 Channel Mapping: Channel 6 */ +#define GPDRQ3_CHSEL_7 0x7000 /* GPDRQ3 Channel Mapping: Channel 7 */ + +#define GPDRQ2_CHSEL_0 0x0000 /* GPDRQ2 Channel Mapping: Channel 0 */ +#define GPDRQ2_CHSEL_1 0x0100 /* GPDRQ2 Channel Mapping: Channel 1 */ +#define GPDRQ2_CHSEL_2 0x0200 /* GPDRQ2 Channel Mapping: Channel 2 */ +#define GPDRQ2_CHSEL_3 0x0300 /* GPDRQ2 Channel Mapping: Channel 3 */ +#define GPDRQ2_CHSEL_5 0x0500 /* GPDRQ2 Channel Mapping: Channel 5 */ +#define GPDRQ2_CHSEL_6 0x0600 /* GPDRQ2 Channel Mapping: Channel 6 */ +#define GPDRQ2_CHSEL_7 0x0700 /* GPDRQ2 Channel Mapping: Channel 7 */ + +#define GPDRQ1_CHSEL_0 0x0000 /* GPDRQ1 Channel Mapping: Channel 0 */ +#define GPDRQ1_CHSEL_1 0x0010 /* GPDRQ1 Channel Mapping: Channel 1 */ +#define GPDRQ1_CHSEL_2 0x0020 /* GPDRQ1 Channel Mapping: Channel 2 */ +#define GPDRQ1_CHSEL_3 0x0030 /* GPDRQ1 Channel Mapping: Channel 3 */ +#define GPDRQ1_CHSEL_5 0x0050 /* GPDRQ1 Channel Mapping: Channel 5 */ +#define GPDRQ1_CHSEL_6 0x0060 /* GPDRQ1 Channel Mapping: Channel 6 */ +#define GPDRQ1_CHSEL_7 0x0070 /* GPDRQ1 Channel Mapping: Channel 7 */ + +#define GPDRQ0_CHSEL_0 0x0000 /* GPDRQ0 Channel Mapping: Channel 0 */ +#define GPDRQ0_CHSEL_1 0x0001 /* GPDRQ0 Channel Mapping: Channel 1 */ +#define GPDRQ0_CHSEL_2 0x0002 /* GPDRQ0 Channel Mapping: Channel 2 */ +#define GPDRQ0_CHSEL_3 0x0003 /* GPDRQ0 Channel Mapping: Channel 3 */ +#define GPDRQ0_CHSEL_5 0x0005 /* GPDRQ0 Channel Mapping: Channel 5 */ +#define GPDRQ0_CHSEL_6 0x0006 /* GPDRQ0 Channel Mapping: Channel 6 */ +#define GPDRQ0_CHSEL_7 0x0007 /* GPDRQ0 Channel Mapping: Channel 7 */ + +/* GP-DMA Resource Channel Map B Register Bit Definitions */ + +#define TXDRQ3_CHSEL_0 0x0000 /* TXDRQ3 Channel Mapping: Channel 0 */ +#define TXDRQ3_CHSEL_1 0x1000 /* TXDRQ3 Channel Mapping: Channel 1 */ +#define TXDRQ3_CHSEL_2 0x2000 /* TXDRQ3 Channel Mapping: Channel 2 */ +#define TXDRQ3_CHSEL_3 0x3000 /* TXDRQ3 Channel Mapping: Channel 3 */ + +#define TXDRQ2_CHSEL_0 0x0000 /* TXDRQ2 Channel Mapping: Channel 0 */ +#define TXDRQ2_CHSEL_1 0x0100 /* TXDRQ2 Channel Mapping: Channel 1 */ +#define TXDRQ2_CHSEL_2 0x0200 /* TXDRQ2 Channel Mapping: Channel 2 */ +#define TXDRQ2_CHSEL_3 0x0300 /* TXDRQ2 Channel Mapping: Channel 3 */ + +#define TXDRQ1_CHSEL_0 0x0000 /* TXDRQ1 Channel Mapping: Channel 0 */ +#define TXDRQ1_CHSEL_1 0x0010 /* TXDRQ1 Channel Mapping: Channel 1 */ +#define TXDRQ1_CHSEL_2 0x0020 /* TXDRQ1 Channel Mapping: Channel 2 */ +#define TXDRQ1_CHSEL_3 0x0030 /* TXDRQ1 Channel Mapping: Channel 3 */ + +#define TXDRQ0_CHSEL_0 0x0000 /* TXDRQ0 Channel Mapping: Channel 0 */ +#define TXDRQ0_CHSEL_1 0x0001 /* TXDRQ0 Channel Mapping: Channel 1 */ +#define TXDRQ0_CHSEL_2 0x0002 /* TXDRQ0 Channel Mapping: Channel 2 */ +#define TXDRQ0_CHSEL_3 0x0003 /* TXDRQ0 Channel Mapping: Channel 3 */ + +/* GP-DMA Channel 0 Extended Page Register Masks */ + +#define DMA0ADR 0x0F /* GP-DMA Channel 0 Extended Page Address */ + +/* GP-DMA Channel 1 Extended Page Register Masks */ + +#define DMA1ADR 0x0F /* GP-DMA Channel 1 Extended Page Address */ + +/* GP-DMA Channel 2 Extended Page Register Masks */ + +#define DMA2ADR 0x0F /* GP-DMA Channel 2 Extended Page Address */ + +/* GP-DMA Channel 3 Extended Page Register Masks */ + +#define DMA3ADR 0x0F /* GP-DMA Channel 3 Extended Page Address */ + +/* GP-DMA Channel 5 Extended Page Register Masks */ + +#define DMA5ADR 0x0F /* GP-DMA Channel 5 Extended Page Address */ + +/* GP-DMA Channel 6 Extended Page Register Masks */ + +#define DMA6ADR 0x0F /* GP-DMA Channel 6 Extended Page Address */ + +/* GP-DMA Channel 7 Extended Page Register Masks */ + +#define DMA7ADR 0x0F /* GP-DMA Channel 7 Extended Page Address */ + +/* GP-DMA Channel 3 Extended Transfer Count Register Masks */ + +#define DMA3TC 0xFF /* GP-DMA Channel 3 Transfer Count Extension */ + +/* GP-DMA Channel 5 Extended Transfer Count Register Masks */ + +#define DMA5TC 0xFF /* GP-DMA Channel 5 Transfer Count Extension */ + +/* GP-DMA Channel 6 Extended Transfer Count Register Masks */ + +#define DMA6TC 0xFF /* GP-DMA Channel 6 Transfer Count Extension */ + +/* GP-DMA Channel 7 Extended Transfer Count Register Masks */ + +#define DMA7TC 0xFF /* GP-DMA Channel 7 Transfer Count Extension */ + +/* Buffer Chaining Control Register Bit Definitions */ + +#define CH7_BCHN_ENB 0x08 /* Buffer Chaining Enable for Channel 7 */ +#define CH6_BCHN_ENB 0x04 /* Buffer Chaining Enable for Channel 6 */ +#define CH5_BCHN_ENB 0x02 /* Buffer Chaining Enable for Channel 5 */ +#define CH3_BCHN_ENB 0x01 /* Buffer Chaining Enable for Channel 3 */ + +/* Buffer Chaining Status Register Bit Definitions */ + +#define CH7_EOB_STA 0x08 /* End of Current Buffer in Channel 7 */ +#define CH6_EOB_STA 0x04 /* End of Current Buffer in Channel 6 */ +#define CH5_EOB_STA 0x02 /* End of Current Buffer in Channel 5 */ +#define CH3_EOB_STA 0x01 /* End of Current Buffer in Channel 3 */ + +/* Buffer Chaining Interrupt Enable Register Bit Definitions */ + +#define CH7_INT_ENB 0x08 /* Interrupt Enable for Channel 7 */ +#define CH6_INT_ENB 0x04 /* Interrupt Enable for Channel 6 */ +#define CH5_INT_ENB 0x02 /* Interrupt Enable for Channel 5 */ +#define CH3_INT_ENB 0x01 /* Interrupt Enable for Channel 3 */ + +/* Buffer Chaining Valid Register Bit Definitions */ + +#define CH7_CBUF_VAL 0x08 /* Chaining Buffer Valid for Channel 7 */ +#define CH6_CBUF_VAL 0x04 /* Chaining Buffer Valid for Channel 6 */ +#define CH5_CBUF_VAL 0x02 /* Chaining Buffer Valid for Channel 5 */ +#define CH3_CBUF_VAL 0x01 /* Chaining Buffer Valid for Channel 3 */ + +/* GP-DMA Channel 3 Next Address Low Register Masks */ + +#define DMA3_NXT_ADRL 0xFFFF /* GP-DMA Channel 3 Next Address Low*/ + +/* GP-DMA Channel 3 Next Address High Register Masks */ + +#define DMA3_NXT_ADRH 0x0FFF /* GP-DMA Channel 3 Next Address High */ + +/* GP-DMA Channel 5 Next Address Low Register Masks */ + +#define DMA5_NXT_ADRL 0xFFFF /* GP-DMA Channel 5 Next Address Low */ + +/* GP-DMA Channel 5 Next Address High Register Masks */ + +#define DMA5_NXT_ADRH 0x0FFF /* GP-DMA Channel 5 Next Address High */ + +/* GP-DMA Channel 6 Next Address Low Register Masks */ + +#define DMA6_NXT_ADRL 0xFFFF /* GP-DMA Channel 6 Next Address Low */ + +/* GP-DMA Channel 6 Next Address High Register Masks */ + +#define DMA6_NXT_ADRH 0x0FFF /* GP-DMA Channel 6 Next Address High */ + +/* GP-DMA Channel 7 Next Address Low Register Masks */ + +#define DMA7_NXT_ADRL 0xFFFF /* GP-DMA Channel 7 Next Address Low */ + +/* GP-DMA Channel 7 Next Address High Register Masks */ + +#define DMA7_NXT_ADRH 0x0FFF /* GP-DMA Channel 7 Next Address High */ + + +/* GP-DMA Channel 3 Next Transfer Count Low Register Masks */ + +#define DMA3_NXT_TCL 0xFFFF /* GP-DMA Channel 3 Next Transfer Count Low*/ + +/* GP-DMA Channel 3 Next Transfer Count High Register Masks */ + +#define DMA3_NXT_TCH 0xFF /* GP-DMA Channel 3 Next Transfer Count High*/ + +/* GP-DMA Channel 5 Next Transfer Count Low Register Masks */ + +#define DMA5_NXT_TCL 0xFFFF /* GP-DMA Channel 5 Next Transfer Count Low */ + +/* GP-DMA Channel 5 Next Transfer Count High Register Masks */ + +#define DMA5_NXT_TCH 0xFF /* GP-DMA Channel 5 Next Transfer Count High*/ + +/* GP-DMA Channel 6 Next Transfer Count Low Register Masks */ + +#define DMA6_NXT_TCL 0xFFFF /* GP-DMA Channel 6 Next Transfer Count Low */ + +/* GP-DMA Channel 6 Next Transfer Count High Register Masks */ + +#define DMA6_NXT_TCH 0xFF /* GP-DMA Channel 6 Next Transfer Count High*/ + +/* GP-DMA Channel 7 Next Transfer Count Low Register Masks */ + +#define DMA7_NXT_TCL 0xFFFF /* GP-DMA Channel 7 Next Transfer Count Low */ + +/* GP-DMA Channel 7 Next Transfer Count High Register Masks */ + +#define DMA7_NXT_TCH 0xFF /* GP-DMA Channel 7 Next Transfer Count High*/ + +/* Slave DMA Channel 0 Memory Address Register Masks */ + +#define DMA0MAR 0xFF /* Lower 16 Bits of DMA Channel 0 Memory Address */ + +/* Slave DMA Channel 0 Transfer Count Register Masks */ + +#define DMA0TC 0xFF /* DMA Channel 0 Transfer Count */ + +/* Slave DMA Channel 1 Memory Address Register Masks */ + +#define DMA1MAR 0xFF /* Lower 16 Bits of DMA Channel 1 Memory Address */ + +/* Slave DMA Channel 1 Transfer Count Register Masks */ + +#define DMA1TC 0xFF /* DMA Channel 1 Transfer Count */ + +/* Slave DMA Channel 2 Memory Address Register Masks */ + +#define DMA2MAR 0xFF /* Lower 16 Bits of DMA Channel 2 Memory Address */ + +/* Slave DMA Channel 2 Transfer Count Register Masks */ + +#define DMA2TC 0xFF /* DMA Channel 2 Transfer Count */ + +/* Slave DMA Channel 3 Memory Address Register Masks */ + +#define DMA3MAR 0xFF /* Lower 16 Bits of DMA Channel 3 Memory Address */ + +/* Slave DMA Channel 3 Transfer Count Register Masks */ + +#define DMA3TC 0xFF /* DMA Channel 3 Transfer Count */ + +/* Slave DMA Channel 0-3 Status Register Bit Definitions */ + +#define DMAR3 0x80 /* Channel 3 DMA Request */ +#define DMAR2 0x40 /* Channel 2 DMA Request */ +#define DMAR1 0x20 /* Channel 1 DMA Request */ +#define DMAR0 0x10 /* Channel 0 DMA Request */ + +#define TC3 0x08 /* Channel 3 Terminal Count */ +#define TC2 0x04 /* Channel 2 Terminal Count */ +#define TC1 0x02 /* Channel 1 Terminal Count */ +#define TC0 0x01 /* Channel 0 Terminal Count */ + +/* Slave DMA Channel 0-3 Control Register Bit Definitions */ + +#define DAKSEN 0x80 /* Internal /DACKX Sense */ +#define DRQSEN 0x40 /* Internal drqx Sense */ +#define WRTSEL 0x20 /* Write Selection Control */ +#define PRITYPE 0x10 /* Priority Type */ +#define COMPTIM 0x08 /* Compressed Timing */ +#define DMA_DIS 0x04 /* Disable DMA Controller */ + +/* Slave Software DRQ(n) Request Register Bit Definitions */ + +#define REQDMA 0x04 /* Software DMA Request */ + +#define REQSEL_CH0 0x00 /* DMA Channel Select: channel 0 */ +#define REQSEL_CH1 0x01 /* DMA Channel Select: channel 1 */ +#define REQSEL_CH2 0x02 /* DMA Channel Select: channel 2 */ +#define REQSEL_CH3 0x03 /* DMA Channel Select: channel 3 */ + +/* Slave DMA Channel 0-3 Mask Register Bit Definitions */ + +#define CHMASK 0x40 /* DMA Channel Mask */ + +#define MSKSEL_CH0 0x00 /* DMA Channel Mask Select: channel 0 */ +#define MSKSEL_CH1 0x01 /* DMA Channel Mask Select: channel 1 */ +#define MSKSEL_CH2 0x02 /* DMA Channel Mask Select: channel 2 */ +#define MSKSEL_CH3 0x03 /* DMA Channel Mask Select: channel 3 */ + +/* Slave DMA Channel 0-3 Mode Register Bit Definitions */ + +#define TRNMOD_DTM 0x00 /* Transfer Mode: Demand transfer */ +#define TRNMOD_STM 0x40 /* Transfer Mode: Single transfer */ +#define TRNMOD_BTM 0x80 /* Transfer Mode: Block transfer */ +#define TRNMOD_CM 0xC0 /* Transfer Mode: Cascade Mode */ + +#define ADDDEC 0x20 /* Address Decrement */ +#define AINIT 0x10 /* Automatic Initilization Control */ + +#define OPSEL_VM 0x00 /* Operation Select: Verify Mode */ +#define OPSEL_WT 0x40 /* Operation Select: Write Transfer Mode */ +#define OPSEL_RT 0x80 /* Operation Select: Read Transfer Mode */ + +#define MODSEL_CH0 0x00 /* DMA Channel Select:channel 0 */ +#define MODSEL_CH1 0x01 /* DMA Channel Select:channel 1 */ +#define MODSEL_CH2 0x02 /* DMA Channel Select:channel 2 */ +#define MODSEL_CH30 0x03 /* DMA Channel Select:channel 3 */ + +/* Slave DMA Clear Byte Pointer Register Masks */ + +#define SLAVE_CBP 0xFF /* Slave DMA Clear Byte Pointer */ + +/* Slave DMA Controller Reset Register Masks */ + +#define SLAVE_RST 0xFF /* Slave DMA Controller Reset */ + +/* Slave DMA Controller Temporary Register Masks */ + +#define SLAVE_TMP 0xFF /* Slave DMa Controller Temporary Register */ + +/* Slave DMA Mask Reset Register Masks */ + +#define SLAVE_MSK_RST 0xFF /* Slave DMA Reset Mask */ + +/* Slave DMA General Mask Register Bit Definitions */ + +#define CH3_DIS 0x08 /* DMA Channel 3 Mask */ +#define CH2_DIS 0x04 /* DMA Channel 2 Mask */ +#define CH1_DIS 0x02 /* DMA Channel 1 Mask */ +#define CH0_DIS 0x01 /* DMA Channel 0 Mask */ + +/* General 0 Register Masks */ + +#define PORT80 0xFF /* General Purpose R/W Register */ + +/* Slave DMA Channel 2 Page Register Masks */ + +#define DMA2MAR 0xFF /* DMA Channel 2 Memory Address Bits [23-16] */ + +/* Slave DMA Channel 3 Page Register Masks */ + +#define DMA3MAR 0xFF /* DMA Channel 3 Memory Address Bits [23-16] */ + +/* Slave DMA Channel 1 Page Register Masks */ + +#define DMA1MAR 0xFF /* DMA Channel 1 Memory Address Bits [23-16] */ + +/* General 1 Register Masks */ + +#define PORT84 0xFF /* General Purpose R/W Register */ + +/* General 2 Register Masks */ + +#define PORT85 0xFF /* General Purpose R/W Register */ + +/* General 3 Register Masks */ + +#define PORT86 0xFF /* General Purpose R/W Register */ + +/* Slave DMA Channel 0 Page Register Masks */ + +#define DMA0MAR 0xFF /* DMA Channel 0 Memory Address Bits [23-16] */ + +/* General 4 Register Masks */ + +#define PORT88 0xFF /* General Purpose R/W Register */ + + + +/* Master DMA Channel 6 Page Register Masks */ + +#define DMA6MAR_H 0xFE /* DMA Channel 6 Memory Address Bits [23-17] */ + +/* Master DMA Channel 7 Page Register Masks */ + +#define DMA7MAR_H 0xFE /* DMA Channel 7 Memory Address Bits [23-17] */ + +/* Master DMA Channel 5 Page Register Masks */ + +#define DMA5MAR_H 0xFE /* DMA Channel 5 Memory Address Bits [23-17] */ + +/* General 5 Register Masks */ + +#define PORT8C 0xFF /* General Purpose R/W Register */ + +/* General 6 Register Masks */ + +#define PORT8D 0xFF /* General Purpose R/W Register */ + +/* General 7 Register Masks */ + +#define PORT8E 0xFF /* General Purpose R/W Register */ + +/* General 8 Register Masks */ + +#define PORT8F 0xFF /* General Purpose R/W Register */ + +/* Master DMA Channel 4 Memory Address Register Masks */ + +#define DMA4MAR 0xFF /* DMA Channel 4 Memory Address */ + +/* Master DMA Channel 4 Transfer Count Register Masks */ + +#define DMA4TC 0xFF /* DMA Channel 4 Transfer Count */ + +/* Master DMA Channel 5 Memory Address Register Masks */ + +#define DMA5MAR 0xFF /* DMA Channel 5 Memory Address */ + +/* Master DMA Channel 5 Transfer Count Register Masks */ + +#define DMA5TC 0xFF /* DMA Channel 5 Transfer Count */ + +/* Master DMA Channel 6 Memory Address Register Masks */ + +#define DMA6MAR 0xFF /* DMA Channel 6 Memory Address */ + +/* Master DMA Channel 6 Transfer Count Register Masks */ + +#define DMA6TC 0xFF /* DMA Channel 6 Transfer Count */ + +/* Master DMA Channel 7 Memory Address Register Masks */ + +#define DMA7MAR 0xFF /* DMA Channel 7 Memory Address */ + +/* Master DMA Channel 7 Transfer Count Register Masks */ + +#define DMA7TC 0xFF /* DMA Channel 7 Transfer Count */ + +/* Master DMA Channel 4-7 Status Register Bit Definitions */ + +#define DMAR7 0x80 /* Channel 7 DMA Request */ +#define DMAR6 0x40 /* Channel 6 DMA Request */ +#define DMAR5 0x20 /* Channel 5 DMA Request */ +#define DMAR4 0x10 /* Channel 4 DMA Request */ + +#define TC7 0x08 /* Channel 7 Terminal Count */ +#define TC6 0x04 /* Channel 6 Terminal Count */ +#define TC5 0x02 /* Channel 5 Terminal Count */ +#define TC4 0x01 /* Channel 4 Terminal Count */ + +/* Master DMA Channel 4-7 Control Bit Definitions already defined previously */ + + /* REQDMA bit already definined */ + +#define REQSEL1_CH4 0x00 /* DMA Channel Select: Channel 4 */ +#define REQSEL1_CH5 0x01 /* DMA Channel Select: Channel 5 */ +#define REQSEL1_CH6 0x02 /* DMA Channel Select: Channel 6 */ +#define REQSEL1_CH7 0x03 /* DMA Channel Select: Channel 7 */ + +/* Master DMA Channel 4-7 Mask Register Definitions */ + + /* CHMASK bit already correctly defined previously */ + +#define MSKSEL_CH4 0x00 /* DMA Channel Mask Select: channel 4 */ +#define MSKSEL_CH5 0x01 /* DMA Channel Mask Select: channel 5 */ +#define MSKSEL_CH6 0x02 /* DMA Channel Mask Select: channel 6 */ +#define MSKSEL_CH7 0x03 /* DMA Channel Mask Select: channel 7 */ + +/* Master DMA Channel 4-7 Mode Register Bit Definitions */ + + /* TRNMOD bits already defined */ + /* ADDDEC bit already defined */ + /* AINIT bit already defined */ + /* OPSEL bits already defined */ + +#define MODSEL_CH4 0x00 /* DMA Channel Select: Channel 4 */ +#define MODSEL_CH5 0x01 /* DMA Channel Select: Channel 5 */ +#define MODSEL_CH6 0x02 /* DMA Channel Select: Channel 6 */ +#define MODSEL_CH7 0x03 /* DMA Channel Select: Channel 7 */ + +/* Master DEMA Clear Byte Pointer Register Masks */ + +#define MASTR_CBP 0xFF /* Master DMA Clear Byte Pointer */ + +/* Master DMA Controller Reset Register Masks */ + +#define MASTR_RST 0xFF /* Master DMA Controller Reset */ + +/* Master DMA Controller Temporary Register Masks */ + +#define MASTR_TMP 0xFF /* Master DMA Controller Temporary Register */ + +/* Master DMA Mask Reset Register Masks */ + +#define MASTR_MSK_RST 0xFF /* Master DMA Reset Mask */ + +/* Master DMA General Mask Register Bit Definitions */ + +#define CH7_DIS 0x08 /* DMA Channel 7 Mask */ +#define CH6_DIS 0x04 /* DMA Channel 6 Mask */ +#define CH5_DIS 0x02 /* DMA Channel 5 Mask */ +#define CH4_DIS 0x01 /* DMA Channel 4 Mask */ + +/**************************** +* Real-Time Clock Registers * +****************************/ + +/* Real-Time Clock Direct-Mapped Registers */ + +#define RTCIDX 0x0070 /* RTC/CMOS RAM Index Register */ +#define RTCDATA 0x0071 /* RTC/CMOS RAM Data Port */ + +/* Real-Time Clock Indexed Registers */ + +#define RTCCURSEC 0x00 /* RTC Current Second */ +#define RTCALMSEC 0x01 /* RTC Alarm Second */ +#define RTCCURMIN 0x02 /* RTC Current Minute */ +#define RTCALMMIN 0x03 /* RTC Alarm Minute */ +#define RTCCURHR 0x04 /* RTC Current Hour */ +#define RTCALMHR 0x05 /* RTC Alarm Hour */ +#define RTCCURDOW 0x06 /* RTC Current Day of Week */ +#define RTCCURDOM 0x07 /* RTC Current Day of Month */ +#define RTCDURMON 0x08 /* RTC Current Month */ +#define RTCCURYR 0x09 /* RTC Current Year */ +#define RTCCTLA 0x0a /* RTC Control A */ +#define RTCCTLB 0x0b /* RTC Control A */ +#define RTCCTLC 0x0c /* RTC Control A */ +#define RTCCTLD 0x0d /* RTC Control A */ + +/* +Real-Time Clock Register Bit Definitions +*/ + +/* RTC/CMOS RAM Index Register Mask */ + +#define CMOSIDX 0x7E /* RTC/CMOS RAM Index */ + +/* RTC/CMOS RAM Data Port Register Mask */ + +#define CMOSDATA 0xFF /* RTC/CMOS Data Port */ + +/* RTC Current Second Register Mask */ + +#define SECOND 0xFF /* RTC Current Second */ + +/* RTC Alarm Second Register Mask */ + +#define ALM_SECOND 0xFF /* RTC Alarm Second */ + +/* RTC Current Minute Register Mask */ + +#define MINUTE 0xFF /* RTC Current Minute */ + +/* RTC Alarm Minute Register Mask */ + +#define ALM_MINUTE 0xFF /* RTC Alarm Minute */ + +/* RTC Current Hour Register Bit Definitions */ + +#define AM_PM 0x80 /* RTC AM/PM Indicator */ + +/* RTC Current Hour Register Mask */ + +#define HOUR 0x7F /* RTC Current Hour */ + +/* RTC Alarm Hour Register Bit Definitions */ + +#define ALARM_AM_PM 0x80 /* RTC Alarm AM/PM Indicator */ + +/* RTC Alarm Hour Register Mask */ + +#define ALM_HOUR 0x7F /* RTC Alarm Hour */ + +/* RTC Current Day of the Week Register Bit Definitions */ + +#define SUNDAY 0x01 /* Sunday day of week */ +#define MONDAY 0x02 /* Monday day of week */ +#define TUESDAY 0x03 /* Tuesday day of week */ +#define WEDNESDAY 0x04 /* Wednesday day of week */ +#define THURDAY 0x05 /* Thursday day of week */ +#define FRIDAY 0x06 /* Friday!!!! day of week */ +#define SATURDAY 0x07 /* Saturday day of week */ + +/* RTC Current Day of the Week Register Mask */ + +#define DAY_OF_WEEK 0xFF /* RTC Current Day of the Week */ + +/* RTC Current Day of the Month Register Mask */ + +#define DAY_OF_MTH 0xFF /* RTC Current Day of the Month */ + +/* RTC Current Month Register Bit Definitions */ + +#define JANUARY 0x01 /* month of January */ +#define FEBRUARY 0x02 /* month of February */ +#define MARCH 0x03 /* month of March */ +#define APRIL 0x04 /* month of April */ +#define MAY 0x05 /* month of May */ +#define JUNE 0x06 /* month of June */ +#define JULY 0x07 /* month of July */ +#define AUGUST 0x08 /* month of August */ +#define SEPTEMBER 0x09 /* month of September */ +#define OCTOBER 0x0a /* month of October */ +#define NOVEMBER 0x0b /* month of November */ +#define DECEMBER 0x0c /* month of December */ + +/* RTC Current Month Register Mask */ + +#define MONTH 0xFF /* RTC Current Month */ + +/* RTC Current Year Register Mask */ + +#define YEAR 0xFF /* RTC Current Year */ + +/* RTC Control A Register Bit Definitions */ + +#define UIP 0x80 /* Update in Progress */ + +#define OSC_CTL_ENB 0x20 /* Enable RTC to be updated once per sec (normal) */ +#define OSC_CTL_HOLD 0x60 /* Hold RTC in reset state */ + +#define RATE_SEL_PID 0x00 /* Rate Selection: Periodic Interrupt Disabled */ +#define RATE_SEL_3_906m 0x01 /* Rate Selection: 3.906 milliseconds */ +#define RATE_SEL_7_812m 0x02 /* Rate Selection: 7.812 milliseconds */ +#define RATE_SEL_122_070u 0x03 /* Rate Selection: 122.070 microseconds */ +#define RATE_SEL_244_141u 0x04 /* Rate Selection: 244.141 microseconds */ +#define RATE_SEL_488_281u 0x05 /* Rate Selection: 488.281 microseconds */ +#define RATE_SEL_976_563u 0x06 /* Rate Selection: 976.563 microseconds */ + +#define RATE_SEL_1_953m 0x09 /* Rate Selection: 1.953 milliseconds */ +#define RATE_SEL_15_625m 0x0a /* Rate Selection: 15.625 milliseconds */ +#define RATE_SEL_31_250m 0x0b /* Rate Selection: 31.250 milliseconds */ +#define RATE_SEL_62_500m 0x0c /* Rate Selection: 62.500 milliseconds */ +#define RATE_SEL_125_000m 0x0d /* Rate Selection: 125.000 milliseconds */ +#define RATE_SEL_250_000m 0x0e /* Rate Selection: 250.000 milliseconds */ +#define RATE_SEL_500_000m 0x0f /* Rate Selection: 500.000 milliseconds */ + +/* RTC Control B Register Bit Definitions */ + +#define SET 0x80 /* Set Bit */ +#define PER_INT_ENB 0x40 /* Periodic Interrupt Enable */ +#define ALM_INT_ENB 0x20 /* Alarm Interrupt Enable */ +#define UPD_INT_ENB 0x10 /* Update-Ended Interrupt Enable */ +#define DATE_MODE 0x04 /* Date Mode */ +#define HOUR_MODE_SEL 0x02 /* 12/24-Hour Mode Select Bit */ +#define DS_ENB 0x01 /* Daylight Savings Enable */ + +/* RTC Status C Register Bit Definitions */ + +#define INT_FLG 0x80 /* Interrupt Request Flag */ +#define PER_INT_FLG 0x40 /* Periodic Interrupt Flag */ +#define ALM_INT_FLG 0x20 /* Alarm Interrupt Flag */ +#define UPD_INT_FLG 0x10 /* Update-Ended Interrupt Flag */ + + +/* RTC Status D Register Bit Definitions */ + +#define RTC_VRT 0x80 /* Valid Ram and Time */ + +/* General-Purpose CMOS RAM Mask */ + +#define RTC_CMOS_REG_X 0xFF /* CMOS RAM Location */ + + + + + + + + + + + + + + + + + + + + + + + +#endif /* _ASM_IC_SC520_DEFS_H_ */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h new file mode 100644 index 0000000..4f206df --- /dev/null +++ b/include/configs/eNET.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel(a)omicron.se. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define DEBUG_PARSER + +#define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_SC520_SSI + +/* + * No video hardware on the eNET + */ +#undef CONFIG_VIDEO /* No Video Hardware */ +#undef CONFIG_CFB_CONSOLE + +#define CFG_SDRAM_DRCTMCTL 0x18 + +#undef CFG_SDRAM_PRECHARGE_DELAY /* CFG_SDRAM_DRCTMCTL Overrides */ +#undef CFG_SDRAM_REFRESH_RATE /* CFG_SDRAM_DRCTMCTL Overrides */ +#undef CFG_SDRAM_RAS_CAS_DELAY /* CFG_SDRAM_DRCTMCTL Overrides */ +#undef CFG_SDRAM_CAS_LATENCY_2T /* CFG_SDRAM_DRCTMCTL Overrides */ +#undef CFG_SDRAM_CAS_LATENCY_3T /* CFG_SDRAM_DRCTMCTL Overrides */ + +#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#define CFG_RESET_GENERIC /* use tripple-fault to reset cpu */ +#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#define CFG_TIMER_SC520 /* use SC520 swtimers */ +#undef CFG_TIMER_GENERIC /* use the i8254 PIT timers */ +#undef CFG_TIMER_TSC /* use the Pentium TSC timers */ +#define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those + * in the SC520 on the CDP */ + +#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */ +#define CFG_RELOC_ADDR 0x03fd0000 /* Address of relocated code */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) + +#define CONFIG_BAUDRATE 9600 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + + + + + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment in NVRAM */ +#define CONFIG_ENV_IS_IN_NVRAM +#define CONFIG_ENV_ADDR 0x19000000 +#define CONFIG_ENV_SIZE 0x1000 +/************************************************************ + * RTC + ***********************************************************/ +#define CONFIG_RTC_MC146818 + +/* + * Enable hardware watchdog. + * + * WARNING: If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the + * bottom (processor) board MUST be removed! + */ +#undef CONFIG_WATCHDOG +#define CONFIG_HW_WATCHDOG + +/* + * PCI stuff + */ +#undef CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* pci plug-and-play */ +#undef CONFIG_PCI_SCAN_SHOW + +#undef CFG_FIRST_PCI_IRQ +#undef CFG_SECOND_PCI_IRQ +#undef CFG_THIRD_PCI_IRQ +#undef CFG_FORTH_PCI_IRQ +/* + * #undef CFG_FIRST_PCI_IRQ 10 + * #undef CFG_SECOND_PCI_IRQ 9 + * #undef CFG_THIRD_PCI_IRQ 11 + * #undef CFG_FORTH_PCI_IRQ 15 + */ +/* + * Hardware watchdog stuff + */ +#define CFG_WATCHDOG_PIO_BIT 0x8000 +#define CFG_WATCHDIG_PIO_DATA SC520_PIODATA15_0 +#define CFG_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 +#define CFG_WATCHDIG_PIO_SET SC520_PIOSET15_0 + +/* + * FPGA stuff + */ +#define CFG_FPGA_PROGRAM_PIO_BIT 0x2000 +#define CFG_FPGA_INIT_PIO_BIT 0x4000 +#define CFG_FPGA_DONE_PIO_BIT 0x8000 +#define CFG_FPGA_PIO_DATA SC520_PIODATA31_16 +#define CFG_FPGA_PIO_DIRECTION SC520_PIODIR31_16 +#define CFG_FPGA_PIO_CLR SC520_PIOCLR31_16 +#define CFG_FPGA_PIO_SET SC520_PIOSET31_16 +#define CFG_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ +#define CFG_FPGA_MAX_INIT_TIME 10 /* milliseconds */ +#define CFG_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ +#define CFG_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ + +#endif /* __CONFIG_H */

2 1

[U-Boot] [RFC][PATCH 2a/3] New i386 board (includes code relocation)
by Graeme Russ 28 Oct '08

28 Oct '08

Split to meet mailing list size limit Initial addition of eNET files - builds clean but will not run until additional i386 code changes are made Signed-off-by: Graeme Russ <graeme.russ(a)gmail.com> -- diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..6f65870 100755 --- a/MAKEALL +++ b/MAKEALL @@ -645,6 +645,7 @@ LIST_I486=" \ sc520_cdp \ sc520_spunk \ sc520_spunk_rel \ + sc520_eNET \ " LIST_x86=" \ diff --git a/Makefile b/Makefile index 7c13ce8..cdfca1c 100644 --- a/Makefile +++ b/Makefile @@ -2843,6 +2843,12 @@ sc520_spunk_config : unconfig sc520_spunk_rel_config : unconfig @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk +######################################################################### +## Serck eNET +######################################################################### +eNET_config : unconfig + @$(MKCONFIG) $(@:_config=) i386 i386 eNET + #======================================================================== # MIPS #======================================================================== diff --git a/board/eNET/Makefile b/board/eNET/Makefile new file mode 100644 index 0000000..a124b33 --- /dev/null +++ b/board/eNET/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2008 +# Graeme Russ, graeme.russ(a)gmail.com. +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel(a)omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := eNET.o flash.o fpga.o +SOBJS := eNET_start16.o eNET_start.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/eNET/config.mk b/board/eNET/config.mk new file mode 100644 index 0000000..6797f8a --- /dev/null +++ b/board/eNET/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2002 +# Daniel Engström, Omicron Ceti AB, daniel(a)omicron.se. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +TEXT_BASE = 0x38040000 diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c new file mode 100644 index 0000000..1b4af58 --- /dev/null +++ b/board/eNET/eNET.c @@ -0,0 +1,640 @@ +/* + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel(a)omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/pci.h> +#include <asm/ic/sc520.h> +#include <spi.h> + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#endif + +#include "hardware.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef SC520_CDP_DEBUG + +#ifdef SC520_CDP_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +extern int do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_bdinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_iminfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +/* extern int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); */ +extern int do_coninfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_itest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_md (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_mm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_nm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_mw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_cp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_imgextract (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern int do_help (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + + +void hw_watchdog_reset(void) +{ + u16 wd_state; + + wd_state = readw(CFG_WATCHDIG_PIO_DATA); + + if (wd_state & CFG_WATCHDOG_PIO_BIT) { + /* Watchdog output high - lower it*/ + writew(CFG_WATCHDOG_PIO_BIT, CFG_WATCHDIG_PIO_CLR); + } + else { + /* Watchdog output low - raise it*/ + writew(CFG_WATCHDOG_PIO_BIT, CFG_WATCHDIG_PIO_SET); + } +} + +/* ------------------------------------------------------------------------- */ + +void init_sc520_enet (void) +{ + + /* Set the UARTxCTL register at it's slower, + * baud clock giving us a 1.8432 MHz reference + */ + write_mmcr_byte(SC520_UART1CTL, 7); + + + /* enable PCI bus arbitrer */ +/* mov ebx, SYSARBCTL ; SC520 control bits for the CPU bus arbiter and the PCI bus arbiter. */ +/* mov byte ptr [ebx], 06h ; */ + write_mmcr_byte(SC520_SYSARBCTL,0x06); /* enable concurrent mode */ + + + /* ?? mov ebx, SYSARBMENB ; SC520 System Arbiter Master Enable */ +/* ?? mov word ptr [ebx], 0003h ; */ + write_mmcr_word(SC520_SYSARBMENB, 0x0003); /* enable external grants */ + + + if (CFG_SC520_HIGH_SPEED) { + write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ + gd->cpu_clk = 133000000; +/* printf("## CPU Speed set to 133MHz\n"); */ + } else { + write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */ +/* printf("## CPU Speed set to 100MHz\n"); */ + gd->cpu_clk = 100000000; + } + + + /* wait at least one millisecond */ + asm("movl $0x2000,%%ecx\n" + "wait_loop: pushl %%ecx\n" + "popl %%ecx\n" + "loop wait_loop\n": : : "ecx"); + + /* turn on the SDRAM write buffer */ + write_mmcr_byte(SC520_DBCTL, 0x11); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl $0x9fffffff, %%eax\n" + "movl %%eax, %%cr0\n" : : : "eax"); +} + +/* + * Theory: + * We first set up all IRQs to be non-pci, edge triggered, + * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets + * called we reallocate irqs to the pci bus with sc520_pci_set_irq() + * as needed. Whe choose the irqs to gram from a configurable list + * inside pci_sc520_fixup_irq() (If this list contains stupid irq's + * such as 0 thngas will not work) + */ + +static void irq_init(void) +{ +#if 0 + /* disable global interrupt mode */ + write_mmcr_byte(SC520_PICICR, 0x40); + + /* set all irqs to edge */ + write_mmcr_byte(SC520_MPICMODE, 0x00); + write_mmcr_byte(SC520_SL1PICMODE, 0x00); + write_mmcr_byte(SC520_SL2PICMODE, 0x00); + + /* active low polarity on PIC interrupt pins, + * active high polarity on all other irq pins */ +/* write_mmcr_word(SC520_INTPINPOL, 0x0000); */ + + /* set irq number mapping */ + write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */ + write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */ + write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */ + write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */ + write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */ + write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */ + write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */ + write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ + write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */ + write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */ + write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */ + write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */ + write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ + write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ +#endif + +/* mov ebx, UART1MAP ; UART1MAP interrupt map */ +/* mov byte ptr [ebx], 02h ; connect to Master PIC IR1 */ +/* mov ebx, GPTMR0MAP ; GP Timer 0 Interrupt Mapping */ +/* mov byte ptr [ebx], 01h ; connect to Master PIC IR0 */ +/* mov ebx, PCIINTAMAP ; PCI Interrupt A Mapping Register (INTA_INT) */ +/* mov byte ptr [ebx], 03h ; connect to Slave 1 PIC IR0 */ +/* mov ebx, PCIINTBMAP ; PCI Interrupt B Mapping Register (INTB_INT) */ +/* mov byte ptr [ebx], 04h ; connect to Slave 1 PIC IR1 */ +/* mov ebx, GP0IMAP ; GPIRQ0 interrupt map (UART_A_INT) */ +/* mov byte ptr [ebx], 07h ; connect to Slave 1 PIC IR4 */ +/* mov ebx, GP1IMAP ; GPIRQ1 interrupt map (UART_B_INT) */ +/* mov byte ptr [ebx], 08h ; connect to Slave 1 PIC IR5 */ +/* mov ebx, GP2IMAP ; GPIRQ2 interrupt map (UART_C_INT) */ +/* mov byte ptr [ebx], 09h ; connect to Slave 1 PIC IR6 */ +/* mov ebx, GP3IMAP ; GPIRQ3 interrupt map (UART_D_INT) */ +/* mov byte ptr [ebx], 0ah ; connect to Slave 1 PIC IR7 */ +/* mov ebx, GP4IMAP ; GPIRQ4 interrupt map (DPRAM1_INT) */ +/* mov byte ptr [ebx], 0bh ; connect to Master PIC IR3 */ +/* mov ebx, GP6IMAP ; GPIRQ6 interrupt map (IRIG_INT) */ +/* mov byte ptr [ebx], 0ch ; connect to Master PIC IR4 */ +/* mov ebx, GP7IMAP ; GPIRQ7 interrupt map (EXP1_INT) */ +/* mov byte ptr [ebx], 0eh ; connect to Slave 2 PIC IR1 */ +/* mov ebx, GP8IMAP ; GPIRQ8 interrupt map (EXP2_INT) */ +/* mov byte ptr [ebx], 0fh ; connect to Slave 2 PIC IR2 */ +/* mov ebx, GP9IMAP ; GPIRQ9 interrupt map (EXP3_INT) */ +/* mov byte ptr [ebx], 010h ; connect to Slave 2 PIC IR3 */ +/* mov ebx, GP10IMAP ; GPIRQ10 interrupt map (EXP4_INT or I2C_INT) */ +/* mov byte ptr [ebx], 011h ; connect to Slave 2 PIC IR4 */ +/* mov ebx, BOOTCSCTL ; BOOTCS Control Register */ +/* mov word ptr [ebx], 0033h ; 3 wait states */ +/* mov ebx, ROMCS1CTL ; ROMCS1 Control Register */ +/* mov word ptr [ebx], 0615h */ +/* mov ebx, ROMCS2CTL ; ROMCS2 Control Register */ +/* mov word ptr [ebx], 0615h */ +/* mov ebx, ADDDECCTL ; SC520 Address Decode Control Register */ +/* mov byte ptr [ebx], 02h ; Enable RTC & UART1, Disable UART2 */ + + write_mmcr_word(SC520_INTPINPOL, 0x0410); + write_mmcr_byte(SC520_UART1MAP, 0x02); + write_mmcr_byte(SC520_GPTMR0MAP, 0x01); + write_mmcr_byte(SC520_PCIINTAMAP, 0x03); + write_mmcr_byte(SC520_PCIINTBMAP, 0x04); + write_mmcr_byte(SC520_GP0IMAP, 0x07); + write_mmcr_byte(SC520_GP1IMAP, 0x08); + write_mmcr_byte(SC520_GP2IMAP, 0x09); + write_mmcr_byte(SC520_GP3IMAP, 0x0a); + write_mmcr_byte(SC520_GP4IMAP, 0x0b); + write_mmcr_byte(SC520_GP6IMAP, 0x0c); + write_mmcr_byte(SC520_GP7IMAP, 0x0e); + write_mmcr_byte(SC520_GP8IMAP, 0x0f); + write_mmcr_byte(SC520_GP9IMAP, 0x10); + write_mmcr_byte(SC520_GP10IMAP, 0x11); + write_mmcr_word(SC520_BOOTCSCTL, 0x0033); + write_mmcr_word(SC520_ROMCS1CTL, 0x0615); + write_mmcr_word(SC520_ROMCS2CTL, 0x0615); + write_mmcr_byte(SC520_ADDDECCTL, 0x02); + +/* write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); */ /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */ +/* write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); */ /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */ +/* write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); */ /* disable internal UART2 INT */ +/* write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); */ /* Map PCI hostbridge INT to NMI */ +/* write_mmcr_word(SC520_ECCMAP, 0x100); */ /* Map SDRAM ECC failure INT to NMI */ + +} + +#if 0 +/* PCI stuff */ +static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + /* a configurable lists of irqs to steal + * when we need one (a board with more pci interrupt pins + * would use a larger table */ + static int irq_list[] = { + CFG_FIRST_PCI_IRQ, + CFG_SECOND_PCI_IRQ, + CFG_THIRD_PCI_IRQ, + CFG_FORTH_PCI_IRQ + }; + static int next_irq_index=0; + + unsigned char tmp_pin; + int pin; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); + pin = (int)tmp_pin; + + pin-=1; /* pci config space use 1-based numbering */ + if (-1 == pin) { + return; /* device use no irq */ + } + + + /* map device number + pin to a pin on the sc520 */ + switch (PCI_DEV(dev)) { + case 20: + pin+=SC520_PCI_INTA; + break; + + case 19: + pin+=SC520_PCI_INTB; + break; + + case 18: + pin+=SC520_PCI_INTC; + break; + + case 17: + pin+=SC520_PCI_INTD; + break; + + default: + return; + } + + pin&=3; /* wrap around */ + + if (sc520_pci_ints[pin] == -1) { + /* re-route one interrupt for us */ + if (next_irq_index > 3) { + return; + } + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + return; + } + next_irq_index++; + } + + + if (-1 != sc520_pci_ints[pin]) { + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + sc520_pci_ints[pin]); + } + PRINTF("fixup_irq: device %d pin %c irq %d\n", + PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); +} + +static struct pci_controller sc520_cdp_hose = { + fixup_irq: pci_sc520_cdp_fixup_irq, +}; + +void pci_init_board(void) +{ + pci_sc520_init(&sc520_cdp_hose); +} +#endif + +#if 0 +/* set up the ISA bus timing and system address mappings */ +static void bus_init(void) +{ + + /* set up the GP IO pins */ + write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ + write_mmcr_byte(SC520_CLKSEL, 0x70); + + + write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */ + write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */ + write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */ + write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */ + write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */ + write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */ + + write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */ + write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */ + write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */ + + /* adjust the memory map: + * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM + * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio + * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ + + /* SRAM = GPCS3 128k @ d0000-effff*/ + write_mmcr_long(SC520_PAR2, 0x4e00400d); + + /* IDE0 = GPCS6 1f0-1f7 */ + write_mmcr_long(SC520_PAR3, 0x380801f0); + + /* IDE1 = GPCS7 3f6 */ + write_mmcr_long(SC520_PAR4, 0x3c0003f6); + /* bootcs */ + write_mmcr_long(SC520_PAR12, 0x8bffe800); + /* romcs2 */ + write_mmcr_long(SC520_PAR13, 0xcbfff000); + /* romcs1 */ + write_mmcr_long(SC520_PAR14, 0xabfff800); + /* 680 LEDS */ + write_mmcr_long(SC520_PAR15, 0x30000640); + + write_mmcr_byte(SC520_ADDDECCTL, 0); + + asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ +} +#endif + +#if 0 +/* + * This function should map a chunk of size bytes + * of the system address space to the ISA bus + * + * The function will return the memory address + * as seen by the host (which may very will be the + * same as the bus address) + */ +u32 isa_map_rom(u32 bus_addr, int size) +{ + u32 par; + + PRINTF("isa_map_rom asked to map %d bytes at %x\n", + size, bus_addr); + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 12; + par--; + par&=0x7f; + par <<= 18; + par |= (bus_addr>>12); + par |= 0x50000000; + + PRINTF ("setting PAR11 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR11, par); + + return bus_addr; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void isa_unmap_rom(u32 addr) +{ + PRINTF("isa_unmap_rom asked to unmap %x", addr); + if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) { + write_mmcr_long(SC520_PAR11, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); +} +#endif + +#ifdef CONFIG_PCI +#define PCI_ROM_TEMP_SPACE 0x10000 +/* + * This function should map a chunk of size bytes + * of the system address space to the PCI bus, + * suitable to map PCI ROMS (bus address < 16M) + * the function will return the host memory address + * which should be converted into a bus address + * before used to configure the PCI rom address + * decoder + */ +u32 pci_get_rom_window(struct pci_controller *hose, int size) +{ + u32 par; + + par = size; + if (par < 0x80000) { + par = 0x80000; + } + par >>= 16; + par--; + par&=0x7ff; + par <<= 14; + par |= (PCI_ROM_TEMP_SPACE>>16); + par |= 0x72000000; + + PRINTF ("setting PAR1 to %x\n", par); + + /* Map rom 0x10000 with PAR1 */ + write_mmcr_long(SC520_PAR1, par); + + return PCI_ROM_TEMP_SPACE; +} + +/* + * this function removed any mapping created + * with pci_get_rom_window() + */ +void pci_remove_rom_window(struct pci_controller *hose, u32 addr) +{ + PRINTF("pci_remove_rom_window: %x", addr); + if (addr == PCI_ROM_TEMP_SPACE) { + write_mmcr_long(SC520_PAR1, 0); + PRINTF(" done\n"); + return; + } + PRINTF(" not ours\n"); + +} + +/* + * This function is called in order to provide acces to the + * legacy video I/O ports on the PCI bus. + * After this function accesses to I/O ports 0x3b0-0x3bb and + * 0x3c0-0x3df shuld result in transactions on the PCI bus. + * + */ +int pci_enable_legacy_video_ports(struct pci_controller *hose) +{ + /* Map video memory to 0xa0000*/ + write_mmcr_long(SC520_PAR0, 0x7200400a); + + /* forward all I/O accesses to PCI */ + write_mmcr_byte(SC520_ADDDECCTL, + read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI); + + + /* so we map away all io ports to pci (only way to access pci io + * below 0x400. But then we have to map back the portions that we dont + * use so that the generate cycles on the GPIO bus where the sio and + * ISA slots are connected, this requre the use of several PAR registers + */ + + /* bring 0x100 - 0x1ef back to ISA using PAR5 */ + write_mmcr_long(SC520_PAR5, 0x30ef0100); + + /* IDE use 1f0-1f7 */ + + /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */ + write_mmcr_long(SC520_PAR6, 0x30ff01f8); + + /* com2 use 2f8-2ff */ + + /* bring 0x300 - 0x3af back to ISA using PAR7 */ + write_mmcr_long(SC520_PAR7, 0x30af0300); + + /* vga use 3b0-3bb */ + + /* bring 0x3bc - 0x3bf back to ISA using PAR8 */ + write_mmcr_long(SC520_PAR8, 0x300303bc); + + /* vga use 3c0-3df */ + + /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */ + write_mmcr_long(SC520_PAR9, 0x301503e0); + + /* ide use 3f6 */ + + /* bring 0x3f7 back to ISA using PAR10 */ + write_mmcr_long(SC520_PAR10, 0x300003f7); + + /* com1 use 3f8-3ff */ + + return 0; +} +#endif + +/* + * Miscelaneous platform dependent initializations + */ + +int board_init(void) +{ +/* init_sc520(); */ + + init_sc520_enet(); + + /* bus_init(); */ + + irq_init(); + + /* max drive current on SDRAM */ +/* write_mmcr_word(SC520_DSCTL, 0x0100); */ + + /* enter debug mode after next reset (only if jumper is also set) */ +/* write_mmcr_byte(SC520_RESCFG, 0x00); */ + + /* Crystal is 33.000MHz */ + gd->bus_clk = 33000000; + + return 0; +} + +int dram_init(void) +{ + init_sc520_dram(); + return 0; +} + +void show_boot_progress(int val) +{ + uchar led_mask; + + led_mask = 0x00; + + if (val < 0) + led_mask |= LED_ERR_BITMASK; + + led_mask |= (uchar)(val & 0x001f); + outb(led_mask, LED_LATCH_ADDRESS); +} + + +int last_stage_init(void) +{ + int minor; + int major; + + major = minor = 0; + + printf("Serck Controls eNET\n"); + printf("last_stage_init() at %08lx\n", (ulong)last_stage_init); + + printf("autoscript => do_autoscript() @ 0x%08lx\n", (ulong)do_autoscript); + printf("bdinfo => do_bdinfo() @ 0x%08lx\n", (ulong)do_bdinfo); + printf("go => do_go() @ 0x%08lx\n", (ulong)do_go); + printf("reset => do_reset() @ 0x%08lx\n", (ulong)do_reset); + printf("bootm => do_bootm() @ 0x%08lx\n", (ulong)do_bootm); + printf("boot => do_bootd() @ 0x%08lx\n", (ulong)do_bootd); + printf("bootd => do_bootd() @ 0x%08lx\n", (ulong)do_bootd); + printf("iminfo => do_iminfo() @ 0x%08lx\n", (ulong)do_iminfo); +/* printf("imls => do_imls() @ 0x%08lx\n", (ulong)do_imls); */ + printf("imls => do_imls() @ <undefined>\n"); + printf("coninfo => do_coninfo() @ 0x%08lx\n", (ulong)do_coninfo); + printf("itest => do_itest() @ 0x%08lx\n", (ulong)do_itest); + printf("loads => do_load_serial() @ 0x%08lx\n", (ulong)do_load_serial); + printf("loadb => do_load_serial_bin() @ 0x%08lx\n", (ulong)do_load_serial_bin); + printf("loady => do_load_serial_bin() @ 0x%08lx\n", (ulong)do_load_serial_bin); + printf("md => do_mem_md() @ 0x%08lx\n", (ulong)do_mem_md); + printf("mm => do_mem_mm() @ 0x%08lx\n", (ulong)do_mem_mm); + printf("nm => do_mem_nm() @ 0x%08lx\n", (ulong)do_mem_nm); + printf("mw => do_mem_mw() @ 0x%08lx\n", (ulong)do_mem_mw); + printf("cp => do_mem_cp() @ 0x%08lx\n", (ulong)do_mem_cp); + printf("cmp => do_mem_cmp() @ 0x%08lx\n", (ulong)do_mem_cmp); + printf("crc32 => do_mem_crc() @ 0x%08lx\n", (ulong)do_mem_crc); + printf("base => do_mem_base() @ 0x%08lx\n", (ulong)do_mem_base); + printf("loop => do_mem_loop() @ 0x%08lx\n", (ulong)do_mem_loop); + printf("mtest => do_mem_mtest() @ 0x%08lx\n", (ulong)do_mem_mtest); + printf("sleep => do_sleep() @ 0x%08lx\n", (ulong)do_sleep); + printf("printenv => do_printenv() @ 0x%08lx\n", (ulong)do_printenv); + printf("setenv => do_setenv() @ 0x%08lx\n", (ulong)do_setenv); + printf("saveenv => do_saveenv() @ 0x%08lx\n", (ulong)do_saveenv); + printf("run => do_run() @ 0x%08lx\n", (ulong)do_run); + printf("imxtract => do_imgextract() @ 0x%08lx\n", (ulong)do_imgextract); + printf("version => do_version() @ 0x%08lx\n", (ulong)do_version); + printf("echo => do_echo() @ 0x%08lx\n", (ulong)do_echo); + printf("help => do_help() @ 0x%08lx\n", (ulong)do_help); + printf("? => do_help() @ 0x%08lx\n", (ulong)do_help); + + + return 0; +} + + diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S new file mode 100644 index 0000000..124660c --- /dev/null +++ b/board/eNET/eNET_start.S @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel(a)omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <asm/ic/sc520_defs.h> + +#include "hardware_defs.h" + +sc520_cdp_registers: +/* + * This is the MMCR configuration array - only change the values here if + * you are absolutely sure you know what you are doing + */ +/* size offset value */ +.word 0x0001 ; .word 0x0040 ; .long 0x00000000 /* SDRAM buffer control */ +.word 0x0001 ; .word 0x0c08 ; .long 0x00000001 /* GP Chip Select Recovery Time */ +.word 0x0001 ; .word 0x0c09 ; .long 0x00000007 /* GP Chip Select Pulse Width */ +.word 0x0001 ; .word 0x0c0a ; .long 0x00000000 /* GP Chip Select Offset */ +.word 0x0001 ; .word 0x0c0b ; .long 0x00000005 /* GP Read pulse width */ +.word 0x0001 ; .word 0x0c0c ; .long 0x00000001 /* GP Read offset */ +.word 0x0001 ; .word 0x0c0d ; .long 0x00000005 /* GP Write pulse width */ +.word 0x0001 ; .word 0x0c0e ; .long 0x00000001 /* GP Write offset */ +.word 0x0002 ; .word 0x0c30 ; .long 0x00000630 /* PIO15_PIO0 Data */ +.word 0x0002 ; .word 0x0c32 ; .long 0x00002000 /* PIO31_PIO16 Data */ +.word 0x0002 ; .word 0x0c2c ; .long 0x00002000 /* GPIO directionreg */ +.word 0x0002 ; .word 0x0c2a ; .long 0x000087b5 /* GPIO directionreg */ +.word 0x0002 ; .word 0x0c22 ; .long 0x00000dfe /* GPIO pin function 31-16 reg */ +.word 0x0002 ; .word 0x0c20 ; .long 0x0000200a /* GPIO pin function 15-0 reg */ +.word 0x0001 ; .word 0x0c24 ; .long 0x000000F8 /* Chip Select Pin Function Select */ +.word 0x0004 ; .word 0x0090 ; .long 0x200713f8 /* PAR2 - Uart A (GPCS0, 0x013f8, 8 Bytes) */ +.word 0x0004 ; .word 0x0094 ; .long 0x2c0712f8 /* PAR3 - Uart B (GPCS3, 0x012f8, 8 Bytes) */ +.word 0x0004 ; .word 0x0098 ; .long 0x300711f8 /* PAR4 - Uart C (GPCS4, 0x011f8, 8 Bytes) */ +.word 0x0004 ; .word 0x009c ; .long 0x340710f8 /* PAR5 - Uart D (GPCS5, 0x010f8, 8 Bytes) */ +.word 0x0004 ; .word 0x00a0 ; .long 0xe3ffc000 /* PAR6 - SDRAM (0x00000000, 128MB) */ +.word 0x0004 ; .word 0x00a4 ; .long 0xaa3fd000 /* PAR7 - StrataFlash (ROMCS1, 0x10000000, 16MB) */ +.word 0x0004 ; .word 0x00a8 ; .long 0xca3fd100 /* PAR8 - StrataFlash (ROMCS2, 0x11000000, 16MB) */ +.word 0x0004 ; .word 0x00ac ; .long 0x4203d900 /* PAR9 - SRAM (GPCS0, 0x19000000, 1MB) */ +.word 0x0004 ; .word 0x00b0 ; .long 0x4e03d910 /* PAR10 -SRAM (GPCS3, 0x19100000, 1MB) */ +.word 0x0004 ; .word 0x00b4 ; .long 0x50018100 /* PAR11 -DP-RAM (GPCS4, 0x18100000, 4kB) */ +.word 0x0004 ; .word 0x00b8 ; .long 0x54020000 /* PAR12 -CFLASH1 (0x200000000, 4kB) */ +.word 0x0004 ; .word 0x00bc ; .long 0x5c020001 /* PAR13 -CFLASH2 (0x200010000, 4kB) */ +.word 0x0004 ; .word 0x00c0 ; .long 0x8bfff800 /* PAR14 - BOOTCS at 0x18000000 */ +.word 0x0004 ; .word 0x00c4 ; .long 0x38201000 /* PAR15 - LEDs etc (GPCS6, 0x1000, 20 Bytes */ +.word 0x0002 ; .word 0x0cb0 ; .long 0x00003333 /* Activate watchdog status register step 1 */ +.word 0x0002 ; .word 0x0cb0 ; .long 0x0000cccc /* Activate watchdog status register step 2 */ +.word 0x0002 ; .word 0x0cb0 ; .long 0x00000000 /* Disable Watchdog */ +.word 0x0000 ; .word 0x0000 ; .long 0x00000000 /* EOT */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + movl $sc520_cdp_registers,%esi +init_loop: + movl $0xfffef000,%edi /* MMCR base to edi */ + movw (%esi), %bx /* load sizer to bx */ + cmpw $0, %bx /* if sie is 0 we're done */ + je done + xorl %edx,%edx + movw 2(%esi), %dx /* load MMCR offset to dx */ + addl %edx, %edi /* add offset to base in edi */ + movl 4(%esi), %eax /* load value in eax */ + cmpw $1, %bx + je byte /* byte op? */ + cmpw $2, %bx + je word /* word op? */ + movl %eax, (%edi) /* must be long, then */ + jmp next +byte: movb %al,(%edi) + jmp next +word: movw %ax,(%edi) +next: addl $8, %esi /* advance esi */ + jmp init_loop +done: + /* The LEDs are now available */ + movw $LED_LATCH_ADDRESS, %dx + movb $0x0f, %al + outb %al, %dx + + /* Initialize 8259 master */ +# mov al, 78h ; Use int vectors 78h to 7fh. +# mov dx, MPICICW2 +# out dx, al +# jmp $+2 +# mov al, 24h ; IR2 and IR5 has a slave PIC. +# out dx, al ; MPICICW3 +# jmp $+2 +# mov al, 01h ; Master, 8086 mode. +# out dx, al ; MPICICW4 +# jmp $+2 +# mov al, 0ffh ; Mask interrupt of master PIC. +# out dx, al ; MPICINTMSK +# jmp $+2 + movb $0x11, %al + movw $MPICICW1, %dx + outb %al, %dx + jmp .+2 + movb $0x78, %al + movw $MPICICW2, %dx + outb %al, %dx + jmp .+2 + movb $0x24, %al + out %al, %dx + jmp .+2 + movb $0x01, %al + outb %al, %dx + jmp .+2 + movb $0xff, %al + outb %al, %dx + jmp .+2 + + /* Initialize 8259 slave1 */ +# mov al, 11h ; Edge, slave 1, ICW4. +# mov dx, S1PICICW1 +# out dx, al +# jmp $+2 +# mov al, 70h ; Use int vectors 70h to 77h. +# mov dx, S1PICICW2 +# out dx, al +# jmp $+2 +# mov al, 02h ; Slave ID = 2. +# out dx, al ; S1PICICW3 +# jmp $+2 +# mov al, 01h ; Enable device. +# out dx, al ; S1PICICW4 +# jmp $+2 +# mov al, 0ffh ; Mask interrupt of slave PIC. +# out dx, al ; S1PICINTMSK +# jmp $+2 + movb $0x11, %al + movw $S1PICICW1, %dx + outb %al, %dx + jmp .+2 + movb $0x70, %al + movw $S1PICICW2, %dx + outb %al, %dx + jmp .+2 + movb $0x02, %al + outb %al, %dx + jmp .+2 + movb $0x01, %al + outb %al, %dx + jmp .+2 + movb $0xff, %al + outb %al, %dx + jmp .+2 + + /* Initialize 8259 slave 2 */ +# mov al, 11h ; Edge, slave 2, ICW4. +# mov dx, S2PICICW1 +# out dx, al +# jmp $+2 +# mov al, 68h ; Use int vectors 68h to 6fh. +# mov dx, S2PICICW2 +# out dx, al +# jmp $+2 +# mov al, 05h ; Slave ID = 5. +# out dx, al ; S2PICICW3 +# jmp $+2 +# mov al, 01h ; Enable Device. +# out dx, al ; S2PICICW4 +# jmp $+2 +# mov al, 0ffh ; Mask interrupt of slave 2 PIC. +# out dx, al ; S2PICINTMSK +# jmp $+2 + movb $0x11, %al + movw $S2PICICW1, %dx + outb %al, %dx + jmp .+2 + movb $0x68, %al + movw $S2PICICW2, %dx + outb %al, %dx + jmp .+2 + movb $0x05, %al + outb %al, %dx + jmp .+2 + movb $0x01, %al + outb %al, %dx + jmp .+2 + movb $0xff, %al + outb %al, %dx + jmp .+2 + + + jmp *%ebp /* return to caller */ + +.globl show_boot_progress_asm +show_boot_progress_asm: + + movb %al, %dl /* Create Working Copy */ + andb $0x80, %dl /* Mask in only Error bit */ + shrb $0x02, %dl /* Shift Error bit to Error LED */ + andb $0x0f, %al /* Mask out 'Error' bit */ + orb %dl, %al /* Mask in ERR LED */ + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + + jmp *%ebp /* return to caller */ + + +.globl cpu_halt_asm +cpu_halt_asm: + movb $0x0f, %al + movw $LED_LATCH_ADDRESS, %dx + outb %al, %dx + hlt + jmp cpu_halt_asm diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S new file mode 100644 index 0000000..e0d2ebb --- /dev/null +++ b/board/eNET/eNET_start16.S @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB <daniel(a)omicron.se>. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * 16bit initialization code. + * This code have to map the area of the boot flash + * that is used by U-boot to its final destination. + */ + +#include "hardware.h" + +.text +.section .start16, "ax" +.code16 +.globl board_init16 +board_init16: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* Map the entire flash at 0x38000000 + * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */ + movl $0xc0, %edi + movl $0x8bfff800, %eax + movl %eax, (%di) + + /* Disable SDRAM write buffer */ + movw $0x40,%di + xorw %ax,%ax + movb %al, (%di) + +#; turn off the cache +# mov eax, cr0 +# or eax,060000000h +# mov cr0, eax +# wbinvd ; flush the cache + + + /* Disabe MMCR alias */ + movw $0xfffc, %dx + movl $0x000000cb, %eax + outl %eax, %dx + + /* the return address is stored in bp */ + jmp *%bp + +.section .bios, "ax" +.code16 +.globl realmode_reset +realmode_reset: + /* Alias MMCR to 0xdf000 */ + movw $0xfffc, %dx + movl $0x800df0cb, %eax + outl %eax, %dx + + /* Set ds to point to MMCR alias */ + movw $0xdf00, %ax + movw %ax, %ds + + /* issue software reset thorugh MMCR */ + movl $0xd72, %edi + movb $0x01, %al + movb %al, (%di) + +1: hlt + jmp 1 diff --git a/board/eNET/flash.c b/board/eNET/flash.c new file mode 100644 index 0000000..168477b --- /dev/null +++ b/board/eNET/flash.c @@ -0,0 +1,641 @@ +/* + * (C) Copyright 2002, 2003 + * Daniel Engström, Omicron Ceti AB, daniel(a)omicron.se + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <pci.h> +#include <asm/ic/sc520.h> + +#define PROBE_BUFFER_SIZE 1024 +static unsigned char buffer[PROBE_BUFFER_SIZE]; + +#define SC520_MAX_FLASH_BANKS 3 +#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ +#define SC520_FLASH_BANK1_BASE 0x10ffffff /* ROMCS0 */ +#define SC520_FLASH_BANK2_BASE 0x11ffffff /* ROMCS1 */ +#define SC520_FLASH_BANKSIZE 0x1000000 + +#define AMD29LV016B_SIZE 0x80000 +#define AMD29LV016B_SECTORS 32 + +flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ + + +static u32 _probe_flash(u32 addr, u32 bw, int il) +{ + u32 result=0; + + /* First do an unlock cycle for the benefit of + * devices that need it */ + + switch (bw) { + + case 1: + *(volatile u8*)(addr+0x5555) = 0xaa; + *(volatile u8*)(addr+0x2aaa) = 0x55; + *(volatile u8*)(addr+0x5555) = 0x90; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5555), 0xf0; + break; + + case 2: + *(volatile u16*)(addr+0xaaaa) = 0xaaaa; + *(volatile u16*)(addr+0x5554) = 0x5555; + + /* Issue identification command */ + if (il == 2) { + *(volatile u16*)(addr+0xaaaa) = 0x9090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+2); + + /* Return device to data mode */ + *(volatile u16*)addr = 0xffff; + *(volatile u16*)(addr+0xaaaa), 0xf0f0; + + } else { + *(volatile u8*)(addr+0xaaaa) = 0x90; + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+2); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0xaaaa), 0xf0; + } + + break; + + case 4: + *(volatile u32*)(addr+0x5554) = 0xaaaaaaaa; + *(volatile u32*)(addr+0xaaa8) = 0x55555555; + + switch (il) { + case 1: + /* Issue identification command */ + *(volatile u8*)(addr+0x5554) = 0x90; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u8*)addr = 0xff; + *(volatile u8*)(addr+0x5554), 0xf0; + break; + + case 2: + /* Issue identification command */ + *(volatile u32*)(addr + 0x5554) = 0x00900090; + + /* Read vendor */ + result = *(volatile u16*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u16*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0x00ff00ff; + *(volatile u32*)(addr+0x5554), 0x00f000f0; + break; + + case 4: + /* Issue identification command */ + *(volatile u32*)(addr+0x5554) = 0x90909090; + + /* Read vendor */ + result = *(volatile u8*)addr; + result <<= 16; + + /* Read device */ + result |= *(volatile u8*)(addr+4); + + /* Return device to data mode */ + *(volatile u32*)addr = 0xffffffff; + *(volatile u32*)(addr+0x5554), 0xf0f0f0f0; + break; + } + break; + } + + + return result; +} + +extern int _probe_flash_end; +asm ("_probe_flash_end:\n" + ".long 0\n"); + +static int identify_flash(unsigned address, int width) +{ + int is; + int device; + int vendor; + int size; + unsigned res; + + u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il); + + size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_probe_flash() routine too large (%d) %p - %p\n", + size, &_probe_flash_end, _probe_flash); + return 0; + } + + memcpy(buffer, _probe_flash, size); + _probe_flash_ptr = (void*)buffer; + + is = disable_interrupts(); + res = _probe_flash_ptr(address, width, 1); + if (is) { + enable_interrupts(); + } + + + vendor = res >> 16; + device = res & 0xffff; + + + return res; +} + +ulong flash_init(void) +{ + int i, j; + ulong size = 0; + + printf("flash_init ()"); + + printf("Test %d Test %08x\n", 2, 1024); + + for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) { + unsigned id; + ulong flashbase = 0; + int sectsize = 0; + + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) { + case 0: + flashbase = SC520_FLASH_BANK0_BASE; + break; + case 1: + flashbase = SC520_FLASH_BANK1_BASE; + break; + case 2: + flashbase = SC520_FLASH_BANK2_BASE; + break; + default: + panic("configured too many flash banks!\n"); + } + + id = identify_flash(flashbase, 4); + switch (id & 0x00ff00ff) { + case 0x000100c8: + /* 29LV016B/29LV017B */ + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_LV016B & FLASH_TYPEMASK); + + flash_info[i].size = AMD29LV016B_SIZE*4; + flash_info[i].sector_count = AMD29LV016B_SECTORS; + sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS; + printf("Bank %d: 4 x AMD 29LV017B\n", i); + break; + + + default: + printf("Bank %d have unknown flash %08x\n", i, id); + flash_info[i].flash_id = FLASH_UNKNOWN; + continue; + } + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + j * sectsize; + } + size += flash_info[i].size; + + flash_protect(FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + + /* + * Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + i386boot_start, + i386boot_end, + &flash_info[0]); +#ifdef CFG_ENV_ADDR + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t *info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + + case (AMD_MANUFACT & FLASH_VENDMASK): + printf("AMD: "); + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_LV016B & FLASH_TYPEMASK): + printf("4x AMD29LV017B (4x16Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + goto done; + break; + } + + break; + default: + printf("Unknown Vendor "); + break; + } + + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +done: ; +} + +/*----------------------------------------------------------------------- + */ + +/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */ +#define __udelay(delay) \ +{ \ + unsigned micro; \ + unsigned milli=0; \ + \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + \ + for (;;) { \ + \ + milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \ + micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \ + \ + if ((delay) <= (micro + (milli * 1000))) { \ + break; \ + } \ + } \ +} while (0) + +static u32 _amd_erase_flash(u32 addr, u32 sector) +{ + unsigned elapsed; + + /* Issue erase */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + *(volatile u32*)(addr + 0x5554) = 0x80808080; + /* And one unlock */ + *(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA; + *(volatile u32*)(addr + 0xaaa8) = 0x55555555; + /* Sector erase command comes last */ + *(volatile u32*)(addr + sector) = 0x30303030; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + __udelay(50); + while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { + + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + *(volatile u32*)(addr) = 0xf0f0f0f0; + return 1; + } + } + + *(volatile u32*)(addr) = 0xf0f0f0f0; + + return 0; +} + +extern int _amd_erase_flash_end; +asm ("_amd_erase_flash_end:\n" + ".long 0\n"); + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + u32 (*_erase_flash_ptr)(u32 a, u32 so); + int prot; + int sect; + unsigned size; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_erase_flash() routine too large (%d) %p - %p\n", + size, &_amd_erase_flash_end, _amd_erase_flash); + return 0; + } + + memcpy(buffer, _amd_erase_flash, size); + _erase_flash_ptr = (void*)buffer; + + } else { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + + if (info->protect[sect] == 0) { /* not protected */ + int res; + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + + if (res) { + printf("Erase timed out, sector %d\n", sect); + return res; + } + + putc('.'); + } + } + + + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) +{ + volatile u32 *addr2 = (u32*)start; + volatile u32 *dest2 = (u32*)dest; + volatile u32 *data2 = (u32*)&data; + unsigned elapsed; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile u32*)dest) & (u32)data) != (u32)data) { + return 2; + } + + addr2[0x5554] = 0xAAAAAAAA; + addr2[0xaaa8] = 0x55555555; + addr2[0x5554] = 0xA0A0A0A0; + + dest2[0] = data; + + elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */ + elapsed = 0; + + /* data polling for D7 */ + while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { + elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); + if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + addr2[0] = 0xf0f0f0f0; + return 1; + } + } + + + addr2[0] = 0xf0f0f0f0; + + return 0; +} + +extern int _amd_write_word_end; +asm ("_amd_write_word_end:\n" + ".long 0\n"); + + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 3 - Unsupported flash type + */ + +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + int flag; + u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data); + unsigned size; + + if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) { + size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; + + if (size > PROBE_BUFFER_SIZE) { + printf("_amd_write_word() routine too large (%d) %p - %p\n", + size, &_amd_write_word_end, _amd_write_word); + return 0; + } + + memcpy(buffer, _amd_write_word, size); + _write_word_ptr = (void*)buffer; + + } else { + printf ("Can't program unknown flash type - aborted\n"); + return 3; + } + + + wp = (addr & ~3); /* get lower word aligned address */ + + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + for (; i<4 && cnt>0; ++i) { + data |= *src++ << (8*i); + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + + for (i=0; i<4; ++i) { + data |= *src++ << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + if (rc != 0) { + return rc; + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return 0; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data |= *src++ << (8*i); + --cnt; + } + + for (; i<4; ++i, ++cp) { + data |= (*(uchar *)cp) << (8*i); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + rc = _write_word_ptr(info->start[0], wp, data); + + /* re-enable interrupts if necessary */ + if (flag) { + enable_interrupts(); + } + + return rc; + +}

2 1

[U-Boot] [RFC][PATCH 0/3] New i386 board (includes code relocation)
by Graeme Russ 28 Oct '08

28 Oct '08

Renamed show_boot_progress in assembler init phase to show_boot_progress_asm to avoid link conflicts with C version Signed-off-by: Graeme Russ <graeme.russ(a)gmail.com> -- diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S index 6ac5a5d..3a8a03f 100644 --- a/board/sc520_cdp/sc520_cdp_asm.S +++ b/board/sc520_cdp/sc520_cdp_asm.S @@ -76,8 +76,8 @@ done: movb $0x88, %al jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl show_boot_progress_asm +show_boot_progress_asm: out %al, $0x80 xchg %al, %ah movw $0x680, %dx diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S index 3430b6a..eda7e91 100644 --- a/board/sc520_spunk/sc520_spunk_asm.S +++ b/board/sc520_spunk/sc520_spunk_asm.S @@ -73,8 +73,8 @@ done: movl $0xfffefc32,%edx jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl show_boot_progress_asm +show_boot_progress_asm: movl $0xfffefc32,%edx xorw $0xffff, %ax movw %ax,(%edx) diff --git a/cpu/i386/start.S b/cpu/i386/start.S index 264ac09..84888aa 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -55,7 +55,7 @@ early_board_init_ret: /* so we try to indicate progress */ movw $0x01, %ax movl $.progress0, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress0: /* size memory */ @@ -74,7 +74,7 @@ mem_init_ret: /* indicate (lack of) progress */ movw $0x81, %ax movl $.progress0a, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress0a: jmp die mem_ok: @@ -82,7 +82,7 @@ mem_ok: /* indicate progress */ movw $0x02, %ax movl $.progress1, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress1: /* create a stack after the bss */ @@ -104,7 +104,7 @@ no_stack: /* indicate (lack of) progress */ movw $0x82, %ax movl $.progress1a, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress1a: jmp die @@ -113,7 +113,7 @@ stack_ok: /* indicate progress */ movw $0x03, %ax movl $.progress2, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress2: /* copy data section to ram, size must be 4-byte aligned */ @@ -136,7 +136,7 @@ data_fail: /* indicate (lack of) progress */ movw $0x83, %ax movl $.progress2a, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress2a: jmp die @@ -145,7 +145,7 @@ data_ok: /* indicate progress */ movw $0x04, %ax movl $.progress3, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress3: /* clear bss section in ram, size must be 4-byte aligned */ @@ -168,7 +168,7 @@ bss_fail: /* indicate (lack of) progress */ movw $0x84, %ax movl $.progress3a, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress3a: jmp die @@ -180,7 +180,7 @@ bss_ok: /* indicate progress */ movw $0x05, %ax movl $.progress4, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress4: call start_i386boot /* Enter, U-boot! */ @@ -188,7 +188,7 @@ bss_ok: /* indicate (lack of) progress */ movw $0x85, %ax movl $.progress4a, %ebp - jmp show_boot_progress + jmp show_boot_progress_asm .progress4a: die: hlt

2 1

[U-Boot] [PATCH 1/5] atmel_lcdfb: Eliminate unneeded #include <asm/arch/hardware.h>
by Haavard Skinnemoen 28 Oct '08

28 Oct '08

atmel_lcdfb doesn't actually need anything from asm/arch/hardware.h. It includes a file that does, asm/arch/gpio.h, but this file doesn't include <asm/arch/hardware.h> like it's supposed to. Add the missing include to asm/arch/gpio.h and remove the workaround from the atmel_lcdfb driver. This makes the driver compile on avr32. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- drivers/video/atmel_lcdfb.c | 1 - include/asm-arm/arch-at91/gpio.h | 1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index b332a82..7f0dceb 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -24,7 +24,6 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/hardware.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> diff --git a/include/asm-arm/arch-at91/gpio.h b/include/asm-arm/arch-at91/gpio.h index c4d7b97..e2d375b 100644 --- a/include/asm-arm/arch-at91/gpio.h +++ b/include/asm-arm/arch-at91/gpio.h @@ -16,6 +16,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/at91_pio.h> +#include <asm/arch/hardware.h> #define PIN_BASE 32 -- 1.5.6.3

5 14

[U-Boot] NET: Updated SMSC LAN9x1x EEPROM program?
by Magnus Lilja 26 Oct '08

26 Oct '08

Hi Is there an up to date smsc9111x_eeprom.c floating around somewhere? I found Mike Frysinger's post from March '08 but it needs updating to compile and work with current mainline U-boot, has anyone already done this? Thanks, Magnus

2 1

[U-Boot] [PATCH] Hardware watchdog support for AT91SAM9260 CPU
by Sergey Lapin 24 Oct '08

24 Oct '08

Signed-off-by: Sergey Lapin <slapin(a)ossfans.org> --- cpu/arm926ejs/at91/Makefile | 1 + cpu/arm926ejs/at91/watchdog.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/at91/watchdog.c diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 44cde1a..7befcd7 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -29,6 +29,7 @@ COBJS-y += ether.o COBJS-y += timer.o COBJS-$(CONFIG_HAS_DATAFLASH) +=spi.o COBJS-y += usb.o +COBJS-$(CONFIG_HW_WATCHDOG) +=watchdog.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) diff --git a/cpu/arm926ejs/at91/watchdog.c b/cpu/arm926ejs/at91/watchdog.c new file mode 100644 index 0000000..da15268 --- /dev/null +++ b/cpu/arm926ejs/at91/watchdog.c @@ -0,0 +1,35 @@ +/* + * watchdog.c - driver for at91sam9260 watchdog + * + * Copyright (c) 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> + +#ifdef CONFIG_HW_WATCHDOG +#define AT91_WDT_CR (AT91_WDT+0x00) +#define AT91_WDT_MR (AT91_WDT+0x04) +#define AT91_WDT_SR (AT91_WDT+0x08) + +void hw_watchdog_reset(void) +{ + at91_sys_write(AT91_WDT_CR, 0xa5000001); +} + +void hw_watchdog_init(void) +{ + /* 16 seconds timer, resets enabled */ + at91_sys_write(AT91_WDT_MR, 0x3FFF2FFF); +} + +void hw_watchdog_disable(void) +{ + /* Can't reenable per documentation */ + at91_sys_write(AT91_WDT_MR, 0x8000); +} +#endif -- 1.5.4.1

3 6

[U-Boot] [PATCH 2/2] IOMUX: Add console multiplexing support.
by Gary Jennejohn 21 Oct '08

21 Oct '08

Since this patch touches net/eth.c it is being sent separately. When CONFIG_IO_MUX, CONFIG_NETCONSOLE and CFG_CONSOLE_IS_IN_ENV are all defined together it is possible that nc (netconsole) is defined as an output device. In this case it is necessary to set GD_FLG_DEVINIT after the network devices have been initialized, otherwise u-boot might try to send output to a device before it is ready, which leads to various errors. Signed-off-by: Gary Jennejohn <garyj(a)denx.de> --- net/eth.c | 24 ++++++++++++++++++++++++ 1 files changed, 24 insertions(+), 0 deletions(-) diff --git a/net/eth.c b/net/eth.c index 432dd60..94b6e3a 100644 --- a/net/eth.c +++ b/net/eth.c @@ -26,6 +26,11 @@ #include <net.h> #include <miiphy.h> +#if defined(CONFIG_IO_MUX) && defined(CONFIG_NETCONSOLE) && \ + defined(CFG_CONSOLE_IS_IN_ENV) +DECLARE_GLOBAL_DATA_PTR; +#endif + #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) /* @@ -256,6 +261,15 @@ int eth_initialize(bd_t *bis) putc ('\n'); } +#if defined(CONFIG_IO_MUX) && defined(CONFIG_NETCONSOLE) && \ + defined(CFG_CONSOLE_IS_IN_ENV) + /* + * Must do this very late because a network device may be set as a + * console at boot time. + */ + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ +#endif + return eth_number; } @@ -532,6 +546,16 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_DRIVER_TI_EMAC) davinci_eth_miiphy_initialize(bis); #endif + +#if defined(CONFIG_IO_MUX) && defined(CONFIG_NETCONSOLE) && \ + defined(CFG_CONSOLE_IS_IN_ENV) + /* + * Must do this very late because a network device may be set as a + * console at boot time. + */ + gd->flags |= GD_FLG_DEVINIT; /* device initialization completed */ +#endif + return 0; } #endif -- 1.5.4.3 --- Gary Jennejohn ********************************************************************* DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de *********************************************************************

3 15

[U-Boot-Users] [PATCH][resubmit] AX88180: new gigabit network driver
by Louis 20 Oct '08

20 Oct '08

Resubmit the driver for the ASIX AX88180 gigabit ethernet chip. Signed-off-by: Louis Su louis(a)asix.com.tw --- drivers/net/Makefile | 1 + drivers/net/ax88180.c | 842 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ax88180.h | 415 ++++++++++++++++++++++++ 3 files changed, 1258 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ax88180.c create mode 100644 drivers/net/ax88180.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 84be288..3a574e0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o +COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c new file mode 100644 index 0000000..5579ef0 --- /dev/null +++ b/drivers/net/ax88180.c @@ -0,0 +1,842 @@ +/* ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + This program is free software; you can distribute it and/or modify + it under the terms of the GNU General Public License (Version 2) as + published by the Free Software Foundation. + This program is distributed in the hope it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, + USA. +*/ + +/* + ======================================================================== + ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver + + The AX88180 Ethernet controller is a high performance and highly + integrated local CPU bus Ethernet controller with embedded 40K bytes + SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any + embedded systems. + The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet + controller that supports both MII and RGMII interfaces and is + compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards. + + Please visit ASIX's web site (http://www.asix.com.tw) for more + details. + + Module Name : ax88180.c + Date : 2008-07-01 + History + 09/06/2006 : New release for AX88180 US2 chip. + 07/01/2008 : Fix up the coding style and using functions + instead of most macros + ======================================================================== +*/ +#include <common.h> +#include <command.h> +#include <net.h> + +#include "ax88180.h" + +#ifdef CONFIG_DRIVER_AX88180 + +/* +=========================================================================== +<<<<<< Local SubProgram Declaration >>>>>> +=========================================================================== +*/ +static void ax88180_rx_handler (void); +static int ax88180_PHY_initial (void); +static void ax88180_meida_config (void); +static unsigned long get_CicadaPHY_meida_mode (void); +static unsigned long get_MarvellPHY_meida_mode (void); +static unsigned short ax88180_mdio_read (unsigned long phyaddr, + unsigned long regaddr); +static void ax88180_mdio_write (unsigned long phyaddr, + unsigned long regaddr, + unsigned short regdata); + +/* +=========================================================================== +<<<<<< Declare Macro/Structure Definition >>>>>> +=========================================================================== +*/ +typedef enum _AX88180_LINK_STATE { + INS_LINK_DOWN, + INS_LINK_UP, + INS_LINK_UNKNOWN +} AX88180_LINK_STATE; + +typedef struct _AX88180_PRIVATE { + unsigned long PhyAddr; + unsigned long PhyID0; + unsigned long FirstTxDesc; + unsigned long NextTxDesc; + unsigned long rxbuf_overflow_count; + AX88180_LINK_STATE LinkState; +} AX88180_PRIVATE; + +AX88180_PRIVATE axlocal; + +#if (DEBUG_FLAGS & DEBUG_MSG) +static inline void ax88180_disp_all_reg (void) +{ + unsigned long tmpval; + int i; + PRINTK (DEBUG_MSG, "ax88180: AX88180 MAC Registers:\n"); + for (i = 0xFC00; i <= 0xFCFF; i += 4) { + READ_MACREG (i, tmpval); + PRINTK (DEBUG_MSG, "0x%04x=0x%08lx ", i, tmpval); + if ((i & 0xF) == 0xC) + PRINTK (DEBUG_MSG, "\n"); + } + PRINTK (DEBUG_MSG, "\n"); +} + +static inline void ax88180_disp_phy_reg (void) +{ + unsigned long tmpval; + tmpval = ax88180_mdio_read (axlocal.PhyAddr, BMCR); + PRINTK (DEBUG_MSG, "BMCR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + PRINTK (DEBUG_MSG, "BMSR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + PRINTK (DEBUG_MSG, "PHYIDR0=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR1); + PRINTK (DEBUG_MSG, "PHYIDR1=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANAR); + PRINTK (DEBUG_MSG, "ANAR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANLPAR); + PRINTK (DEBUG_MSG, "ANLPAR=0x%04x \n", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, ANER); + PRINTK (DEBUG_MSG, "ANER=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, AUX_1000_CTRL); + PRINTK (DEBUG_MSG, "1G_CTRL=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, AUX_1000_STATUS); + PRINTK (DEBUG_MSG, "1G_STATUS=0x%04x \n", (unsigned int)tmpval); + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_SSR); + PRINTK (DEBUG_MSG, "M88_SSR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_IER); + PRINTK (DEBUG_MSG, "M88_IER=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_ISR); + PRINTK (DEBUG_MSG, "M88_ISR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SCR); + PRINTK (DEBUG_MSG, "M88_EXT_SCR=0x%04x ", + (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SSR); + PRINTK (DEBUG_MSG, "M88_EXT_SSR=0x%04x \n", + (unsigned int)tmpval); + } else if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + tmpval = ax88180_mdio_read (axlocal.PhyAddr, CIS_IMR); + PRINTK (DEBUG_MSG, "CIS_IMR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, CIS_ISR); + PRINTK (DEBUG_MSG, "CIS_ISR=0x%04x ", (unsigned int)tmpval); + tmpval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + PRINTK (DEBUG_MSG, "CIS_AUX=0x%04x \n", + (unsigned int)tmpval); + } + READ_MACREG (RXCFG, tmpval); + PRINTK (DEBUG_MSG, "RXCFG=0x%08lx ", tmpval); + READ_MACREG (MACCFG0, tmpval); + PRINTK (DEBUG_MSG, "MACCFG0=0x%08lx ", tmpval); + READ_MACREG (MACCFG1, tmpval); + PRINTK (DEBUG_MSG, "MACCFG1=0x%08lx ", tmpval); + READ_MACREG (MACCFG2, tmpval); + PRINTK (DEBUG_MSG, "MACCFG2=0x%08lx \n\n", tmpval); +} +#else +static inline void ax88180_disp_all_reg (void) {} +static inline void ax88180_disp_phy_reg (void) {} +#endif + +/* +=========================================================================== +<<<<<< Local SubProgram Bodies >>>>>> +=========================================================================== +*/ +static int +ax88180_mdio_check_complete (void) +{ + int us_cnt = 10000; + unsigned long tmpval; + + /* MDIO read/write should not take more than 10 ms */ + while (--us_cnt) { + READ_MACREG (MDIOCTRL, tmpval); + if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0)) + break; + } + + return us_cnt; +} + +static unsigned short +ax88180_mdio_read (unsigned long phyaddr, unsigned long regaddr) +{ + unsigned long tmpval = 0; + + WRITE_MACREG (MDIOCTRL, READ_PHY | (regaddr << 8) | phyaddr); + + if (ax88180_mdio_check_complete ()) + READ_MACREG (MDIODP, tmpval); + else + printf("Failed to read PHY register!\n"); + return (unsigned short)(tmpval & 0xFFFF); +} + +static void +ax88180_mdio_write (unsigned long phyaddr, unsigned long regaddr, + unsigned short regdata) +{ + WRITE_MACREG (MDIODP, regdata); + WRITE_MACREG (MDIOCTRL, WRITE_PHY | (regaddr << 8) | phyaddr); + + if(!ax88180_mdio_check_complete ()) + printf("Failed to write PHY register!\n"); +} + +static int ax88180_phy_reset (void) +{ + unsigned short delay_cnt = 500; + + ax88180_mdio_write (axlocal.PhyAddr, BMCR, PHY_RESET | AUTONEG_EN); + + /* Wait for the reset to complete, or time out (500 ms) */ + while (ax88180_mdio_read (axlocal.PhyAddr, BMCR) & PHY_RESET) { + udelay (1000); + if (--delay_cnt == 0) { + printf("Failed to reset PHY!\n"); + return -1; + } + } + + return 0; +} + +static void ax88180_mac_reset (void) +{ + unsigned long tmpval; + + WRITE_MACREG (MISC, MISC_RESET_MAC); + READ_MACREG (MISC, tmpval); + WRITE_MACREG (MISC, MISC_NORMAL); + WRITE_MACREG (RXINDICATOR, DEFAULT_RXINDICATOR); + WRITE_MACREG (TXCMD, DEFAULT_TXCMD); + WRITE_MACREG (TXBS, DEFAULT_TXBS); + WRITE_MACREG (TXDES0, DEFAULT_TXDES0); + WRITE_MACREG (TXDES1, DEFAULT_TXDES1); + WRITE_MACREG (TXDES2, DEFAULT_TXDES2); + WRITE_MACREG (TXDES3, DEFAULT_TXDES3); + WRITE_MACREG (TXCFG, DEFAULT_TXCFG); + WRITE_MACREG (MACCFG2, DEFAULT_MACCFG2); + WRITE_MACREG (MACCFG3, DEFAULT_MACCFG3); + WRITE_MACREG (TXLEN, DEFAULT_TXLEN); + WRITE_MACREG (RXBTHD0, DEFAULT_RXBTHD0); + WRITE_MACREG (RXBTHD1, DEFAULT_RXBTHD1); + WRITE_MACREG (RXFULTHD, DEFAULT_RXFULTHD); + WRITE_MACREG (DOGTHD0, DEFAULT_DOGTHD0); + WRITE_MACREG (DOGTHD1, DEFAULT_DOGTHD1); +} + +static int ax88180_poll_tx_complete (void) +{ + unsigned long tmp_data, txbs_txdp; + int TimeOutCnt = 10000; + + txbs_txdp = 1 << axlocal.NextTxDesc; + + while (TimeOutCnt--) { + + READ_MACREG (TXBS, tmp_data); + if ((tmp_data & txbs_txdp) == 0) + break; + + udelay (100); + } + + if (TimeOutCnt) + return 0; + else + return -TimeOutCnt; +} + +static void ax88180_rx_handler (void) +{ + unsigned char *rxdata; + unsigned long tmp_data; + unsigned long rx_packet_len; + unsigned int data_size; + unsigned int dword_count, byte_count; + unsigned long rxcurt_ptr, rxbound_ptr, next_ptr; + int i; + int j; + + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + PRINTK (RX_MSG, "ax88180: RX original RXBOUND=0x%08lx," + " RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + + while (next_ptr != rxcurt_ptr) { + WRITE_MACREG (RXINDICATOR, RX_START_READ); + READ_RXBUF (rx_packet_len); + if ((rx_packet_len == 0) || (rx_packet_len > MAX_RX_SIZE)) { + WRITE_MACREG (RXINDICATOR, RX_STOP_READ); + ax88180_mac_reset (); + printf ("ax88180: Invalid Rx packet length!" + " (len=0x%08lx)\n", rx_packet_len); + + printf ("ax88180: RX RXBOUND=0x%08lx," + "RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + return; + } + data_size = (unsigned int)rx_packet_len; + rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1; + rxbound_ptr &= RX_PAGE_NUM_MASK; + + rxdata = (unsigned char *)NetRxPackets[0]; + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + dword_count = data_size >> 1; + byte_count = data_size & 0x1; +#else + dword_count = data_size >> 2; + byte_count = data_size & 0x3; +#endif + for (i = 0; i < dword_count; i++) { + READ_RXBUF (tmp_data); +#if defined (CONFIG_DRIVER_AX88180_16BIT) + *((unsigned short *)rxdata + i) = tmp_data; +#else + *((unsigned long *)rxdata + i) = tmp_data; +#endif + } + if (byte_count != 0) { + READ_RXBUF (tmp_data); + for (j = 0; j < byte_count; j++) { + *(rxdata + (dword_count * 4) + j) = + (unsigned char)(tmp_data >> (j * 8)); + } + } + + WRITE_MACREG (RXINDICATOR, RX_STOP_READ); + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], data_size); + + WRITE_MACREG (RXBOUND, rxbound_ptr); + + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK; + + PRINTK (RX_MSG, "ax88180: RX updated RXBOUND=0x%08lx," + "RXCURT=0x%08lx\n", rxbound_ptr, rxcurt_ptr); + } + + if (axlocal.rxbuf_overflow_count > 0) + axlocal.rxbuf_overflow_count--; + + return; +} + +static int ax88180_PHY_initial (void) +{ + unsigned long tmp_regval; + int i; + int ret; + + /* Check avaliable PHY chipset */ + axlocal.PhyAddr = MARVELL_88E1111_PHYADDR; + axlocal.PhyID0 = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + PRINTK (DEBUG_MSG, "ax88180: Found Marvell 88E1111 PHY." + " (PHY Addr=0x%lx)\n", axlocal.PhyAddr); + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, M88_EXT_SSR); + if ((tmp_regval & HWCFG_MODE_MASK) == RGMII_COPPER_MODE) { + ax88180_mdio_write (axlocal.PhyAddr, M88_EXT_SCR, + DEFAULT_EXT_SCR); + if ((ret = ax88180_phy_reset ()) < 0) + return ret; + ax88180_mdio_write (axlocal.PhyAddr, M88_IER, + LINK_CHANGE_INT); + } + } else { + axlocal.PhyAddr = CICADA_CIS8201_PHYADDR; + axlocal.PhyID0 = ax88180_mdio_read (axlocal.PhyAddr, PHYIDR0); + if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + PRINTK (DEBUG_MSG, "ax88180: Found CICADA CIS8201 PHY" + " chipset. (PHY Addr=0x%lx)\n", + axlocal.PhyAddr); + ax88180_mdio_write (axlocal.PhyAddr, CIS_IMR, + (CIS_INT_ENABLE | LINK_CHANGE_INT)); + + /* + Set CIS_SMI_PRIORITY bit before force the media mode + */ + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + tmp_regval &= ~CIS_SMI_PRIORITY; + ax88180_mdio_write (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS, tmp_regval); + } else { + printf ("ax88180: Unknown PHY chipset!!\n"); + return -1; + } + } + + /* Waiting for auto-negotiation complete. */ + /* This may take up to 5 seconds */ + PRINTK (DEBUG_MSG, + "ax88180: Waiting for auto-negotiation completion......\n"); + for (i = 0; i < 5000; i++) { + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + if (tmp_regval & AUTONEG_COMPLETE) { + break; + } + udelay (1000); + } + + return 0; +} + +static void ax88180_meida_config (void) +{ + unsigned long bmcr_val, bmsr_val; + unsigned long rxcfg_val, maccfg0_val, maccfg1_val; + unsigned long RealMediaMode; + int i; + + /* Waiting 200 msecs for PHY link stable */ + for (i = 0; i < 200; i++) { + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + if (bmsr_val & LINKOK) { + break; + } + udelay (1000); + } + + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, BMSR); + PRINTK (DEBUG_MSG, "ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val); + + if (bmsr_val & LINKOK) { + bmcr_val = ax88180_mdio_read (axlocal.PhyAddr, BMCR); + if (bmcr_val & AUTONEG_EN) { + /* Waiting for Auto-negotiation completion */ + /* This may take up to 5 seconds */ + PRINTK (DEBUG_MSG, "ax88180: Auto-negotiation is " + "enabled. Waiting for NWay completion..\n"); + for (i = 0; i < 5000; i++) { + bmsr_val = ax88180_mdio_read (axlocal.PhyAddr, + BMSR); + if (bmsr_val & AUTONEG_COMPLETE) { + break; + } + udelay (1000); + } + } else + PRINTK (DEBUG_MSG, + "ax88180: Auto-negotiation is disabled.\n"); + + PRINTK (DEBUG_MSG, "ax88180: BMCR=0x%04x, BMSR=0x%04x\n", + (unsigned int)bmcr_val, (unsigned int)bmsr_val); + + /* Get real media mode here */ + if (axlocal.PhyID0 == MARVELL_88E1111_PHYIDR0) { + RealMediaMode = get_MarvellPHY_meida_mode (); + } else if (axlocal.PhyID0 == CICADA_CIS8201_PHYIDR0) { + RealMediaMode = get_CicadaPHY_meida_mode (); + } else { + RealMediaMode = MEDIA_1000FULL; + } + + switch (RealMediaMode) { + default: + case MEDIA_1000FULL: + PRINTK (DEBUG_MSG, + "ax88180: 1000Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | RXFLOW_EN | + FULLDUPLEX | DEFAULT_MACCFG1; + break; + + case MEDIA_1000HALF: + PRINTK (DEBUG_MSG, + "ax88180: 1000Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1; + break; + + case MEDIA_100FULL: + PRINTK (DEBUG_MSG, + "ax88180: 100Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = SPEED100 | TXFLOW_ENABLE + | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX + | DEFAULT_MACCFG1; + break; + + case MEDIA_100HALF: + PRINTK (DEBUG_MSG, + "ax88180: 100Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = SPEED100 | DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + + case MEDIA_10FULL: + PRINTK (DEBUG_MSG, + "ax88180: 10Mbps Full-duplex mode.\n"); + rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG; + maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0; + maccfg1_val = RXFLOW_EN | FULLDUPLEX + | DEFAULT_MACCFG1; + break; + + case MEDIA_10HALF: + PRINTK (DEBUG_MSG, + "ax88180: 10Mbps Half-duplex mode.\n"); + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + break; + } + + axlocal.LinkState = INS_LINK_UP; + } else { + rxcfg_val = DEFAULT_RXCFG; + maccfg0_val = DEFAULT_MACCFG0; + maccfg1_val = DEFAULT_MACCFG1; + + axlocal.LinkState = INS_LINK_DOWN; + } + + WRITE_MACREG (RXCFG, rxcfg_val); + WRITE_MACREG (MACCFG0, maccfg0_val); + WRITE_MACREG (MACCFG1, maccfg1_val); + + return; +} + +static unsigned long +get_MarvellPHY_meida_mode (void) +{ + unsigned long m88_ssr; + unsigned long MediaMode; + + m88_ssr = ax88180_mdio_read (axlocal.PhyAddr, M88_SSR); + switch (m88_ssr & SSR_MEDIA_MASK) { + default: + case SSR_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case SSR_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case SSR_100FULL: + MediaMode = MEDIA_100FULL; + break; + case SSR_100HALF: + MediaMode = MEDIA_100HALF; + break; + case SSR_10FULL: + MediaMode = MEDIA_10FULL; + break; + case SSR_10HALF: + MediaMode = MEDIA_10HALF; + break; + } + + return MediaMode; +} + +static unsigned long +get_CicadaPHY_meida_mode (void) +{ + unsigned long tmp_regval; + unsigned long MediaMode; + + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + CIS_AUX_CTRL_STATUS); + switch (tmp_regval & CIS_MEDIA_MASK) { + default: + case CIS_1000FULL: + MediaMode = MEDIA_1000FULL; + break; + case CIS_1000HALF: + MediaMode = MEDIA_1000HALF; + break; + case CIS_100FULL: + MediaMode = MEDIA_100FULL; + break; + case CIS_100HALF: + MediaMode = MEDIA_100HALF; + break; + case CIS_10FULL: + MediaMode = MEDIA_10FULL; + break; + case CIS_10HALF: + MediaMode = MEDIA_10HALF; + break; + } + + return MediaMode; +} + +/* +=========================================================================== +<<<<<< Exported SubProgram Bodies >>>>>> +=========================================================================== +*/ +void eth_halt (void) +{ + /* Disable AX88180 TX/RX functions */ + WRITE_MACREG (CMD, WAKEMOD); +} + +int eth_init (bd_t *bd) +{ + unsigned long tmp_regval; + unsigned long macid0_val, macid1_val, macid2_val; + int ret, i; + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + *((volatile unsigned short *)(AX88180_BASE + 6)) = (START_BASE >> 8); + *((volatile unsigned short *)AX88180_BASE ) = 1; +#endif + memset (&axlocal, 0, sizeof (AX88180_PRIVATE)); + + ax88180_mac_reset (); + + /* Disable AX88180 interrupt */ + WRITE_MACREG (IMR, CLEAR_IMR); + + /* Disable AX88180 TX/RX functions */ + WRITE_MACREG (CMD, WAKEMOD); + + axlocal.LinkState = INS_LINK_UNKNOWN; + + /* Initial PHY registers */ + if ((ret = ax88180_PHY_initial ()) < 0) + return ret; + ax88180_meida_config (); + + /* Reload MAC address from EEPROM */ + WRITE_MACREG (PROMCTRL, RELOAD_EEPROM); + + /* Waiting for reload eeprom completion */ + for (i = 0; i < 500; i++) { + READ_MACREG (PROMCTRL, tmp_regval); + if ((tmp_regval & RELOAD_EEPROM) == 0) + break; + udelay (1000); + } + + /* Get MAC addresses */ + READ_MACREG (MACID0, macid0_val); + READ_MACREG (MACID1, macid1_val); + READ_MACREG (MACID2, macid2_val); + + bd->bi_enetaddr[0] = (unsigned char)macid0_val; + bd->bi_enetaddr[1] = (unsigned char)(macid0_val >> 8); + bd->bi_enetaddr[2] = (unsigned char)macid1_val; + bd->bi_enetaddr[3] = (unsigned char)(macid1_val >> 8); + bd->bi_enetaddr[4] = (unsigned char)macid2_val; + bd->bi_enetaddr[5] = (unsigned char)(macid2_val >> 8); + + if (((macid0_val | macid1_val | macid2_val) == 0) || + (bd->bi_enetaddr[0] & 0x01)) { + /* try to get MAC address from environment */ + u8 i; + char *s, *e; + unsigned short tmp16; + + s = getenv ("ethaddr"); + for (i = 0; i < 6; ++i) { + bd->bi_enetaddr[i] = s ? + simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + tmp16 = bd->bi_enetaddr[1]; + macid0_val = (tmp16 << 8) | bd->bi_enetaddr[0]; + tmp16 = bd->bi_enetaddr[3]; + macid1_val = (tmp16 << 8) | bd->bi_enetaddr[2]; + tmp16 = bd->bi_enetaddr[5]; + macid2_val = (tmp16 << 8) | bd->bi_enetaddr[4]; + + WRITE_MACREG (MACID0, macid0_val); + WRITE_MACREG (MACID1, macid1_val); + WRITE_MACREG (MACID2, macid2_val); + } + + WRITE_MACREG (RXFILTER, DEFAULT_RXFILTER); + + /* Initial variables here */ + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + axlocal.rxbuf_overflow_count = 0; + + ax88180_disp_all_reg (); + + /* Check if there is any invalid interrupt status. If yes, clear it. */ + READ_MACREG (ISR, tmp_regval); + PRINTK (DEBUG_MSG, "ax88180: The interrupt status = 0x%08lx\n", + tmp_regval); + if (tmp_regval) + WRITE_MACREG (ISR, tmp_regval); + + /* Start AX88180 TX/RX functions */ + WRITE_MACREG (CMD, RXEN | TXEN | WAKEMOD); + + return 0; +} + +/* Get a data block via Ethernet */ +int eth_rx (void) +{ + unsigned long ISR_Status; + unsigned long rxcurt_ptr, rxbound_ptr; + unsigned long tmp_regval; + + /* Read and check interrupt status here...... */ + READ_MACREG (ISR, ISR_Status); + + while (ISR_Status) { + /* Clear the interrupt status */ + WRITE_MACREG (ISR, ISR_Status); + + PRINTK (INT_MSG, + "\nax88180: The interrupt status = 0x%08lx\n", + ISR_Status); + + if (ISR_Status & ISR_PHY) { + /* Read ISR register once to clear PHY interrupt bit */ + tmp_regval = ax88180_mdio_read (axlocal.PhyAddr, + M88_ISR); + ax88180_meida_config (); + ax88180_disp_phy_reg (); + } + + if (ISR_Status & ISR_RXBUFFOVR) { + axlocal.rxbuf_overflow_count++; + READ_MACREG (RXCURT, rxcurt_ptr); + READ_MACREG (RXBOUND, rxbound_ptr); + PRINTK (INT_MSG, "ax88180: RX Buffer overflow! " + "count=%d, RXBOUND=0x%08lx, RXCURT=0x%08lx\n", + (int)axlocal.rxbuf_overflow_count, rxbound_ptr, + rxcurt_ptr); + + if (axlocal.rxbuf_overflow_count > 10) { + ax88180_mac_reset (); + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + axlocal.rxbuf_overflow_count = 0; + } + } + + if (ISR_Status & ISR_RX) { + ax88180_rx_handler (); + } + + /* Read and check interrupt status here...... */ + READ_MACREG (ISR, ISR_Status); + } + + return 0; +} + +/* Send a data block via Ethernet. */ +int eth_send (volatile void *packet, int length) +{ + volatile unsigned char *txdata; + unsigned long TXDES_addr; + unsigned long txcmd_txdp, txbs_txdp; + unsigned long tmp_data; + int i; + + if (axlocal.LinkState != INS_LINK_UP) { + return 0; + } + + txdata = (volatile unsigned char *)packet; + + axlocal.FirstTxDesc = axlocal.NextTxDesc; + txbs_txdp = 1 << axlocal.FirstTxDesc; + + READ_MACREG (TXBS, tmp_data); + READ_MACREG (TXBS, tmp_data); + PRINTK (TX_MSG, "ax88180: Checking available TXDP (TXBS=0x%08lx)\n", + tmp_data); + + /* check the available transmit descriptor */ + if (tmp_data & txbs_txdp) { + /* we should never get here. */ + /* we are running out of resource */ + return 0; + } + + PRINTK (TX_MSG, "ax88180: TXDP%d is available, i=%d\n", + (int)axlocal.FirstTxDesc, i); + + txcmd_txdp = axlocal.FirstTxDesc << 13; + TXDES_addr = TXDES0 + (axlocal.FirstTxDesc << 2); + + WRITE_MACREG (TXCMD, txcmd_txdp | length | TX_START_WRITE); + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + for (i = 0; i < length; i += 2) { + tmp_data = + (unsigned short)*(txdata + i) + + (unsigned short)(*(txdata + i + 1) << 8); + WRITE_TXBUF (tmp_data); + } +#else + for (i = 0; i < length; i += 4) { + tmp_data = + (unsigned long)*(txdata + i) + + (unsigned long)(*(txdata + i + 1) << 8) + + (unsigned long)(*(txdata + i + 2) << 16) + + (unsigned long)(*(txdata + i + 3) << 24); + WRITE_TXBUF (tmp_data); + } +#endif + + WRITE_MACREG (TXCMD, txcmd_txdp | length); + WRITE_MACREG (TXBS, txbs_txdp); + WRITE_MACREG (TXDES_addr, TXDPx_ENABLE | length); + + axlocal.NextTxDesc = (axlocal.NextTxDesc + 1) & TXDP_MASK; + + /* + Check the available transmit descriptor, if we had exhausted all + transmit descriptor ,then we have to wait for at least one free + descriptor + */ + txbs_txdp = 1 << axlocal.NextTxDesc; + READ_MACREG (TXBS, tmp_data); + if (tmp_data & txbs_txdp) { + if (ax88180_poll_tx_complete () < 0) { + ax88180_mac_reset (); + axlocal.FirstTxDesc = TXDP0; + axlocal.NextTxDesc = TXDP0; + printf ("ax88180: Transmit time out occurred!\n"); + } + } + + return 0; +} +#endif /* CONFIG_DRIVER_AX88180 */ + diff --git a/drivers/net/ax88180.h b/drivers/net/ax88180.h new file mode 100644 index 0000000..ae4b1b3 --- /dev/null +++ b/drivers/net/ax88180.h @@ -0,0 +1,415 @@ +/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */ +/* + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#include <asm/types.h> +#include <config.h> + +#ifdef CONFIG_DRIVER_AX88180 + +#define ENABLE_JUMBO 1 +#define DISABLE_JUMBO 0 + +#define ENABLE_BURST 1 +#define DISABLE_BURST 0 + +#define NORMAL_RX_MODE 0 +#define RX_LOOPBACK_MODE 1 +#define RX_INIFINIT_LOOP_MODE 2 +#define TX_INIFINIT_LOOP_MODE 3 + +#define DEFAULT_ETH_MTU 1500 + +/* Jumbo packet size 4086 bytes included 4 bytes CRC*/ +#define MAX_JUMBO_MTU 4072 + +/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */ +#define MAX_TX_JUMBO_SIZE 4086 + +/* Max Rx Jumbo size is 15K Bytes */ +#define MAX_RX_SIZE 0x3C00 + +#define MARVELL_88E1111_PHYADDR 0x18 +#define MARVELL_88E1111_PHYIDR0 0x0141 + +#define CICADA_CIS8201_PHYADDR 0x01 +#define CICADA_CIS8201_PHYIDR0 0x000F + +#define MEDIA_AUTO 0 +#define MEDIA_1000FULL 1 +#define MEDIA_1000HALF 2 +#define MEDIA_100FULL 3 +#define MEDIA_100HALF 4 +#define MEDIA_10FULL 5 +#define MEDIA_10HALF 6 + +#define AUTO_MEDIA 0 +#define FORCE_MEDIA 1 + +#define TXDP_MASK 3 +#define TXDP0 0 +#define TXDP1 1 +#define TXDP2 2 +#define TXDP3 3 + +#define CMD_MAP_SIZE 0x100 + +#if defined (CONFIG_DRIVER_AX88180_16BIT) + #define AX88180_MEMORY_SIZE 0x00004000 + #define START_BASE 0x1000 + + #define RX_BUF_SIZE 0x1000 + #define TX_BUF_SIZE 0x0F00 + + #define TX_BASE START_BASE + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) + #define RX_BASE (CMD_BASE + CMD_MAP_SIZE) +#else + #define AX88180_MEMORY_SIZE 0x00010000 + + #define RX_BUF_SIZE 0x8000 + #define TX_BUF_SIZE 0x7C00 + + #define RX_BASE 0x0000 + #define TX_BASE (RX_BASE + RX_BUF_SIZE) + #define CMD_BASE (TX_BASE + TX_BUF_SIZE) +#endif + +/* AX88180 Memory Mapping Definition */ +#define RXBUFFER_START RX_BASE + #define RX_PACKET_LEN_OFFSET 0 + #define RX_PAGE_NUM_MASK 0x7FF //RX pages 0~7FFh +#define TXBUFFER_START TX_BASE + +/* AX88180 MAC Register Definition */ +#define CMD (CMD_BASE + 0x0000) + #define WAKEMOD 0x00000001 + #define TXEN 0x00000100 + #define RXEN 0x00000200 + #define DEFAULT_CMD WAKEMOD +#define IMR (CMD_BASE + 0x0004) + #define IMR_RXBUFFOVR 0x00000001 + #define IMR_WATCHDOG 0x00000002 + #define IMR_TX 0x00000008 + #define IMR_RX 0x00000010 + #define IMR_PHY 0x00000020 + #define CLEAR_IMR 0x00000000 + #define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\ + IMR_RXBUFFOVR | IMR_WATCHDOG) +#define ISR (CMD_BASE + 0x0008) + #define ISR_RXBUFFOVR 0x00000001 + #define ISR_WATCHDOG 0x00000002 + #define ISR_TX 0x00000008 + #define ISR_RX 0x00000010 + #define ISR_PHY 0x00000020 +#define TXCFG (CMD_BASE + 0x0010) + #define AUTOPAD_CRC 0x00000050 + #define DEFAULT_TXCFG AUTOPAD_CRC +#define TXCMD (CMD_BASE + 0x0014) + #define TXCMD_TXDP_MASK 0x00006000 + #define TXCMD_TXDP0 0x00000000 + #define TXCMD_TXDP1 0x00002000 + #define TXCMD_TXDP2 0x00004000 + #define TXCMD_TXDP3 0x00006000 + #define TX_START_WRITE 0x00008000 + #define TX_STOP_WRITE 0x00000000 + #define DEFAULT_TXCMD 0x00000000 +#define TXBS (CMD_BASE + 0x0018) + #define TXDP0_USED 0x00000001 + #define TXDP1_USED 0x00000002 + #define TXDP2_USED 0x00000004 + #define TXDP3_USED 0x00000008 + #define DEFAULT_TXBS 0x00000000 +#define TXDES0 (CMD_BASE + 0x0020) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES0 0x00000000 +#define TXDES1 (CMD_BASE + 0x0024) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES1 0x00000000 +#define TXDES2 (CMD_BASE + 0x0028) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES2 0x00000000 +#define TXDES3 (CMD_BASE + 0x002C) + #define TXDPx_ENABLE 0x00008000 + #define TXDPx_LEN_MASK 0x00001FFF + #define DEFAULT_TXDES3 0x00000000 +#define RXCFG (CMD_BASE + 0x0030) + #define RXBUFF_PROTECT 0x00000001 + #define RXTCPCRC_CHECK 0x00000010 + #define RXFLOW_ENABLE 0x00000100 + #define DEFAULT_RXCFG RXBUFF_PROTECT +#define RXCURT (CMD_BASE + 0x0034) + #define DEFAULT_RXCURT 0x00000000 +#define RXBOUND (CMD_BASE + 0x0038) + #define DEFAULT_RXBOUND 0x7FF //RX pages 0~7FFh +#define MACCFG0 (CMD_BASE + 0x0040) + #define MACCFG0_BIT3_0 0x00000007 + #define IPGT_VAL 0x00000150 + #define TXFLOW_ENABLE 0x00001000 + #define SPEED100 0x00008000 + #define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0) +#define MACCFG1 (CMD_BASE + 0x0044) + #define RGMII_EN 0x00000002 + #define RXFLOW_EN 0x00000020 + #define FULLDUPLEX 0x00000040 + #define MAX_JUMBO_LEN_MASK 0x00000780 + #define RXJUMBO_EN 0x00000800 + #define GIGA_MODE_EN 0x00001000 + #define RXCRC_CHECK 0x00002000 + #define RXPAUSE_DA_CHECK 0x00004000 + + #define JUMBO_LEN_4K 0x00000200 + #define JUMBO_LEN_15K 0x00000780 + #define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK |\ + RGMII_EN) + #define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK) +#define MACCFG2 (CMD_BASE + 0x0048) + #define MACCFG2_BIT15_8 0x00000100 + #define JAM_LIMIT_MASK 0x000000FC + #define DEFAULT_JAM_LIMIT 0x00000064 + #define DEFAULT_MACCFG2 MACCFG2_BIT15_8 +#define MACCFG3 (CMD_BASE + 0x004C) + #define IPGR2_VAL 0x0000000E + #define IPGR1_VAL 0x00000600 + #define NOABORT 0x00008000 + #define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL) +#define TXPAUT (CMD_BASE + 0x0054) + #define DEFAULT_TXPAUT 0x001FE000 +#define RXBTHD0 (CMD_BASE + 0x0058) + #define DEFAULT_RXBTHD0 0x00000300 +#define RXBTHD1 (CMD_BASE + 0x005C) + #define DEFAULT_RXBTHD1 0x00000600 +#define RXFULTHD (CMD_BASE + 0x0060) + #define DEFAULT_RXFULTHD 0x00000100 +#define MISC (CMD_BASE + 0x0068) + /* Normal operation mode */ + #define MISC_NORMAL 0x00000003 + /* Clear bit 0 to reset MAC */ + #define MISC_RESET_MAC 0x00000002 + /* Clear bit 1 to reset PHY */ + #define MISC_RESET_PHY 0x00000001 + /* Clear bit 0 and 1 to reset MAC and PHY */ + #define MISC_RESET_MAC_PHY 0x00000000 + #define DEFAULT_MISC MISC_NORMAL +#define MACID0 (CMD_BASE + 0x0070) +#define MACID1 (CMD_BASE + 0x0074) +#define MACID2 (CMD_BASE + 0x0078) +#define TXLEN (CMD_BASE + 0x007C) + #define DEFAULT_TXLEN 0x000005FC +#define RXFILTER (CMD_BASE + 0x0080) + #define RX_RXANY 0x00000001 + #define RX_MULTICAST 0x00000002 + #define RX_UNICAST 0x00000004 + #define RX_BROADCAST 0x00000008 + #define RX_MULTI_HASH 0x00000010 + #define DISABLE_RXFILTER 0x00000000 + #define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST) +#define MDIOCTRL (CMD_BASE + 0x0084) + #define PHY_ADDR_MASK 0x0000001F + #define REG_ADDR_MASK 0x00001F00 + #define READ_PHY 0x00004000 + #define WRITE_PHY 0x00008000 +#define MDIODP (CMD_BASE + 0x0088) +#define GPIOCTRL (CMD_BASE + 0x008C) +#define RXINDICATOR (CMD_BASE + 0x0090) + #define RX_START_READ 0x00000001 + #define RX_STOP_READ 0x00000000 + #define DEFAULT_RXINDICATOR RX_STOP_READ +#define TXST (CMD_BASE + 0x0094) +#define MDCCLKPAT (CMD_BASE + 0x00A0) +#define RXIPCRCCNT (CMD_BASE + 0x00A4) +#define RXCRCCNT (CMD_BASE + 0x00A8) +#define TXFAILCNT (CMD_BASE + 0x00AC) +#define PROMDP (CMD_BASE + 0x00B0) +#define PROMCTRL (CMD_BASE + 0x00B4) + #define RELOAD_EEPROM 0x00000200 +#define MAXRXLEN (CMD_BASE + 0x00B8) +#define HASHTAB0 (CMD_BASE + 0x00C0) +#define HASHTAB1 (CMD_BASE + 0x00C4) +#define HASHTAB2 (CMD_BASE + 0x00C8) +#define HASHTAB3 (CMD_BASE + 0x00CC) +#define DOGTHD0 (CMD_BASE + 0x00E0) + #define DEFAULT_DOGTHD0 0x0000FFFF +#define DOGTHD1 (CMD_BASE + 0x00E4) + #define START_WATCHDOG_TIMER 0x00008000 + #define DEFAULT_DOGTHD1 0x00000FFF +#define SOFTRST (CMD_BASE + 0x00EC) + #define SOFTRST_NORMAL 0x00000003 + #define SOFTRST_RESET_MAC 0x00000002 + +/* External PHY Register Definition */ +#define BMCR 0x0000 + #define LINE_SPEED_MSB 0x0040 + #define DUPLEX_MODE 0x0100 + #define RESTART_AUTONEG 0x0200 + #define POWER_DOWN 0x0800 + #define AUTONEG_EN 0x1000 + #define LINE_SPEED_LSB 0x2000 + #define PHY_RESET 0x8000 + + #define MEDIAMODE_MASK (LINE_SPEED_MSB | LINE_SPEED_LSB |\ + DUPLEX_MODE) + #define BMCR_SPEED_1000 LINE_SPEED_MSB + #define BMCR_SPEED_100 LINE_SPEED_LSB + #define BMCR_SPEED_10 0x0000 + + #define BMCR_1000FULL (BMCR_SPEED_1000 | DUPLEX_MODE) + #define BMCR_100FULL (BMCR_SPEED_100 | DUPLEX_MODE) + #define BMCR_100HALF BMCR_SPEED_100 + #define BMCR_10FULL DUPLEX_MODE + #define BMCR_10HALF 0x0000 +#define BMSR 0x0001 + #define LINKOK 0x0004 + #define AUTONEG_ENABLE_STS 0x0008 + #define AUTONEG_COMPLETE 0x0020 +#define PHYIDR0 0x0002 +#define PHYIDR1 0x0003 +#define ANAR 0x0004 + #define ANAR_PAUSE 0x0400 + #define ANAR_100FULL 0x0100 + #define ANAR_100HALF 0x0080 + #define ANAR_10FULL 0x0040 + #define ANAR_10HALF 0x0020 + #define ANAR_8023BIT 0x0001 +#define ANLPAR 0x0005 +#define ANER 0x0006 +#define AUX_1000_CTRL 0x0009 + #define ENABLE_1000HALF 0x0100 + #define ENABLE_1000FULL 0x0200 + #define DEFAULT_AUX_1000_CTRL (ENABLE_1000HALF | ENABLE_1000FULL) +#define AUX_1000_STATUS 0x000A + #define LP_1000HALF 0x0400 + #define LP_1000FULL 0x0800 + +/* Marvell 88E1111 Gigabit PHY Register Definition */ +#define M88_SSR 0x0011 + #define SSR_SPEED_MASK 0xC000 + #define SSR_SPEED_1000 0x8000 + #define SSR_SPEED_100 0x4000 + #define SSR_SPEED_10 0x0000 + #define SSR_DUPLEX 0x2000 + #define SSR_MEDIA_RESOLVED_OK 0x0800 + + #define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX) + #define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX) + #define SSR_1000HALF SSR_SPEED_1000 + #define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX) + #define SSR_100HALF SSR_SPEED_100 + #define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX) + #define SSR_10HALF SSR_SPEED_10 +#define M88_IER 0x0012 + #define LINK_CHANGE_INT 0x0400 +#define M88_ISR 0x0013 + #define LINK_CHANGE_STATUS 0x0400 +#define M88_EXT_SCR 0x0014 + #define RGMII_RXCLK_DELAY 0x0080 + #define RGMII_TXCLK_DELAY 0x0002 + #define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY) +#define M88_EXT_SSR 0x001B + #define HWCFG_MODE_MASK 0x000F + #define RGMII_COPPER_MODE 0x000B + +/* CICADA CIS8201 Gigabit PHY Register Definition */ +#define CIS_IMR 0x0019 + #define CIS_INT_ENABLE 0x8000 + #define CIS_LINK_CHANGE_INT 0x2000 +#define CIS_ISR 0x001A + #define CIS_INT_PENDING 0x8000 + #define CIS_LINK_CHANGE_STATUS 0x2000 +#define CIS_AUX_CTRL_STATUS 0x001C + #define CIS_AUTONEG_COMPLETE 0x8000 + #define CIS_SPEED_MASK 0x0018 + #define CIS_SPEED_1000 0x0010 + #define CIS_SPEED_100 0x0008 + #define CIS_SPEED_10 0x0000 + #define CIS_DUPLEX 0x0020 + + #define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX) + #define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX) + #define CIS_1000HALF CIS_SPEED_1000 + #define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX) + #define CIS_100HALF CIS_SPEED_100 + #define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX) + #define CIS_10HALF CIS_SPEED_10 + #define CIS_SMI_PRIORITY 0x0004 + +/* Debug Message Display Level Definition */ +#define TX_MSG 0x0001 +#define RX_MSG 0x0002 +#define INT_MSG 0x0004 +#define DEBUG_MSG 0x0008 +#define NO_MSG 0x0000 +#define DEBUG_FLAGS (NO_MSG) + +#define PRINTK(flag, args...) if (flag & DEBUG_FLAGS) printf (args) + +/* + Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer +*/ +#if defined (CONFIG_DRIVER_AX88180_16BIT) +#define READ_RXBUF(data) \ + do { \ + data = *(volatile unsigned short *) \ + (AX88180_BASE + RXBUFFER_START); \ + } while (0) + +#define WRITE_TXBUF(data) \ + do { \ + *(volatile unsigned short *)(AX88180_BASE + TXBUFFER_START) \ + = data; \ + } while (0) + +#define READ_MACREG(regaddr, regdata) \ + do { \ + regdata = *(volatile unsigned short *) \ + (AX88180_BASE + regaddr); \ + } while (0) + +#define WRITE_MACREG(regaddr, regdata) \ + do { \ + *(volatile unsigned short*)(AX88180_BASE + regaddr) \ + = regdata; \ + } while (0) +#else +#define READ_RXBUF(data) \ + do { \ + data = *(volatile unsigned long *) \ + (AX88180_BASE + RXBUFFER_START); \ + } while (0) + +#define WRITE_TXBUF(data) \ + do { \ + *(volatile unsigned long *)(AX88180_BASE + TXBUFFER_START) \ + = data; \ + } while (0) + +#define READ_MACREG(regaddr, regdata) \ + do { \ + regdata = *(volatile unsigned long*)(AX88180_BASE + regaddr); \ + } while (0) + +#define WRITE_MACREG(regaddr, regdata) \ + do { \ + *(volatile unsigned long*)(AX88180_BASE + regaddr) \ + = regdata; \ + } while (0) +#endif /* end of CONFIG_DRIVER_AX88180_16BIT */ + +#endif /*end of CONFIG_DRIVER_AX88180 */ -- 1.5.4.5

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[U-Boot] [PATCH 01/24] FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.
by Kumar Gala 19 Oct '08

19 Oct '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc86xx/ddr-8641.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index 932ef22..f936182 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -35,7 +35,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); out_be32(&ddr->cs0_config, regs->cs[i].config); } else if (i == 1) { -- 1.5.5.1

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