The port now uses the CFI-driver so board/RRvision/flash.c has been removed.
Signed-off-by: Gary Jennejohn <garyj(a)denx.de>
---
Makefile | 385 +++++++++++++++++++++++++++++++
board/RRvision/Makefile | 4 +-
board/RRvision/RRvision.c | 9 +-
board/RRvision/flash.c | 522 ------------------------------------------
common/lcd.c | 9 +-
cpu/mpc8xx/cpu_init.c | 2 +-
cpu/mpc8xx/fec.c | 8 +
cpu/mpc8xx/lcd.c | 185 ++++++++++++++-
cpu/mpc8xx/video.c | 22 ++-
include/configs/RRvision.h | 210 +++++++++++++----
include/configs/TTTech_env.h | 99 ++++++++
tools/Makefile | 20 ++
12 files changed, 891 insertions(+), 584 deletions(-)
delete mode 100644 board/RRvision/flash.c
create mode 100644 include/configs/TTTech_env.h
diff --git a/common/lcd.c b/common/lcd.c
index ebf377a..e54d4f5 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -70,6 +70,13 @@
# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
# error Default Color Map overlaps with Logo Color Map
# endif
+
+# ifndef CONFIG_LCD_LOGO_X
+# define CONFIG_LCD_LOGO_X 0
+# endif
+# ifndef CONFIG_LCD_LOGO_Y
+# define CONFIG_LCD_LOGO_Y 0
+# endif
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -768,7 +775,7 @@ static void *lcd_logo (void)
#endif /* CONFIG_SPLASH_SCREEN */
#ifdef CONFIG_LCD_LOGO
- bitmap_plot (0, 0);
+ bitmap_plot (CONFIG_LCD_LOGO_X, CONFIG_LCD_LOGO_Y);
#endif /* CONFIG_LCD_LOGO */
#ifdef CONFIG_MPC823
diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index fb3414a..400c2bc 100644
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -62,7 +62,7 @@ void cpu_init_f (volatile immap_t * immr)
#endif /* CONFIG_WATCHDOG */
/* SIUMCR - contains debug pin configuration (11-6) */
-#ifndef CONFIG_SVM_SC8xx
+#if !defined (CONFIG_SVM_SC8xx) && !defined (CONFIG_RRVISION)
immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
#else
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 37eb481..59da088 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -837,6 +837,8 @@ static void fec_halt(struct eth_device* dev)
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
+#define PHY_ID_DP83846A 0x20005c20 /* NatSem DP83846A */
+#define PHY_ID_DP83847 0x20005c30 /* NatSem DP83847 */
/* send command to phy using mii, wait for result */
static uint
@@ -924,6 +926,12 @@ static int mii_discover_phy(struct eth_device *dev)
case PHY_ID_KSM8995M:
printf("MICREL KS8995M\n");
break;
+ case PHY_ID_DP83846A:
+ printf("NatSem DP83846A\n");
+ break;
+ case PHY_ID_DP83847:
+ printf("NatSem DP83847\n");
+ break;
default:
printf("0x%08x\n", phytype);
break;
diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c
index 3c64a9b..13469a8 100644
--- a/cpu/mpc8xx/lcd.c
+++ b/cpu/mpc8xx/lcd.c
@@ -55,6 +55,10 @@
#undef CONFIG_LCD_INFO
#endif
+#if defined(CONFIG_RRVISION) && defined(TTTECH_NO_SCREEN_INFO)
+#undef CONFIG_LCD_INFO
+#endif
+
/*----------------------------------------------------------------------*/
#ifdef CONFIG_KYOCERA_KCS057QV1AJ
/*
@@ -114,7 +118,7 @@ vidinfo_t panel_info = {
*/
vidinfo_t panel_info = {
640, 480, 212, 158, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
- 3, 0, 0, 1, 1, 144, 2, 0, 33
+ 3, 0, 0, 1, 1, 88, 2, 0, 33
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_NEC_NL6448BC33_54 */
@@ -122,16 +126,115 @@ vidinfo_t panel_info = {
#ifdef CONFIG_SHARP_LQ104V7DS01
/*
- * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
+ * SHARP LQ104V7DS01. 10", 640x480. Active, color, single scan.
*/
vidinfo_t panel_info = {
- 640, 480, 132, 99, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_LOW,
- 3, 0, 0, 1, 1, 25, 1, 0, 33
+ 660, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 3, 0, 0, 1, 1, 99, 30, 0, 20
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ104V7DS01 */
/*----------------------------------------------------------------------*/
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_SHARP_LQ104V1DG61
+/*
+ * SHARP LQ104V1DG61. 10", 640x480. Active, color, single scan.
+ */
+vidinfo_t panel_info = {
+ 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 3, 0, 0, 1, 1, 80, 30, 0, 20
+
+};
+#endif /* CONFIG_SHARP_LQ104V1DG61 */
+/*----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_NEC_NL8060BC26
+#undef LCD_DF
+#define LCD_DF 4
+/*
+ * NEC_NL8060BC26. 10.4"", 800x600. Active, color, single scan.
+ */
+vidinfo_t panel_info = {
+ 800, /* Number of columns (i.e. 640) */
+ 600, /* Number of rows (i.e. 480) */
+ 211, /* Width of display area in millimeters */
+ 158, /* Height of display area in millimeters */
+ CFG_HIGH, /* Clock polarity */
+ CFG_HIGH, /* Output Enable polarity */
+ CFG_LOW, /* Horizontal Sync polarity */
+ CFG_LOW, /* Vertical Sync polarity */
+ CFG_HIGH, /* Data polarity */
+ 3, /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
+ 0, /* LCD Bus width, 0 = 4, 1 = 8 */
+ 0, /* Split display, 0 = single-scan, 1 = dual-scan */
+ 1, /* Color, 0 = mono, 1 = color */
+ 1, /* 0 = passive, 1 = TFT */
+ 80, /* Wait between lines */
+ 30, /* Vertical sync pulse width */
+ 0, /* LCD AC timing */
+ 20 /* Wait between frames */
+};
+#endif /* CONFIG_NEC_NL8060BC26 */
+/*----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_PM070WL3
+#undef LCD_DF
+#define LCD_DF 4
+/*
+ * PM070-WL3. 7"", 800x480. Active, color, single scan.
+ */
+vidinfo_t panel_info = {
+ 800, /* Number of columns (i.e. 640) */
+ 480, /* Number of rows (i.e. 480) */
+ 153, /* Width of display area in millimeters */
+ 92, /* Height of display area in millimeters */
+ CFG_HIGH, /* Clock polarity */
+ CFG_HIGH, /* Output Enable polarity */
+ CFG_LOW, /* Horizontal Sync polarity */
+ CFG_LOW, /* Vertical Sync polarity */
+ CFG_HIGH, /* Data polarity */
+ 3, /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
+ 0, /* LCD Bus width, 0 = 4, 1 = 8 */
+ 0, /* Split display, 0 = single-scan, 1 = dual-scan */
+ 1, /* Color, 0 = mono, 1 = color */
+ 1, /* 0 = passive, 1 = TFT */
+ 80, /* Wait between lines */
+ 30, /* Vertical sync pulse width */
+ 0, /* LCD AC timing */
+ 20 /* Wait between frames */
+};
+#endif /* CONFIG_PM070WL3 */
+/*----------------------------------------------------------------------*/
+
+
+#ifdef CONFIG_HLD1045AE1
+vidinfo_t panel_info = {
+ 640, 480, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 3, 0, 0, 1, 1, 80, 3, 0, 33
+ /* wbl, vpw, lcdac, wbf */
+};
+#endif /* CONFIG_HLD1045AE1 */
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_AUO_T070W1D1
+#undef LCD_DF
+#define LCD_DF 12
+
+vidinfo_t panel_info = {
+ 480, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_LOW, CFG_LOW, CFG_HIGH,
+ 3, 1, 0, 1, 1, 80, 4, 0, 16
+ /* wbl, vpw, lcdac, wbf */
+};
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_AUO_T070W1D1 */
+/*----------------------------------------------------------------------*/
+
#ifdef CONFIG_SHARP_16x9
/*
* Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
@@ -144,6 +247,44 @@ vidinfo_t panel_info = {
#endif /* CONFIG_SHARP_16x9 */
/*----------------------------------------------------------------------*/
+#ifdef CONFIG_SHARP_LQ050Q5DR01
+/*
+ * Sharp LQ050Q5DR01 display. Active, color, single scan.
+ */
+#undef LCD_DF
+#define LCD_DF 12
+
+vidinfo_t panel_info = {
+ 320, 241, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 3, 1, 0, 1, 1, 15, 4, 0, 3
+ /* wbl, vpw, lcdac, wbf */
+};
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_SHARP_LQ050Q5DR01 */
+/*----------------------------------------------------------------------*/
+
+#ifdef CONFIG_SHARP_LQ070Q5TR01
+/*
+ * Sharp LQ070Q5DR01 display. Active, color, single scan.
+ * !!! The actual screen size is only 480x240, but the HSYNC period has to
+ * be at least 680 pixels. The HSYNC period is given by 4 + vl_width + wbl.
+ * Changing wbl moves the picture on the screen. The only parameter to change
+ * is the screen width. Therefore we need a bitplane wider than the screen.
+ * The same holds for the VSYNC period. This is given byx VPW + WBF + vl_height.
+ * Changing VPW or WBF moves the picture up/down. Therefore we can only
+ * change vl_height. As a consequence the bitplane needs to be higher
+ * than the screen as well.
+ */
+
+vidinfo_t panel_info = {
+ 680, 246, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+ 3, 0, 0, 1, 1, 7, 4, 0, 3
+ /* wbl, vpw, lcdac, wbf */
+};
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_SHARP_LQ070Q5TR01 */
+/*----------------------------------------------------------------------*/
+
#ifdef CONFIG_SHARP_LQ057Q3DC02
/*
* Sharp LQ057Q3DC02 display. Active, color, single scan.
@@ -170,6 +311,22 @@ vidinfo_t panel_info = {
/* wbl, vpw, lcdac, wbf */
};
#endif /* CONFIG_SHARP_LQ64D341 */
+/*-----------------------------------------------------------------*/
+
+#ifdef CONFIG_UMSH_7189JD1F
+/*
+ * UMSH 7189JD1F FSTN Monochrome 320x240 4 Data bits doesn't work
+ */
+#undef LCD_DF
+#define LCD_DF 10
+
+vidinfo_t panel_info = {
+ 320, 240, 0, 0, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_LOW,
+ LCD_BPP, 0, 0, 0, 0, 33, 0, 1, 0
+};
+
+#undef LCD_TEST_PATTERN
+#endif
#ifdef CONFIG_SHARP_LQ065T9DR51U
/*
@@ -396,6 +553,23 @@ void lcd_ctrl_init (void *lcdbase)
immr->im_ioport.iop_pddat |= 0x0200;
#endif
+/*
+ * Workaround for RRVision with 10" LCD Display. see issue26199.
+ * This Workaround works with the Displays SHARP LQ104V7DS01 and SHARP
+ * LQ104V1DG61
+ */
+#if defined(CONFIG_RRVISION) && (defined(CONFIG_SHARP_LQ104V7DS01) || \
+ defined(CONFIG_SHARP_LQ104V1DG61))
+ /* PDPAR Bit 6 - DD6 => 0 */
+ immr->im_ioport.iop_pdpar &= ~0x0200;
+
+ /* PDDIR Bit 6 - DR6 => 1 */
+ immr->im_ioport.iop_pddir |= 0x0200;
+
+ /* PDDAT Bit 6 - D6 => 0 */
+ immr->im_ioport.iop_pddat &= ~0x0200;
+#endif /* CONFIG_SHARP_LQ104V7DS01 */
+
/* Load the physical address of the linear frame buffer
* into the LCD controller.
* BIG NOTE: This has to be modified to load A and B depending
@@ -483,7 +657,6 @@ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_MONOCHROME
-static
void lcd_initcolregs (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
@@ -564,12 +737,10 @@ void lcd_enable (void)
#endif
#ifdef CONFIG_RRVISION
debug ("PC4->Output(1): enable LVDS\n");
- debug ("PC5->Output(0): disable PAL clock\n");
immr->im_ioport.iop_pddir |= 0x1000;
immr->im_ioport.iop_pcpar &= ~(0x0C00);
immr->im_ioport.iop_pcdir |= 0x0C00 ;
immr->im_ioport.iop_pcdat |= 0x0800 ;
- immr->im_ioport.iop_pcdat &= ~(0x0400);
debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
immr->im_ioport.iop_pdpar,
immr->im_ioport.iop_pddir,
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index 8bf8e46..5bbd693 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -68,6 +68,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define VIDEO_INFO_X VIDEO_LOGO_WIDTH+8
#define VIDEO_INFO_Y 16
+#if defined(CONFIG_RRVISION) && defined(TTTECH_NO_SCREEN_INFO)
+#undef VIDEO_INFO
+#endif
+
/************************************************************************/
/* ** VIDEO ENCODER CONSTANTS */
/************************************************************************/
@@ -115,10 +119,15 @@ DECLARE_GLOBAL_DATA_PTR;
#define VIDEO_BURST_LEN (VIDEO_COLS/8)
#ifdef VIDEO_MODE_YUYV
+
+#if defined(CONFIG_RRVISION)
+#define VIDEO_BG_COL 0x80108010 /* Background color in YUYV format */
+#else
#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */
+#endif /* CONFIG_RRVISION */
#else
#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */
-#endif
+#endif /* VIDEO_MODE_YUYV */
/************************************************************************/
/* ** FONT AND LOGO DATA */
@@ -132,6 +141,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define VIDEO_LOGO_WIDTH DEF_U_BOOT_LOGO_WIDTH
#define VIDEO_LOGO_HEIGHT DEF_U_BOOT_LOGO_HEIGHT
#define VIDEO_LOGO_ADDR &u_boot_logo
+
+#ifndef CONFIG_VIDEO_LOGO_X
+#define CONFIG_VIDEO_LOGO_X 0
+#endif
+#ifndef CONFIG_VIDEO_LOGO_Y
+#define CONFIG_VIDEO_LOGO_Y 0
+#endif
+
#endif
/************************************************************************/
@@ -1171,7 +1188,8 @@ static void *video_logo (void)
char info[80];
#endif /* VIDEO_INFO */
- easylogo_plot (VIDEO_LOGO_ADDR, screen, width, 0, 0);
+ easylogo_plot (VIDEO_LOGO_ADDR, screen, width, CONFIG_VIDEO_LOGO_X,
+ CONFIG_VIDEO_LOGO_Y);
#ifdef VIDEO_INFO
sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index 6a71801..1ffd9f3 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -29,12 +29,19 @@
#define __CONFIG_H
/*
+ * Extra environment settings common for TTTech. Moved fron include
+ * to include/configs.
+ */
+#include <configs/TTTech_env.h>
+
+/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_RRVISION 1 /* ...on a RRvision board */
+#define CONFIG_C2CHIP 1 /* ... C2/C2NF Chip */
#define CONFIG_8xx_GCLK_FREQ 64000000
@@ -48,39 +55,93 @@
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#endif
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "setenv stdout serial"
+#define CONFIG_PREBOOT "run holdpower; run sensor_supply_on"
#undef CONFIG_BOOTARGS
-#define CONFIG_ETHADDR 00:50:C2:00:E0:70
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#define CONFIG_IPADDR 10.0.0.5
-#define CONFIG_SERVERIP 10.0.0.2
-#define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
- ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "load=tftp 100000 /tftpboot/u-boot.bin\0" \
- "update=protect off 1:0-8;era 1:0-8;" \
- "cp.b 100000 40000000 ${filesize};" \
- "setenv filesize;saveenv\0" \
- "kernel_addr=40040000\0" \
- "ramdisk_addr=40100000\0" \
- "kernel_img=/tftpboot/uImage\0" \
- "kernel_load=tftp 200000 ${kernel_img}\0" \
- "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
- "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addtty;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0"
+#define CONFIG_ETHADDR 00:50:C2:00:E0:70
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_IPADDR 10.120.30.2
+#define CONFIG_SERVERIP 10.120.20.27
+#define CONFIG_NETMASK 255.255.0.0
+#define CONFIG_GATEWAYIP 10.255.255.254
+#define CONFIG_NETDEV "eth0"
+#define CONFIG_STDIN "serial"
+#define CONFIG_STDOUT "serial"
+#define CONFIG_STDERR "serial"
+
+#define CONFIG_ROOTPATH /tftpboot/root/
+
+#ifdef CONFIG_LCD
+# define SENSOR_SUPPLY_ON \
+ "sensor_supply_on=mw.w fff00960 C02; mw.w fff00966 800\0"
+#else
+# define SENSOR_SUPPLY_ON \
+ "sensor_supply_on=mw.w fff00960 402; mw.w fff00966 0\0"
+#endif
+
+#ifdef CONFIG_TTTECH_BIGMEM
+# define MEM_ALLOC \
+ "flash_st_ub=40000000\0" \
+ "flash_en_ub=400FFFFF\0" \
+ "flash_st_lx=40100000\0" \
+ "flash_en_lx=401BFFFF\0" \
+ "flash_st_rd=401C0000\0" \
+ "flash_en_rd=407BFFFF\0" \
+ "flash_st_jf=407C0000\0" \
+ "flash_en_jf=43FFFFFF\0" \
+ "rd_size=6144\0"
+#else
+#ifdef CONFIG_CODESYS
+# define MEM_ALLOC \
+ "flash_st_ub=40000000\0" \
+ "flash_en_ub=4003FFFF\0" \
+ "flash_st_lx=40040000\0" \
+ "flash_en_lx=400FFFFF\0" \
+ "flash_st_rd=40100000\0" \
+ "flash_en_rd=402FFFFF\0" \
+ "flash_st_jf=40300000\0" \
+ "flash_en_jf=407FFFFF\0" \
+ "rd_size=4096\0"
+#else
+# define MEM_ALLOC \
+ "flash_st_ub=40000000\0" \
+ "flash_en_ub=4003FFFF\0" \
+ "flash_st_lx=40040000\0" \
+ "flash_en_lx=400FFFFF\0" \
+ "flash_st_rd=40100000\0" \
+ "flash_en_rd=403FFFFF\0" \
+ "flash_st_jf=40400000\0" \
+ "flash_en_jf=407FFFFF\0" \
+ "rd_size=6144\0"
+#endif
+#endif
+
+#ifdef CONFIG_PRODTEST
+# define CONFIG_BOOTCOMMAND "run prodtest"
+#else
+# define CONFIG_BOOTCOMMAND "saveenv; run updateall"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "img_lx=/tftpboot/kernel-rrv.bin\0" \
+ "img_lxpt=/tftpboot/uImage_prodtest\0" \
+ "img_rd=/tftpboot/rd-rrv.bin\0" \
+ "img_rdpt=/tftpboot/rdisk_prodtest.bin\0" \
+ "img_ub=/tftpboot/boot-rrv.bin\0" \
+ "img_ubpt=/tftpboot/uboot_prodtest.bin\0" \
+ "img_sc=/tftpboot/setenv_rrv.img\0" \
+ "img_jf=/tftpboot/jffs-rrv.bin\0" \
+ "bootcmd_prodtest=run flash_self\0" \
+ "holdpower=mw.w fff00950 40; mw.w fff00956 40\0" \
+ SENSOR_SUPPLY_ON \
+ "changeip=\0" \
+ "runscr=run ${loadscr};autoscr 100000\0" \
+ "hostname=ttcvision\0" \
+ CONFIG_BOOTCOMMAND \
+ CONFIG_TTTECH_ENV_SETTINGS \
+ MEM_ALLOC
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
@@ -90,6 +151,12 @@
#undef CONFIG_STATUS_LED /* disturbs display */
+/*
+ * Note that the ocan driver under Linux does its own mapping, so we
+ * don't need it here. Also note that enabling this needs some work
+ * because the default mapping below is wrong (CS3 is the TTP-Controller
+ * not the CAN)
+ */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/*
@@ -107,16 +174,25 @@
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
+#define TTTECH_NO_SCREEN_INFO /* was CFG_NO_SCREEN_INFO */
-#ifndef CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_LOGO_X ((panel_info.vl_col - BMP_LOGO_WIDTH) / 2)
+#define CONFIG_LCD_LOGO_Y ((panel_info.vl_row - BMP_LOGO_HEIGHT) / 2)
+#define CFG_WHITE_ON_BLACK
+#else
#define CONFIG_VIDEO 1 /* To enable the video initialization */
-
/* Video related */
#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
+#define CONFIG_VIDEO_LOGO_X ((VIDEO_COLS - VIDEO_LOGO_WIDTH) / 2)
+#define CONFIG_VIDEO_LOGO_Y ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / 2)
#endif
+#define CFG_CONSOLE_IS_IN_ENV
+
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C /* I2C bit-banged */
@@ -135,9 +211,9 @@
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+#define I2C_SDA(bit) if((bit)) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+#define I2C_SCL(bit) if((bit)) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
@@ -150,11 +226,15 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#undef CONFIG_CMD_REGINFO /* could be useful */
#undef CONFIG_CMD_PCMCIA
#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
/*
@@ -206,7 +286,11 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
+#ifdef CONFIG_TTTECH_BIGMEM /* set in Makefile */
+#define CFG_MONITOR_LEN (256 << 12) /* Reserve 1024 kB for Monitor */
+#else
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
@@ -220,16 +304,42 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
+#define CFG_FLASH_CFI /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+#ifdef CONFIG_TTTECH_BIGMEM
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#else
+#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+#endif
/* timeout values are in ticks = ms */
-#define CFG_FLASH_ERASE_TOUT (120*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */
+#ifdef CONFIG_TTTECH_BIGMEM
+#define CFG_FLASH_ERASE_TOUT (120 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (10 * CFG_HZ) /* Timeout for Flash Write */
+#else
+#define CFG_FLASH_ERASE_TOUT (120 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (1 * CFG_HZ) /* Timeout for Flash Write */
+#endif
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#ifdef CONFIG_TTTECH_BIGMEM
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
+#else
+/* this is actually in the first sector of the flash */
+#define CFG_ENV_OFFSET 0x8100 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#endif
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
@@ -251,7 +361,7 @@
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
-#if defined(CONFIG_WATCHDOG)
+#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
@@ -264,9 +374,9 @@
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
@@ -306,7 +416,7 @@
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
-#define CFG_SCCR (/* SCCR_TBS | */ SCCR_RTSEL | SCCR_RTDIV | \
+#define CFG_SCCR (/* SCCR_TBS | SCCR_RTSEL | SCCR_RTDIV | */ \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
@@ -400,6 +510,10 @@
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+/*
+ * Note that the CAN chip uses CS7 (not 3) so before enabling this,
+ * correct the setting.
+ */
#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
@@ -411,6 +525,14 @@
BR_PS_8 | BR_MS_UPMB | BR_V )
#endif /* CONFIG_CAN_DRIVER */
+#ifdef CONFIG_C2CHIP
+#define CFG_C2_BASE 0x20000000 /* C2 mapped at 0x00FFE000 - last 32KB of SDRAM*/
+#define CFG_C2_OR_AM 0xFFF00000 /* 1MB address mask */
+#define CFG_OR3_C2 (OR_AM_MSK | OR_CSNT_SAM | OR_ACS_DIV2 | \
+ OR_SCY_15_CLK | OR_EHTR | OR_BI | OR_TRLX)
+#define CFG_BR3_C2 ((CFG_C2_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#endif /* CONFIG_C2CHIP */
+
/*
* Memory Periodic Timer Prescaler
*
diff --git a/include/configs/TTTech_env.h b/include/configs/TTTech_env.h
new file mode 100644
index 0000000..8cdeafd
--- /dev/null
+++ b/include/configs/TTTech_env.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2008
+ * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TTTECH_ENV_H
+#define __TTTECH_ENV_H
+
+/*
+ * Extra environment settings shared by various TTTech configs
+ */
+
+#define CONFIG_TTTECH_ENV_SETTINGS \
+ "netdev=" CONFIG_NETDEV "\0" \
+ "stderr=" CONFIG_STDERR "\0" \
+ "stdin=" CONFIG_STDIN "\0" \
+ "stdout=" CONFIG_STDOUT "\0" \
+ "bootcmd_appl=run flash_self\0" \
+ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
+ ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
+ "addnostartapp=setenv bootargs ${bootargs} nostartapp=yes\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+ "addpanic=setenv bootargs ${bootargs} panic=1\0" \
+ "nfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs ${bootargs} root=/dev/ram rw " \
+ "ramdisk_size=${rd_size}\0" \
+ "cleansave=setenv img; setenv filesize; " \
+ "setenv flash_st; setenv flash_en; sleep 1; saveenv\0" \
+ "load=tftp 100000 ${img}\0" \
+ "flash=protect off all;era ${flash_st} ${flash_en};" \
+ "cp.b 100000 ${flash_st} ${filesize}\0" \
+ "update=run load flash\0" \
+ "loadlx=setenv img ${img_lx}; run load\0" \
+ "updatelx=setenv img ${img_lx}; " \
+ "setenv flash_st ${flash_st_lx}; " \
+ "setenv flash_en ${flash_en_lx}; run update\0" \
+ "updatelxpt=setenv img ${img_lxpt}; " \
+ "setenv flash_st ${flash_st_lx}; " \
+ "setenv flash_en ${flash_en_lx}; run update\0" \
+ "updaterd=setenv img ${img_rd}; " \
+ "setenv flash_st ${flash_st_rd}; " \
+ "setenv flash_en ${flash_en_rd}; run update; " \
+ "setenv boot_cmd ${bootcmd_appl} \0" \
+ "updateub=setenv img ${img_ub}; " \
+ "setenv flash_st ${flash_st_ub}; " \
+ "setenv flash_en ${flash_en_ub};" \
+ "run update;" \
+ "protect off all;" \
+ "era 40008000 4000FFFF;reset; \0" \
+ "updateubpt=setenv img ${img_ubpt}; " \
+ "setenv flash_st ${flash_st_ub}; " \
+ "setenv flash_en ${flash_en_ub};" \
+ "run update;\0" \
+ "updaterdpt=setenv img ${img_rdpt}; " \
+ "setenv flash_st ${flash_st_rd}; " \
+ "setenv flash_en ${flash_en_rd}; run update\0" \
+ "updatepb=run updateub\0" \
+ "updatejf=setenv img ${img_jf}; " \
+ "setenv flash_st ${flash_st_jf}; " \
+ "setenv flash_en ${flash_en_jf}; run update\0" \
+ "net_nfs=run loadlx nfsargs addip addtty;bootm\0" \
+ "flash_nfs=run nfsargs addip addtty;bootm ${flash_st_lx}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${flash_st_lx} ${flash_st_rd}\0" \
+ "prodtest=run updatelxpt;run updaterdpt;" \
+ "setenv bootcmd ${bootcmd_prodtest};" \
+ "run cleansave;" \
+ "reset\0" \
+ "application=run updateub; run updatelx; run updaterd;" \
+ "setenv bootcmd ${bootcmd_appl};" \
+ "run cleansave;" \
+ "reset\0" \
+ "updateall=run updatelx;" \
+ "run updatejf; run updaterd;" \
+ "setenv bootcmd=" \
+ "run cleansave;" \
+ "reset\0" \
+ "test=run addnostartapp flash_self\0"
+
+#endif /* __TTTECH_ENV_H */
diff --git a/tools/Makefile b/tools/Makefile
index 8533a8e..f68acba 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -41,6 +41,26 @@ LIBFDT_OBJ_FILES = $(obj)fdt.o $(obj)fdt_ro.o $(obj)fdt_rw.o $(obj)fdt_strerror.
LOGO_H = $(OBJTREE)/include/bmp_logo.h
+ifeq ($(LOGO),palfin)
+LOGO_BMP= logos/linux_logo_ttcontrol_palfin.bmp
+else
+ifeq ($(LOGO),ttcontrol)
+LOGO_BMP= logos/linux_logo_ttcontrol.bmp
+else
+ifeq ($(LOGO),patria)
+LOGO_BMP= logos/linux_logo_ttcontrol_patria.bmp
+else
+ifeq ($(LOGO),eaton)
+LOGO_BMP= logos/linux_logo_ttcontrol_eaton.bmp
+else
+ifeq ($(LOGO),void)
+LOGO_BMP= logos/linux_logo_void.bmp
+endif
+endif
+endif
+endif
+endif
+
ifeq ($(LOGO_BMP),)
LOGO_BMP= logos/denx.bmp
endif
--
1.5.4.3
---
Gary Jennejohn
*********************************************************************
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de
*********************************************************************
