June 2008 - U-Boot

[U-Boot-Users] [PATCH v2] PPC: add accessor macros to clear and set bits in one shot
by Wolfgang Grandegger 04 Jun '08

04 Jun '08

PPC: add accessor macros to clear and set bits in one shot This patch adds macros from linux/include/asm-powerpc/io.h to clear and set bits in one shot using the in_be32, out_be32, etc. accessor functions. They are very handy to manipulate bits it I/O registers. This patch is required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- include/asm-ppc/io.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) Index: u-boot/include/asm-ppc/io.h =================================================================== --- u-boot.orig/include/asm-ppc/io.h +++ u-boot/include/asm-ppc/io.h @@ -238,6 +238,42 @@ extern inline void out_be32(volatile uns __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching

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[U-Boot-Users] [PATCH] PPC: add accessor macros to clear and set bits in one shot
by Wolfgang Grandegger 04 Jun '08

04 Jun '08

PPC: add accessor macros to clear and set bits in one shot This patch adds macros from linux/include/asm-powerpc/io.h to clear and set bits in one shot using the in_be32, out_be32, etc. accessor functions. They are very handy to manipulate bits it I/O registers. This patch is required for my forthcoming FSL NAND UPM driver re-write and the support for the TQM8548 module. Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- include/asm-ppc/io.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) Index: u-boot/include/asm-ppc/io.h =================================================================== --- u-boot.orig/include/asm-ppc/io.h +++ u-boot/include/asm-ppc/io.h @@ -238,6 +238,34 @@ extern inline void out_be32(volatile uns __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } +/* access ports */ +#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) +#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) + +#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) +#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) + +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching

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[U-Boot-Users] [PATCH 1/2] Add support for mpc8313 based BUBBATWO
by Tor Krill 04 Jun '08

04 Jun '08

These patches add support for the mpc8313 based BUBBATWO board. Signed-off-by: Tor Krill <tor(a)excito.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + include/configs/BUBBATWO.h | 516 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 524 insertions(+), 0 deletions(-) create mode 100644 include/configs/BUBBATWO.h diff --git a/MAINTAINERS b/MAINTAINERS index ac7572c..c188728 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -224,6 +224,10 @@ Sangmoon Kim <dogoil(a)etinsys.com> debris MPC8245 KVME080 MPC8245 +Tor Krill <tor(a)excito.com> + + BUBBATWO MPC8313 + Thomas Lange <thomas(a)corelatus.se> GTH MPC860 diff --git a/MAKEALL b/MAKEALL index 0674069..da28c7a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -332,6 +332,7 @@ LIST_83xx=" \ MPC837XERDB \ sbc8349 \ TQM834x \ + BUBBATWO \ " diff --git a/Makefile b/Makefile index 3401203..93f563f 100644 --- a/Makefile +++ b/Makefile @@ -1993,6 +1993,9 @@ MPC8313ERDB_66_config: unconfig fi ; @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale +BUBBATWO_config: unconfig + @$(MKCONFIG) BUBBATWO ppc mpc83xx bubbatwo excito + MPC8315ERDB_config: unconfig @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale diff --git a/include/configs/BUBBATWO.h b/include/configs/BUBBATWO.h new file mode 100644 index 0000000..4e27c6f --- /dev/null +++ b/include/configs/BUBBATWO.h @@ -0,0 +1,516 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. + * Copyright (C) Excito Elektronik i Skåne, 2008. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Excito Bubba|TWO board configuration file + * Based on the devikit config MPC8313ERDB.h + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 +#define CONFIG_EXCB2 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#define CFG_MEMTEST_START 0x00001000 +#define CFG_MEMTEST_END 0x0fe00000 + +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +/* + * DDR configs for different memsizes. + * Memory size is read out from boardversion. + */ +#define CFG_DDR_CONFIG_256 ( CSCONFIG_EN \ + | CSCONFIG_BANK_BIT_3 | 0x00010000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80014102 */ +#define CFG_DDR_CONFIG_128 ( CSCONFIG_EN \ + | 0x00010000 /* TODO */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80010102 */ + +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ + | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ + | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ + | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ + | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) + /* 0x00220802 */ +#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ + | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ + | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ + | (10 << TIMING_CFG1_REFREC_SHIFT ) \ + | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ + | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ + | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) + /* 0x3835a322 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ + | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ + | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ + | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ + | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x05100500 */ +#if defined(CONFIG_DDR_2T_TIMING) +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_2T_EN \ + | SDRAM_CFG_DBW_32 ) +#else +#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE ) + /* 0x43080000 */ +#endif +#define CFG_SDRAM_CFG2 0x00401000; +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44480632 */ +#define CFG_DDR_MODE_2 0x8000C000; + +#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ +#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_LEGACY /* Use legacy mode not cfi-compliant */ +#define CFG_FLASH_LEGACY_512Kx16 /* Spansion 16bit 512KB on 16bit bus */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 1 /* flash size in MB */ +#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* Not supported by cfi legacy */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + /* 0xFF006FF7 TODO SLOW 16 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 11 /* sectors per device */ + +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ + +/* local bus read write buffer mapping */ +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ +#define CFG_LBLAWBAR3_PRELIM 0xFA000000 +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CONFIG_NET_MULTI +#define CFG_VSC8601_SKEWFIX + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#define CONFIG_PCI_SKIP_HOST_BRIDGE + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 + +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0x01 +#define TSEC2_PHY_ADDR 0x00 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_ISL1208 +#define CFG_I2C_RTC_ADDR 0x6f + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_SCSI +#define CONFIG_CMD_CACHE + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 + +/* For disk access */ +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_SATA_SIL3114 +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#define CONFIG_CMD_SATA +#define CFG_SATA_MAX_DEVICE 4 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x4000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +/* 66MHz IN, 133MHz CSB, 266 DDR, 333 CORE */ +/* 0x62050000 */ +#define CFG_HRCW_LOW (\ + 0x20000000 /* reserved, must be set */ |\ + HRCWL_DDRCM |\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2_5X1) + +/* 0xa0606c00 */ +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_RGMII |\ + HRCWH_TSEC2M_IN_RGMII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +/* System IO Config */ +#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +#define CFG_SICRL (SICRL_SPI_A | SICRL_SPI_B | SICRL_SPI_C | SICRL_SPI_D) /* SPI is IO */ + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ETHADDR 00:22:02:00:95:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETH1ADDR 00:22:02:00:95:02 + +#define CONFIG_IPADDR 192.168.0.49 +#define CONFIG_SERVERIP 192.168.0.200 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.0.0.0 +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME bubbatwo +#define CONFIG_ROOTPATH /nfs/root/path +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE bubba.dtb + +#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_BAUDRATE 115200 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "bootfile" MK_STR(CONFIG_BOOTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "diskdev=/dev/sda1\0" \ + "bootdev=sata 0:2\0" \ + "linux=setenv bootargs root=$diskdev; "\ + "ext2load $bootdev 0x400000 /boot/$bootfile; " \ + "ext2load $bootdev 0x600000 /boot/$fdtfile; "\ + "bootm 0x400000 - 0x600000\0"\ + "bootcmd=run linux\0" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ -- 1.5.5.3

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[U-Boot-Users] [PATCH] NAND FSL UPM: driver re-write using the hwcontrol callback
by Wolfgang Grandegger 04 Jun '08

04 Jun '08

NAND FSL UPM: driver re-write using the hwcontrol callback This is a re-write of the NAND FSL UPM driver using the more universal hwcontrol callback (instead of the cmdfunc callback). Here is a brief list of furher modifications: - For the time being, the UPM setup writing the UPM array has been removed from the driver and must now be done by the board specific code. - The bus width definition in "struct fsl_upm_nand" is now in bits to comply with the corresponding Linux driver. - chip->dev_read is only set if fun->dev_ready != NULL, which is required for boards not connecting the R/B pin. - A few issue have been fixed with MxMR bit manipulation like in the corresponding Linux driver. Note: I think the "io_addr" field of "struct fsl_upm" could be removed as well, because the address is already determined by "nand->IO_ADDR_[RW]", but I'm not 100% sure. This patch has been tested on a TQM8548 modules with the NAND chip Micron MT29F8G08FABWP. This patch is based on the following patches posted to this list a few minutes ago: [PATCH] PPC: add accessor macros to clear and set bits in one shot [PATCH] 83xx/85xx/86xx: add more MxMR local bus definitions Anton, could you please verify if it works on your MPC8360ERDK board as well. A patch will follow. In principle, the NAND driver of the TQM8272 should work with it as well. Signed-off-by: Wolfgang Grandegger <wg(a)grandegger.com> --- drivers/mtd/nand/fsl_upm.c | 133 +++++++++++++++++--------------------------- include/linux/mtd/fsl_upm.h | 1 2 files changed, 52 insertions(+), 82 deletions(-) Index: u-boot/drivers/mtd/nand/fsl_upm.c =================================================================== --- u-boot.orig/drivers/mtd/nand/fsl_upm.c +++ u-boot/drivers/mtd/nand/fsl_upm.c @@ -20,112 +20,89 @@ #include <linux/mtd/fsl_upm.h> #include <nand.h> -#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */ -#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */ -#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */ -#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */ +static int fsl_upm_in_pattern; static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); + clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); } static void fsl_upm_end_pattern(struct fsl_upm *upm) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) + clrbits32(upm->mxmr, MxMR_OP_RUNP); + + while (in_be32(upm->mxmr) & MxMR_OP_RUNP) eieio(); } static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) { - out_be32(upm->mar, cmd << (32 - width * 8)); - out_8(upm->io_addr, 0x0); -} - -static void fsl_upm_setup(struct fsl_upm *upm) -{ - int i; - - /* write upm array */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA); - - for (i = 0; i < 64; i++) { - out_be32(upm->mdr, upm->array[i]); + out_be32(upm->mar, cmd << (32 - width)); + switch (width) { + case 8: out_8(upm->io_addr, 0x0); + break; + case 16: + out_be16(upm->io_addr, 0x0); + break; + case 32: + out_be32(upm->io_addr, 0x0); + break; } - - /* normal operation */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) - eieio(); } -static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, - int page_addr) +static void nand_hwcontrol (struct mtd_info *mtd, int cmd) { struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv; - fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->oobblock) { - /* OOB area */ - column -= mtd->oobblock; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - fsl_upm_run_pattern(&fun->upm, fun->width, readcmd); + switch (cmd) { + case NAND_CTL_SETCLE: + fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_SETALE: + fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_CLRCLE: + case NAND_CTL_CLRALE: + fsl_upm_end_pattern(&fun->upm); + fsl_upm_in_pattern--; + break; } +#if 1 + /* Temorary check */ + if (fsl_upm_in_pattern < 0 || fsl_upm_in_pattern > 1) + printf("fsl_upm: Oops, unexpected fsl_upm_in_pattern %d\n", + fsl_upm_in_pattern); +#endif +} - fsl_upm_run_pattern(&fun->upm, fun->width, command); - - fsl_upm_end_pattern(&fun->upm); - - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - - if (column != -1) - fsl_upm_run_pattern(&fun->upm, fun->width, column); +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *chip = mtd->priv; - if (page_addr != -1) { - fsl_upm_run_pattern(&fun->upm, fun->width, page_addr); - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 8) & 0xFF); - if (chip->chipsize > (32 << 20)) { - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 16) & 0x0f); - } - } + if (fsl_upm_in_pattern) { + struct fsl_upm_nand *fun = chip->priv; - fsl_upm_end_pattern(&fun->upm); + fsl_upm_run_pattern(&fun->upm, fun->width, byte); - if (fun->wait_pattern) { /* * Some boards/chips needs this. At least on MPC8360E-RDK we * need it. Probably weird chip, because I don't see any need * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are * 0-2 unexpected busy states per block read. */ - while (!fun->dev_ready()) - debug("unexpected busy state\n"); + if (fun->wait_pattern) { + while (!fun->dev_ready()) + debug("unexpected busy state\n"); + } + } else { + out_8(chip->IO_ADDR_W, byte); } } -static void nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - struct nand_chip *chip = mtd->priv; - - out_8(chip->IO_ADDR_W, byte); -} - static u8 nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -164,10 +141,6 @@ static int nand_verify_buf(struct mtd_in return 0; } -static void nand_hwcontrol(struct mtd_info *mtd, int cmd) -{ -} - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -179,22 +152,20 @@ static int nand_dev_ready(struct mtd_inf int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) { /* yet only 8 bit accessors implemented */ - if (fun->width != 1) + if (fun->width != 8 && fun->width != 16 && fun->width != 32) return -ENOSYS; - fsl_upm_setup(&fun->upm); - chip->priv = fun; chip->chip_delay = fun->chip_delay; chip->eccmode = NAND_ECC_SOFT; - chip->cmdfunc = fun_cmdfunc; chip->hwcontrol = nand_hwcontrol; chip->read_byte = nand_read_byte; chip->read_buf = nand_read_buf; chip->write_byte = nand_write_byte; chip->write_buf = nand_write_buf; chip->verify_buf = nand_verify_buf; - chip->dev_ready = nand_dev_ready; + if (fun->dev_ready) + chip->dev_ready = nand_dev_ready; return 0; } Index: u-boot/include/linux/mtd/fsl_upm.h =================================================================== --- u-boot.orig/include/linux/mtd/fsl_upm.h +++ u-boot/include/linux/mtd/fsl_upm.h @@ -16,7 +16,6 @@ #include <linux/mtd/nand.h> struct fsl_upm { - const u32 *array; void __iomem *mdr; void __iomem *mxmr; void __iomem *mar;

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[U-Boot-Users] Ethernet POST freeze on 440EPx boards (PMC440, sequoia)
by Matthias Fuchs 04 Jun '08

04 Jun '08

Hi, I noticed some strange issues with our PMC440 (PPC440PEx based) board and also with the sequoia eval platform. In a certain configuration these boards stuck during the Ethernet POST tests. When they got stuck, it is even not possible to attach with a BDI2000. On the console you only see this: U-Boot 1.3.1 (May 30 2008 - 17:01:42) CPU: AMCC PowerPC 440EPx Rev. A at 533.333 MHz (PLB=133, OPB=66, EBC=66 MHz) Security/Kasumi support Bootstrap Option H - Boot ROM Location I2C (Addr 0x52) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Sequoia - AMCC PPC440EPx Evaluation Board, Rev. F, PCI=33 MHz I2C: ready DTT: 1 is 38 C DRAM: 256 MB FLASH: 64 MB NAND: 32 MiB PCI: Bus Dev VenId DevId Class Int 00 0c 168c 0013 0200 43 In: serial Out: serial Err: serial USB: Host(int phy) Device(ext phy) Net: ppc_4xx_eth0, ppc_4xx_eth1 I first noticed this behavior on our PMC440 boards. These boards are similiar to the Sequoia platform (256MB DDR2 RAM, 2x Gigabit Ethernet, ...). Playing with some printfs I found out that the board got stuck in the Ethernet POST. When I disable U-Boot's LOG_BUFFER feature the problem dissapears. First I never noticed this bahavior on the sequoia platform and I thought about a PMC440 specific issue. Then I compiled U-Boot 1.3.1 for the sequoia platform (1.3.1 is used on PMC440 until now). Last week I got the same issue on the sequoia platform. Not that often as on the PMC440, but the same issue. Because it is easy to reproduce on PMC440 boards, I played a little bit with different configurations: 1) With LOG_BUFFER enabled: often, about every 2nd boot 2) Without LOG_BUFFER (POST messages come out in the console) -> issue never seens 3) Modified 4xx Ether POST with RX Buffers in OCM -> issue never seens 4) DCACHE turned on -> issue never seens On the sequoia board I've only seens it after a reboot from Linux. But on PMC440 also after poweron. This must not have any meaning because I do more testing with our board than with the eval board :-) printf debugging showed up that the boards get stuck in post/cpu/ppc4xx/ether.c in test_ctlr()/ether_post_send(). Some packets are send, recevied and checked correctly. Then suddenly at a random packet size ether_post_send() freezes the board. Did anybody else see this behavior? Did we miss any EMAC errata? Matthias

2 1

[U-Boot-Users] [Patch 05/17] U-Boot-V2:ARM: Introduce capability to have different stack/malloc area
by Menon, Nishanth 04 Jun '08

04 Jun '08

The default setup of ARM memory allocation is as follows: ---- Stack Area ---- Heap Area --- _u_boot_start Rest of U-Boot.. This is an excellent strategy to catch stack overflow and memory buffer overflow issues. However, in conditions where: a) U-Boot is automatically loaded by h/w in the default location without a writable memory area above it, this will crash, b) Multiple non-contiguous memory areas available in system (e.g. SRAM and SDRAM), but the area where U-Boot is loaded is restricted in size and cannot fit the required heap and stack areas. In these cases, we need to have ability to move the Heap and stack to the area of our choice. This patch introduces CONFIG_MALLOC_START for machine configurations which require this. This would need to be enabled only if MACH_CAN_MODIFY_MALLOC_START is defined by the machine configurations that desire it. I have clubbed both heap and stack area to still catch some of those overflow issues. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- arch/arm/Kconfig | 22 ++++++++++++++++++++++ arch/arm/cpu/start-arm.S | 9 +++++++++ arch/arm/lib/arm.c | 5 +++++ 3 files changed, 36 insertions(+) Index: u-boot-v2.git/arch/arm/lib/arm.c =================================================================== --- u-boot-v2.git.orig/arch/arm/lib/arm.c 2008-05-20 17:19:42.000000000 -0500 +++ u-boot-v2.git/arch/arm/lib/arm.c 2008-05-20 17:26:33.000000000 -0500 @@ -6,8 +6,13 @@ int arm_mem_malloc_init(void) { +#ifndef CONFIG_MALLOC_START mem_malloc_init((void *)(_u_boot_start - CFG_MALLOC_LEN), (void *)_u_boot_start); +#else + mem_malloc_init((void *)(CONFIG_MALLOC_START - CFG_MALLOC_LEN), + (void *)CONFIG_MALLOC_START); +#endif return 0; } Index: u-boot-v2.git/arch/arm/Kconfig =================================================================== --- u-boot-v2.git.orig/arch/arm/Kconfig 2008-05-20 17:19:42.000000000 -0500 +++ u-boot-v2.git/arch/arm/Kconfig 2008-05-20 17:26:33.000000000 -0500 @@ -168,6 +168,28 @@ If you want to start a 2.6 kernel and use an initrd image say y here. +config MACH_CAN_MODIFY_MALLOC_START + bool + +config MALLOC_START_MODIFY + bool "Change Malloc Address location from default" + default n + depends on MACH_CAN_MODIFY_MALLOC_START + help + Say Y here if you meanto put malloc and stack elsewhere. + The default is to put Malloc and stack just above the + interrupt vectors(_start). It is usually desired to keep it here + as we can catch stack overflow and corruption issues easily. + USE THIS OPTION WITH CAUTION + +config MALLOC_START + hex + prompt "Provide Alternate Malloc Start address" + depends on MALLOC_START_MODIFY + help + Provide the alternate malloc start address. Remember that the area + that will be used will be (this address) to (this address - CFG_MALLOC_LEN - CONFIG_STACKSIZE) + endmenu source common/Kconfig Index: u-boot-v2.git/arch/arm/cpu/start-arm.S =================================================================== --- u-boot-v2.git.orig/arch/arm/cpu/start-arm.S 2008-05-20 17:26:30.000000000 -0500 +++ u-boot-v2.git/arch/arm/cpu/start-arm.S 2008-05-20 17:26:33.000000000 -0500 @@ -90,11 +90,20 @@ * FIXME *************************************************************************/ +#ifndef CONFIG_MALLOC_START _MALLOC_START: .word _start - CFG_MALLOC_LEN _STACK_START: .word _start - CFG_MALLOC_LEN - CONFIG_STACKSIZE +#else +_MALLOC_START: + .word CONFIG_MALLOC_START - CFG_MALLOC_LEN + +_STACK_START: + .word CONFIG_MALLOC_START - CFG_MALLOC_LEN - CONFIG_STACKSIZE +#endif + /* * These are defined in the board-specific linker script.

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[U-Boot-Users] [PATCH] Blackfin: bf533-ezkit: shuffle flash defines a little
by Mike Frysinger 04 Jun '08

04 Jun '08

Some of the flash defines weren't in the correct location and caused build problems in some configurations, so let's move types and defines to better local locations. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- board/bf533-ezkit/bf533-ezkit.c | 25 ++++--------------------- board/bf533-ezkit/flash-defines.h | 26 ++++---------------------- board/bf533-ezkit/flash.c | 24 ++++++------------------ 3 files changed, 14 insertions(+), 61 deletions(-) diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 738f69c..b039811 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -1,34 +1,17 @@ /* - * U-boot - ezkit533.c + * U-Boot - bf533-ezkit.c * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <common.h> -#if defined(CONFIG_MISC_INIT_R) #include "psd4256.h" -#endif +#include "flash-defines.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index 4e043e0..bb69fa8 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -1,28 +1,12 @@ /* - * U-boot - flash-defines.h + * U-Boot - flash-defines.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #ifndef __FLASHDEFINES_H__ @@ -50,6 +34,7 @@ #define FLASH_SIZE 0x220000 #define FLASH_MAN_ST 2 #define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 #define RESET_VAL 0xF0 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; @@ -68,9 +53,6 @@ int write_flash(long nOffset, int nValue); void get_sector_number(long lOffset, int *pnSector); int GetSectorProtectionStatus(flash_info_t * info, int nSector); int GetOffset(int nBlock); -int AFP_NumSectors = 40; -long AFP_SectorSize1 = 0x10000; -int AFP_SectorSize2 = 0x4000; #define WRITESEQ1 0x0AAA #define WRITESEQ2 0x0554 diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index cdf4dc6..ba75d99 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -1,34 +1,22 @@ /* * U-boot - flash.c Flash driver for PSD4256GV * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Licensed under the GPL-2 or later. */ #include <asm/io.h> #include "flash-defines.h" +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + void flash_reset(void) { reset_flash(); -- 1.5.5.3

3 9

[U-Boot-Users] [Patch 16/17] U-Boot-V2:ARM:OMAP3:SDP3430 Add support for SDP3430 board file
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch introduces support for SDP3430 board file. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- board/omap/board-sdp343x.c | 531 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 531 insertions(+) Index: u-boot-v2.git/board/omap/board-sdp343x.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/board-sdp343x.c 2008-05-20 17:26:44.000000000 -0500 @@ -0,0 +1,531 @@ +/** + * @file + * @brief SDP3430 Specific Board Initialization routines + * + * FileName: board/omap/board-sdp343x.c + * + * SDP3430 from Texas Instruments as described here: + * http://www.ti.com/omap3430_devplatform + * This file provides initialization in two stages: + * @li boot time initialization - do basics required to get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for SDP3430. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <console.h> +#include <init.h> +#include <driver.h> +#include <asm/io.h> +#include <ns16550.h> +#include <asm/arch/silicon.h> +#include <asm/arch/sdrc.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/syslib.h> +#include <asm/arch/control.h> +#include <asm/arch/omap3-mux.h> +#include "board-sdp343x.h" + +/******************** Board Boot Time *******************/ +static void sdrc_init(void); +static void mux_config(void); + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +void board_init(void) +{ + int in_sdram = running_in_sdram(); + mux_config(); + if (!in_sdram) + sdrc_init(); +} + +/** + * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0 + * + * @return void + */ +static void sdrc_init(void) +{ + /* issues software reset of SDRAM interface */ + /* No idle ack and RESET enable */ + __raw_writel(0x0A, SDRC_REG(SYSCONFIG)); + sdelay(100); + /* No idle ack and RESET disable */ + __raw_writel(0x08, SDRC_REG(SYSCONFIG)); + + /* SDRC Sharing register */ + /* 32-bit SDRAM on data lane [31:0] - CS0 */ + /* pin tri-stated = 1 */ + __raw_writel(0x00000100, SDRC_REG(SHARING)); + + /* ----- SDRC_REG(CS0 Configuration --------- */ + /* SDRC_REG(MCFG0 register */ + __raw_writel(0x02D04011, SDRC_REG(MCFG_0)); + + /* SDRC_REG(RFR_CTRL0 register */ + __raw_writel(0x0003DE01, SDRC_REG(RFR_CTRL_0)); + + /* SDRC_REG(ACTIM_CTRLA0 register */ + __raw_writel(0X5A9A4486, SDRC_REG(ACTIM_CTRLA_0)); + + /* SDRC_REG(ACTIM_CTRLB0 register */ + __raw_writel(0x00000010, SDRC_REG(ACTIM_CTRLB_0)); + + /* Disble Power Down of CKE cuz of 1 CKE on combo part */ + __raw_writel(0x00000081, SDRC_REG(POWER)); + + /* SDRC_REG(Manual command register */ + __raw_writel(0x00000000, SDRC_REG(MANUAL_0)); /* NOP command */ + __raw_writel(0x00000001, SDRC_REG(MANUAL_0)); /* Precharge command */ + __raw_writel(0x00000002, SDRC_REG(MANUAL_0)); /* Auto-refresh command */ + __raw_writel(0x00000002, SDRC_REG(MANUAL_0)); /* Auto-refresh command */ + + /* SDRC MR0 register */ + __raw_writel(0x00000032, SDRC_REG(MR_0)); /* Burst length =4 */ + + /* CAS latency = 3 */ + /* Write Burst = Read Burst */ + /* Serial Mode */ + + /* SDRC DLLA control register */ + /* Enable DLL, Load counter with 115 (middle of range) */ + /* Delay is 90 degrees */ + __raw_writel(0x0000730E, SDRC_REG(DLLA_CTRL)); + + /* + * Clear the enable DLL bit to use DLLA in unlock mode + * (counter value is continuously asserted) + */ + __raw_writel(0x0000730A, SDRC_REG(DLLA_CTRL)); + + /* SDRC DLLB control register + * Enable DLL, Load counter with 128 (middle of range) + * Delay is 90 degrees + */ + __raw_writel(0x0000730E, SDRC_REG(DLLB_CTRL)); + + /* + * Clear the enable DLL bit to use DLLB in unlock mode + * (counter value is continuously asserted) + */ + __raw_writel(0x0000730A, SDRC_REG(DLLB_CTRL)); + + return; +} + +/** + * @brief Do the pin muxing required for Board operation. + * + * See @ref MUX_VAL for description of the muxing mode. Since some versions + * of Linux depend on all pin muxing being done at U-Boot level, we may need to + * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing. + * + * @return void + */ +static void mux_config(void) +{ + /* Essential MUX Settings */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */ + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)); /* GPIO_55 - FLASH_DIS*/ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)); /* GPIO_56 - TORCH_EN*/ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4)); /* GPIO_57 - AGPS SLP */ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)); /* GPMC_58 - WLAN_IRQ */ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /* GPMC_NADV_ALE */ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); /* GPMC_NBE0_CLE */ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */ + + /* SERIAL INTERFACE */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); /* UART3_CTS_RCTX */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); /* UART3_RTS_SD */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /* UART3_RX_IRRX */ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /* UART3_TX_IRTX */ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /* HSUSB0_CLK */ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /* HSUSB0_STP */ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /* HSUSB0_DIR */ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /* HSUSB0_NXT */ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA0 */ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA1 */ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA2 */ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA3 */ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA4 */ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA5 */ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA6 */ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /* HSUSB0_DATA7 */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */ +#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */ + /* CAMERA */ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /* GPIO_98 - CAM_RESET */ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */ + /* AUDIO INTERFACE */ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); /* MCBSP2_CLKX*/ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */ + /* EXPANSION CARD */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */ + /* WIRELESS LAN */ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)); /* MMC2_DIR_DAT0 */ + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)); /* MMC2_DIR_DAT1 */ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)); /* MMC2_DIR_CMD */ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)); /* MMC2_CLKIN */ + /* BLUETOOTH */ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); /* MCBSP3_DX */ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); /* MCBSP3_DR */ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); /* MCBSP3_CLKX */ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); /* MCBSP3_FSX */ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */ + /* MODEM INTERFACE */ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)); /* SSI1_DAT_RX */ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); /* MCBSP1_CLKR */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)); /* GPIO_157 - BT_WKUP*/ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); /* MCBSP1_DX */ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); /* MCBSP_CLKS */ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); /* MCBSP1_FSX */ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); /* MCBSP1_CLKX */ + /* SERIAL INTERFACE */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); /* MCSPI1_CLK */ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); /* MCSPI1_SIMO*/ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); /* MCSPI1_SOMI*/ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); /* MCSPI1_CS0 */ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)); /* MCSPI1_CS1 */ + MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)); /* GPIO_176-NOR_DPD */ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); /* MCSPI1_CS3 */ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); /* MCSPI2_CLK */ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); /* MCSPI2_SIMO*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); /* MCSPI2_SOMI*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); /* MCSPI2_CS0 */ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); /* MCSPI2_CS1 */ + /* CONTROL AND DEBUG */ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)); /* GPIO_8-LCD_ENBKL*/ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /* SYS_OFF_MODE */ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /* SYS_CLKOUT1 */ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */ + MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); /* HSUSB1_TLL_STP */ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); /* HSUSB1_TLL_CLK */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1)); /* HSUSB1_TLL_DATA0 */ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1)); /* MCSPI3_CS0 */ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1)); /* HSUSB1_TLL_DATA2 */ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1)); /* HSUSB1_TLL_DATA7 */ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_DATA4 */ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_DATA5 */ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_DATA6 */ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_DATA3 */ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_DIR */ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); /* HSUSB1_TLL_NXT */ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_CLK */ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_STP */ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_DIR */ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_NXT */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_DATA0 */ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); /* HSUSB2_TLL_DATA1 */ + /* DIE TO DIE */ + MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); /* D2D_CLK26MI */ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); /* D2D_NRESPWRON */ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); /* D2D_NRESWARM */ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); /* D2D_ARM9NIRQ */ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); /* D2D_UMA2P6FIQ */ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); /* D2D_SPINT */ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); /* D2D_FRINT */ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); /* D2D_DMAREQ0 */ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); /* D2D_DMAREQ1 */ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); /* D2D_DMAREQ2 */ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); /* D2D_DMAREQ3 */ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); /* D2D_N3GTRST */ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); /* D2D_N3GTDI */ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); /* D2D_N3GTDO */ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); /* D2D_N3GTMS */ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); /* D2D_N3GTCK */ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); /* D2D_N3GRTCK */ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); /* D2D_MSTDBY */ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); /* D2D_SWAKEUP */ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); /* D2D_IDLEREQ */ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); /* D2D_IDLEACK */ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); /* D2D_MWRITE */ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); /* D2D_SWRITE */ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); /* D2D_MREAD */ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); /* D2D_SREAD */ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); /* D2D_MBUSFLAG */ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); /* D2D_SBUSFLAG */ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /* SDRC_CKE0 */ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /* SDRC_CKE1 NOT USED*/ +#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */ +} + +/******************** Board Run Time *******************/ + +static struct NS16550_plat serial_plat = { + .clock = 48000000, /* 48MHz (APLL96/2) */ + .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, +}; + +static struct device_d sdp3430_serial_device = { + .name = "serial_ns16550", + .id = "uart3", + .map_base = OMAP_UART3_BASE, + .size = 1024, + .platform_data = (void *)&serial_plat, + .type = DEVICE_TYPE_CONSOLE, +}; + +/** + * @brief UART serial port initialization - remember to enable COM clocks in arch + * + * @return result of device registration + */ +static int sdp3430_console_init(void) +{ + /* Register the serial port */ + return register_device(&sdp3430_serial_device); +} + +console_initcall(sdp3430_console_init); Index: u-boot-v2.git/board/omap/board-sdp343x.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/board-sdp343x.h 2008-05-20 17:26:43.000000000 -0500 @@ -0,0 +1,33 @@ +/** + * @file + * @brief exported APIs for board header. + * + * FileName: board/omap/board-sdp343x.h + * + * We may choose to add board specific defines here at a later point of time + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __BOARD_SDP343X_H_ +#define __BOARD_SDP343X_H_ + +void board_init(void); +#endif /* __BOARD_SDP343X_H_ */

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[U-Boot-Users] [Patch 15/17] U-Boot-V2:ARM:OMAP3:SDP3430: Add support for SDP3430 support files
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch introduces support for infrastructure required for SDP3430. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- arch/arm/configs/omap3430_sdp3430_per_uart_defconfig | 184 +++++++++++++++++++ arch/arm/mach-omap/Kconfig | 33 +++ board/omap/Kconfig | 48 ++++ board/omap/Makefile | 25 ++ board/omap/config.h | 38 +++ board/omap/env/bin/init | 1 board/omap/platform.S | 65 ++++++ 7 files changed, 392 insertions(+), 2 deletions(-) Index: u-boot-v2.git/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/arch/arm/configs/omap3430_sdp3430_per_uart_defconfig 2008-05-21 10:45:46.000000000 -0500 @@ -0,0 +1,184 @@ +# +# Automatically generated make config: don't edit +# U-Boot version: 2.0.0-rc5-git +# Wed May 21 10:45:02 2008 +# +CONFIG_ARCH_TEXT_BASE=0x40200000 +CONFIG_BOARDINFO="Texas Instrument's SDP343x" +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y +CONFIG_ARMCORTEXA8=y +CONFIG_ARCH_OMAP=y +# CONFIG_MACH_MX1ADS is not set +# CONFIG_MACH_SCB9328 is not set +# CONFIG_MACH_PCM038 is not set +# CONFIG_MACH_IMX27ADS is not set +# CONFIG_MACH_ECO920 is not set +# CONFIG_MACH_NXDB500 is not set +# CONFIG_MACH_PCM037 is not set +CONFIG_MACH_OMAP=y + +# +# OMAP Features +# +CONFIG_ARCH_OMAP3=y +CONFIG_OMAP_CONFIG_STACKSIZE=0x00002000 +CONFIG_OMAP_MALLOC_LEN=0x00002000 +CONFIG_OMAP_CLOCK_ALL=y +CONFIG_OMAP_CLOCK_SOURCE_S32K=y +CONFIG_OMAP3_CLOCK_CONFIG=y +# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set + +# +# OMAP Platform Features +# +CONFIG_MACH_OMAP343xSDP=y +# CONFIG_MACH_OMAP_ADVANCED_MUX is not set + +# +# Arm specific settings +# +# CONFIG_CMDLINE_TAG is not set +# CONFIG_SETUP_MEMORY_TAGS is not set +# CONFIG_INITRD_TAG is not set +CONFIG_MACH_CAN_MODIFY_MALLOC_START=y +CONFIG_MALLOC_START_MODIFY=y +CONFIG_MALLOC_START=0x87FFFC00 +# CONFIG_ARMCORTEXA8_DCACHE_SKIP is not set +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +# CONFIG_CMD_MEMORY is not set + +# +# General Settings +# +CONFIG_TEXT_BASE=0x40200000 +CONFIG_BROKEN=y +# CONFIG_EXPERIMENTAL is not set +# CONFIG_KALLSYMS is not set +CONFIG_MACH_HAS_LOWLEVEL_INIT=y +CONFIG_MACH_DO_LOWLEVEL_INIT=y +CONFIG_ARCH_HAS_LOWLEVEL_INIT=y +CONFIG_PROMPT="X-load 343x> " +CONFIG_BAUDRATE=115200 +# CONFIG_CMDLINE_EDITING is not set +CONFIG_SIMPLE_READLINE=y +# CONFIG_LONGHELP is not set +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +# CONFIG_SHELL_HUSH is not set +CONFIG_SHELL_SIMPLE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_ACTIVATE_FIRST=y +# CONFIG_OF_FLAT_TREE is not set +# CONFIG_PARTITION is not set +# CONFIG_DEFAULT_ENVIRONMENT is not set + +# +# Debugging +# +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set + +# +# Commands +# + +# +# scripting +# +# CONFIG_CMD_EDIT is not set +# CONFIG_CMD_EXEC is not set +# CONFIG_CMD_SLEEP is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_LOADENV is not set +# CONFIG_CMD_EXPORT is not set +# CONFIG_CMD_PRINTENV is not set +# CONFIG_CMD_HELP is not set +# CONFIG_CMD_READLINE is not set + +# +# file commands +# +# CONFIG_CMD_LS is not set +# CONFIG_CMD_RM is not set +# CONFIG_CMD_CAT is not set +# CONFIG_CMD_MKDIR is not set +# CONFIG_CMD_RMDIR is not set +# CONFIG_CMD_CP is not set +# CONFIG_CMD_PWD is not set +# CONFIG_CMD_CD is not set +# CONFIG_CMD_MOUNT is not set +# CONFIG_CMD_UMOUNT is not set + +# +# console +# +# CONFIG_CMD_CLEAR is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_SPLASH is not set + +# +# memory +# +CONFIG_LOAD_ADDR=0x80000000 +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADY is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_MEMINFO is not set +# CONFIG_CMD_CRC is not set +# CONFIG_CMD_MTEST is not set + +# +# flash +# +# CONFIG_CMD_FLASH is not set + +# +# booting +# +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_RESET is not set +CONFIG_CMD_GO=y +# CONFIG_CMD_TIMEOUT is not set +# CONFIG_CMD_PARTITION is not set +# CONFIG_NET is not set + +# +# Drivers +# + +# +# serial drivers +# +CONFIG_DRIVER_SERIAL_NS16550=y +# CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS is not set +# CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_16_BITS is not set +# CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_32_BITS is not set +CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_32=y +# CONFIG_DRIVER_SERIAL_NS16550_REG_SIZE_8_BITS_PAD_TO_64 is not set +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y + +# +# SPI drivers +# +# CONFIG_SPI is not set + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +# CONFIG_DRIVER_CFI_OLD is not set +# CONFIG_NAND is not set + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_CRC16=y Index: u-boot-v2.git/board/omap/Kconfig =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/Kconfig 2008-05-21 10:44:40.000000000 -0500 @@ -0,0 +1,48 @@ +# OMAP based Board Specific Configuration file +# +# (C) Copyright 2008 +# OMAP Architecture specific features +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan(a)ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +menu "OMAP Platform Features" + depends on MACH_OMAP + +config BOARDINFO + default "Texas Instrument's SDP343x" if MACH_OMAP343xSDP + +choice + prompt "Select OMAP platform" + +config MACH_OMAP343xSDP + bool "Texas Instrument's SDP343x" + select MACH_HAS_LOWLEVEL_INIT + select OMAP_CLOCK_ALL + help + Say Y here if you are using SDP343x platform +endchoice + +config MACH_OMAP_ADVANCED_MUX + bool "Enable advanced pin muxing" + depends on MACH_OMAP343xSDP + default n + help + Say Y here if you would like to have complete pin muxing to be + done at boot time + +endmenu Index: u-boot-v2.git/board/omap/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/Makefile 2008-05-21 10:44:40.000000000 -0500 @@ -0,0 +1,25 @@ +# OMAP Board Specific Makefile +# +# (C) Copyright 2008 +# OMAP Architecture specific features +# Texas Instruments, <www.ti.com> +# Nishanth Menon <x0nishan(a)ti.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += platform.o +obj-$(CONFIG_MACH_OMAP343xSDP) += board-sdp343x.o + Index: u-boot-v2.git/board/omap/config.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/config.h 2008-05-21 10:44:40.000000000 -0500 @@ -0,0 +1,38 @@ +/** + * @file + * @brief provide a wrapper for standard malloc and stack size defines + * + * FileName: board/omap/config.h + * + * Standard defines should be configurable for us to move Stack and malloc + * areas around this defines some basics for that + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MACH_OMAP_CONFIG_H +#define __MACH_OMAP_CONFIG_H + +/** define CFG_MALLOC_LEN from Kconfig define */ +#define CFG_MALLOC_LEN CONFIG_OMAP_MALLOC_LEN +/** define CONFIG_STACKSIZE from Kconfig define */ +#define CONFIG_STACKSIZE CONFIG_OMAP_CONFIG_STACKSIZE + +#endif /* __MACH_OMAP_CONFIG_H */ Index: u-boot-v2.git/board/omap/platform.S =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/platform.S 2008-05-21 10:44:40.000000000 -0500 @@ -0,0 +1,65 @@ +/** + * @file + * @brief Wrapper to call board level initialization routine + * + * FileName: board/omap/platform.S + * + * board_init_lowlevel is defined here. This calls board_init which + * is linked to the binary - the board_init only has a SRAM stack. + * so it needs to be careful about the usage of global variables + * and the likes. Enabled only if CONFIG_MACH_DO_LOWLEVEL_INIT is + * defined + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/silicon.h> + +#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT +/** + * @fn void board_init_lowlevel(void) + * + * @brief This provides a assembly wrapper setting up SRAM before calling + * board_init + * + * @return void + */ +.globl board_init_lowlevel +board_init_lowlevel: + /* Setup a temporary stack so that we can call C functions + * Yes. this might have been already done by arch code. + * No harm in being a bit redundant to avoid future complications + */ + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + str lr, [sp] /* stash current link register */ + mov ip, lr /* save link reg across call */ + /* Do the pin muxes, sdram init etc..board-xxx.c */ + bl board_init + ldr lr, [sp] /* restore current link register */ + ldr ip, [sp] /* restore save ip */ + /* back to arch calling code */ + mov pc, lr +SRAM_STACK: + .word OMAP_SRAM_STACK + +#endif /* CONFIG_MACH_DO_LOWLEVEL_INIT */ Index: u-boot-v2.git/arch/arm/mach-omap/Kconfig =================================================================== --- u-boot-v2.git.orig/arch/arm/mach-omap/Kconfig 2008-05-21 10:44:40.000000000 -0500 +++ u-boot-v2.git/arch/arm/mach-omap/Kconfig 2008-05-21 10:44:40.000000000 -0500 @@ -30,6 +30,7 @@ bool "OMAP3" select ARMCORTEXA8 select ARCH_HAS_LOWLEVEL_INIT + select OMAP_CLOCK_SOURCE_S32K help Say Y here if you are using Texas Instrument's OMAP343x based platform @@ -56,10 +57,38 @@ help Select the load address +### Generic Clock configurations to be enabled by Mach - invisible to enable. +config OMAP_CLOCK_UART + bool +config OMAP_CLOCK_UART2 + bool +config OMAP_CLOCK_UART3 + bool +config OMAP_CLOCK_I2C + bool + +# Blind enable all possible clocks.. think twice before you do this. +config OMAP_CLOCK_ALL + bool + +config OMAP_CLOCK_SOURCE_S32K + bool + config OMAP3_CLOCK_CONFIG - depends on ARCH_OMAP - bool "Clock Configuration" + prompt "Clock Configuration" + bool + depends on ARCH_OMAP3 + default y help Say Y here if you like to have OMAP3 Clock configuration done. +config OMAP3_COPY_CLOCK_SRAM + prompt "SRAM copy of Clock code" + bool + depends on OMAP3_CLOCK_CONFIG + default y + help + Say Y here if you like to have initial OMAP3 Clock configuration done from SRAM. + +source board/omap/Kconfig endmenu Index: u-boot-v2.git/board/omap/env/bin/init =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/board/omap/env/bin/init 2008-05-21 10:44:40.000000000 -0500 @@ -0,0 +1 @@ +# Dummy Init environment script

1 1

[U-Boot-Users] [Patch 13/17] U-Boot-V2:ARM:OMAP3: Add generic Headers
by Menon, Nishanth 04 Jun '08

04 Jun '08

This patch adds the generic OMAP headers and OMAP specific headers. Signed-off-by: Nishanth Menon<x0nishan(a)ti.com> --- include/asm-arm/arch-omap/bits.h | 65 ++++ include/asm-arm/arch-omap/control.h | 98 ++++++ include/asm-arm/arch-omap/gpmc.h | 105 +++++++ include/asm-arm/arch-omap/intc.h | 58 ++++ include/asm-arm/arch-omap/omap3-mux.h | 423 ++++++++++++++++++++++++++++++ include/asm-arm/arch-omap/omap3-silicon.h | 130 +++++++++ include/asm-arm/arch-omap/omap3-smx.h | 69 ++++ include/asm-arm/arch-omap/sdrc.h | 97 ++++++ include/asm-arm/arch-omap/silicon.h | 38 ++ include/asm-arm/arch-omap/sys_info.h | 97 ++++++ include/asm-arm/arch-omap/syslib.h | 39 ++ include/asm-arm/arch-omap/timers.h | 60 ++++ include/asm-arm/arch-omap/wdt.h | 49 +++ 13 files changed, 1328 insertions(+) Index: u-boot-v2.git/include/asm-arm/arch-omap/bits.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/bits.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,65 @@ +/** + * @file + * + * @brief Provide a bunch of common BIT access macros + * + * FileName: include/asm-arm/arch-omap/bits.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_OMAP_BITS_H +#define __ASM_OMAP_BITS_H + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif /*__ASM_OMAP_BITS_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/control.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/control.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,98 @@ +/** + * @file + * @brief This file contains the Control register defines + * + * FileName: include/asm-arm/arch-omap/control.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_CONTROL_H +#define __ASM_ARCH_OMAP_CONTROL_H + +/** + * Control register defintion which unwraps to the real register + * offset + base address + */ +#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME) + +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCRATCHPAD_BASE (0x910) +#define CONTROL_SCRATCHPAD_ROM_BASE (0x860) +#define CONTROL_STATUS (0x2f0) +#define CONTROL_SYSCONFIG (0x010) +#define CONTROL_DEVCONF0 (0x274) +#define CONTROL_DEVCONF1 (0x2D8) +#define CONTROL_IVA2_BOOTMOD (0x404) +#define CONTROL_IVA2_BOOTADDR (0x400) +#define CONTROL_PBIAS_1 (0x520) +#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4) +#define CONTROL_MEM_DFTRW0 (0x278) +#define CONTROL_MEM_DFTRW1 (0x27C) +#define CONTROL_MSUSPENDMUX_0 (0x290) +#define CONTROL_MSUSPENDMUX_1 (0x294) +#define CONTROL_MSUSPENDMUX_2 (0x298) +#define CONTROL_MSUSPENDMUX_3 (0x29C) +#define CONTROL_MSUSPENDMUX_4 (0x2A0) +#define CONTROL_MSUSPENDMUX_5 (0x2A4) +#define CONTROL_SEC_CTRL (0x2B0) +#define CONTROL_CSIRXFE (0x2DC) +#define CONTROL_DEBOBS_0 (0x420) +#define CONTROL_DEBOBS_1 (0x424) +#define CONTROL_DEBOBS_2 (0x428) +#define CONTROL_DEBOBS_3 (0x42C) +#define CONTROL_DEBOBS_4 (0x430) +#define CONTROL_DEBOBS_5 (0x434) +#define CONTROL_DEBOBS_6 (0x438) +#define CONTROL_DEBOBS_7 (0x43C) +#define CONTROL_DEBOBS_8 (0x440) +#define CONTROL_PROG_IO0 (0x444) +#define CONTROL_PROG_IO1 (0x448) +#define CONTROL_DSS_DPLL_SPREADING (0x450) +#define CONTROL_CORE_DPLL_SPREADING (0x454) +#define CONTROL_PER_DPLL_SPREADING (0x458) +#define CONTROL_USBHOST_DPLL_SPREADING (0x45C) +#define CONTROL_TEMP_SENSOR (0x524) +#define CONTROL_SRAMLDO4 (0x528) +#define CONTROL_SRAMLDO5 (0x52C) +#define CONTROL_CSI (0x530) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) + +/** Provide the Regoffset, Value */ +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP_CTRL_BASE + (OFFSET)) + +/** + * macro for Padconfig Registers @see + * include/asm/arch-arm/arch-omap/omap3-mux.h + */ +#define CP(X) (CONTROL_PADCONF_##X) + +#endif /* __ASM_ARCH_OMAP_CONTROL_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/gpmc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/gpmc.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,105 @@ +/** + * @file + * @brief This file contains the GPMC specific register definitions + * + * FileName: include/asm-arm/arch-omap/gpmc.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +/** GPMC Reg Wrapper */ +#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME) + +#define GPMC_SYS_CONFIG (0x10) +#define GPMC_IRQ_ENABLE (0x1C) +#define GPMC_TIMEOUT_CONTROL (0x40) +#define GPMC_CFG (0x50) +#define GPMC_PREFETCH_CONFIG_1 (0x1E0) +#define GPMC_PREFETCH_CONFIG_2 (0x1E4) +#define GPMC_PREFETCH_CTRL (0x1EC) +#define GPMC_CONFIG1_0 (0x60) +#define GPMC_CONFIG1_1 (0x90) +#define GPMC_CONFIG1_2 (0xC0) +#define GPMC_CONFIG1_3 (0xF0) +#define GPMC_CONFIG1_4 (0x120) +#define GPMC_CONFIG1_5 (0x150) +#define GPMC_CONFIG1_6 (0x180) +#define GPMC_CONFIG1_7 (0x1B0) +#define GPMC_CONFIG2_0 (0x64) +#define GPMC_CONFIG2_1 (0x94) +#define GPMC_CONFIG2_2 (0xC4) +#define GPMC_CONFIG2_3 (0xF4) +#define GPMC_CONFIG2_4 (0x124) +#define GPMC_CONFIG2_5 (0x154) +#define GPMC_CONFIG2_6 (0x184) +#define GPMC_CONFIG2_7 (0x1B4) +#define GPMC_CONFIG3_0 (0x68) +#define GPMC_CONFIG3_1 (0x98) +#define GPMC_CONFIG3_2 (0xC8) +#define GPMC_CONFIG3_3 (0xF8) +#define GPMC_CONFIG3_4 (0x128) +#define GPMC_CONFIG3_5 (0x158) +#define GPMC_CONFIG3_6 (0x188) +#define GPMC_CONFIG3_7 (0x1B8) +#define GPMC_CONFIG4_0 (0x6C) +#define GPMC_CONFIG4_1 (0x9C) +#define GPMC_CONFIG4_2 (0xCC) +#define GPMC_CONFIG4_3 (0xFC) +#define GPMC_CONFIG4_4 (0x12C) +#define GPMC_CONFIG4_5 (0x15C) +#define GPMC_CONFIG4_6 (0x18C) +#define GPMC_CONFIG4_7 (0x1BC) +#define GPMC_CONFIG5_0 (0x70) +#define GPMC_CONFIG5_1 (0xA0) +#define GPMC_CONFIG5_2 (0xD0) +#define GPMC_CONFIG5_3 (0x100) +#define GPMC_CONFIG5_4 (0x130) +#define GPMC_CONFIG5_5 (0x160) +#define GPMC_CONFIG5_6 (0x190) +#define GPMC_CONFIG5_7 (0x1C0) +#define GPMC_CONFIG6_0 (0x74) +#define GPMC_CONFIG6_1 (0xA4) +#define GPMC_CONFIG6_2 (0xD4) +#define GPMC_CONFIG6_3 (0x104) +#define GPMC_CONFIG6_4 (0x134) +#define GPMC_CONFIG6_5 (0x164) +#define GPMC_CONFIG6_6 (0x194) +#define GPMC_CONFIG6_7 (0x1C4) +#define GPMC_CONFIG7_0 (0x78) +#define GPMC_CONFIG7_1 (0xA8) +#define GPMC_CONFIG7_2 (0xD8) +#define GPMC_CONFIG7_3 (0x108) +#define GPMC_CONFIG7_4 (0x138) +#define GPMC_CONFIG7_5 (0x168) +#define GPMC_CONFIG7_6 (0x198) +#define GPMC_CONFIG7_7 (0x1C8) + +#endif /* __ASM_ARCH_OMAP_GPMC_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/intc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/intc.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,58 @@ +/** + * @file + * @brief This file contains the Interrupt controller register defines + * + * FileName: include/asm-arm/arch-omap/intc.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_INTC_H +#define __ASM_ARCH_OMAP_INTC_H + +/** Interrupt Controller Register wrapper */ +#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME) + +#define INTC_MIR_0 (0x084) +#define INTC_MIR_1 (0x0A4) +#define INTC_MIR_2 (0x0C4) +#define INTC_MIR_SET_0 (0x08C) +#define INTC_MIR_SET_1 (0x0AC) +#define INTC_MIR_SET_2 (0x0CC) +#define INTC_MIR_CLEAR_0 (0x094) +#define INTC_MIR_CLEAR_1 (0x0B4) +#define INTC_MIR_CLEAR_2 (0x0D4) +#define INTC_PS_SYSCONFIG (0x010) +#define INTC_PS_PROTECTION (0x04C) +#define INTC_PS_IDLE (0x050) +#define INTC_PS_THRESHOLD (0x068) +#define INTC_PS_PENDING_IRQ0 (0x098) +#define INTC_PS_PENDING_IRQ1 (0x0B8) +#define INTC_PS_PENDING_IRQ2 (0x0D8) + +#endif /* __ASM_ARCH_OMAP_INTC_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/omap3-silicon.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/omap3-silicon.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,130 @@ +/** + * @file + * @brief This file contains the processor specific definitions of + * the TI OMAP34XX. For more info on OMAP34XX, + * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf + * + * FileName: include/asm-arm/arch-omap/omap3-silicon.h + * + * OMAP34XX base address defines go here. + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap3-silicon.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H + +/* PLEASE PLACE ONLY BASE DEFINES HERE */ + +/** OMAP Internal Bus Base addresses */ +#define OMAP_L4_CORE_BASE 0x48000000 +#define OMAP_INTC_BASE 0x48200000 +#define OMAP_L4_WKUP_BASE 0x48300000 +#define OMAP_L4_PER_BASE 0x49000000 +#define OMAP_L4_EMU_BASE 0x54000000 +#define OMAP_SGX_BASE 0x50000000 +#define OMAP_IVA_BASE 0x5C000000 +#define OMAP_SMX_APE_BASE 0x68000000 +#define OMAP_SMS_BASE 0x6C000000 +#define OMAP_SDRC_BASE 0x6D000000 +#define OMAP_GPMC_BASE 0x6E000000 + +/** Peripheral Base Addresses */ +#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000) +#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000) +#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000) + +#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000) +#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000) +#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000) + +#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000) +#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000) +#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000) + +#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000) +#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000) +#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000) +#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000) +#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000) +#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000) +#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000) +#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000) +#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000) +#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000) +#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000) + +#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000) +#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000) + +#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000) + +#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000) +#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000) +#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000) + +#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000) + +#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000) +#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000) +#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000) +#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000) +#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000) +#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000) + +/** MPU WDT Definition */ +#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE + +/** Interrupt Vector base address */ +#define OMAP_SRAM_INTVECT 0x4020F800 +#define OMAP_SRAM_INTVECT_COPYSIZE 0x64 +/** Temporary stack for us to use C calls in low_level_init */ +#define OMAP_SRAM_STACK 0x4020FFFC + +/** Gives the silicon revision */ +#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000) +#define IDCODE_REG (OMAP_TAP_BASE + 0x204) + +/************ Generic Chip specific Definitions **********/ +/** + * CHIP F number HAWKEYE (hex) + * OMAP3430 ES1.0 F771609 B6D6 + * OMAP3430 ES2.0 F771609A B7AE + */ +#define HAWKEYE_ES1 0x0B6D6000 +#define HAWKEYE_ES2 0x0B7AE000 +#define HAWKEYE_ES2_1 0x1B7AE000 +#define HAWKEYE_MASK 0x0FFFF000 +#define VERSION_MASK 0xF0000000 +#define DEVICE_MASK (BIT8|BIT9|BIT10) + +#define OMAP_SDRC_CS0 0x80000000 +#define OMAP_SDRC_CS1 0xA0000000 + +#endif /* __ASM_ARCH_OMAP3_H */ + Index: u-boot-v2.git/include/asm-arm/arch-omap/omap3-smx.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/omap3-smx.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,69 @@ +/** + * @file + * @brief This file contains the SMX specific register definitions + * + * FileName: include/asm-arm/arch-omap/omap3-smx.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_SMX_H +#define __ASM_ARCH_OMAP_SMX_H + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +/* IVA2 */ +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +/* SMS */ +#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10) +#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48) +#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +#endif /* __ASM_ARCH_OMAP_SMX_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/sdrc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/sdrc.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file contains the SDRC specific register definitions + * + * FileName: include/asm-arm/arch-omap/sdrc.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_ARCH_SDRC_H +#define _ASM_ARCH_SDRC_H + +#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME) +#define OMAP_SDRC_SYSCONFIG (0x10) +#define OMAP_SDRC_STATUS (0x14) +#define OMAP_SDRC_CS_CFG (0x40) +#define OMAP_SDRC_SHARING (0x44) +#define OMAP_SDRC_DLLA_CTRL (0x60) +#define OMAP_SDRC_DLLA_STATUS (0x64) +#define OMAP_SDRC_DLLB_CTRL (0x68) +#define OMAP_SDRC_DLLB_STATUS (0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define OMAP_SDRC_POWER (0x70) +#define WAKEUPPROC BIT26 + +#define OMAP_SDRC_MCFG_0 (0x80) +#define OMAP_SDRC_MCFG_1 (0xB0) +#define OMAP_SDRC_MR_0 (0x84) +#define OMAP_SDRC_MR_1 (0xB4) +#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C) +#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0) +#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4) +#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8) +#define OMAP_SDRC_RFR_CTRL_0 (0xA4) +#define OMAP_SDRC_RFR_CTRL_1 (0xD4) +#define OMAP_SDRC_MANUAL_0 (0xA8) +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +#define SDRC_CS0_OSET 0x0 +/* Mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS1_OSET 0x30 + +#define SDRC_STACKED 0 +#define SDRC_IP_DDR 1 +#define SDRC_COMBO_DDR 2 +#define SDRC_IP_SDR 3 + + +#define SDRC_B_R_C (0 << 6) /* bank-row-column */ +#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */ +#define SDRC_R_B_C (2 << 6) /* row-bank-column */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +#endif /* _ASM_ARCH_SDRC_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/silicon.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/silicon.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SILICON_H +#define __ASM_ARCH_OMAP_SILICON_H + +#include <asm/arch/bits.h> + +/* Each platform silicon header comes here */ +#ifdef CONFIG_ARCH_OMAP3 +#include <asm/arch/omap3-silicon.h> +#endif + +/* If Architecture specific init functions are present */ +#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT +#ifndef __ASSEMBLY__ +void a_init(void); +#endif /* __ASSEMBLY__ */ +#endif + +#endif /* __ASM_ARCH_OMAP_SILICON_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/sys_info.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/sys_info.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file defines the macros apis which are useful for most OMAP + * platforms. + * + * FileName: include/asm-arm/arch-omap/sys_info.h + * + * These are implemented by the System specific code in omapX-generic.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SYS_INFO_H_ +#define __ASM_ARCH_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 +#define CPU_2430 0x2430 +#define CPU_2420 0x2420 +#define CPU_1710 0x1710 +#define CPU_1610 0x1610 + +/** + * CPU revision + */ +#define CPU_ES1 1 +#define CPU_ES1P1 2 +#define CPU_ES1P2 3 +#define CPU_ES2 4 +#define CPU_ES2P1 5 +#define CPU_ES2P2 6 +#define CPU_ES3 7 +#define CPU_ES3P1 8 +#define CPU_ES3P2 9 +#define CPU_ES4 10 +#define CPU_ES4P1 11 +#define CPU_ES4P2 12 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/** These are implemented by the System specific code in omapX-generic.c */ +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_sdr_cs_size(u32 offset); +inline u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 get_base(void); +u32 running_in_flash(void); +u32 running_in_sram(void); +u32 running_in_sdram(void); +u32 get_boot_type(void); +u32 get_device_type(void); + +#endif /*__ASM_ARCH_SYS_INFO_H_ */ Index: u-boot-v2.git/include/asm-arm/arch-omap/syslib.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/syslib.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,39 @@ +/** + * @file + * @brief These Apis are OMAP independent support functions + * + * FileName: include/asm-arm/arch-omap/syslib.h + * + * Implemented by arch/arm/mach-omap/syslib.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SYSLIB_H_ +#define __ASM_ARCH_OMAP_SYSLIB_H_ + +/** System Independent functions */ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */ Index: u-boot-v2.git/include/asm-arm/arch-omap/timers.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/timers.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,60 @@ +/** + * @file + * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers. + * + * FileName: include/asm-arm/arch-omap/timers.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_GPT_H +#define __ASM_ARCH_GPT_H + +/** General Purpose timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +/* Enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0<<2) | BIT1 | BIT0) + +/** Sync 32Khz Timer registers */ +#define S32K_CR (OMAP_32KTIMER_BASE + 0x10) +#define S32K_FREQUENCY 32768 + +#endif /*__ASM_ARCH_GPT_H */ Index: u-boot-v2.git/include/asm-arm/arch-omap/wdt.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ u-boot-v2.git/include/asm-arm/arch-omap/wdt.h 2008-05-20 18:11:10.000000000 -0500 @@ -0,0 +1,49 @@ +/** + * @file + * @brief This file contains the Watchdog timer specific register definitions + * + * FileName: include/asm-arm/arch-omap/wdt.h + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_WDT_H +#define __ASM_ARCH_OMAP_WDT_H + +/** Watchdog Register defines */ +#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME) +#define OMAP_WDT_WIDR (0x000) +#define OMAP_WDT_SYSCONFIG (0x010) +#define OMAP_WDT_WD_SYSSTATUS (0x014) +#define OMAP_WDT_WISR (0x018) +#define OMAP_WDT_WIER (0x01C) +#define OMAP_WDT_WCLR (0x024) +#define OMAP_WDT_WCRR (0x028) +#define OMAP_WDT_WLDR (0x02C) +#define OMAP_WDT_WTGR (0x030) +#define OMAP_WDT_WWPS (0x034) +#define OMAP_WDT_WSPR (0x048) + +/* Unlock Code for Watchdog timer to disable the same */ +#define WDT_DISABLE_CODE1 0xAAAA +#define WDT_DISABLE_CODE2 0x5555 + +#endif /* __ASM_ARCH_OMAP_WDT_H */

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