June 2008 - U-Boot

[U-Boot-Users] [PATCH] mtd: SPI Flash: Support the ST Microelectronics M25P80 and M25P40
by Jason McMullan 23 Jun '08

23 Jun '08

This commit adds MTD support for the M25P80 (1Mx8) and the M25P40 (512kx8) SPI Flash components from ST Microelectronics. Tested with the M25P40, but should work for the M25P80 according to the spec sheet. --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/spi_flash.c | 6 + drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/mtd/spi/stmicro.c | 320 ++++++++++++++++++++++++++++++++++ 4 files changed, 328 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/stmicro.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index af6af97..01b288a 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libspi_flash.a COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o +COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 962aa32..35ce822 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -134,6 +134,12 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, flash = spi_flash_probe_atmel(spi, idcode); break; #endif +#ifdef CONFIG_SPI_FLASH_STMICRO + case 0x00: + case 0xff: + flash = spi_flash_probe_stmicro(spi, idcode); + break; +#endif default: debug("SF: Unsupported manufacturer %02X\n", idcode[0]); flash = NULL; diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 1438050..e5f758e 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -43,3 +43,4 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c new file mode 100644 index 0000000..4043cb3 --- /dev/null +++ b/drivers/mtd/spi/stmicro.c @@ -0,0 +1,320 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan(a)netapp.com> + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_M25PXX_WREN 0x06 /* Write Enable */ +#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ +#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ +#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ +#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ +#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_M25PXX_PP 0x02 /* Page Program */ +#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ +#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ +#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ +#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ + +#define STM_ID_M25P40 0x12 +#define STM_ID_M25P80 0x13 + +#define STMICRO_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct stmicro_spi_flash_params { + uint8_t esig; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint8_t nr_sectors; + const char *name; +}; + +struct stmicro_spi_flash { + const struct stmicro_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct stmicro_spi_flash * +to_stmicro_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct stmicro_spi_flash, flash); +} + +static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { + { + .esig = STM_ID_M25P40, + .l2_page_size = 8, + .pages_per_sector = 256, + .nr_sectors = 8, + .name = "M25P40", + }, + { + .esig = STM_ID_M25P80, + .l2_page_size = 8, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25P80", + }, +}; + +static int stmicro_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + u8 cmd[4] = { CMD_M25PXX_RDSR, 0xff, 0xff, 0xff }; + + ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) + return -1; + + if ((status & STMICRO_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & STMICRO_SR_WIP) == 0) + return 0; + + /* Timed out */ + return -1; +} + +/* + * Assemble the address part of a command for STMicro devices in + * non-power-of-two page size mode. + */ +static void stmicro_build_address(struct stmicro_spi_flash *stm, u8 *cmd, u32 offset) +{ + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + + /* + * The "extra" space per page is the power-of-two page size + * divided by 32. + */ + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = page_addr >> (16 - page_shift); + cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[2] = byte_addr; +} + +static int stmicro_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + stmicro_build_address(stm, cmd + 1, offset); + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int stmicro_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_M25PXX_PP; + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[3] = byte_addr; + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: STMicro Page Program failed\n"); + goto out; + } + + ret = stmicro_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: STMicro page programming timed out\n"); + goto out; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: STMicro: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long sector_size; + unsigned int page_shift; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * This function currently uses sector erase only. + * probably speed things up by using bulk erase + * when possible. + */ + + page_shift = stm->params->l2_page_size; + sector_size = (1 << page_shift) * stm->params->pages_per_sector; + + if (offset % sector_size || len % sector_size) { + debug("SF: Erase offset/length not multiple of sector size\n"); + return -1; + } + + len /= sector_size; + cmd[0] = CMD_M25PXX_SE; + cmd[2] = 0x00; + cmd[3] = 0x00; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + cmd[1] = (offset / sector_size) + actual; + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: STMicro page erase failed\n"); + goto out; + } + + ret = stmicro_wait_ready(flash, 2 * CFG_HZ); /* Up to 2 seconds */ + if (ret < 0) { + debug("SF: STMicro page erase timed out\n"); + goto out; + } + } + + debug("SF: STMicro: Successfully erased %u bytes @ 0x%x\n", + len * sector_size, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode) +{ + const struct stmicro_spi_flash_params *params; + unsigned long page_size; + struct stmicro_spi_flash *stm; + unsigned int i; + int ret; + u8 id[4]; + + ret = spi_flash_cmd(spi, CMD_M25PXX_RES, id, 4); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { + params = &stmicro_spi_flash_table[i]; + if (params->esig == id[3]) + break; + } + + if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { + debug("SF: Unsupported STMicro ID %02x\n", + id[3]); + return NULL; + } + + stm = malloc(sizeof(struct stmicro_spi_flash)); + if (!stm) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = stmicro_write; + stm->flash.erase = stmicro_erase; + stm->flash.read = stmicro_read_fast; + stm->flash.size = page_size * params->pages_per_sector + * params->nr_sectors; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, page_size, stm->flash.size); + + return &stm->flash; +} -- 1.5.4.3

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[U-Boot-Users] Regarding NAND BOOT support in MPC832x
by amit.sharma＠spectross.com 23 Jun '08

23 Jun '08

Dear Sir, We are designing a DSL router based on MPC8323 network processor. We are having two option for booting process NOR as well as NAND but we want implement NAND BOOT in our board. Queries: 1)Is there any version of u-boot that support NAND BOOT for any development board based on MPC832x? Kindly revert back asap. Best Regards, From: Amit Sharma Junior Design Engineer Spectross Digital System 4,Siri Fort Road New Delhi, 110049 Tel :- 011-26264077 www.spectross.com

1 0

[U-Boot-Users] Non-static global variables cause relocation to fail
by Timur Tabi 22 Jun '08

22 Jun '08

I tried to find documentation on this, but couldn't. I've discovered, on PowerPC 85xx systems at least, that the mere presence of a non-static global variable, even if it isn't used by any code, will cause relocation to fail. Exactly how it fails, I can't say, but U-Boot does hang. If I make the global variable static, the problem goes away. Note that I have no code that actually references the variable. It just sits there, occupying space. Fortunately, the data structure doesn't need to be non-static. I just forgot to put 'static' in its definition. Of course, it would have been nice to know this up front. Can someone explain why this is the case? Do I need to do anything special in my code to access global variables, static or not static? -- Timur Tabi Linux kernel developer at Freescale

3 9

[U-Boot-Users] Compilation with gcc4 : Unknown values in msr
by valerian NA 20 Jun '08

20 Jun '08

Hi all, I sent two days ago, a mail concerning a trouble to compile u-boot with gcc4.3.2. I solve this problem by moving a section and concatenate with another in the beginning (you can have a look to the u-boot.lds to see the way the sections are organised). This section is named ".rodata.str1.1" (I have just added one line in the script) Linker script : http://superuploader.net/1b01c39a7a52380fa48d40d81f17ae97-u-boot-lds.html But now when I try to boot I have this error message : U-Boot 1.1.6-4 MPC8272 Reset Status: Check Stop, External Soft, External Hard CLOCK: CPU= 264 MHz, CPM= 198 MHz, BUS= 66 MHz, PCI= 33 MHz CPU: MPC8272 (HiP7 Rev 14, Mask 1.0 1K50M) at 264 MHz BOARD: type RMP100, rev.B, capabilities 802a, EPLD ver.1 I2C: ready DRAM: 64 MB DSP: 600Mhz-64Mo FLASH: 8 MB Bus Fault @ 0x03fe9450, fixup 0x00000000 Machine check in kernel mode. Caused by (from msr): regs 03bdfd78 Unknown values in msr NIP: 03FE9450 XER: 20000000 LR: 03FE93F0 REGS: 03bdfd78 TRAP: 0200 DAR: 03FFF6D4 MSR: 00003000 EE: 0 PR: 0 FP: 1 ME: 1 IR/DR: 00 GPR00: 0001A06C 03BDFE68 FFFFFAFF 0BFDC9FC 00000000 00000000 F0010000 F0003F80 GPR08: F0002104 480000D8 480000D8 00000021 03BDFC50 FB7FFFFF 04003000 07FE0000 GPR16: FFFFFFFF FFFFFFFA FF7FFFFF EFFFEFB7 00003002 00000001 00000000 03FE3098 GPR24: 00000108 FFEDFFFF 0000FFFF 0000FFFF 03BDFF64 03BDFF0C 0400345C 00800000 Call backtrace: machine check So I think I have a trouble in the organisation of sections. Maybe to see bugs, I made a objdump of 2 u-boot. One compiled with gcc3 and another compiled with gcc4. Dump gcc3 http://superuploader.net/9b6c29af92deddb0cbfffe467ae51a97-dump-gcc3-txt.html Dump gcc4 http://superuploader.net/90568c2250a4e92e1f37bb14210678bb-dump-gcc4-txt.html I don't know where I have to look, someone can help me to see where I have to work ? And with what tools ? And any documentation which can help me. Thanks again for your attention, Val.

2 1

[U-Boot-Users] [PATCH] NAND: Rename DEBUG to MTDDEBUG to avoid namespace pollution.
by Scott Wood 20 Jun '08

20 Jun '08

This is particularly problematic now that non-NAND-specific code is including <nand.h>, and thus all debugging code is being compiled regardless of whether it was requested, as reported by Scott McNutt <smcnutt(a)psyent.com>. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- cpu/arm926ejs/davinci/nand.c | 10 +++- drivers/mtd/nand/nand_base.c | 103 +++++++++++++++++++++++------------ drivers/mtd/nand/nand_bbt.c | 4 +- drivers/mtd/onenand/onenand_base.c | 95 +++++++++++++++++---------------- drivers/mtd/onenand/onenand_bbt.c | 6 +- include/linux/mtd/mtd.h | 4 +- 6 files changed, 132 insertions(+), 90 deletions(-) diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index ffc770f..36468e6 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -240,7 +240,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in return 0; case 1: /* Uncorrectable error */ - DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "ECC UNCORRECTED_ERROR 1\n"); return(-1); case 12: /* Correctable error */ @@ -256,7 +257,9 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; - DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit); + MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC " + "error at offset: %d, bit: %d\n", + find_byte, find_bit); page_data[find_byte] ^= (1 << find_bit); @@ -266,7 +269,8 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0) return(0); } - DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "UNCORRECTED_ERROR default\n"); return(-1); } } diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 740d3fc..6416d15 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -962,7 +962,9 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa status = this->waitfunc (mtd, this, FL_WRITING); /* See if device thinks it succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "%s: Failed write, page 0x%08x, ", + __FUNCTION__, page); return -EIO; } } else { @@ -1010,7 +1012,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int for (j = 0; j < eccsteps; j++) { /* Loop through and verify the data */ if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } datidx += mtd->eccsize; @@ -1018,7 +1022,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int if (!hweccbytes) continue; if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } oobofs += hweccbytes; @@ -1029,7 +1035,9 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int */ if (oobmode) { if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) { - DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: " + "Failed write verify, page 0x%08x ", + __FUNCTION__, page); goto out; } } else { @@ -1042,9 +1050,11 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int for (i = 0; i < ecccnt; i++) { int idx = oobsel->eccpos[i]; if (oobdata[idx] != oob_buf[oobofs + idx] ) { - DEBUG (MTD_DEBUG_LEVEL0, + MTDDEBUG (MTD_DEBUG_LEVEL0, "%s: Failed ECC write " - "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); + "verify, page 0x%08x, " + "%6i bytes were succesful\n", + __FUNCTION__, page, i); goto out; } } @@ -1131,11 +1141,13 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, int oobreadlen; - DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_ecc: Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -1252,7 +1264,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, * generator for an error, reads back the syndrome and * does the error correction on the fly */ if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr); ecc_failed++; } @@ -1291,7 +1303,9 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, } if (ecc_status == -1) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + "Failed ECC read, page 0x%08x\n", + page); ecc_failed++; } } @@ -1388,7 +1402,8 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t struct nand_chip *this = mtd->priv; int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; - DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", + (unsigned int) from, (int) len); /* Shift to get page */ page = (int)(from >> this->page_shift); @@ -1402,7 +1417,8 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_oob: Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -1488,7 +1504,8 @@ int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_read_raw: Attempt read beyond end of device\n"); return -EINVAL; } @@ -1626,14 +1643,16 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, u_char *oobbuf, *bufstart; int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); - DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow write past end of device */ if ((to + len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: Attempt to write past end of page\n"); return -EINVAL; } @@ -1695,7 +1714,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, */ ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0)); if (ret) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: write_page failed %d\n", ret); goto out; } /* Next oob page */ @@ -1719,7 +1739,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, page - startpage, oobbuf, oobsel, chipnr, (eccbuf != NULL)); if (ret) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: " + "verify_pages failed %d\n", ret); goto out; } *retlen = written; @@ -1752,7 +1773,8 @@ cmp: if (!ret) *retlen = written; else - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_write_ecc: verify_pages failed %d\n", ret); out: /* Deselect and wake up anyone waiting on the device */ @@ -1777,7 +1799,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * int column, page, status, ret = -EIO, chipnr; struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", + (unsigned int) to, (int) len); /* Shift to get page */ page = (int) (to >> this->page_shift); @@ -1791,7 +1814,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * /* Do not allow write past end of page */ if ((column + len) > mtd->oobsize) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Attempt to write past end of page\n"); return -EINVAL; } @@ -1821,8 +1845,9 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask); if (!ffchars) { if (!(ffchars = kmalloc (mtd->oobsize, GFP_KERNEL))) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " - "No memory for padding array, need %d bytes", mtd->oobsize); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "No memory for padding array, " + "need %d bytes", mtd->oobsize); ret = -ENOMEM; goto out; } @@ -1847,7 +1872,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * /* See if device thinks it succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Failed write, page 0x%08x\n", page); ret = -EIO; goto out; } @@ -1859,7 +1885,8 @@ static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask); if (this->verify_buf(mtd, buf, len)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " + "Failed write verify, page 0x%08x\n", page); ret = -EIO; goto out; } @@ -1919,12 +1946,14 @@ static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsig for (i = 0; i < count; i++) total_len += (int) vecs[i].iov_len; - DEBUG (MTD_DEBUG_LEVEL3, - "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count); + MTDDEBUG (MTD_DEBUG_LEVEL3, + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", + (unsigned int) to, (unsigned int) total_len, count); /* Do not allow write past end of page */ if ((to + total_len) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_writev: Attempted write past end of device\n"); return -EINVAL; } @@ -2117,24 +2146,26 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb int page, len, status, pages_per_block, ret, chipnr; struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, - "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", + (unsigned int) instr->addr, (unsigned int) instr->len); /* Start address must align on block boundary */ if (instr->addr & ((1 << this->phys_erase_shift) - 1)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); return -EINVAL; } /* Length must align on block boundary */ if (instr->len & ((1 << this->phys_erase_shift) - 1)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Length not block aligned\n"); return -EINVAL; } /* Do not allow erase past end of device */ if ((instr->len + instr->addr) > mtd->size) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Erase past end of device\n"); return -EINVAL; } @@ -2156,7 +2187,8 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb /* Check the WP bit */ /* Check, if it is write protected */ if (nand_check_wp(mtd)) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "nand_erase: Device is write protected!!!\n"); instr->state = MTD_ERASE_FAILED; goto erase_exit; } @@ -2186,7 +2218,8 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb /* See if block erase succeeded */ if (status & 0x01) { - DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); + MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " + "Failed erase, page 0x%08x\n", page); instr->state = MTD_ERASE_FAILED; instr->fail_addr = (page << this->page_shift); goto erase_exit; @@ -2229,7 +2262,7 @@ static void nand_sync (struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; - DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); /* Grab the lock and see if the device is available */ nand_get_device (this, mtd, FL_SYNCING); diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index eff76d7..a97743b 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -1038,8 +1038,8 @@ int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt) block = (int) (offs >> (this->bbt_erase_shift - 1)); res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; - DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, res, block >> 1); + MTDDEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: " + "(block %d) 0x%02x\n", (unsigned int)offs, res, block >> 1); switch ((int)res) { case 0x00: return 0; diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d1b9f8f..d32e382 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -293,22 +293,22 @@ static int onenand_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); if (ctrl & ONENAND_CTRL_ERROR) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: controller error = 0x%04x\n", ctrl); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: controller error = 0x%04x\n", ctrl); return -EAGAIN; } if (ctrl & ONENAND_CTRL_LOCK) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: it's locked error = 0x%04x\n", ctrl); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: it's locked error = 0x%04x\n", ctrl); return -EIO; } if (interrupt & ONENAND_INT_READ) { ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); if (ecc & ONENAND_ECC_2BIT_ALL) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_wait: ECC error = 0x%04x\n", ecc); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_wait: ECC error = 0x%04x\n", ecc); return -EBADMSG; } } @@ -524,13 +524,14 @@ static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, int thislen; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_ecc: " + "from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_ecc: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_ecc: " + "Attempt read beyond end of device\n"); *retlen = 0; return -EINVAL; } @@ -561,8 +562,8 @@ static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, break; if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_ecc: read failed = %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_read_ecc: read failed = %d\n", ret); break; } @@ -615,16 +616,17 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, int read = 0, thislen, column; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_oob: " + "from = 0x%08x, len = %i\n", + (unsigned int)from, (int)len); /* Initialize return length value */ *retlen = 0; /* Do not allow reads past end of device */ if (unlikely((from + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_oob: Attempt read beyond end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_oob: " + "Attempt read beyond end of device\n"); return -EINVAL; } @@ -652,8 +654,8 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, break; if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_read_oob: read failed = %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_read_oob: read failed = %d\n", ret); break; } @@ -733,23 +735,24 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, int written = 0; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_ecc: " + "to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow writes past end of device */ if (unlikely((to + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: Attempt write to past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " + "Attempt write to past end of device\n"); return -EINVAL; } /* Reject writes, which are not page aligned */ if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: Attempt to write not page aligned data\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " + "Attempt to write not page aligned data\n"); return -EINVAL; } @@ -772,8 +775,8 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, ret = this->wait(mtd, FL_WRITING); if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: write filaed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_write_ecc: write filaed %d\n", ret); break; } @@ -782,8 +785,8 @@ static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, /* Only check verify write turn on */ ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page); if (ret) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_ecc: verify failed %d\n", ret); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_write_ecc: verify failed %d\n", ret); break; } @@ -836,16 +839,17 @@ int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, int column, status; int written = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_oob: " + "to = 0x%08x, len = %i\n", + (unsigned int)to, (int)len); /* Initialize retlen, in case of early exit */ *retlen = 0; /* Do not allow writes past end of device */ if (unlikely((to + len) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_write_oob: Attempt write to past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_oob: " + "Attempt write to past end of device\n"); return -EINVAL; } @@ -904,28 +908,29 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) int len; int ret = 0; - DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", - (unsigned int)instr->addr, (unsigned int)instr->len); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + (unsigned int)instr->addr, (unsigned int)instr->len); block_size = (1 << this->erase_shift); /* Start address must align on block boundary */ if (unlikely(instr->addr & (block_size - 1))) { - DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Unaligned address\n"); return -EINVAL; } /* Length must align on block boundary */ if (unlikely(instr->len & (block_size - 1))) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Length not block aligned\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Length not block aligned\n"); return -EINVAL; } /* Do not allow erase past end of device */ if (unlikely((instr->len + instr->addr) > mtd->size)) { - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Erase past end of device\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, + "onenand_erase: Erase past end of device\n"); return -EINVAL; } @@ -950,12 +955,12 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) /* Check, if it is write protected */ if (ret) { if (ret == -EPERM) - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Device is write protected!!!\n"); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " + "Device is write protected!!!\n"); else - DEBUG(MTD_DEBUG_LEVEL0, - "onenand_erase: Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); + MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " + "Failed erase, block %d\n", + (unsigned)(addr >> this->erase_shift)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; goto erase_exit; @@ -988,7 +993,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) */ void onenand_sync(struct mtd_info *mtd) { - DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); + MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); /* Grab the lock and see if the device is available */ onenand_get_device(mtd, FL_SYNCING); diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index 5a610ee..87344ab 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -156,9 +156,9 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) block = (int)(offs >> (bbm->bbt_erase_shift - 1)); res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; - DEBUG(MTD_DEBUG_LEVEL2, - "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + MTDDEBUG (MTD_DEBUG_LEVEL2, + "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, block >> 1, res); switch ((int)res) { case 0x00: diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 71cb2d5..05ba375 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -201,13 +201,13 @@ static inline void mtd_erase_callback(struct erase_info *instr) #define MTD_DEBUG_LEVEL3 (3) /* Noisy */ #ifdef CONFIG_MTD_DEBUG -#define DEBUG(n, args...) \ +#define MTDDEBUG(n, args...) \ do { \ if (n <= CONFIG_MTD_DEBUG_VERBOSE) \ printk(KERN_INFO args); \ } while(0) #else /* CONFIG_MTD_DEBUG */ -#define DEBUG(n, args...) do { } while(0) +#define MTDDEBUG(n, args...) do { } while(0) #endif /* CONFIG_MTD_DEBUG */ -- 1.5.6.rc1.6.gc53ad

1 0

[U-Boot-Users] LL_TEMAC on Avnet MiniModule-FX12
by llandre 20 Jun '08

20 Jun '08

Hi all, I ported U-Boot 1.3.1 on Avnet MiniModule-FX12 (the repository I'm working with has been patched previously with ML403 patch). Here is my first dirty patch: http://www.dave.eu/download/misc/mmfx12/mmfx12-0.8.3.patch U-Boot works fine and it boots correctly from flash, however ethernet interface (LL_TEMAC) does not work. For example, when I try to perform a TFTP download, the XEmac_PollSend function never returns because the following loop never ends: /* * Loop on the MAC's status to wait for the transmit to complete. The * transmit status is in the FIFO when the XMIT_DONE bit is set. */ do { IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress); } while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0); Please note that the FPGA bitstream is ok because the linux kernel works fine and can mount root file system via NFS so I pretty sure something is wrong in my U-Boot port. Anybody experienced similar problems? TIA, llandre DAVE Electronics System House - R&D Department web: http://www.dave.eu email: r&d2(a)dave-tech.it

2 2

[U-Boot-Users] [PATCH 1/3] avr32: Add GPIO manipulation functions
by Haavard Skinnemoen 20 Jun '08

20 Jun '08

From: Peter Ma <pma(a)mediamatech.com> Adds GPIO manipulation functions for AVR32 AP7 platform. Signed-off-by: Peter Ma <pma(a)mediamatech.com> [haavard.skinnemoen(a)atmel.com: coding style fixup, slight simplification] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- This and the following two patches enables SPI flash support on ATNGW100. I want to merge this for v1.3.4 so that the new SPI flash code can get more exposure. I consider all three patches very low risk, so I hope it's ok to merge it outside the merge window. If not, please speak up. Haavard cpu/at32ap/pio.c | 56 ++++++++++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 8 ++++ 2 files changed, 64 insertions(+), 0 deletions(-) diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c index 9ba0b8e..f64004b 100644 --- a/cpu/at32ap/pio.c +++ b/cpu/at32ap/pio.c @@ -58,3 +58,59 @@ void gpio_select_periph_B(unsigned int pin, int use_pullup) else pio2_writel(base, PUDR, mask); } + +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (gpiof_flags & GPIOF_OUTPUT) { + if (gpiof_flags & GPIOF_MULTIDRV) + pio2_writel(base, MDER, mask); + else + pio2_writel(base, MDDR, mask); + pio2_writel(base, PUDR, mask); + pio2_writel(base, OER, mask); + } else { + if (gpiof_flags & GPIOF_PULLUP) + pio2_writel(base, PUER, mask); + else + pio2_writel(base, PUDR, mask); + if (gpiof_flags & GPIOF_DEGLITCH) + pio2_writel(base, IFER, mask); + else + pio2_writel(base, IFDR, mask); + pio2_writel(base, ODR, mask); + } + + pio2_writel(base, PER, mask); +} + +void gpio_set_value(unsigned int pin, int value) +{ + void *base = gpio_pin_to_addr(pin); + uint32_t mask = 1 << (pin & 0x1f); + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + if (value) + pio2_writel(base, SODR, mask); + else + pio2_writel(base, CODR, mask); +} + +int gpio_get_value(unsigned int pin) +{ + void *base = gpio_pin_to_addr(pin); + int value; + + if (!base) + panic("Invalid GPIO pin %u\n", pin); + + value = pio2_readl(base, PDSR); + return (value >> (pin & 0x1f)) & 1; +} diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index ef20cea..8c922c7 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -180,6 +180,11 @@ #define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) #define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) +#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */ +#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */ +#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */ +#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */ + static inline void *gpio_pin_to_addr(unsigned int pin) { switch (pin >> 5) { @@ -200,6 +205,9 @@ static inline void *gpio_pin_to_addr(unsigned int pin) void gpio_select_periph_A(unsigned int pin, int use_pullup); void gpio_select_periph_B(unsigned int pin, int use_pullup); +void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags); +void gpio_set_value(unsigned int pin, int value); +int gpio_get_value(unsigned int pin); void gpio_enable_ebi(void); -- 1.5.5.3

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[U-Boot-Users] i.MX31: mx31_gpio_mux() problem
by Magnus Lilja 20 Jun '08

20 Jun '08

Hi all While I was using the mx31_gpio_mux() function in cpu/arm1136/mx31/generic.c to modify the IOMUX for some IO pads I discovered that only the first 256 pads can be modified by this function. It's pretty easy to fix this (see patch below) but I wonder if it's really the right way to fix this problem. Currently mx31_gpio_mux() takes only one argument, mode, which contains both the pad number and the new mode. Current use: mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO); (the patch below changes << 8 to << 9 and modifies the mx31_gpiomux() function accordingly) Perhaps it's better to split the above into two arguments, pad number and pad mode, the function will then be called with: mx31_gpio_mux(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC); I prefer the second approach (i.e. not the one in the patch below). Any comments on which solution we prefer? Regards, Magnus Lilja --- board/imx31_litekit/imx31_litekit.c | 14 +++++++------- board/mx31ads/mx31ads.c | 14 +++++++------- cpu/arm1136/mx31/generic.c | 4 ++-- include/asm-arm/arch-mx31/mx31-regs.h | 12 ++++++------ 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c index 263dd9f..09ce6f8 100644 --- a/board/imx31_litekit/imx31_litekit.c +++ b/board/imx31_litekit/imx31_litekit.c @@ -53,13 +53,13 @@ int board_init (void) mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); /* SPI2 */ - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS2); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SCLK); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SPI_RDY); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_MOSI); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_MISO); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS0); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS1); /* start SPI2 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c index dd0e150..b29d1b0 100644 --- a/board/mx31ads/mx31ads.c +++ b/board/mx31ads/mx31ads.c @@ -58,13 +58,13 @@ int board_init (void) mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); /* SPI2 */ - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0); - mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS2); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SCLK); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SPI_RDY); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_MOSI); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_MISO); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS0); + mx31_gpio_mux((MUX_CTL_FUNC << 9) | MUX_CTL_CSPI2_SS1); /* start SPI2 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c index 29c08c1..f897a2a 100644 --- a/cpu/arm1136/mx31/generic.c +++ b/cpu/arm1136/mx31/generic.c @@ -81,12 +81,12 @@ void mx31_gpio_mux(unsigned long mode) { unsigned long reg, shift, tmp; - reg = IOMUXC_BASE + (mode & 0xfc); + reg = IOMUXC_BASE + (mode & 0x1fc); shift = (~mode & 0x3) * 8; tmp = __REG(reg); tmp &= ~(0xff << shift); - tmp |= ((mode >> 8) & 0xff) << shift; + tmp |= ((mode >> 9) & 0xff) << shift; __REG(reg) = tmp; } diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 02b7dcb..b1c6327 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -130,13 +130,13 @@ * these macros can be used in mx31_gpio_mux() and have the form * MUX_[contact name]__[pin function] */ -#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) -#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) -#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) -#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) +#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 9) | MUX_CTL_RXD1) +#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 9) | MUX_CTL_TXD1) +#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 9) | MUX_CTL_RTS1) +#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 9) | MUX_CTL_CTS1) -#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) -#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 9) | MUX_CTL_CSPI2_MOSI) +#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 9) | MUX_CTL_CSPI2_MISO) /* * Memory regions and CS

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[U-Boot-Users] Value of CFG_PCI_MEMBASE
by Sachin Rane 20 Jun '08

20 Jun '08

Hi, In the 'include/configs/ocotea.h" file: 8<----------------------------------------------------------------------------------------------------- #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ 8<----------------------------------------------------------------------------------------------------- But the Memory map of the Ocotea board (PPC440GX® Evaluation Board User's Manual) has mentioned about the PCI memory as: Start Address (32 Bit) - 9000 0000 End Address (32 Bit) - 9FFF FFFF Start Address (36 Bit) - 3 0000 0000 End Address (36 Bit) - 3 0FFF FFFF Size - 256MB 256 MB I am not clear about the logic behind the value assigned to CFG_PCI_MEMBASE i.e. 0x80000000 Can you help me to figure it out? Regards, Sachin Rane

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[U-Boot-Users] Sascha Erlacher/BBL/MS/PHILIPS is out of the office.
by Sascha Erlacher 20 Jun '08

20 Jun '08

I will be out of the office starting 20.06.2008 and will not return until 26.06.2008. I will respond to your message when I return.

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