May 2008 - U-Boot

[U-Boot-Users] [PATCH] MAKEALL: add inka4x0 board
by Wolfgang Denk 05 May '08

05 May '08

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- MAKEALL | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 38911ed..791eabc 100755 --- a/MAKEALL +++ b/MAKEALL @@ -42,6 +42,7 @@ LIST_5xxx=" \ fo300 \ icecube_5100 \ icecube_5200 \ + inka4x0 \ lite5200b \ mcc200 \ mecp5200 \ -- 1.5.4.2

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05 May '08

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[U-Boot-Users] u-boot BOOTELF clearing SHT_NOBITS sections
by Baruch Cochavy 05 May '08

05 May '08

Hi, u-boot's bootelf clears (memset to 0) sections of SHT_NOBITS type. This covers .bss sections - however, it might also includes other sections, not expected to be cleared as per some users expectations (stacks, for example). I am beginning to wonder if this behavior is correct/desired: if one tries to bootelf an ELF file which happens to resizde somewhere inside the .bss section, or some other data section of the loaded code, bootelf clears it (or part of it...) while loading, corrupting the code to be loaded. AFAIK, .bss is normally zeroed out in crt0 (or equivalent), so there is no need (?) to zero it in bootelf. Bootelf may also defer all such actions (clearing section) to the end of the loading process. Please feel free to correct me I I am wrong... Thanks, Baruch Cochavy

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[U-Boot-Users] [PATCH] Fix implicit declaration build warnings
by Marcel Ziswiler 05 May '08

05 May '08

- warning: implicit declaration of function ‘serial_initialize’ Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- lib_arm/board.c | 1 + lib_m68k/board.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index 22d573a..67506b3 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -44,6 +44,7 @@ #include <devices.h> #include <version.h> #include <net.h> +#include <serial.h> #ifdef CONFIG_DRIVER_SMC91111 #include "../drivers/net/smc91111.h" diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 9159206..6654f97 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -45,6 +45,7 @@ #include <status_led.h> #endif #include <net.h> +#include <serial.h> #if defined(CONFIG_CMD_BEDBUG) #include <cmd_bedbug.h> #endif -- 1.5.4.1

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[U-Boot-Users] [PATCH] adsvix: Fix undefined reference to inb and outb build errors
by Marcel Ziswiler 05 May '08

05 May '08

- undefined reference to `inb' - undefined reference to `outb' Signed-off-by: Marcel Ziswiler <marcel(a)ziswiler.com> --- include/configs/adsvix.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h index 703d312..58914cb 100644 --- a/include/configs/adsvix.h +++ b/include/configs/adsvix.h @@ -310,6 +310,7 @@ #define CONFIG_PXA_PCMCIA 1 #define CONFIG_PXA_IDE 1 +#define __io #define CONFIG_PCMCIA_SLOT_A 1 /* just to keep build system happy */ -- 1.5.4.1

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[U-Boot-Users] [PATCH] kb9202 board: fix build problem.
by Wolfgang Denk 04 May '08

04 May '08

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- include/configs/kb9202.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 75d9c3b..7dcce83 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -54,10 +54,13 @@ #define CFG_LONGHELP +#ifndef roundup +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#endif /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_MALLOC_LEN (roundup(CFG_ENV_SIZE,4096) + 128*1024) #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_BAUDRATE 115200 -- 1.5.4.2

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[U-Boot-Users] [PATCH] arm920t: start.S coding style cleanup
by Jean-Christophe PLAGNIOL-VILLARD 04 May '08

04 May '08

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- cpu/arm920t/start.S | 178 +++++++++++++++++++++++++-------------------------- 1 files changed, 88 insertions(+), 90 deletions(-) diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index acc00ad..3067d8c 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -1,9 +1,9 @@ /* - * armboot - Startup Code for ARM920 CPU-core + * armboot - Startup Code for ARM920 CPU-core * - * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> - * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> - * Copyright (c) 2002 Gary Jennejohn <gj(a)denx.de> + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <gj(a)denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -39,7 +39,7 @@ .globl _start -_start: b start_code +_start: b start_code ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -77,18 +77,18 @@ _TEXT_BASE: .globl _armboot_start _armboot_start: - .word _start + .word _start /* * These are defined in the board-specific linker script. */ .globl _bss_start _bss_start: - .word __bss_start + .word __bss_start .globl _bss_end _bss_end: - .word _end + .word _end #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ @@ -99,7 +99,7 @@ IRQ_STACK_START: /* IRQ stack memory (calculated at run-time) */ .globl FIQ_STACK_START FIQ_STACK_START: - .word 0x0badc0de + .word 0x0badc0de #endif @@ -111,10 +111,10 @@ start_code: /* * set the cpu to SVC32 mode */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr, r0 bl coloured_LED_init bl red_LED_on @@ -136,20 +136,20 @@ copyex: #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) /* turn off the watchdog */ -# if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ +#if defined(CONFIG_S3C2400) +#define pWTCON 0x15300000 +#define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +#define CLKDIVN 0x14800014 /* clock divisor register */ #else -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ +#define pWTCON 0x53000000 +#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +#define INTSUBMSK 0x4A00001C +#define CLKDIVN 0x4C000014 /* clock divisor register */ # endif - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] /* * mask all IRQs by setting all bits in the INTMR - default @@ -157,11 +157,11 @@ copyex: mov r1, #0xffffffff ldr r0, =INTMSK str r1, [r0] -# if defined(CONFIG_S3C2410) +#if defined(CONFIG_S3C2410) ldr r1, =0x3ff ldr r0, =INTSUBMSK str r1, [r0] -# endif +#endif /* FCLK:HCLK:PCLK = 1:2:4 */ /* default FCLK is 120 MHz ! */ @@ -181,40 +181,40 @@ copyex: #ifndef CONFIG_AT91RM9200 #ifndef CONFIG_SKIP_RELOCATE_UBOOT -relocate: /* relocate U-Boot to RAM */ - adr r0, _start /* r0 <- current position of code */ +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r3-r10} /* copy from source address [r0] */ - stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end addreee [r2] */ + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ -#endif - /* Set up the stack */ +#endif /* !CONFIG_AT91RM9200 */ + /* Set up the stack */ stack_setup: - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif - sub sp, r0, #12 /* leave 3 words for abort-stack */ + sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: - ldr r0, _bss_start /* find start of bss segment */ - ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l @@ -223,7 +223,6 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot - /* ************************************************************************* * @@ -235,7 +234,6 @@ _start_armboot: .word start_armboot ************************************************************************* */ - #ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* @@ -249,10 +247,10 @@ cpu_init_crit: * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 /* @@ -261,7 +259,7 @@ cpu_init_crit: * find a lowlevel_init.S in your board directory. */ mov ip, lr -#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) #else bl lowlevel_init @@ -278,9 +276,9 @@ cpu_init_crit: ************************************************************************* */ -@ -@ IRQ stack frame. -@ +/* + * IRQ stack frame. + */ #define S_FRAME_SIZE 72 #define S_OLD_R0 68 @@ -303,8 +301,8 @@ cpu_init_crit: #define S_R1 4 #define S_R0 0 -#define MODE_SVC 0x13 -#define I_BIT 0x80 +#define MODE_SVC 0x13 +#define I_BIT 0x80 /* * use bad_save_user_regs for abort/prefetch/undef/swi ... @@ -313,95 +311,95 @@ cpu_init_crit: .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 + stmia sp, {r0 - r12} /* Calling r0-r12 */ ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack - ldmia r2, {r2 - r3} @ get pc, cpsr - add r0, sp, #S_FRAME_SIZE @ restore sp_SVC + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) /* set base 2 words into abort stack */ + ldmia r2, {r2 - r3} /* get pc, cpsr */ + add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ add r5, sp, #S_SP mov r1, lr - stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + stmia r5, {r0 - r3} /* save sp_SVC, lr_SVC, pc, cpsr */ mov r0, sp .endm .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC - mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 + stmia sp, {r0 - r12} /* Calling r0-r12 */ + add r7, sp, #S_PC + stmdb r7, {sp, lr}^ /* Calling SP, LR */ + str lr, [r7, #0] /* Save calling PC */ + mrs r6, spsr + str r6, [r7, #4] /* Save CPSR */ + str r0, [r7, #8] /* Save OLD_R0 */ mov r0, sp .endm .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr + ldmia sp, {r0 - lr}^ /* Calling r0 - lr */ mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC + ldr lr, [sp, #S_PC] /* Get PC */ add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr + subs pc, lr, #4 /* return & move spsr_svc into cpsr */ .endm .macro get_bad_stack - ldr r13, _armboot_start @ setup our mode stack + ldr r13, _armboot_start /* setup our mode stack */ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) /* reserved a couple spots in abort stack */ - str lr, [r13] @ save caller lr / spsr + str lr, [r13] /* save caller lr / spsr */ mrs lr, spsr - str lr, [r13, #4] + str lr, [r13, #4] - mov r13, #MODE_SVC @ prepare SVC-Mode - @ msr spsr_c, r13 + mov r13, #MODE_SVC /* prepare SVC-Mode */ + /* msr spsr_c, r13 */ msr spsr, r13 mov lr, pc movs pc, lr .endm - .macro get_irq_stack @ setup IRQ stack + .macro get_irq_stack /* setup IRQ stack */ ldr sp, IRQ_STACK_START .endm - .macro get_fiq_stack @ setup FIQ stack + .macro get_fiq_stack /* setup FIQ stack */ ldr sp, FIQ_STACK_START .endm /* * exception handlers */ - .align 5 + .align 5 undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -409,7 +407,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -417,7 +415,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -426,12 +424,12 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif -- 1.5.4.5

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[U-Boot-Users] [PATCH] fix building when saveenv is disabled in some setups
by Mike Frysinger 04 May '08

04 May '08

If you enable environment in the flash, but disable the embedded option, and you disable the saveenv command, then the #if nested logic will trigger a compile failure: env_flash.c: In function ‘env_relocate_spec’: env_flash.c:399: error: ‘flash_addr’ undeclared (first use in this function) The fix is to add CMD_SAVEENV ifdef protection like everywhere else. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/env_flash.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/common/env_flash.c b/common/env_flash.c index eccfb62..a92160d 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -378,7 +378,9 @@ void env_relocate_spec (void) puts ("*** Warning - some problems detected " "reading environment; recovered successfully\n\n"); #endif /* CFG_ENV_ADDR_REDUND */ +#ifdef CMD_SAVEENV memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE); +#endif #endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */ } -- 1.5.5.1

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[U-Boot-Users] [U-Boot Users][PATCH] ADS5121 IO Pin Configuration
by Martha J Marx 04 May '08

04 May '08

Adds configurable IO Pin initialization for ADS5121 and consolidates existing IO pin initialization. Signed-off-by: Martha J Marx <mmarx@si...> --- board/ads5121/ads5121.c | 10 +-- cpu/mpc512x/Makefile | 2 +- cpu/mpc512x/fec.c | 15 ---- cpu/mpc512x/iopin.c | 72 ++++++++++++++++ cpu/mpc512x/iopin.h | 200 +++++++++++++++++++++++++++++++++++++++++++++ include/configs/ads5121.h | 1 + 6 files changed, 277 insertions(+), 23 deletions(-) create mode 100644 cpu/mpc512x/iopin.c create mode 100644 cpu/mpc512x/iopin.h diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 35544f1..69bf4b5 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -47,6 +47,7 @@ #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) long int fixed_sdram(void); +extern void iopin_initialize (void); int board_early_init_f (void) { @@ -204,17 +205,12 @@ int checkboard (void) { ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile unsigned long *reg; - int i; printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); + /* initialize function mux & slew rate IO inter alia on IO Pins */ + iopin_initialize(); - /* change the slew rate on all pata pins to max */ - reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]); - for (i = 0; i < 9; i++) - reg[i] |= 0x00000003; return 0; } #ifdef CONFIG_MISC_INIT_R diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index 2be35b2..8ba8ae8 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index c226a8a..e9df7de 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -604,13 +604,10 @@ static int mpc512x_fec_recv (struct eth_device *dev) /********************************************************************/ int mpc512x_fec_initialize (bd_t * bis) { - - immap_t *im = (immap_t*) CFG_IMMR; mpc512x_fec_priv *fec; struct eth_device *dev; int i; char *tmp, *end, env_enetaddr[6]; - uint32 *reg; void * bd; fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); @@ -639,18 +636,6 @@ int mpc512x_fec_initialize (bd_t * bis) fec512x_miiphy_read, fec512x_miiphy_write); #endif - /* - * Initialize I\O pins - */ - reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); - - for (i = 0; i < 15; i++) - reg[i] = IOCTRL_MUX_FEC | 0x00000001; - - im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001; - im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001; - im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001; - /* Clean up space FEC's MIB and FIFO RAM ...*/ memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c new file mode 100644 index 0000000..e2b536b --- /dev/null +++ b/cpu/mpc512x/iopin.c @@ -0,0 +1,72 @@ +/* + * mpc512x I/O pin/pad initialization + */ +#include <common.h> +#include <linux/types.h> +#include "iopin.h" + +/* + * IO PAD TYPES for all types fmux is used to select the funtion and ds sets the slew rate + * STD nothing extra (can set ds & fmux only) + * STD_PU pue=1 to enable the pull & pud sets whether up or down resistors + * STD_ST can set the Schmitt trigger + * STD_PU_ST pue & pud sets pull-up/down resistors & st sets the Schmitt trigger + * PCI hold sets output delay + * PCI_ST hold sets output delay and st sets the Schmitt trigger + */ +static struct iopin_t { + u_short p_offset; /* offset from IOCTL_MEM_OFFSET */ + u_short p_no; /* number of pins to set this way */ + u_short bit_or:7; /* Do bitwise OR instead of setting */ + u_short fmux:2; /* pad function select 0-3 */ + u_short hold:2; /* PCI pad types only; */ + u_short pud:1; /* pull resistor; PU types only; */ + /* if pue=1 then 0=pull-down, 1=pull-up */ + u_short pue:1; /* Pull resistor enable; _PU types only */ + u_short st:1; /* Schmitt trigger enable; _ST types only */ + u_short ds:2; /* Slew rate class, 0=class1, ..., 3=class4 */ + } ioregs_init[] = { +#ifdef CONFIG_ADS5121 +/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ + {IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3}, +/* Set highest Slew on 9 PATA pins */ + {IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3}, +/* FUNC1=FEC_COL Sets Next 15 to FEC pads */ + {IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3}, +/* FUNC1=SPDIF_TXCLK */ + {IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3}, +/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ + {IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3}, +/* FUNC2=DIU CLK */ + {IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3}, +/* FUNC2=DIU_HSYNC */ + {IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3}, +/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ + {IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3} +#endif + }; + +void iopin_initialize(void) +{ + short i, j, n, p; + u_long *reg; + + if (sizeof(ioregs_init) == 0) + return; + + immap_t *im = (immap_t *)CFG_IMMR; + reg = (u_long *)&(im->io_ctrl.regs[0]); + n = sizeof(ioregs_init) / sizeof(ioregs_init[0]); + + for (i = 0; i < n; i++) { + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].p_no; p++, j++) { + /* lowest 9 bits sets the register */ + if (ioregs_init[i].bit_or) + reg[j] |= *((u_long *) &ioregs_init[i].p_no) & 0x000001ff; + else + reg[j] = *((u_long *) &ioregs_init[i].p_no) & 0x000001ff; + } + } + return; +} diff --git a/cpu/mpc512x/iopin.h b/cpu/mpc512x/iopin.h new file mode 100644 index 0000000..5ef107d --- /dev/null +++ b/cpu/mpc512x/iopin.h @@ -0,0 +1,200 @@ +/* + * mpc512x I/O pin/pad initialization + */ +#define IOCTL_MEM 0x000 +#define IOCTL_GP 0x004 +#define IOCTL_LPC_CLK 0x008 +#define IOCTL_LPC_OE 0x00C +#define IOCTL_LPC_RWB 0x010 +#define IOCTL_LPC_ACK 0x014 +#define IOCTL_LPC_CS0 0x018 +#define IOCTL_NFC_CE0 0x01C +#define IOCTL_LPC_CS1 0x020 +#define IOCTL_LPC_CS2 0x024 +#define IOCTL_LPC_AX03 0x028 +#define IOCTL_EMB_AX02 0x02C +#define IOCTL_EMB_AX01 0x030 +#define IOCTL_EMB_AX00 0x034 +#define IOCTL_EMB_AD31 0x038 +#define IOCTL_EMB_AD30 0x03C +#define IOCTL_EMB_AD29 0x040 +#define IOCTL_EMB_AD28 0x044 +#define IOCTL_EMB_AD27 0x048 +#define IOCTL_EMB_AD26 0x04C +#define IOCTL_EMB_AD25 0x050 +#define IOCTL_EMB_AD24 0x054 +#define IOCTL_EMB_AD23 0x058 +#define IOCTL_EMB_AD22 0x05C +#define IOCTL_EMB_AD21 0x060 +#define IOCTL_EMB_AD20 0x064 +#define IOCTL_EMB_AD19 0x068 +#define IOCTL_EMB_AD18 0x06C +#define IOCTL_EMB_AD17 0x070 +#define IOCTL_EMB_AD16 0x074 +#define IOCTL_EMB_AD15 0x078 +#define IOCTL_EMB_AD14 0x07C +#define IOCTL_EMB_AD13 0x080 +#define IOCTL_EMB_AD12 0x084 +#define IOCTL_EMB_AD11 0x088 +#define IOCTL_EMB_AD10 0x08C +#define IOCTL_EMB_AD09 0x090 +#define IOCTL_EMB_AD08 0x094 +#define IOCTL_EMB_AD07 0x098 +#define IOCTL_EMB_AD06 0x09C +#define IOCTL_EMB_AD05 0x0A0 +#define IOCTL_EMB_AD04 0x0A4 +#define IOCTL_EMB_AD03 0x0A8 +#define IOCTL_EMB_AD02 0x0AC +#define IOCTL_EMB_AD01 0x0B0 +#define IOCTL_EMB_AD00 0x0B4 +#define IOCTL_PATA_CE1 0x0B8 +#define IOCTL_PATA_CE2 0x0BC +#define IOCTL_PATA_ISOLATE 0x0C0 +#define IOCTL_PATA_IOR 0x0C4 +#define IOCTL_PATA_IOW 0x0C8 +#define IOCTL_PATA_IOCHRDY 0x0CC +#define IOCTL_PATA_INTRQ 0x0D0 +#define IOCTL_PATA_DRQ 0x0D4 +#define IOCTL_PATA_DACK 0x0D8 +#define IOCTL_NFC_WP 0x0DC +#define IOCTL_NFC_RB 0x0E0 +#define IOCTL_NFC_ALE 0x0E4 +#define IOCTL_NFC_CLE 0x0E8 +#define IOCTL_NFC_WE 0x0EC +#define IOCTL_NFC_RE 0x0F0 +#define IOCTL_PCI_AD31 0x0F4 +#define IOCTL_PCI_AD30 0x0F8 +#define IOCTL_PCI_AD29 0x0FC +#define IOCTL_PCI_AD28 0x100 +#define IOCTL_PCI_AD27 0x104 +#define IOCTL_PCI_AD26 0x108 +#define IOCTL_PCI_AD25 0x10C +#define IOCTL_PCI_AD24 0x110 +#define IOCTL_PCI_AD23 0x114 +#define IOCTL_PCI_AD22 0x118 +#define IOCTL_PCI_AD21 0x11C +#define IOCTL_PCI_AD20 0x120 +#define IOCTL_PCI_AD19 0x124 +#define IOCTL_PCI_AD18 0x128 +#define IOCTL_PCI_AD17 0x12C +#define IOCTL_PCI_AD16 0x130 +#define IOCTL_PCI_AD15 0x134 +#define IOCTL_PCI_AD14 0x138 +#define IOCTL_PCI_AD13 0x13C +#define IOCTL_PCI_AD12 0x140 +#define IOCTL_PCI_AD11 0x144 +#define IOCTL_PCI_AD10 0x148 +#define IOCTL_PCI_AD09 0x14C +#define IOCTL_PCI_AD08 0x150 +#define IOCTL_PCI_AD07 0x154 +#define IOCTL_PCI_AD06 0x158 +#define IOCTL_PCI_AD05 0x15C +#define IOCTL_PCI_AD04 0x160 +#define IOCTL_PCI_AD03 0x164 +#define IOCTL_PCI_AD02 0x168 +#define IOCTL_PCI_AD01 0x16C +#define IOCTL_PCI_AD00 0x170 +#define IOCTL_PCI_CBE0 0x174 +#define IOCTL_PCI_CBE1 0x178 +#define IOCTL_PCI_CBE2 0x17C +#define IOCTL_PCI_CBE3 0x180 +#define IOCTL_PCI_GNT2 0x184 +#define IOCTL_PCI_REQ2 0x188 +#define IOCTL_PCI_GNT1 0x18C +#define IOCTL_PCI_REQ1 0x190 +#define IOCTL_PCI_GNT0 0x194 +#define IOCTL_PCI_REQ0 0x198 +#define IOCTL_PCI_INTA 0x19C +#define IOCTL_PCI_CLK 0x1A0 +#define IOCTL_PCI_RST_OUT 0x1A4 +#define IOCTL_PCI_FRAME 0x1A8 +#define IOCTL_PCI_IDSEL 0x1AC +#define IOCTL_PCI_DEVSEL 0x1B0 +#define IOCTL_PCI_IRDY 0x1B4 +#define IOCTL_PCI_TRDY 0x1B8 +#define IOCTL_PCI_STOP 0x1BC +#define IOCTL_PCI_PAR 0x1C0 +#define IOCTL_PCI_PERR 0x1C4 +#define IOCTL_PCI_SERR 0x1C8 +#define IOCTL_SPDIF_TXCLK 0x1CC +#define IOCTL_SPDIF_TX 0x1D0 +#define IOCTL_SPDIF_RX 0x1D4 +#define IOCTL_I2C0_SCL 0x1D8 +#define IOCTL_I2C0_SDA 0x1DC +#define IOCTL_I2C1_SCL 0x1E0 +#define IOCTL_I2C1_SDA 0x1E4 +#define IOCTL_I2C2_SCL 0x1E8 +#define IOCTL_I2C2_SDA 0x1EC +#define IOCTL_IRQ0 0x1F0 +#define IOCTL_IRQ1 0x1F4 +#define IOCTL_CAN1_TX 0x1F8 +#define IOCTL_CAN2_TX 0x1FC +#define IOCTL_J1850_TX 0x200 +#define IOCTL_J1850_RX 0x204 +#define IOCTL_PSC_MCLK_IN 0x208 +#define IOCTL_PSC0_0 0x20C +#define IOCTL_PSC0_1 0x210 +#define IOCTL_PSC0_2 0x214 +#define IOCTL_PSC0_3 0x218 +#define IOCTL_PSC0_4 0x21C +#define IOCTL_PSC1_0 0x220 +#define IOCTL_PSC1_1 0x224 +#define IOCTL_PSC1_2 0x228 +#define IOCTL_PSC1_3 0x22C +#define IOCTL_PSC1_4 0x230 +#define IOCTL_PSC2_0 0x234 +#define IOCTL_PSC2_1 0x238 +#define IOCTL_PSC2_2 0x23C +#define IOCTL_PSC2_3 0x240 +#define IOCTL_PSC2_4 0x244 +#define IOCTL_PSC3_0 0x248 +#define IOCTL_PSC3_1 0x24C +#define IOCTL_PSC3_2 0x250 +#define IOCTL_PSC3_3 0x254 +#define IOCTL_PSC3_4 0x258 +#define IOCTL_PSC4_0 0x25C +#define IOCTL_PSC4_1 0x260 +#define IOCTL_PSC4_2 0x264 +#define IOCTL_PSC4_3 0x268 +#define IOCTL_PSC4_4 0x26C +#define IOCTL_PSC5_0 0x270 +#define IOCTL_PSC5_1 0x274 +#define IOCTL_PSC5_2 0x278 +#define IOCTL_PSC5_3 0x27C +#define IOCTL_PSC5_4 0x280 +#define IOCTL_PSC6_0 0x284 +#define IOCTL_PSC6_1 0x288 +#define IOCTL_PSC6_2 0x28C +#define IOCTL_PSC6_3 0x290 +#define IOCTL_PSC6_4 0x294 +#define IOCTL_PSC7_0 0x298 +#define IOCTL_PSC7_1 0x29C +#define IOCTL_PSC7_2 0x2A0 +#define IOCTL_PSC7_3 0x2A4 +#define IOCTL_PSC7_4 0x2A8 +#define IOCTL_PSC8_0 0x2AC +#define IOCTL_PSC8_1 0x2B0 +#define IOCTL_PSC8_2 0x2B4 +#define IOCTL_PSC8_3 0x2B8 +#define IOCTL_PSC8_4 0x2BC +#define IOCTL_PSC9_0 0x2C0 +#define IOCTL_PSC9_1 0x2C4 +#define IOCTL_PSC9_2 0x2C8 +#define IOCTL_PSC9_3 0x2CC +#define IOCTL_PSC9_4 0x2D0 +#define IOCTL_PSC10_0 0x2D4 +#define IOCTL_PSC10_1 0x2D8 +#define IOCTL_PSC10_2 0x2DC +#define IOCTL_PSC10_3 0x2E0 +#define IOCTL_PSC10_4 0x2E4 +#define IOCTL_PSC11_0 0x2E8 +#define IOCTL_PSC11_1 0x2EC +#define IOCTL_PSC11_2 0x2F0 +#define IOCTL_PSC11_3 0x2F4 +#define IOCTL_PSC11_4 0x2F8 +#define IOCTL_HRESET 0x2FC +#define IOCTL_SRESET 0x300 +#define IOCTL_CKSTP_OUT 0x304 +#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 +#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C +#define IOCTL_USB2_PHY_DRVV_BUS 0x310 diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 5f82855..04b2a96 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -27,6 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_ADS5121 1 /* * Memory map for the ADS5121 board: * -- 1.5.2.4

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[U-Boot-Users] [U-Boot Users][PATCH] ADS5121 Rev 3 Configuration Changes
by Martha J Marx 04 May '08

04 May '08

Configuration changes added to support ADS5121 Rev 3 version of the board. This includes changes to the ref clock, memory size (from 256 to 512), the addition of PCI functionality and Makefile options to build either the Rev 3 or Rev 2 U-Boot. The new README explains these options. Signed-off-by: Martha J Marx <mmarx@si...> --- Makefile | 9 ++++----- board/ads5121/README | 9 +++++++++ board/ads5121/ads5121.c | 34 ++++++++++++++++++++++++++++++---- cpu/mpc512x/cpu.c | 8 ++++++-- include/configs/ads5121.h | 27 +++++++++++++++++++++++---- 5 files changed, 72 insertions(+), 15 deletions(-) create mode 100644 board/ads5121/README diff --git a/Makefile b/Makefile index ac0a17f..f91c75b 100644 --- a/Makefile +++ b/Makefile @@ -742,12 +742,11 @@ motionpro_config: unconfig ## MPC512x Systems ######################################################################### ads5121_config \ -ads5121_PCI_config \ - : unconfig +ads5121_256_config \ + : unconfig @mkdir -p $(obj)include - @if [ "$(findstring _PCI_,$@)" ] ; then \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - $(XECHO) "... with PCI enabled" ; \ + @if [ "$(findstring 256,$@)" ] ; then \ + echo "#define CONFIG_ADS5121_256 1" > $(obj)include/config.h; \ fi @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121 diff --git a/board/ads5121/README b/board/ads5121/README new file mode 100644 index 0000000..ec49ba8 --- /dev/null +++ b/board/ads5121/README @@ -0,0 +1,9 @@ +To configure for the Rev 3.x ADS5121 type +make ads5121_config +This will automatically include PCI and the Real Time CLock abilities, +and set the correct frequency and memory configuration. + +To configure for the Rev 2 ADS5121 type +make ads5121_256_config + + diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8629b03..35544f1 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -26,7 +26,9 @@ #include <asm/bitops.h> #include <command.h> #include <fdt_support.h> - +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#endif /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ @@ -50,7 +52,6 @@ int board_early_init_f (void) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 lpcaw; - /* * Initialize Local Window for the CPLD registers access (CS2 selects * the CPLD chip) @@ -58,7 +59,6 @@ int board_early_init_f (void) im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); im->lpc.cs_cfg[2] = CFG_CS2_CFG; - /* * According to MPC5121e RM, configuring local access windows should * be followed by a dummy read of the config register that was @@ -73,8 +73,22 @@ int board_early_init_f (void) * Without this the flash identification routine fails, as it needs to issue * write commands in order to establish the device ID. */ - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; +#ifdef CONFIG_ADS5121_256 + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; +#else + if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) { + + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + } else { + /* running from Backup flash */ + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32; + } +#endif + /* + * Configure Flash Speed + */ + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; /* * Enable clocks */ @@ -203,6 +217,18 @@ int checkboard (void) reg[i] |= 0x00000003; return 0; } +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + /* + * I2C writes to turn on DVI + */ + static uchar buf[1] = {0xbf}; + i2c_set_bus_num(2); + i2c_write(0x38, 0x8, 1, buf, 1); + return 0; +} +#endif #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index bed77ac..3b45bfe 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -133,8 +133,9 @@ void watchdog_reset (void) #ifdef CONFIG_OF_LIBFDT void ft_cpu_setup(void *blob, bd_t *bd) { - char * cpu_path = "/cpus/" OF_CPU; - char * eth_path = "/" OF_SOC "/ethernet@2800"; + char *cpu_path = "/cpus/" OF_CPU; + char *eth_path = "/" OF_SOC "/ethernet@2800"; + char *eth_path_old = "/" OF_SOC_OLD "/ethernet@2800"; do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); @@ -143,6 +144,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); /* this is so old kernels with old device trees will boot */ + do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0); + do_fixup_by_path(blob, eth_path_old, "local-mac-address", bd->bi_enetaddr, 6, 0); + do_fixup_by_path(blob, eth_path_old, "address", bd->bi_enetaddr, 6, 0); } #endif diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 81e7c1e..5f82855 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -48,9 +48,15 @@ /* CONFIG_PCI is defined at config time */ +#ifdef CONFIG_ADS5121_256 #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ +#else +#define CFG_MPC512X_CLKIN 33333333 /* in Hz */ +#define CONFIG_PCI +#endif #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R /* call board_last_stage_init() */ #define CFG_IMMR 0x80000000 @@ -60,7 +66,11 @@ /* * DDR Setup - manually set all parameters as there's no SPD etc. */ +#ifdef CONFIG_ADS5121_256 #define CFG_DDR_SIZE 256 /* MB */ +#else +#define CFG_DDR_SIZE 512 /* MB */ +#endif #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE @@ -108,14 +118,20 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ - +#ifdef CONFIG_ADS5121_256 #define CFG_MDDRC_SYS_CFG 0xF8604A00 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CFG_MDDRC_TIME_CFG1 0x54EC1168 +#define CFG_MDDRC_TIME_CFG2 0x35210864 +#else +#define CFG_MDDRC_SYS_CFG 0xFA804A00 +#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CFG_MDDRC_TIME_CFG1 0x68EC1168 +#define CFG_MDDRC_TIME_CFG2 0x34310864 +#endif #define CFG_MDDRC_SYS_CFG_EN 0xF0000000 #define CFG_MDDRC_TIME_CFG0 0x00003D2E #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E -#define CFG_MDDRC_TIME_CFG1 0x54EC1168 -#define CFG_MDDRC_TIME_CFG2 0x35210864 #define CFG_MICRON_NOP 0x01380000 #define CFG_MICRON_PCHG_ALL 0x01100400 @@ -175,8 +191,11 @@ #define CFG_SRAM_BASE 0x30000000 #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ - +#ifdef ADS5121_256_CONFIG #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ +#else +#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ +#endif #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ /* Use SRAM for initial stack */ -- 1.5.2.4

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