May 2008 - U-Boot

[U-Boot-Users] Command table relocation
by Chetan Nanda 25 May '08

25 May '08

Hi All, In u-boot code (in board.c file) there is a comment which goes like this: /* * We have to relocate the command table manually */ Why we need to relocate the code for command table separately? Does command table code not linked with rest of the code? And where is the linker script that is being used while linking? Thanks, Chetan Nanda

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[U-Boot-Users] [PATCH 1/2][MIPS] Add asm headers
by Shinya Kuribayashi 25 May '08

25 May '08

These headers are used to probe and utilize CPU informartion. - <asm/cpu-features.h> - <asm/cpu-info.h> - <asm/cpu.h> - <asm/fpu.h> - <asm/hazards.h> Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- include/asm-mips/cpu-features.h | 218 +++++++++++++++++++++++++++++++ include/asm-mips/cpu-info.h | 70 ++++++++++ include/asm-mips/cpu.h | 265 ++++++++++++++++++++++++++++++++++++++ include/asm-mips/fpu.h | 42 ++++++ include/asm-mips/hazards.h | 270 +++++++++++++++++++++++++++++++++++++++ include/asm-mips/mipsregs.h | 1 6 files changed, 866 insertions(+), 0 deletions(-) create mode 100644 include/asm-mips/cpu-features.h create mode 100644 include/asm-mips/cpu-info.h create mode 100644 include/asm-mips/cpu.h create mode 100644 include/asm-mips/fpu.h create mode 100644 include/asm-mips/hazards.h diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h new file mode 100644 index 0000000..618e7a6 --- /dev/null +++ b/include/asm-mips/cpu-features.h @@ -0,0 +1,218 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <asm/cpu.h> +#include <asm/cpu-info.h> + +#ifndef current_cpu_type +#define current_cpu_type() current_cpu_data.cputype +#endif + +/* + * SMP assumption: Options of CPU 0 are a superset of all processors. + * This is true for all known MIPS systems. + */ +#ifndef cpu_has_tlb +#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) +#endif +#ifndef cpu_has_4kex +#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) +#endif +#ifndef cpu_has_3k_cache +#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) +#endif +#define cpu_has_6k_cache 0 +#define cpu_has_8k_cache 0 +#ifndef cpu_has_4k_cache +#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) +#endif +#ifndef cpu_has_tx39_cache +#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) +#endif +#ifndef cpu_has_fpu +#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) +#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) +#else +#define raw_cpu_has_fpu cpu_has_fpu +#endif +#ifndef cpu_has_32fpr +#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) +#endif +#ifndef cpu_has_counter +#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) +#endif +#ifndef cpu_has_watch +#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) +#endif +#ifndef cpu_has_divec +#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) +#endif +#ifndef cpu_has_vce +#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) +#endif +#ifndef cpu_has_cache_cdex_p +#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) +#endif +#ifndef cpu_has_cache_cdex_s +#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) +#endif +#ifndef cpu_has_prefetch +#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) +#endif +#ifndef cpu_has_mcheck +#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) +#endif +#ifndef cpu_has_ejtag +#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) +#endif +#ifndef cpu_has_llsc +#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) +#endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) +#endif +#ifndef cpu_has_mdmx +#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) +#endif +#ifndef cpu_has_mips3d +#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) +#endif +#ifndef cpu_has_smartmips +#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) +#endif +#ifndef cpu_has_vtag_icache +#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) +#endif +#ifndef cpu_has_dc_aliases +#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) +#endif +#ifndef cpu_has_ic_fills_f_dc +#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) +#endif +#ifndef cpu_has_pindexed_dcache +#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) +#endif + +/* + * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors + * such as the R10000 have I-Caches that snoop local stores; the embedded ones + * don't. For maintaining I-cache coherency this means we need to flush the + * D-cache all the way back to whever the I-cache does refills from, so the + * I-cache has a chance to see the new data at all. Then we have to flush the + * I-cache also. + * Note we may have been rescheduled and may no longer be running on the CPU + * that did the store so we can't optimize this into only doing the flush on + * the local CPU. + */ +#ifndef cpu_icache_snoops_remote_store +#ifdef CONFIG_SMP +#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) +#else +#define cpu_icache_snoops_remote_store 1 +#endif +#endif + +# ifndef cpu_has_mips32r1 +# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) +# endif +# ifndef cpu_has_mips32r2 +# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) +# endif +# ifndef cpu_has_mips64r1 +# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) +# endif +# ifndef cpu_has_mips64r2 +# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) +# endif + +/* + * Shortcuts ... + */ +#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) +#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) +#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) +#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) + +#ifndef cpu_has_dsp +#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) +#endif + +#ifndef cpu_has_mipsmt +#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) +#endif + +#ifndef cpu_has_userlocal +#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI) +#endif + +#ifdef CONFIG_32BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_64BIT +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex 0 +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg 1 +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +#elif !defined(cpu_has_vint) +# define cpu_has_vint 0 +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +#elif !defined(cpu_has_veic) +# define cpu_has_veic 0 +#endif + +#ifndef cpu_has_inclusive_pcaches +#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size() cpu_data[0].dcache.linesz +#endif +#ifndef cpu_icache_line_size +#define cpu_icache_line_size() cpu_data[0].icache.linesz +#endif +#ifndef cpu_scache_line_size +#define cpu_scache_line_size() cpu_data[0].scache.linesz +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h new file mode 100644 index 0000000..2437063 --- /dev/null +++ b/include/asm-mips/cpu-info.h @@ -0,0 +1,70 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 Waldorf GMBH + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef __ASM_CPU_INFO_H +#define __ASM_CPU_INFO_H + +/* + * Descriptor for a cache + */ +struct cache_desc { + unsigned int waysize; /* Bytes per way */ + unsigned short sets; /* Number of lines per set */ + unsigned char ways; /* Number of ways */ + unsigned char linesz; /* Size of line in bytes */ + unsigned char waybit; /* Bits to select in a cache set */ + unsigned char flags; /* Flags describing cache properties */ +}; + +/* + * Flag definitions + */ +#define MIPS_CACHE_NOT_PRESENT 0x00000001 +#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */ +#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */ +#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */ +#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */ +#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ + +struct cpuinfo_mips { + unsigned long udelay_val; + unsigned long asid_cache; + + /* + * Capability and feature descriptor structure for MIPS CPU + */ + unsigned long options; + unsigned long ases; + unsigned int processor_id; + unsigned int fpu_id; + unsigned int cputype; + int isa_level; + int tlbsize; + struct cache_desc icache; /* Primary I-cache */ + struct cache_desc dcache; /* Primary D or combined I/D cache */ + struct cache_desc scache; /* Secondary cache */ + struct cache_desc tcache; /* Tertiary/split secondary cache */ + int srsets; /* Shadow register sets */ + int core; /* physical core number */ + void *data; /* Additional data */ +} __attribute__((aligned(1UL << 5))); + +extern struct cpuinfo_mips cpu_data[]; +#define current_cpu_data cpu_data[0] +#define raw_current_cpu_data cpu_data[0] + +extern void cpu_probe(void); +extern void cpu_report(void); + +extern const char *__cpu_name[]; +#define cpu_name_string() __cpu_name[0] + +#endif /* __ASM_CPU_INFO_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h new file mode 100644 index 0000000..58715e8 --- /dev/null +++ b/include/asm-mips/cpu.h @@ -0,0 +1,265 @@ +/* + * cpu.h: Values of the PRId register used to match up + * various MIPS cpu types. + * + * Copyright (C) 1996 David S. Miller (dm(a)engr.sgi.com) + * Copyright (C) 2004 Maciej W. Rozycki + */ +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* + * Assigned Company values for bits 23:16 of the PRId Register + * (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from + * MTI, the PRId register is defined in this (backwards compatible) + * way: + * + * +----------------+----------------+----------------+----------------+ + * | Company Options| Company ID | Processor ID | Revision | + * +----------------+----------------+----------------+----------------+ + * 31 24 23 16 15 8 7 + * + * I don't have docs for all the previous processors, but my impression is + * that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 + * spec. + */ + +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MIPS 0x010000 +#define PRID_COMP_BROADCOM 0x020000 +#define PRID_COMP_ALCHEMY 0x030000 +#define PRID_COMP_SIBYTE 0x040000 +#define PRID_COMP_SANDCRAFT 0x050000 +#define PRID_COMP_NXP 0x060000 +#define PRID_COMP_TOSHIBA 0x070000 +#define PRID_COMP_LSI 0x080000 +#define PRID_COMP_LEXRA 0x0b0000 + +/* + * Assigned values for the product ID register. In order to detect a + * certain CPU type exactly eventually additional registers may need to + * be examined. These are valid when 23:16 == PRID_COMP_LEGACY + */ +#define PRID_IMP_R2000 0x0100 +#define PRID_IMP_AU1_REV1 0x0100 +#define PRID_IMP_AU1_REV2 0x0200 +#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ +#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ +#define PRID_IMP_R4000 0x0400 +#define PRID_IMP_R6000A 0x0600 +#define PRID_IMP_R10000 0x0900 +#define PRID_IMP_R4300 0x0b00 +#define PRID_IMP_VR41XX 0x0c00 +#define PRID_IMP_R12000 0x0e00 +#define PRID_IMP_R14000 0x0f00 +#define PRID_IMP_R8000 0x1000 +#define PRID_IMP_PR4450 0x1200 +#define PRID_IMP_R4600 0x2000 +#define PRID_IMP_R4700 0x2100 +#define PRID_IMP_TX39 0x2200 +#define PRID_IMP_R4640 0x2200 +#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ +#define PRID_IMP_R5000 0x2300 +#define PRID_IMP_TX49 0x2d00 +#define PRID_IMP_SONIC 0x2400 +#define PRID_IMP_MAGIC 0x2500 +#define PRID_IMP_RM7000 0x2700 +#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ +#define PRID_IMP_RM9000 0x3400 +#define PRID_IMP_R5432 0x5400 +#define PRID_IMP_R5500 0x5500 + +#define PRID_IMP_UNKNOWN 0xff00 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_MIPS + */ + +#define PRID_IMP_4KC 0x8000 +#define PRID_IMP_5KC 0x8100 +#define PRID_IMP_20KC 0x8200 +#define PRID_IMP_4KEC 0x8400 +#define PRID_IMP_4KSC 0x8600 +#define PRID_IMP_25KF 0x8800 +#define PRID_IMP_5KE 0x8900 +#define PRID_IMP_4KECR2 0x9000 +#define PRID_IMP_4KEMPR2 0x9100 +#define PRID_IMP_4KSD 0x9200 +#define PRID_IMP_24K 0x9300 +#define PRID_IMP_34K 0x9500 +#define PRID_IMP_24KE 0x9600 +#define PRID_IMP_74K 0x9700 +#define PRID_IMP_1004K 0x9900 +#define PRID_IMP_LOONGSON1 0x4200 +#define PRID_IMP_LOONGSON2 0x6300 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE + */ + +#define PRID_IMP_SB1 0x0100 +#define PRID_IMP_SB1A 0x1100 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT + */ + +#define PRID_IMP_SR71000 0x0400 + +/* + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM + */ + +#define PRID_IMP_BCM4710 0x4000 +#define PRID_IMP_BCM3302 0x9000 + +/* + * Definitions for 7:0 on legacy processors + */ + +#define PRID_REV_MASK 0x00ff + +#define PRID_REV_TX4927 0x0022 +#define PRID_REV_TX4937 0x0030 +#define PRID_REV_R4400 0x0040 +#define PRID_REV_R3000A 0x0030 +#define PRID_REV_R3000 0x0020 +#define PRID_REV_R2000A 0x0010 +#define PRID_REV_TX3912 0x0010 +#define PRID_REV_TX3922 0x0030 +#define PRID_REV_TX3927 0x0040 +#define PRID_REV_VR4111 0x0050 +#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ +#define PRID_REV_VR4121 0x0060 +#define PRID_REV_VR4122 0x0070 +#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ +#define PRID_REV_VR4130 0x0080 +#define PRID_REV_34K_V1_0_2 0x0022 + +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) + +/* + * FPU implementation/revision register (CP1 control register 0). + * + * +---------------------------------+----------------+----------------+ + * | 0 | Implementation | Revision | + * +---------------------------------+----------------+----------------+ + * 31 16 15 8 7 0 + */ + +#define FPIR_IMP_NONE 0x0000 + +enum cpu_type_enum { + CPU_UNKNOWN, + + /* + * R2000 class processors + */ + CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, + CPU_R3081, CPU_R3081E, + + /* + * R6000 class processors + */ + CPU_R6000, CPU_R6000A, + + /* + * R4000 class processors + */ + CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, + CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, + CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432, + CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, + CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, + CPU_SR71000, CPU_RM9000, CPU_TX49XX, + + /* + * R8000 class processors + */ + CPU_R8000, + + /* + * TX3900 class processors + */ + CPU_TX3912, CPU_TX3922, CPU_TX3927, + + /* + * MIPS32 class processors + */ + CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, + CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, + CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + + /* + * MIPS64 class processors + */ + CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, + + CPU_LAST +}; + +/* + * ISA Level encodings + * + */ +#define MIPS_CPU_ISA_I 0x00000001 +#define MIPS_CPU_ISA_II 0x00000002 +#define MIPS_CPU_ISA_III 0x00000004 +#define MIPS_CPU_ISA_IV 0x00000008 +#define MIPS_CPU_ISA_V 0x00000010 +#define MIPS_CPU_ISA_M32R1 0x00000020 +#define MIPS_CPU_ISA_M32R2 0x00000040 +#define MIPS_CPU_ISA_M64R1 0x00000080 +#define MIPS_CPU_ISA_M64R2 0x00000100 + +#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ + MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) +#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ + MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) + +/* + * CPU Option encodings + */ +#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ +#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ +#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ +#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ +#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ +#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */ +#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */ +#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */ +#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */ +#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ +#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ +#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */ +#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */ +#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ + +/* + * CPU ASE encodings + */ +#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ +#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ +#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ +#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ +#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ +#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ + +#endif /* _ASM_CPU_H */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h new file mode 100644 index 0000000..4d8684b --- /dev/null +++ b/include/asm-mips/fpu.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2002 MontaVista Software Inc. + * Author: Jun Sun, jsun(a)mvista.com or jsun(a)junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ASM_FPU_H +#define _ASM_FPU_H + +#include <asm/mipsregs.h> +#include <asm/cpu.h> +#include <asm/cpu-features.h> +#include <asm/hazards.h> + +#define __enable_fpu() \ +do { \ + set_c0_status(ST0_CU1); \ + enable_fpu_hazard(); \ +} while (0) + +#define __disable_fpu() \ +do { \ + clear_c0_status(ST0_CU1); \ + disable_fpu_hazard(); \ +} while (0) + +#define enable_fpu() \ +do { \ + if (cpu_has_fpu) \ + __enable_fpu(); \ +} while (0) + +#define disable_fpu() \ +do { \ + if (cpu_has_fpu) \ + __disable_fpu(); \ +} while (0) + +#endif /* _ASM_FPU_H */ diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h new file mode 100644 index 0000000..7420886 --- /dev/null +++ b/include/asm-mips/hazards.h @@ -0,0 +1,270 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf(a)linux-mips.org> + * Copyright (C) MIPS Technologies, Inc. + * written by Ralf Baechle <ralf(a)linux-mips.org> + */ +#ifndef _ASM_HAZARDS_H +#define _ASM_HAZARDS_H + +#ifdef __ASSEMBLY__ +#define ASMMACRO(name, code...) .macro name; code; .endm +#else + +#include <asm/cpu-features.h> + +#define ASMMACRO(name, code...) \ +__asm__(".macro " #name "; " #code "; .endm"); \ + \ +static inline void name(void) \ +{ \ + __asm__ __volatile__ (#name); \ +} + +/* + * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine. + */ +extern void mips_ihb(void); + +#endif + +ASMMACRO(_ssnop, + sll $0, $0, 1 + ) + +ASMMACRO(_ehb, + sll $0, $0, 3 + ) + +/* + * TLB hazards + */ +#if defined(CONFIG_CPU_MIPSR2) + +/* + * MIPSR2 defines ehb for hazard avoidance + */ + +ASMMACRO(mtc0_tlbw_hazard, + _ehb + ) +ASMMACRO(tlbw_use_hazard, + _ehb + ) +ASMMACRO(tlb_probe_hazard, + _ehb + ) +ASMMACRO(irq_enable_hazard, + _ehb + ) +ASMMACRO(irq_disable_hazard, + _ehb + ) +ASMMACRO(back_to_back_c0_hazard, + _ehb + ) +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ + __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) + +#elif defined(CONFIG_CPU_MIPSR1) + +/* + * These are slightly complicated by the fact that we guarantee R1 kernels to + * run fine on R2 processors. + */ +ASMMACRO(mtc0_tlbw_hazard, + _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlbw_use_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(tlb_probe_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(irq_disable_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +ASMMACRO(back_to_back_c0_hazard, + _ssnop; _ssnop; _ssnop; _ehb + ) +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ +#define __instruction_hazard() \ +do { \ + unsigned long tmp; \ + \ + __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ + " jr.hb %0 \n" \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ +} while (0) + +#define instruction_hazard() \ +do { \ + if (cpu_has_mips_r2) \ + __instruction_hazard(); \ +} while (0) + +#elif defined(CONFIG_CPU_R10000) + +/* + * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. + */ + +ASMMACRO(mtc0_tlbw_hazard, + ) +ASMMACRO(tlbw_use_hazard, + ) +ASMMACRO(tlb_probe_hazard, + ) +ASMMACRO(irq_enable_hazard, + ) +ASMMACRO(irq_disable_hazard, + ) +ASMMACRO(back_to_back_c0_hazard, + ) +#define instruction_hazard() do { } while (0) + +#elif defined(CONFIG_CPU_RM9000) + +/* + * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent + * use of the JTLB for instructions should not occur for 4 cpu cycles and use + * for data translations should not occur for 3 cpu cycles. + */ + +ASMMACRO(mtc0_tlbw_hazard, + _ssnop; _ssnop; _ssnop; _ssnop + ) +ASMMACRO(tlbw_use_hazard, + _ssnop; _ssnop; _ssnop; _ssnop + ) +ASMMACRO(tlb_probe_hazard, + _ssnop; _ssnop; _ssnop; _ssnop + ) +ASMMACRO(irq_enable_hazard, + ) +ASMMACRO(irq_disable_hazard, + ) +ASMMACRO(back_to_back_c0_hazard, + ) +#define instruction_hazard() do { } while (0) + +#elif defined(CONFIG_CPU_SB1) + +/* + * Mostly like R4000 for historic reasons + */ +ASMMACRO(mtc0_tlbw_hazard, + ) +ASMMACRO(tlbw_use_hazard, + ) +ASMMACRO(tlb_probe_hazard, + ) +ASMMACRO(irq_enable_hazard, + ) +ASMMACRO(irq_disable_hazard, + _ssnop; _ssnop; _ssnop + ) +ASMMACRO(back_to_back_c0_hazard, + ) +#define instruction_hazard() do { } while (0) + +#else + +/* + * Finally the catchall case for all other processors including R4000, R4400, + * R4600, R4700, R5000, RM7000, NEC VR41xx etc. + * + * The taken branch will result in a two cycle penalty for the two killed + * instructions on R4000 / R4400. Other processors only have a single cycle + * hazard so this is nice trick to have an optimal code for a range of + * processors. + */ +ASMMACRO(mtc0_tlbw_hazard, + nop; nop + ) +ASMMACRO(tlbw_use_hazard, + nop; nop; nop + ) +ASMMACRO(tlb_probe_hazard, + nop; nop; nop + ) +ASMMACRO(irq_enable_hazard, + _ssnop; _ssnop; _ssnop; + ) +ASMMACRO(irq_disable_hazard, + nop; nop; nop + ) +ASMMACRO(back_to_back_c0_hazard, + _ssnop; _ssnop; _ssnop; + ) +#define instruction_hazard() do { } while (0) + +#endif + +/* FPU hazards */ + +#if defined(CONFIG_CPU_SB1) +ASMMACRO(enable_fpu_hazard, + .set push; + .set mips64; + .set noreorder; + _ssnop; + bnezl $0, .+4; + _ssnop; + .set pop +) +ASMMACRO(disable_fpu_hazard, +) + +#elif defined(CONFIG_CPU_MIPSR2) +ASMMACRO(enable_fpu_hazard, + _ehb +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#else +ASMMACRO(enable_fpu_hazard, + nop; nop; nop; nop +) +ASMMACRO(disable_fpu_hazard, + _ehb +) +#endif + +#endif /* _ASM_HAZARDS_H */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index be7e5c6..384d2c0 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -16,6 +16,7 @@ #if 0 #include <linux/linkage.h> #endif +#include <asm/hazards.h> /* * The following macros are especially useful for __asm__

2 6

[U-Boot-Users] [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines
by Shinya Kuribayashi 24 May '08

24 May '08

Also get rid of some #ifdefs in *.c files. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/Makefile | 15 +++++++++------ cpu/mips/asc_serial.c | 3 --- cpu/mips/au1x00_eth.c | 4 ---- cpu/mips/au1x00_serial.c | 4 ---- cpu/mips/au1x00_usb_ohci.c | 2 +- 5 files changed, 10 insertions(+), 18 deletions(-) diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 29dd941..69cc16a 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -25,13 +25,16 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o -COBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ - cpu.o cpu-probe.o interrupts.o incaip_clock.o -SOBJS = incaip_wdt.o cache.o +SOBJS-y = cache.o +COBJS-y = cpu.o cpu-probe.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o +COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o +COBJS-$(CONFIG_PURPLE) += asc_serial.o +COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c index 3498b61..be686c2 100644 --- a/cpu/mips/asc_serial.c +++ b/cpu/mips/asc_serial.c @@ -4,8 +4,6 @@ #include <config.h> -#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) - #ifdef CONFIG_PURPLE #define serial_init asc_serial_init #define serial_putc asc_serial_putc @@ -368,4 +366,3 @@ int serial_tstc (void) return res; } -#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index aeb9662..d0cf8e0 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,8 +23,6 @@ */ #include <config.h> -#ifdef CONFIG_SOC_AU1X00 - #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" /* We just assume that we are running 100FD for now */ @@ -307,5 +305,3 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } - -#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index ec10ac0..6309794 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -26,9 +26,6 @@ */ #include <config.h> - -#ifdef CONFIG_SOC_AU1X00 - #include <common.h> #include <asm/au1x00.h> @@ -132,4 +129,3 @@ int serial_tstc (void) } return 0; } -#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index e03b125..1ca8aaf 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include <config.h> -#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI) +#ifdef CONFIG_USB_OHCI /* #include <pci.h> no PCI on the AU1x00 */

1 0

[U-Boot-Users] [MIPS] Rename Alchemy processor configs into CONFIGO_SOC_*
by Shinya Kuribayashi 24 May '08

24 May '08

CONFIG_SOC_AU1X00 Common Alchemy Au1x00 stuff. All Alchemy processor based machines need to have this config as a system type specifier. CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 Machine type specifiers. Each port should have one of aboves. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/au1x00_eth.c | 12 ++++++------ cpu/mips/au1x00_serial.c | 4 ++-- cpu/mips/au1x00_usb_ohci.c | 2 +- include/asm-mips/addrspace.h | 6 +++--- include/asm-mips/au1x00.h | 6 +++--- include/configs/dbau1x00.h | 10 +++++----- include/configs/gth2.h | 4 ++-- include/configs/pb1x00.h | 8 ++++---- 8 files changed, 26 insertions(+), 26 deletions(-) diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d70c5fe..aeb9662 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,7 +23,7 @@ */ #include <config.h> -#ifdef CONFIG_AU1X00 +#ifdef CONFIG_SOC_AU1X00 #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" @@ -33,20 +33,20 @@ /* I assume ethernet behaves like au1000 */ -#ifdef CONFIG_AU1000 +#ifdef CONFIG_SOC_AU1000 /* Base address differ between cpu:s */ #define ETH0_BASE AU1000_ETH0_BASE #define MAC0_ENABLE AU1000_MAC0_ENABLE #else -#ifdef CONFIG_AU1100 +#ifdef CONFIG_SOC_AU1100 #define ETH0_BASE AU1100_ETH0_BASE #define MAC0_ENABLE AU1100_MAC0_ENABLE #else -#ifdef CONFIG_AU1500 +#ifdef CONFIG_SOC_AU1500 #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define ETH0_BASE AU1550_ETH0_BASE #define MAC0_ENABLE AU1550_MAC0_ENABLE #else @@ -308,4 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } -#endif /* CONFIG_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index 42c668e..ec10ac0 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -27,7 +27,7 @@ #include <config.h> -#ifdef CONFIG_AU1X00 +#ifdef CONFIG_SOC_AU1X00 #include <common.h> #include <asm/au1x00.h> @@ -132,4 +132,4 @@ int serial_tstc (void) } return 0; } -#endif /* CONFIG_SERIAL_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index dbf72dc..e03b125 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include <config.h> -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) +#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI) /* #include <pci.h> no PCI on the AU1x00 */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 767804c..3a1e6d6 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -131,13 +131,13 @@ * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) +#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_AU1X00 */ +#else /* !CONFIG_SOC_AU1X00 */ #define UNCACHED_SDRAM(a) KSEG1ADDR(a) -#endif /* CONFIG_AU1X00 */ +#endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ /* diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h index 6a33197..2a948e8 100644 --- a/include/asm-mips/au1x00.h +++ b/include/asm-mips/au1x00.h @@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x) #define CP0_DEBUG $23 /* SDRAM Controller */ -#ifdef CONFIG_AU1550 +#ifdef CONFIG_SOC_AU1550 #define MEM_SDMODE0 0xB4000800 #define MEM_SDMODE1 0xB4000808 @@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000888 #define MEM_SDWRMD2 0xB4000890 -#else /* CONFIG_AU1550 */ +#else /* CONFIG_SOC_AU1550 */ #define MEM_SDMODE0 0xB4000000 #define MEM_SDMODE1 0xB4000004 @@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000028 #define MEM_SDWRMD2 0xB400002C -#endif /* CONFIG_AU1550 */ +#endif /* CONFIG_SOC_AU1550 */ #define MEM_SDSLEEP 0xB4000030 #define MEM_SDSMCKE 0xB4000034 diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index ddb98ac..d039e7a 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -30,21 +30,21 @@ #define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #ifdef CONFIG_DBAU1550 /* Cabernet */ -#define CONFIG_AU1550 1 +#define CONFIG_SOC_AU1550 1 #else #error "No valid board set" #endif diff --git a/include/configs/gth2.h b/include/configs/gth2.h index 50487fa..a0e8481 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -30,9 +30,9 @@ #define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_GTH2 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #define CONFIG_MISC_INIT_R 1 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 899959a..842ec6a 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -30,16 +30,16 @@ #define CONFIG_CPU_MIPS32_R1 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 -#define CONFIG_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_PB1000 -#define CONFIG_AU1000 1 +#define CONFIG_SOC_AU1000 1 #else #ifdef CONFIG_PB1100 -#define CONFIG_AU1100 1 +#define CONFIG_SOC_AU1100 1 #else #ifdef CONFIG_PB1500 -#define CONFIG_AU1500 1 +#define CONFIG_SOC_AU1500 1 #else #error "No valid board set" #endif

1 0

[U-Boot-Users] [MIPS] mips_config.mk: Misc fixes
by Shinya Kuribayashi 24 May '08

24 May '08

- Kill redundant `-pipe' (this will be added by $(TOPDIR)/config.mk) - Modify comments Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- mips_config.mk | 7 +++---- 1 files changed, 3 insertions(+), 4 deletions(-) diff --git a/mips_config.mk b/mips_config.mk index 67fb67d..05eb05d 100644 --- a/mips_config.mk +++ b/mips_config.mk @@ -40,10 +40,9 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # LDFLAGS_vmlinux += -G 0 -static -n -nostdlib # MODFLAGS += -mlong-calls # - -# -# Meanwhile, U-Boot rely on PIC. We add proper switches explicitly. +# On the other hand, we want PIC in the U-Boot code to relocate it from ROM +# to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic -pipe +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib

1 0

[U-Boot-Users] [MIPS] Kill unused <version.h> inclusions
by Shinya Kuribayashi 24 May '08

24 May '08

Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/dbau1x00/lowlevel_init.S | 1 - board/gth2/lowlevel_init.S | 1 - board/incaip/lowlevel_init.S | 1 - board/pb1x00/lowlevel_init.S | 1 - board/purple/lowlevel_init.S | 1 - board/qemu-mips/lowlevel_init.S | 1 - board/tb0229/lowlevel_init.S | 1 - cpu/mips/cache.S | 1 - cpu/mips/incaip_wdt.S | 1 - cpu/mips/start.S | 1 - 10 files changed, 0 insertions(+), 10 deletions(-) diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 27b51f7..13e6bfc 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index bf615c1..4c4f0eb 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index 08f7f21..fe525ec 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index 98bb394..b145e43 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S index b9d03fc..1bd3edb 100644 --- a/board/purple/lowlevel_init.S +++ b/board/purple/lowlevel_init.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #define MC_IOGP 0xBF800800 diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S index 836e027..b0f7072 100644 --- a/board/qemu-mips/lowlevel_init.S +++ b/board/qemu-mips/lowlevel_init.S @@ -1,7 +1,6 @@ /* Memory sub-system initialization code */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h> diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S index df31806..5fce856 100644 --- a/board/tb0229/lowlevel_init.S +++ b/board/tb0229/lowlevel_init.S @@ -10,7 +10,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 1b0efc3..7966079 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/asm.h> #include <asm/regdef.h> #include <asm/mipsregs.h> diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 329386b..3ade3cd 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -24,7 +24,6 @@ #include <config.h> -#include <version.h> #include <asm/regdef.h> diff --git a/cpu/mips/start.S b/cpu/mips/start.S index d881879..09e4aab 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -23,7 +23,6 @@ */ #include <config.h> -#include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h>

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[U-Boot-Users] [PATCH v2 ARM/AT91 0/26] AT91SAM/CAP patches for U-Boot 1.3.4
by Stelian Pop 24 May '08

24 May '08

Hi, This is the second version of the AT91CAP9/AT91SAM9 patches, which hopefully addresses all the feedbacks I got on the first one. The first patches: 01 to 04 fix the copyright notices of some already merged files. Those patches may be merged immediately since it would be good to have those in 1.3.3-final. The patches 05 to 13 fix a number of things in the AT91CAP9 and AT91SAM9260 ports (NAND 8/16 bit support, dataflash offsets, SPI timings, consistent Linux bootargs). The patches 14 to 17 add support for some new Atmel boards: - AT91SAM9261 - AT91SAM9263 - AT91SAM9RL The patches 18 to 25 add a driver for the LCD controller on the Atmel boards (except 9260). The driver could probably be adapted, with minimum efforts, to the AVR32 boards. And finally, the last patch adds support for the revision 'C' of the AT91CAP9 silicon, which needs a special initialisation sequence to switch from the internal RC oscillator to the external 32k clock. Thanks, Stelian.

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Re: [U-Boot-Users] RapidIO on custom board (MPC8548 )
by Adam Nowak 24 May '08

24 May '08

Thanks John. I should explain that I have only MPC8548 on the board. Other elements with access via RapidIO will be on another board which is not connected now. I guess that the common transport size does not matter in this case because we do not have any communication. Should I assume that the most probable reason of hung up i the mapping of memory? The kernel hung up in function in_be32(regs_win + RIO_CCSR). This is access to configuration register. Thanks, Adam On Mon, 2008-05-19 at 09:22 +0100, John Traill wrote: > Adam, > > Make sure you have matching common transport sizes in your system - Section 4.4.3.16 RapidIO System Size in the 8548 manual. >

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[U-Boot-Users] [Patch 00/17] U-Boot-V2: Support for OMAP3 and SDP3430
by Menon, Nishanth 24 May '08

24 May '08

Greetings, This patch series introduces support required for OMAP Boards and an example of OMAP3430 based SDP3430 platform is introduced for U-Boot V2. This series of patches provide a very basic SRAM boot support. The u-boot.bin file generated is around 28K in size and may be delivered as part of Peripheral boot process as described in OMAP3430 TRM[1] page 3728 section 26.4.5. I have used SRAM for this configuration and heap and stack are in SDRAM in this example. SDP3430 details can be seen in [2]. Please note that there is further work required for this to be completely useful. Probably requires M18 CFI support, NAND 16/8 bit support, MMC(and FAT), OneNAND support and USBTTY support to be fully functional and useful. Other platforms that may possibly leverage out of these are: a) OMAP3430 based Zoom MDK [3] b) OMAP3530 based beagle board [4] c) OMAP353x based EVM [5] d) Pandora [6] And others that I don't know of :). Please feel free to add.. And ofcourse, we could move all old OMAPs based platforms across also.. I thank Dirk for guiding me on creation of patches, Laurent for pointing out the dcache issue in my first rev and lots of folks for writing the initial code. Regards, Nishanth Menon Ref: ---- [1] http://focus.ti.com/pdfs/wtbu/swpu114g.pdf [2] http://www.ti.com/omap3430_devplatform [3] http://www.omapzoom.org/ [4] http://beagleboard.org/ [5] http://www.mistralsolutions.com/business_divisons/omap_3evm.php [6] http://openpandora.org/

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[U-Boot-Users] [PATCH] Add Marvell 88E1118 support for TSEC
by Ron Madrid 24 May '08

24 May '08

Add Marvell 88E1118 support for TSEC Signed-off-by: Ron Madrid <ron_madrid(a)sbcglobal.net> --- drivers/net/tsec.c | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index c7af930..397ae71 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -1128,6 +1128,36 @@ struct phy_info phy_info_M88E1111S = { }, }; +struct phy_info phy_info_M88E1118 = { + 0x01410e1, + "Marvell 88E1118", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x16, 0x0002, NULL}, /* Change Page Number */ + {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */ + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + {0x16, 0x0000, NULL}, /* Change Page Number */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv) { uint mii_data = read_phy_reg(priv, mii_reg); @@ -1492,6 +1522,7 @@ struct phy_info *phy_info[] = { &phy_info_BCM5464S, &phy_info_M88E1011S, &phy_info_M88E1111S, + &phy_info_M88E1118, &phy_info_M88E1145, &phy_info_M88E1149S, &phy_info_dm9161, -- 1.5.5.1

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