April 2008 - U-Boot

[U-Boot-Users] AT91SAM9260 + DP83848 phy
by Dave Bender 29 Apr '08

29 Apr '08

Dear list, I am currently working on a custom board, trying to get the National DP83848 Phy to work properly with the AT91SAM9260 in u-boot 1.2.0; Everything goes fine (reset is ok, can read phy id) until I read the link status bit. The link status bit is never set, so I never get a good connection. I have tried the following: -Bit banged the MDIO directly to the via the parallel port as per National's suggestion. The link status bit went high in this case, so I do not believe there are any wiring faults in our board. Does anybody know of a u-boot driver for the phy with the AT91SAM9260? Has anyone had any success with this combination? Thanks, Dave

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[U-Boot-Users] [PATCH] 85xx/86xx: Rename DDR init address and init extended address register
by Kumar Gala 29 Apr '08

29 Apr '08

Rename init_addr and init_ext_addr to match the docs between 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Can you guys ack and decide who will actually apply this. - k include/asm-ppc/immap_85xx.h | 4 ++-- include/asm-ppc/immap_86xx.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 813be5f..2d07625 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -106,8 +106,8 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_address; /* 0x2148 - DDR training initialization address */ - uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + uint init_addr; /* 0x2148 - DDR training initialization address */ + uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ char res8_1[16]; uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index fd4aa54..0b78c94 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -126,7 +126,7 @@ typedef struct ccsr_ddr { uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_addr_ext; /* 0x214C - DDR training initialzation extended address */ + uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ char res10[2728]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ -- 1.5.4.1

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[U-Boot-Users] [PATCH] 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
by Kumar Gala 29 Apr '08

29 Apr '08

All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Can you guys ack and decide who will actually apply this. - k board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/sbc8548/sbc8548.c | 2 +- board/sbc8641d/sbc8641d.c | 4 ++-- cpu/mpc85xx/spd_sdram.c | 4 ++-- cpu/mpc86xx/spd_sdram.c | 4 ++-- include/asm-ppc/immap_85xx.h | 2 +- include/asm-ppc/immap_86xx.h | 2 +- include/configs/MPC8610HPCD.h | 2 +- include/configs/sbc8641d.h | 2 +- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index d9a740e..3a855b5 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -192,7 +192,7 @@ long int fixed_sdram(void) ddr->cs0_bnds = 0x0000001f; ddr->cs0_config = 0x80010202; - ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 31e7d67..bb1f927 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -130,7 +130,7 @@ fixed_sdram(void) ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8a6ced3..46496da 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -299,7 +299,7 @@ long int fixed_sdram (void) ddr->cs1_config = 0x80010101; ddr->cs2_config = 0x00000000; ddr->cs3_config = 0x00000000; - ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_3 = 0x00000000; ddr->timing_cfg_0 = 0x00220802; ddr->timing_cfg_1 = 0x38377322; ddr->timing_cfg_2 = 0x0fa044C7; diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index b3dd9c8..519f332 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -135,7 +135,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR_CS1_CONFIG; ddr->cs2_config = CFG_DDR_CS2_CONFIG; ddr->cs3_config = CFG_DDR_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR_TIMING_3; ddr->timing_cfg_0 = CFG_DDR_TIMING_0; ddr->timing_cfg_1 = CFG_DDR_TIMING_1; ddr->timing_cfg_2 = CFG_DDR_TIMING_2; @@ -166,7 +166,7 @@ long int fixed_sdram (void) ddr->cs1_config = CFG_DDR2_CS1_CONFIG; ddr->cs2_config = CFG_DDR2_CS2_CONFIG; ddr->cs3_config = CFG_DDR2_CS3_CONFIG; - ddr->ext_refrec = CFG_DDR2_EXT_REFRESH; + ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH; ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 435458a..e3a8249 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -610,8 +610,8 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); ddr->timing_cfg_1 = (0 diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 60a7818..8485841 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, /* * Sneak in some Extended Refresh Recovery. */ - ddr->ext_refrec = (trfc_high << 16); - debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); + ddr->timing_cfg_3 = (trfc_high << 16); + debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); ddr->timing_cfg_1 = (0 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index dc6e278..813be5f 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -92,7 +92,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061..fd4aa54 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -109,7 +109,7 @@ typedef struct ccsr_ddr { uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 9e70198..585411c 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -114,7 +114,7 @@ #if 0 /* TODO */ #define CFG_DDR_CS0_BNDS 0x0000000F #define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ -#define CFG_DDR_EXT_REFRESH 0x00000000 +#define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00260802 #define CFG_DDR_TIMING_1 0x3935d322 #define CFG_DDR_TIMING_2 0x14904cc8 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 18cedff..20da73e 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -136,7 +136,7 @@ #define CFG_DDR_CS1_CONFIG 0x00000000 #define CFG_DDR_CS2_CONFIG 0x00000000 #define CFG_DDR_CS3_CONFIG 0x00000000 - #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 0x00220802 #define CFG_DDR_TIMING_1 0x38377322 #define CFG_DDR_TIMING_2 0x002040c7 -- 1.5.4.1

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[U-Boot-Users] Please pull u-boot-mpc85xx.git
by Andy Fleming 29 Apr '08

29 Apr '08

are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master Kumar Gala (1): 85xx: Additional fixes and cleanup of MP code cpu/mpc85xx/mp.c | 6 +++++- cpu/mpc85xx/release.S | 3 ++- 2 files changed, 7 insertions(+), 2 deletions(-)

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[U-Boot-Users] [PATCH] ppc flush_cache: add watch-dog triggering into the loops.
by Wolfgang Denk 29 Apr '08

29 Apr '08

From: Yuri Tikhonov <yur(a)emcraft.com> Some boards (e.g. lwmon5) need rather a frequent watch-dog kicking. Since the time it takes for the flush_cache() function to complete its job depends on the size of data being flushed, one may encounter watch-dog resets on such boards when, for example, download big files over ethernet. Signed-off-by: Yuri Tikhonov <yur(a)emcraft.com> --- lib_ppc/cache.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index 27e1a82..5bfb220 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -23,6 +23,7 @@ #include <common.h> #include <asm/cache.h> +#include <watchdog.h> void flush_cache (ulong start_addr, ulong size) { @@ -35,6 +36,7 @@ void flush_cache (ulong start_addr, ulong size) addr < end_addr; addr += CFG_CACHELINE_SIZE) { asm ("dcbst 0,%0": :"r" (addr)); + WATCHDOG_RESET(); } asm ("sync"); /* Wait for all dcbst to complete on bus */ @@ -42,6 +44,7 @@ void flush_cache (ulong start_addr, ulong size) addr < end_addr; addr += CFG_CACHELINE_SIZE) { asm ("icbi 0,%0": :"r" (addr)); + WATCHDOG_RESET(); } } asm ("sync"); /* Always flush prefetch queue in any case */ -- 1.5.4.2

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[U-Boot-Users] [PATCH] ppc4xx: Fix Katmai CFG_MONITOR_LEN
by Stefan Roese 29 Apr '08

29 Apr '08

Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/katmai.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 122b700..aad28fb 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -48,7 +48,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -- 1.5.5.1

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[U-Boot-Users] Status of the Yaffs patches?
by Stuart Wood 29 Apr '08

29 Apr '08

Hi All, Can anyone give me an update on the status of integrating YAFFS binary image reading and writing into U-Boot? -- Stuart Wood Lab X Technologies, LLC

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[U-Boot-Users] Top 10 ways on how to increase sex drive
by Ihle 29 Apr '08

29 Apr '08

Your girlfriend will thank you for taking our new herbal drugs http://www.delpot.com/

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[U-Boot-Users] [PATCH] ppc4xx: Completely remove bogus dflush()
by Stefan Roese 29 Apr '08

29 Apr '08

Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/netstal/hcu5/sdram.c | 6 +++--- cpu/ppc4xx/44x_spd_ddr2.c | 5 +++-- cpu/ppc4xx/denali_spd_ddr2.c | 4 ++-- cpu/ppc4xx/start.S | 29 ----------------------------- 4 files changed, 8 insertions(+), 36 deletions(-) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0b16b50..6b1b53a 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -34,11 +34,11 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <ppc440.h> void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); #define DDR_DCR_BASE 0x10 #define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ @@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) #endif sync(); - eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 9e722b9..5b5de48 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -40,6 +40,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ @@ -237,7 +238,6 @@ static void DQS_calibration_process(void); static void ppc440sp_sdram_register_dump(void); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); static u32 mfdcr_any(u32 dcr) { @@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address, } else { /* ECC bit set method for cached memory */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); } blank_string(strlen(str)); diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index e20c9eb..acf0f49 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -92,7 +92,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); /* * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed @@ -1201,7 +1200,8 @@ long int initdram(int board_type) #else #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file #endif - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CFG_SDRAM_BASE, dram_size); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8d2777d..a513b45 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1675,35 +1675,6 @@ trap_reloc: sync blr function_epilog(dcbz_area) - -/*----------------------------------------------------------------------------+ -| dflush. Assume 32K at vector address is cachable. -+----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - mfspr r8,dvlim - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 -..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - mtspr dvlim,r8 - sync - mtmsr r9 - blr - function_epilog(dflush) #endif /* CONFIG_440 */ #endif /* CONFIG_NAND_SPL */ -- 1.5.5.1

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[U-Boot-Users] [PATCH] ppc4xx: Change ECC initialization on lwmon5 to use clean_dcache_range()
by Stefan Roese 29 Apr '08

29 Apr '08

As it seems the "old" ECC initialization routine by using dflush() didn't write all lines in the dcache back to memory on lwmon5. This could lead to ECC error upon Linux booting. This patch changes the program_ecc() routine to now use clean_dcache_range() instead of dflush(). clean_dcache_range() uses dcbst which is exactly what we want in this case. Since dflush() is known is cause problems, this routine will be removed completely and replaced by clean_dcache_range() with an additional patch. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/lwmon5/sdram.c | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 7c3cf49..36b5100 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -34,6 +34,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/io.h> +#include <asm/cache.h> #include <ppc440.h> #include <watchdog.h> @@ -59,7 +60,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); static u32 is_ecc_enabled(void) { @@ -106,6 +106,7 @@ static void program_ecc(u32 start_address, { u32 val; u32 current_addr = start_address; + u32 size; int bytes_remaining; sync(); @@ -123,12 +124,18 @@ static void program_ecc(u32 start_address, * watchdog. */ while (bytes_remaining > 0) { - dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + size = min((64 << 20), bytes_remaining); + + /* Write zero's to SDRAM */ + dcbz_area(current_addr, size); + + /* Write modified dcache lines back to memory */ + clean_dcache_range(current_addr, current_addr + size); + current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } - dflush(); sync(); wait_ddr_idle(); -- 1.5.5.1

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