April 2008 - U-Boot

[U-Boot-Users] [PATCH v2 4/7] add SMSC LAN9x1x Network driver
by Guennadi Liakhovetski 14 Apr '08

14 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds a driver for the following smsc network controllers: LAN9115 LAN9116 LAN9117 LAN9215 LAN9216 LAN9217 Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: Removed C++ style comments drivers/net/Makefile | 1 + drivers/net/smc911x.c | 668 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 669 insertions(+), 0 deletions(-) create mode 100644 drivers/net/smc911x.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 320dc3e..9482398 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -54,6 +54,7 @@ COBJS-y += rtl8139.o COBJS-y += rtl8169.o COBJS-y += s3c4510b_eth.o COBJS-y += smc91111.o +COBJS-y += smc911x.o COBJS-y += tigon3.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c new file mode 100644 index 0000000..5830368 --- /dev/null +++ b/drivers/net/smc911x.c @@ -0,0 +1,667 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_DRIVER_SMC911X + +#include <command.h> +#include <net.h> +#include <miiphy.h> + +#define mdelay(n) udelay((n)*1000) + +#define __REG(x) (*((volatile u32 *)(x))) + +/* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +#define RX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x00) + +#define TX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x20) +#define TX_CMD_A_INT_ON_COMP (0x80000000) +#define TX_CMD_A_INT_BUF_END_ALGN (0x03000000) +#define TX_CMD_A_INT_4_BYTE_ALGN (0x00000000) +#define TX_CMD_A_INT_16_BYTE_ALGN (0x01000000) +#define TX_CMD_A_INT_32_BYTE_ALGN (0x02000000) +#define TX_CMD_A_INT_DATA_OFFSET (0x001F0000) +#define TX_CMD_A_INT_FIRST_SEG (0x00002000) +#define TX_CMD_A_INT_LAST_SEG (0x00001000) +#define TX_CMD_A_BUF_SIZE (0x000007FF) +#define TX_CMD_B_PKT_TAG (0xFFFF0000) +#define TX_CMD_B_ADD_CRC_DISABLE (0x00002000) +#define TX_CMD_B_DISABLE_PADDING (0x00001000) +#define TX_CMD_B_PKT_BYTE_LENGTH (0x000007FF) + +#define RX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x40) +#define RX_STS_PKT_LEN (0x3FFF0000) +#define RX_STS_ES (0x00008000) +#define RX_STS_BCST (0x00002000) +#define RX_STS_LEN_ERR (0x00001000) +#define RX_STS_RUNT_ERR (0x00000800) +#define RX_STS_MCAST (0x00000400) +#define RX_STS_TOO_LONG (0x00000080) +#define RX_STS_COLL (0x00000040) +#define RX_STS_ETH_TYPE (0x00000020) +#define RX_STS_WDOG_TMT (0x00000010) +#define RX_STS_MII_ERR (0x00000008) +#define RX_STS_DRIBBLING (0x00000004) +#define RX_STS_CRC_ERR (0x00000002) +#define RX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x44) +#define TX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x48) +#define TX_STS_TAG (0xFFFF0000) +#define TX_STS_ES (0x00008000) +#define TX_STS_LOC (0x00000800) +#define TX_STS_NO_CARR (0x00000400) +#define TX_STS_LATE_COLL (0x00000200) +#define TX_STS_MANY_COLL (0x00000100) +#define TX_STS_COLL_CNT (0x00000078) +#define TX_STS_MANY_DEFER (0x00000004) +#define TX_STS_UNDERRUN (0x00000002) +#define TX_STS_DEFERRED (0x00000001) +#define TX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x4C) +#define ID_REV __REG(CONFIG_DRIVER_SMC911X_BASE + 0x50) +#define ID_REV_CHIP_ID (0xFFFF0000) /* RO */ +#define ID_REV_REV_ID (0x0000FFFF) /* RO */ + +#define INT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x54) +#define INT_CFG_INT_DEAS (0xFF000000) /* R/W */ +#define INT_CFG_INT_DEAS_CLR (0x00004000) +#define INT_CFG_INT_DEAS_STS (0x00002000) +#define INT_CFG_IRQ_INT (0x00001000) /* RO */ +#define INT_CFG_IRQ_EN (0x00000100) /* R/W */ +#define INT_CFG_IRQ_POL (0x00000010) /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_TYPE (0x00000001) /* R/W Not Affected by SW Reset */ + +#define INT_STS __REG(CONFIG_DRIVER_SMC911X_BASE + 0x58) +#define INT_STS_SW_INT (0x80000000) /* R/WC */ +#define INT_STS_TXSTOP_INT (0x02000000) /* R/WC */ +#define INT_STS_RXSTOP_INT (0x01000000) /* R/WC */ +#define INT_STS_RXDFH_INT (0x00800000) /* R/WC */ +#define INT_STS_RXDF_INT (0x00400000) /* R/WC */ +#define INT_STS_TX_IOC (0x00200000) /* R/WC */ +#define INT_STS_RXD_INT (0x00100000) /* R/WC */ +#define INT_STS_GPT_INT (0x00080000) /* R/WC */ +#define INT_STS_PHY_INT (0x00040000) /* RO */ +#define INT_STS_PME_INT (0x00020000) /* R/WC */ +#define INT_STS_TXSO (0x00010000) /* R/WC */ +#define INT_STS_RWT (0x00008000) /* R/WC */ +#define INT_STS_RXE (0x00004000) /* R/WC */ +#define INT_STS_TXE (0x00002000) /* R/WC */ +/*#define INT_STS_ERX (0x00001000)*/ /* R/WC */ +#define INT_STS_TDFU (0x00000800) /* R/WC */ +#define INT_STS_TDFO (0x00000400) /* R/WC */ +#define INT_STS_TDFA (0x00000200) /* R/WC */ +#define INT_STS_TSFF (0x00000100) /* R/WC */ +#define INT_STS_TSFL (0x00000080) /* R/WC */ +/*#define INT_STS_RXDF (0x00000040)*/ /* R/WC */ +#define INT_STS_RDFO (0x00000040) /* R/WC */ +#define INT_STS_RDFL (0x00000020) /* R/WC */ +#define INT_STS_RSFF (0x00000010) /* R/WC */ +#define INT_STS_RSFL (0x00000008) /* R/WC */ +#define INT_STS_GPIO2_INT (0x00000004) /* R/WC */ +#define INT_STS_GPIO1_INT (0x00000002) /* R/WC */ +#define INT_STS_GPIO0_INT (0x00000001) /* R/WC */ +#define INT_EN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x5C) +#define INT_EN_SW_INT_EN (0x80000000) /* R/W */ +#define INT_EN_TXSTOP_INT_EN (0x02000000) /* R/W */ +#define INT_EN_RXSTOP_INT_EN (0x01000000) /* R/W */ +#define INT_EN_RXDFH_INT_EN (0x00800000) /* R/W */ +/*#define INT_EN_RXDF_INT_EN (0x00400000)*/ /* R/W */ +#define INT_EN_TIOC_INT_EN (0x00200000) /* R/W */ +#define INT_EN_RXD_INT_EN (0x00100000) /* R/W */ +#define INT_EN_GPT_INT_EN (0x00080000) /* R/W */ +#define INT_EN_PHY_INT_EN (0x00040000) /* R/W */ +#define INT_EN_PME_INT_EN (0x00020000) /* R/W */ +#define INT_EN_TXSO_EN (0x00010000) /* R/W */ +#define INT_EN_RWT_EN (0x00008000) /* R/W */ +#define INT_EN_RXE_EN (0x00004000) /* R/W */ +#define INT_EN_TXE_EN (0x00002000) /* R/W */ +/*#define INT_EN_ERX_EN (0x00001000)*/ /* R/W */ +#define INT_EN_TDFU_EN (0x00000800) /* R/W */ +#define INT_EN_TDFO_EN (0x00000400) /* R/W */ +#define INT_EN_TDFA_EN (0x00000200) /* R/W */ +#define INT_EN_TSFF_EN (0x00000100) /* R/W */ +#define INT_EN_TSFL_EN (0x00000080) /* R/W */ +/*#define INT_EN_RXDF_EN (0x00000040)*/ /* R/W */ +#define INT_EN_RDFO_EN (0x00000040) /* R/W */ +#define INT_EN_RDFL_EN (0x00000020) /* R/W */ +#define INT_EN_RSFF_EN (0x00000010) /* R/W */ +#define INT_EN_RSFL_EN (0x00000008) /* R/W */ +#define INT_EN_GPIO2_INT (0x00000004) /* R/W */ +#define INT_EN_GPIO1_INT (0x00000002) /* R/W */ +#define INT_EN_GPIO0_INT (0x00000001) /* R/W */ + +#define BYTE_TEST __REG(CONFIG_DRIVER_SMC911X_BASE + 0x64) +#define FIFO_INT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x68) +#define FIFO_INT_TX_AVAIL_LEVEL (0xFF000000) /* R/W */ +#define FIFO_INT_TX_STS_LEVEL (0x00FF0000) /* R/W */ +#define FIFO_INT_RX_AVAIL_LEVEL (0x0000FF00) /* R/W */ +#define FIFO_INT_RX_STS_LEVEL (0x000000FF) /* R/W */ + +#define RX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x6C) +#define RX_CFG_RX_END_ALGN (0xC0000000) /* R/W */ +#define RX_CFG_RX_END_ALGN4 (0x00000000) /* R/W */ +#define RX_CFG_RX_END_ALGN16 (0x40000000) /* R/W */ +#define RX_CFG_RX_END_ALGN32 (0x80000000) /* R/W */ +#define RX_CFG_RX_DMA_CNT (0x0FFF0000) /* R/W */ +#define RX_CFG_RX_DUMP (0x00008000) /* R/W */ +#define RX_CFG_RXDOFF (0x00001F00) /* R/W */ +/*#define RX_CFG_RXBAD (0x00000001)*/ /* R/W */ + +#define TX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x70) +/*#define TX_CFG_TX_DMA_LVL (0xE0000000)*/ /* R/W */ +/*#define TX_CFG_TX_DMA_CNT (0x0FFF0000)*/ /* R/W Self Clearing */ +#define TX_CFG_TXS_DUMP (0x00008000) /* Self Clearing */ +#define TX_CFG_TXD_DUMP (0x00004000) /* Self Clearing */ +#define TX_CFG_TXSAO (0x00000004) /* R/W */ +#define TX_CFG_TX_ON (0x00000002) /* R/W */ +#define TX_CFG_STOP_TX (0x00000001) /* Self Clearing */ + +#define HW_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x74) +#define HW_CFG_TTM (0x00200000) /* R/W */ +#define HW_CFG_SF (0x00100000) /* R/W */ +#define HW_CFG_TX_FIF_SZ (0x000F0000) /* R/W */ +#define HW_CFG_TR (0x00003000) /* R/W */ +#define HW_CFG_PHY_CLK_SEL (0x00000060) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY (0x00000000) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY (0x00000020) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS (0x00000040) /* R/W */ +#define HW_CFG_SMI_SEL (0x00000010) /* R/W */ +#define HW_CFG_EXT_PHY_DET (0x00000008) /* RO */ +#define HW_CFG_EXT_PHY_EN (0x00000004) /* R/W */ +#define HW_CFG_32_16_BIT_MODE (0x00000004) /* RO */ +#define HW_CFG_SRST_TO (0x00000002) /* RO */ +#define HW_CFG_SRST (0x00000001) /* Self Clearing */ + +#define RX_DP_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x78) +#define RX_DP_CTRL_RX_FFWD (0x80000000) /* R/W */ +#define RX_DP_CTRL_FFWD_BUSY (0x80000000) /* RO */ + +#define RX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x7C) +#define RX_FIFO_INF_RXSUSED (0x00FF0000) /* RO */ +#define RX_FIFO_INF_RXDUSED (0x0000FFFF) /* RO */ + +#define TX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x80) +#define TX_FIFO_INF_TSUSED (0x00FF0000) /* RO */ +#define TX_FIFO_INF_TDFREE (0x0000FFFF) /* RO */ + +#define PMT_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x84) +#define PMT_CTRL_PM_MODE (0x00003000) /* Self Clearing */ +#define PMT_CTRL_PHY_RST (0x00000400) /* Self Clearing */ +#define PMT_CTRL_WOL_EN (0x00000200) /* R/W */ +#define PMT_CTRL_ED_EN (0x00000100) /* R/W */ +#define PMT_CTRL_PME_TYPE (0x00000040) /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_WUPS (0x00000030) /* R/WC */ +#define PMT_CTRL_WUPS_NOWAKE (0x00000000) /* R/WC */ +#define PMT_CTRL_WUPS_ED (0x00000010) /* R/WC */ +#define PMT_CTRL_WUPS_WOL (0x00000020) /* R/WC */ +#define PMT_CTRL_WUPS_MULTI (0x00000030) /* R/WC */ +#define PMT_CTRL_PME_IND (0x00000008) /* R/W */ +#define PMT_CTRL_PME_POL (0x00000004) /* R/W */ +#define PMT_CTRL_PME_EN (0x00000002) /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_READY (0x00000001) /* RO */ + +#define GPIO_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x88) +#define GPIO_CFG_LED3_EN (0x40000000) /* R/W */ +#define GPIO_CFG_LED2_EN (0x20000000) /* R/W */ +#define GPIO_CFG_LED1_EN (0x10000000) /* R/W */ +#define GPIO_CFG_GPIO2_INT_POL (0x04000000) /* R/W */ +#define GPIO_CFG_GPIO1_INT_POL (0x02000000) /* R/W */ +#define GPIO_CFG_GPIO0_INT_POL (0x01000000) /* R/W */ +#define GPIO_CFG_EEPR_EN (0x00700000) /* R/W */ +#define GPIO_CFG_GPIOBUF2 (0x00040000) /* R/W */ +#define GPIO_CFG_GPIOBUF1 (0x00020000) /* R/W */ +#define GPIO_CFG_GPIOBUF0 (0x00010000) /* R/W */ +#define GPIO_CFG_GPIODIR2 (0x00000400) /* R/W */ +#define GPIO_CFG_GPIODIR1 (0x00000200) /* R/W */ +#define GPIO_CFG_GPIODIR0 (0x00000100) /* R/W */ +#define GPIO_CFG_GPIOD4 (0x00000010) /* R/W */ +#define GPIO_CFG_GPIOD3 (0x00000008) /* R/W */ +#define GPIO_CFG_GPIOD2 (0x00000004) /* R/W */ +#define GPIO_CFG_GPIOD1 (0x00000002) /* R/W */ +#define GPIO_CFG_GPIOD0 (0x00000001) /* R/W */ + +#define GPT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x8C) +#define GPT_CFG_TIMER_EN (0x20000000) /* R/W */ +#define GPT_CFG_GPT_LOAD (0x0000FFFF) /* R/W */ + +#define GPT_CNT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x90) +#define GPT_CNT_GPT_CNT (0x0000FFFF) /* RO */ + +#define ENDIAN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x98) +#define FREE_RUN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x9C) +#define RX_DROP __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA0) +#define MAC_CSR_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY (0x80000000) /* Self Clearing */ +#define MAC_CSR_CMD_R_NOT_W (0x40000000) /* R/W */ +#define MAC_CSR_CMD_CSR_ADDR (0x000000FF) /* R/W */ + +#define MAC_CSR_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA8) +#define AFC_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0xAC) +#define AFC_CFG_AFC_HI (0x00FF0000) /* R/W */ +#define AFC_CFG_AFC_LO (0x0000FF00) /* R/W */ +#define AFC_CFG_BACK_DUR (0x000000F0) /* R/W */ +#define AFC_CFG_FCMULT (0x00000008) /* R/W */ +#define AFC_CFG_FCBRD (0x00000004) /* R/W */ +#define AFC_CFG_FCADD (0x00000002) /* R/W */ +#define AFC_CFG_FCANY (0x00000001) /* R/W */ + +#define E2P_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY (0x80000000) /* Self Clearing */ +#define E2P_CMD_EPC_CMD (0x70000000) /* R/W */ +#define E2P_CMD_EPC_CMD_READ (0x00000000) /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS (0x10000000) /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN (0x20000000) /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE (0x30000000) /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL (0x40000000) /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE (0x50000000) /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL (0x60000000) /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD (0x70000000) /* R/W */ +#define E2P_CMD_EPC_TIMEOUT (0x00000200) /* RO */ +#define E2P_CMD_MAC_ADDR_LOADED (0x00000100) /* RO */ +#define E2P_CMD_EPC_ADDR (0x000000FF) /* R/W */ + +#define E2P_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB4) +#define E2P_DATA_EEPROM_DATA (0x000000FF) /* R/W */ +/* end of LAN register offsets and bit definitions */ + +/* MAC Control and Status registers */ +#define MAC_CR (0x01) /* R/W */ + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL (0x80000000) +/* TODO: delete this bit? It is not described in the data sheet. */ +#define MAC_CR_HBDIS (0x10000000) +#define MAC_CR_RCVOWN (0x00800000) +#define MAC_CR_LOOPBK (0x00200000) +#define MAC_CR_FDPX (0x00100000) +#define MAC_CR_MCPAS (0x00080000) +#define MAC_CR_PRMS (0x00040000) +#define MAC_CR_INVFILT (0x00020000) +#define MAC_CR_PASSBAD (0x00010000) +#define MAC_CR_HFILT (0x00008000) +#define MAC_CR_HPFILT (0x00002000) +#define MAC_CR_LCOLL (0x00001000) +#define MAC_CR_BCAST (0x00000800) +#define MAC_CR_DISRTY (0x00000400) +#define MAC_CR_PADSTR (0x00000100) +#define MAC_CR_BOLMT_MASK (0x000000C0) +#define MAC_CR_DFCHK (0x00000020) +#define MAC_CR_TXEN (0x00000008) +#define MAC_CR_RXEN (0x00000004) + +#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */ +#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */ +#define HASHH (0x04) /* R/W */ +#define HASHL (0x05) /* R/W */ + +#define MII_ACC (0x06) /* R/W */ +#define MII_ACC_PHY_ADDR (0x0000F800) +#define MII_ACC_MIIRINDA (0x000007C0) +#define MII_ACC_MII_WRITE (0x00000002) +#define MII_ACC_MII_BUSY (0x00000001) + +#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */ + +#define FLOW (0x08) /* R/W */ +#define FLOW_FCPT (0xFFFF0000) +#define FLOW_FCPASS (0x00000004) +#define FLOW_FCEN (0x00000002) +#define FLOW_FCBSY (0x00000001) + +#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */ +#define VLAN1_VTI1 (0x0000ffff) + +#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */ +#define VLAN2_VTI2 (0x0000ffff) + +#define WUFF (0x0B) /* WO */ + +#define WUCSR (0x0C) /* R/W */ +#define WUCSR_GUE (0x00000200) +#define WUCSR_WUFR (0x00000040) +#define WUCSR_MPR (0x00000020) +#define WUCSR_WAKE_EN (0x00000004) +#define WUCSR_MPEN (0x00000002) + +/* Chip ID values */ +#define CHIP_9115 0x115 +#define CHIP_9116 0x116 +#define CHIP_9117 0x117 +#define CHIP_9118 0x118 +#define CHIP_9215 0x115a +#define CHIP_9216 0x116a +#define CHIP_9217 0x117a +#define CHIP_9218 0x118a + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { 0, NULL }, +}; + +#define DRIVERNAME "smc911x" + +u32 smc911x_get_mac_csr(u8 reg) +{ + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg; + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + + return MAC_CSR_DATA; +} + +void smc911x_set_mac_csr(u8 reg, u32 data) +{ + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + MAC_CSR_DATA = data; + MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | reg; + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); +} + +static int smx911x_handle_mac_address(bd_t *bd) +{ + unsigned long addrh, addrl; + unsigned char *m = bd->bi_enetaddr; + + /* if the environment has a valid mac address then use it */ + if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) { + addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24; + addrh = m[4] | m[5] << 8; + smc911x_set_mac_csr(ADDRH, addrh); + smc911x_set_mac_csr(ADDRL, addrl); + } else { + /* if not, try to get one from the eeprom */ + addrh = smc911x_get_mac_csr(ADDRH); + addrl = smc911x_get_mac_csr(ADDRL); + + m[0] = (addrl ) & 0xff; + m[1] = (addrl >> 8 ) & 0xff; + m[2] = (addrl >> 16 ) & 0xff; + m[3] = (addrl >> 24 ) & 0xff; + m[4] = (addrh ) & 0xff; + m[5] = (addrh >> 8 ) & 0xff; + + /* we get 0xff when there is no eeprom connected */ + if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) { + printf(DRIVERNAME ": no valid mac address in environment " + "and no eeprom found\n"); + return -1; + } + } + + printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + m[0], m[1], m[2], m[3], m[4], m[5]); + + return 0; +} + +static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val) +{ + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + smc911x_set_mac_csr( MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); + + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + *val = smc911x_get_mac_csr(MII_DATA); + + return 0; +} + +static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val) +{ + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + smc911x_set_mac_csr(MII_DATA, val); + smc911x_set_mac_csr(MII_ACC, + phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); + + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + return 0; +} + +static int smc911x_phy_reset(void) +{ + u32 reg; + + reg = PMT_CTRL; + reg &= ~0xfffff030; + reg |= PMT_CTRL_PHY_RST; + PMT_CTRL = reg; + + mdelay(100); + + return 0; +} + +static void smc911x_phy_configure(void) +{ + int timeout; + u16 status; + + smc911x_phy_reset(); + + smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET); + mdelay(1); + smc911x_miiphy_write(1, PHY_ANAR, 0x01e1); + smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + + timeout = 5000; + do { + mdelay(1); + if ((timeout--) == 0) + goto err_out; + + if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0) + goto err_out; + } while (!(status & PHY_BMSR_LS)); + + printf(DRIVERNAME ": phy initialized\n"); + + return; + +err_out: + printf(DRIVERNAME ": autonegotiation timed out\n"); +} + +static void smc911x_reset(void) +{ + int timeout; + + /* Take out of PM setting first */ + if (PMT_CTRL & PMT_CTRL_READY) { + /* Write to the bytetest will take out of powerdown */ + BYTE_TEST = 0x0; + + timeout = 10; + + while ( timeout-- && !(PMT_CTRL & PMT_CTRL_READY)) + udelay(10); + if (!timeout) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + INT_EN = 0; + + HW_CFG = HW_CFG_SRST; + + timeout = 1000; + while (timeout-- && E2P_CMD & E2P_CMD_EPC_BUSY) + udelay(10); + + if(!timeout) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); + AFC_CFG = 0x0050287F; + + /* Set to LED outputs */ + GPIO_CFG = 0x70070000; +} + +static void smc911x_enable(void) +{ + /* Enable TX */ + HW_CFG = 8 << 16 | HW_CFG_SF; + + GPT_CFG = GPT_CFG_TIMER_EN | 10000; + + TX_CFG = TX_CFG_TX_ON; + + /* no padding to start of packets */ + RX_CFG = 0; + + smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); + +} + +int eth_init(bd_t *bd) +{ + unsigned long val, i; + + printf(DRIVERNAME ": initializing\n"); + + val = BYTE_TEST; + if(val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val); + goto err_out; + } + + val = ID_REV >> 16; + for(i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04x\n", val); + goto err_out; + } + + printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + + smc911x_reset(); + + /* Configure the PHY, initialize the link state */ + smc911x_phy_configure(); + + if (smx911x_handle_mac_address(bd)) + goto err_out; + + /* Turn on Tx + Rx */ + smc911x_enable(); + + return 0; + +err_out: + return -1; +} + +int eth_send(volatile void *packet, int length) +{ + u32 *data = (u32*)packet; + u32 tmplen; + u32 status; + + TX_DATA_FIFO = TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length; + TX_DATA_FIFO = length; + + tmplen = (length + 3) / 4; + + while(tmplen--) + TX_DATA_FIFO = *data++; + + /* wait for transmission */ + while (!((TX_FIFO_INF & TX_FIFO_INF_TSUSED) >> 16)); + + /* get status. Ignore 'no carrier' error, it has no meaning for + * full duplex operation + */ + status = TX_STATUS_FIFO & (TX_STS_LOC | TX_STS_LATE_COLL | + TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); + + if(!status) + return 0; + + printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", + status & TX_STS_LOC ? "TX_STS_LOC " : "", + status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", + status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", + status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", + status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); + + return -1; +} + +void eth_halt(void) +{ + smc911x_reset(); +} + +int eth_rx(void) +{ + u32 *data = (u32 *)NetRxPackets[0]; + u32 pktlen, tmplen; + u32 status; + + if((RX_FIFO_INF & RX_FIFO_INF_RXSUSED) >> 16) { + status = RX_STATUS_FIFO; + pktlen = (status & RX_STS_PKT_LEN) >> 16; + + RX_CFG = 0; + + tmplen = (pktlen + 2+ 3) / 4; + while(tmplen--) + *data++ = RX_DATA_FIFO; + + if(status & RX_STS_ES) + printf(DRIVERNAME + ": dropped bad packet. Status: 0x%08x\n", + status); + else + NetReceive(NetRxPackets[0], pktlen); + } + + return 0; +} + +#endif /* CONFIG_DRIVER_SMC911X */ -- 1.5.4

7 13

[U-Boot-Users] [PATCH v2] Introduce phys_size_t and move phys_addr_t into asm/types.h
by Kumar Gala 14 Apr '08

14 Apr '08

Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's that have larger physical addresses like 44x, 85xx, and 86xx. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-arm/io.h | 2 -- include/asm-arm/types.h | 3 +++ include/asm-avr32/io.h | 2 -- include/asm-avr32/types.h | 3 +++ include/asm-blackfin/io.h | 2 -- include/asm-blackfin/types.h | 3 +++ include/asm-i386/io.h | 2 -- include/asm-i386/types.h | 3 +++ include/asm-m68k/io.h | 2 -- include/asm-m68k/types.h | 3 +++ include/asm-microblaze/io.h | 2 -- include/asm-microblaze/types.h | 3 +++ include/asm-mips/io.h | 2 -- include/asm-mips/types.h | 8 ++++++++ include/asm-nios/io.h | 2 -- include/asm-nios/types.h | 3 +++ include/asm-nios2/io.h | 2 -- include/asm-ppc/io.h | 2 -- include/asm-ppc/types.h | 8 ++++++++ include/asm-sh/io.h | 2 -- include/asm-sh/types.h | 3 +++ 21 files changed, 40 insertions(+), 22 deletions(-) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 029b7f9..c33b9e8 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -38,8 +38,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h index e56f19d..71dc049 100644 --- a/include/asm-arm/types.h +++ b/include/asm-arm/types.h @@ -45,6 +45,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index ba14674..d030c26 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -101,8 +101,6 @@ static inline void sync(void) * This implementation works for memory below 512MiB (flash, etc.) as * well as above 3.5GiB (internal peripherals.) */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (1 << 7) #define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h index 2dbea4b..c303e3c 100644 --- a/include/asm-avr32/types.h +++ b/include/asm-avr32/types.h @@ -71,6 +71,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #ifdef CONFIG_LBD typedef u64 sector_t; #define HAVE_SECTOR_T diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 2149685..da58914 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -45,8 +45,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr); * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 9fd8e03..2160ba0 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -78,6 +78,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif #endif diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index db4f442..2c57140 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -210,8 +210,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index bdbde41..9a40e38 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -45,6 +45,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 33c454a..1fccc12 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -232,8 +232,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h index e944d3f..44b4ca5 100644 --- a/include/asm-m68k/types.h +++ b/include/asm-m68k/types.h @@ -44,6 +44,9 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 90d1842..aa37a60 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -134,8 +134,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h index 3895dc4..77094f6 100644 --- a/include/asm-microblaze/types.h +++ b/include/asm-microblaze/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e27d1f1..7137072 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -470,8 +470,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index f49a217..d4bb859 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -78,8 +78,16 @@ typedef unsigned long long u64; #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ || defined(CONFIG_64BIT) typedef u64 dma_addr_t; + +typedef u64 phys_addr_t; +typedef u64 phys_size_t; + #else typedef u32 dma_addr_t; + +typedef u32 phys_addr_t; +typedef u32 phys_size_t; + #endif typedef u64 dma64_addr_t; diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 6fc339f..12a0bd9 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -114,8 +114,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h index 24c98a8..636e12f 100644 --- a/include/asm-nios/types.h +++ b/include/asm-nios/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _NIOS_TYPES_H */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index a52b95c..2f1ec26 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -34,8 +34,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 91c9c1e..00b7ec5 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -243,8 +243,6 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h index 7adf145..864391f 100644 --- a/include/asm-ppc/types.h +++ b/include/asm-ppc/types.h @@ -44,6 +44,14 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 51fd10b..7400293 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -233,8 +233,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h index 7ba69d9..aed4a6e 100644 --- a/include/asm-sh/types.h +++ b/include/asm-sh/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ -- 1.5.4.1

2 1

[U-Boot-Users] [PATCH] Fix host tool build breakage, take two
by Bartlomiej Sieka 14 Apr '08

14 Apr '08

Revert commit 87c8431f and fix build breakage so that the build continues to work on FC systems. Signed-off-by: Bartlomiej Sieka <tur(a)semihalf.com> --- Patch tested on FC and kubuntu. Could people that reported Haavard's patch fixing the build for them try this one out and report back? diff --git a/include/fdt.h b/include/fdt.h index 39beada..48ccfd9 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -3,10 +3,6 @@ #ifndef __ASSEMBLY__ -#ifdef USE_HOSTCC -#include <stdint.h> -#endif - struct fdt_header { uint32_t magic; /* magic word FDT_MAGIC */ uint32_t totalsize; /* total size of DT block */ diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 98c522a..ab5c301 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -21,15 +21,16 @@ #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H -#include <stddef.h> -#include <linux/types.h> -#include <asm/byteorder.h> #ifdef USE_HOSTCC +#include <stdint.h> #include <string.h> #else #include <linux/string.h> +#include <linux/types.h> #endif /* USE_HOSTCC */ +#include <stddef.h> +#include <asm/byteorder.h> extern struct fdt_header *fdt; /* Pointer to the working fdt */ #define fdt32_to_cpu(x) __be32_to_cpu(x)

10 24

[U-Boot-Users] [PATCH] Add support for setting the I2C bus speed in fsl_i2c.c
by Timur Tabi 14 Apr '08

14 Apr '08

Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro, but fsl_i2c.c ignores it and uses conservative value when programming the I2C bus speed. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- This patch is for U-Boot 1.3.3. It affects 83xx, 85xx, and 86xx. drivers/i2c/fsl_i2c.c | 114 +++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 105 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 22485ea..dde0571 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -32,6 +32,8 @@ #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 +DECLARE_GLOBAL_DATA_PTR; + /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 0. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify @@ -43,24 +45,111 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif -static volatile struct fsl_i2c *i2c_dev[2] = { +static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; + +static const struct fsl_i2c *i2c_dev[2] = { (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), #ifdef CFG_I2C2_OFFSET (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) #endif }; +/* I2C speed map for a DFSR value of 1 */ + +/* + * Map I2C frequency dividers to FDR and DFSR values + * + * This structure is used to define the elements of a table that maps I2C + * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be + * programmed into the Frequency Divider Ratio (FDR) and Digital Filter + * Sampling Rate (DFSR) registers. + * + * The actual table should be defined in the board file, and it must be called + * fsl_i2c_speed_map[]. + * + * The last entry of the table must have a value of {-1, X}, where X is same + * FDR/DFSR values as the second-to-last entry. This guarantees that any + * search through the array will always find a match. + * + * The values of the divider must be in increasing numerical order, i.e. + * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. + * + * For this table, the values are based on a value of 1 for the DFSR + * register. See the application note AN2919 "Determining the I2C Frequency + * Divider Ratio for SCL" + */ +static const struct { + unsigned short divider; + u8 dfsr; + u8 fdr; +} fsl_i2c_speed_map[] = { + {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, + {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, + {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, + {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, + {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, + {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, + {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, + {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, + {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, + {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, + {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, + {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, + {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, + {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, + {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, + {61440, 1, 31}, {-1, 1, 31} +}; + +/** + * Set the I2C bus speed for a given I2C device + * + * @param dev: the I2C device + * @i2c_clk: I2C bus clock frequency + * @speed: the desired speed of the bus + * + * The I2C device must be stopped before calling this function. + * + * The return value is the actual bus speed that is set. + */ +static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, + unsigned int i2c_clk, unsigned int speed) +{ + unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); + unsigned int i; + u8 fdr, dfsr; + + /* + * We want to choose an FDR/DFSR that generates an I2C bus speed that + * is equal to or lower than the requested speed. That means that we + * want the first divider that is equal to or greater than the + * calculated divider. + */ + + for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) + if (fsl_i2c_speed_map[i].divider >= divider) { + dfsr = fsl_i2c_speed_map[i].dfsr; + fdr = fsl_i2c_speed_map[i].fdr; + speed = i2c_clk / fsl_i2c_speed_map[i].divider; + break; + } + + writeb(fdr, &dev->fdr); /* set bus speed */ + writeb(dfsr, &dev->dfsrr); /* set default filter */ + + return speed; +} + void i2c_init(int speed, int slaveadd) { - volatile struct fsl_i2c *dev; + struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - writeb(0x3F, &dev->fdr); /* set bus speed */ - writeb(0x3F, &dev->dfsrr); /* set default filter */ + i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ @@ -70,12 +159,11 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - writeb(0x3F, &dev->fdr); /* set bus speed */ - writeb(0x3F, &dev->dfsrr); /* set default filter */ + i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#endif /* CFG_I2C2_OFFSET */ +#endif } static __inline__ int @@ -279,7 +367,14 @@ int i2c_set_bus_num(unsigned int bus) int i2c_set_bus_speed(unsigned int speed) { - return -1; + unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; + + writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ + i2c_bus_speed[i2c_bus_num] = + set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ + + return 0; } unsigned int i2c_get_bus_num(void) @@ -289,7 +384,8 @@ unsigned int i2c_get_bus_num(void) unsigned int i2c_get_bus_speed(void) { - return 0; + return i2c_bus_speed[i2c_bus_num]; } + #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ -- 1.5.4

6 15

[U-Boot-Users] s3c2410 no success (my fault)
by pat 14 Apr '08

14 Apr '08

I just don't know enough about how u-boot and C work to get u-boot 1.3.x working on my s3c2410 board. I managed to get 1.2.0 going with the nand commands added (not mtdpart though) which should be enough to get linux booted (though I'm not entirely sure the nand commands are actually working - experimenting with jffs2 now). If anyone is working on s3c stuff and wants me to try running their versions I'd be happy to help. Machine config is: AM29LV800 (1mb) K9F1208 (64mb total) 64MB ram SD Card Ethernet (cs8900) USB 800x480 LCD (driven by s3c2410) touchscreen (driven by s3c2410) I have no way to switch between NOR and NAND boot though so u-boot has to start in NOR unfortunately (might be why I can't get 1.3.x to work?). I have a wiggler clone but I'm still trying to figure out how use openocd to debug with.

1 0

[U-Boot-Users] [PATCH 2/3] drivers: clean up the ata_piix.h
by Dave Liu 14 Apr '08

14 Apr '08

Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- drivers/block/ata_piix.h | 26 +++++++++++++++----------- 1 files changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h index ed2e4d5..f9f0194 100644 --- a/drivers/block/ata_piix.h +++ b/drivers/block/ata_piix.h @@ -1,3 +1,5 @@ +#ifndef __ATA_PIIX_H__ +#define __ATA_PIIX_H__ #if (DEBUG_SATA) #define PRINTF(fmt,args...) printf (fmt ,##args) @@ -51,17 +53,17 @@ struct sata_port { static inline void ata_dump_id (u16 * id) { - PRINTF ("49==0x%04x " - "53==0x%04x " - "63==0x%04x " - "64==0x%04x " - "75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]); - PRINTF ("80==0x%04x " - "81==0x%04x " - "82==0x%04x " - "83==0x%04x " - "84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]); - PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]); + PRINTF ("49 = 0x%04x " + "53 = 0x%04x " + "63 = 0x%04x " + "64 = 0x%04x " + "75 = 0x%04x \n", id[49], id[53], id[63], id[64], id[75]); + PRINTF ("80 = 0x%04x " + "81 = 0x%04x " + "82 = 0x%04x " + "83 = 0x%04x " + "84 = 0x%04x \n", id[80], id[81], id[82], id[83], id[84]); + PRINTF ("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]); } #endif @@ -88,3 +90,5 @@ int init_sata (int dev); #ifdef DRV_DECL /*Defines Driver Specific variables */ struct sata_port port[CFG_SATA_MAXBUS]; #endif + +#endif /* __ATA_PIIX_H__ */ -- 1.5.4.rc4

2 1

[U-Boot-Users] [PATCH 3/3] drivers: code clean up
by Dave Liu 14 Apr '08

14 Apr '08

Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- drivers/block/libata.c | 36 ++++++++++++++++++------------------ include/sata.h | 5 +++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/block/libata.c b/drivers/block/libata.c index bbe16a2..90e9a43 100644 --- a/drivers/block/libata.c +++ b/drivers/block/libata.c @@ -109,39 +109,39 @@ void ata_dump_id(u16 *id) n_sectors = ata_id_n_sectors(id); printf("Capablity: %d sectors\n\r", n_sectors); - printf ("id[49]: capabilities ==0x%04x\n" - "id[53]: field valid ==0x%04x\n" - "id[63]: mwdma ==0x%04x\n" - "id[64]: pio ==0x%04x\n" - "id[75]: queue depth ==0x%04x\n", + printf ("id[49]: capabilities = 0x%04x\n" + "id[53]: field valid = 0x%04x\n" + "id[63]: mwdma = 0x%04x\n" + "id[64]: pio = 0x%04x\n" + "id[75]: queue depth = 0x%04x\n", id[49], id[53], id[63], id[64], id[75]); - printf ("id[76]: sata capablity ==0x%04x\n" - "id[78]: sata features supported ==0x%04x\n" - "id[79]: sata features enable ==0x%04x\n", + printf ("id[76]: sata capablity = 0x%04x\n" + "id[78]: sata features supported = 0x%04x\n" + "id[79]: sata features enable = 0x%04x\n", id[76], id[78], id[79]); - printf ("id[80]: major version ==0x%04x\n" - "id[81]: minor version ==0x%04x\n" - "id[82]: command set supported 1 ==0x%04x\n" - "id[83]: command set supported 2 ==0x%04x\n" - "id[84]: command set extension ==0x%04x\n", + printf ("id[80]: major version = 0x%04x\n" + "id[81]: minor version = 0x%04x\n" + "id[82]: command set supported 1 = 0x%04x\n" + "id[83]: command set supported 2 = 0x%04x\n" + "id[84]: command set extension = 0x%04x\n", id[80], id[81], id[82], id[83], id[84]); - printf ("id[85]: command set enable 1 ==0x%04x\n" - "id[86]: command set enable 2 ==0x%04x\n" - "id[87]: command set default ==0x%04x\n" - "id[88]: udma ==0x%04x\n" - "id[93]: hardware reset result ==0x%04x\n", + printf ("id[85]: command set enable 1 = 0x%04x\n" + "id[86]: command set enable 2 = 0x%04x\n" + "id[87]: command set default = 0x%04x\n" + "id[88]: udma = 0x%04x\n" + "id[93]: hardware reset result = 0x%04x\n", id[85], id[86], id[87], diff --git a/include/sata.h b/include/sata.h index b4b7029..57ee9ac 100644 --- a/include/sata.h +++ b/include/sata.h @@ -1,6 +1,11 @@ +#ifndef __SATA_H__ +#define __SATA_H__ + int init_sata(int dev); int scan_sata(int dev); ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer); ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer); int sata_initialize(void); + +#endif -- 1.5.4.rc4

2 1

[U-Boot-Users] [PATCH v2 2/7] core support for Freescale mx31
by Guennadi Liakhovetski 14 Apr '08

14 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds the core support for Freescale mx31 Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- No changes wrt v1 cpu/arm1136/mx31/Makefile | 45 +++++++ cpu/arm1136/mx31/generic.c | 101 ++++++++++++++ cpu/arm1136/mx31/interrupts.c | 102 +++++++++++++++ cpu/arm1136/mx31/serial.c | 231 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 138 ++++++++++++++++++++ include/asm-arm/arch-mx31/mx31.h | 32 +++++ 6 files changed, 649 insertions(+), 0 deletions(-) create mode 100644 cpu/arm1136/mx31/Makefile create mode 100644 cpu/arm1136/mx31/generic.c create mode 100644 cpu/arm1136/mx31/interrupts.c create mode 100644 cpu/arm1136/mx31/serial.c create mode 100644 include/asm-arm/arch-mx31/mx31-regs.h create mode 100644 include/asm-arm/arch-mx31/mx31.h diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile new file mode 100644 index 0000000..b648ffd --- /dev/null +++ b/cpu/arm1136/mx31/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = interrupts.o serial.o generic.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c new file mode 100644 index 0000000..529c0f6 --- /dev/null +++ b/cpu/arm1136/mx31/generic.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx31-regs.h> + +static u32 mx31_decode_pll(u32 reg, u32 infreq) +{ + u32 mfi = (reg >> 10) & 0xf; + u32 mfn = reg & 0x3f; + u32 mfd = (reg >> 16) & 0x3f; + u32 pd = (reg >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + mfd += 1; + pd += 1; + + return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) / + (mfd * pd)) << 10; +} + +u32 mx31_get_mpl_dpdgck_clk(void) +{ + u32 infreq; + + if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM) + infreq = CONFIG_MX31_CLK32 * 1024; + else + infreq = CONFIG_MX31_HCLK_FREQ; + + return mx31_decode_pll(__REG(CCM_MPCTL), infreq); +} + +u32 mx31_get_mcu_main_clk(void) +{ + /* For now we assume mpl_dpdgck_clk == mcu_main_clk + * which should be correct for most boards + */ + return mx31_get_mpl_dpdgck_clk(); +} + +u32 mx31_get_ipg_clk(void) +{ + u32 freq = mx31_get_mcu_main_clk(); + u32 pdr0 = __REG(CCM_PDR0); + + freq /= ((pdr0 >> 3) & 0x7) + 1; + freq /= ((pdr0 >> 6) & 0x3) + 1; + + return freq; +} + +void mx31_dump_clocks(void) +{ + u32 cpufreq = mx31_get_mcu_main_clk(); + printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000); + printf("ipg clock : %dHz\n", mx31_get_ipg_clk()); +} + +void mx31_gpio_mux(unsigned long mode) +{ + unsigned long reg, shift, tmp; + + reg = IOMUXC_BASE + (mode & 0xfc); + shift = (~mode & 0x3) * 8; + + tmp = __REG(reg); + tmp &= ~(0xff << shift); + tmp |= ((mode >> 8) & 0xff) << shift; + __REG(reg) = tmp; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + printf("CPU: Freescale i.MX31 at %d MHz\n", + mx31_get_mcu_main_clk() / 1000000); + return 0; +} +#endif + diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c new file mode 100644 index 0000000..21b77a5 --- /dev/null +++ b/cpu/arm1136/mx31/interrupts.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx31-regs.h> + +#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ + +/* General purpose timers registers */ +#define GPTCR __REG(TIMER_BASE) /* Control register */ +#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int i; + + /* setup GP Timer 1 */ + GPTCR = GPTCR_SWR; + for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ + GPTPR = 0; /* 32Khz */ + GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ + + return 0; +} + +void reset_timer_masked (void) +{ + GPTCR = 0; + GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ +} + +ulong get_timer_masked (void) +{ + ulong val = GPTCNT; + return val; +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_cpu (ulong addr) +{ + __REG16(WDOG_BASE) = 4; +} diff --git a/cpu/arm1136/mx31/serial.c b/cpu/arm1136/mx31/serial.c new file mode 100644 index 0000000..a829ba7 --- /dev/null +++ b/cpu/arm1136/mx31/serial.c @@ -0,0 +1,231 @@ +/* + * (c) 2007 Sascha Hauer <s.hauer(a)pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> + +#if defined CONFIG_MX31_UART + +#include <asm/arch/mx31.h> + +#define __REG(x) (*((volatile u32 *)(x))) + +#ifdef CFG_MX31_UART1 +#define UART_PHYS 0x43f90000 +#elif defined(CFG_MX31_UART2) +#define UART_PHYS 0x43f94000 +#elif defined(CFG_MX31_UART3) +#define UART_PHYS 0x5000c000 +#elif defined(CFG_MX31_UART4) +#define UART_PHYS 0x43fb0000 +#elif defined(CFG_MX31_UART5) +#define UART_PHYS 0x43fb4000 +#else +#error "define CFG_MX31_UARTx to use the mx31 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ + u32 clk = mx31_get_ipg_clk(); + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); + +} + +int serial_getc (void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + return __REG(UART_PHYS + URXD); +} + +void serial_putc (const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} + + +#endif /* CONFIG_MX31 */ diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h new file mode 100644 index 0000000..c004478 --- /dev/null +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -0,0 +1,138 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX31_REGS_H +#define __ASM_ARCH_MX31_REGS_H + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +#define CCM_BASE 0x53f80000 +#define CCM_CCMR (CCM_BASE + 0x00) +#define CCM_PDR0 (CCM_BASE + 0x04) +#define CCM_PDR1 (CCM_BASE + 0x08) +#define CCM_RCSR (CCM_BASE + 0x0c) +#define CCM_MPCTL (CCM_BASE + 0x10) +#define CCM_UPCTL (CCM_BASE + 0x10) +#define CCM_SPCTL (CCM_BASE + 0x18) +#define CCM_COSR (CCM_BASE + 0x1C) + +#define CCMR_MDS (1 << 7) +#define CCMR_SBYCS (1 << 4) +#define CCMR_MPE (1 << 3) +#define CCMR_PRCS_MASK (3 << 1) +#define CCMR_FPM (1 << 1) +#define CCMR_CKIH (2 << 1) + +#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) +#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) +#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) +#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) +#define PDR0_MCU_PODF(x) ((x) & 0x7) + +#define PLL_PD(x) (((x) & 0xf) << 26) +#define PLL_MFD(x) (((x) & 0x3ff) << 16) +#define PLL_MFI(x) (((x) & 0xf) << 10) +#define PLL_MFN(x) (((x) & 0x3ff) << 0) + +#define WEIM_BASE 0xb8002000 +#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +#define IOMUXC_BASE 0x43FAC000 +#define IOMUXC_GPR (IOMUXC_BASE + 0x8) +#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) +#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) + +#define IPU_BASE 0x53fc0000 +#define IPU_CONF IPU_BASE + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define WDOG_BASE 0x53FDC000 + +/* + * Signal Multiplexing (IOMUX) + */ + +/* bits in the SW_MUX_CTL registers */ +#define MUX_CTL_OUT_GPIO_DR (0 << 4) +#define MUX_CTL_OUT_FUNC (1 << 4) +#define MUX_CTL_OUT_ALT1 (2 << 4) +#define MUX_CTL_OUT_ALT2 (3 << 4) +#define MUX_CTL_OUT_ALT3 (4 << 4) +#define MUX_CTL_OUT_ALT4 (5 << 4) +#define MUX_CTL_OUT_ALT5 (6 << 4) +#define MUX_CTL_OUT_ALT6 (7 << 4) +#define MUX_CTL_IN_NONE (0 << 0) +#define MUX_CTL_IN_GPIO (1 << 0) +#define MUX_CTL_IN_FUNC (2 << 0) +#define MUX_CTL_IN_ALT1 (4 << 0) +#define MUX_CTL_IN_ALT2 (8 << 0) + +#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) +#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) +#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) +#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) + +/* Register offsets based on IOMUXC_BASE */ +/* 0x00 .. 0x7b */ +#define MUX_CTL_RTS1 0x7c +#define MUX_CTL_CTS1 0x7d +#define MUX_CTL_DTR_DCE1 0x7e +#define MUX_CTL_DSR_DCE1 0x7f +#define MUX_CTL_CSPI2_SCLK 0x80 +#define MUX_CTL_CSPI2_SPI_RDY 0x81 +#define MUX_CTL_RXD1 0x82 +#define MUX_CTL_TXD1 0x83 +#define MUX_CTL_CSPI2_MISO 0x84 +/* 0x85 .. 0x8a */ +#define MUX_CTL_CSPI2_MOSI 0x8b + +/* The modes a specific pin can be in + * these macros can be used in mx31_gpio_mux() and have the form + * MUX_[contact name]__[pin function] + */ +#define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) +#define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) +#define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) +#define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) + +#define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) +#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) + + +#endif /* __ASM_ARCH_MX31_REGS_H */ + diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h new file mode 100644 index 0000000..f89a401 --- /dev/null +++ b/include/asm-arm/arch-mx31/mx31.h @@ -0,0 +1,32 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX31_H +#define __ASM_ARCH_MX31_H + +u32 mx31_get_mpl_dpdgck_clk(void); +u32 mx31_get_mcu_main_clk(void); +u32 mx31_get_ipg_clk(void); +void mx31_gpio_mux(unsigned long mode); + +#endif /* __ASM_ARCH_MX31_H */ -- 1.5.4

2 1

Re: [U-Boot-Users] [PATCH] Altera Stratix II support
by Wolfgang Denk 14 Apr '08

14 Apr '08

From: "eran liberty" <eran.liberty(a)gmail.com> Adds Support for Altera's Stratix II. Within your board specific init file you will have to call 1. fpga_init (/* relocated code offset. usually => */ gd->reloc_off); 2. fpga_add (fpga_altera, (Altera_desc*)&altera_desc); Altera_desc* contines (for example): { Altera_StratixII, /* part type */ passive_serial, /* interface type */ 1, /* bytes of data part can accept */ (void *)(&funcs), /* interface function table */ 0L, /* base interface address */ 0 /* implementation specific cookie */ } funcs is the interface. It is of type altera_board_specific_func. It looks like this: altera_board_specific_func func = { pre_fn, config_fn, status_fn, done_fn, clk_fn, data_fn, abort_fn, post_fn, }; you will have to implement these functions, which is usually bit banging some gpio. Signed-off-by: Eran Liberty <liberty(a)extricom.com> --- Posted on behalf of Eran Liberty -- wd Index: include/stratixII.h =================================================================== --- include/stratixII.h (revision 0) +++ include/stratixII.h (revision 0) @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom, eran.liberty(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _STRATIXII_H_ +#define _STRATIXII_H_ + +extern int StratixII_load (Altera_desc * desc, void *image, size_t size); +extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize); +extern int StratixII_info (Altera_desc * desc); +extern int StratixII_reloc (Altera_desc * desc, ulong reloc_off); + +#endif /* _STRATIXII_H_ */ Index: include/altera.h =================================================================== --- include/altera.h (revision 121) +++ include/altera.h (working copy) @@ -27,22 +27,21 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ -/* - * See include/xilinx.h for another working example. - */ - /* Altera Model definitions *********************************************************************/ #define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) #define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) +#define CFG_STRATIX_II CFG_FPGA_DEV( 0x4 ) #define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) #define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) +#define CFG_ALTERA_STRATIX_II (CFG_FPGA_ALTERA | CFG_STRATIX_II) /* Add new models here */ /* Altera Interface definitions *********************************************************************/ #define CFG_ALTERA_IF_PS CFG_FPGA_IF( 0x1 ) /* passive serial */ +#define CFG_ALTERA_IF_FPP CFG_FPGA_IF( 0x2 ) /* fast passive parallel */ /* Add new interfaces here */ typedef enum { /* typedef Altera_iface */ @@ -52,6 +51,8 @@ passive_parallel_asynchronous, /* parallel data */ passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ altera_jtag_mode, /* jtag/tap serial (not used ) */ + fast_passive_parallel, /* fast passive parallel (FPP) */ + fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */ max_altera_iface_type /* insert all new types before this */ } Altera_iface; /* end, typedef Altera_iface */ @@ -59,6 +60,7 @@ min_altera_type, /* insert all new types after this */ Altera_ACEX1K, /* ACEX1K Family */ Altera_CYC2, /* CYCLONII Family */ + Altera_StratixII, /* StratixII Familiy */ /* Add new models here */ max_altera_type /* insert all new types before this */ } Altera_Family; /* end, typedef Altera_Family */ @@ -91,4 +93,15 @@ typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_clk_fn clk; + Altera_data_fn data; + Altera_abort_fn abort; + Altera_post_fn post; +} altera_board_specific_func; + #endif /* _ALTERA_H_ */ Index: common/fpga.c =================================================================== --- common/fpga.c (revision 121) +++ common/fpga.c (working copy) @@ -199,10 +199,6 @@ memset( desc_table, 0, sizeof(desc_table)); PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); -#if 0 - PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX ); - PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA ); -#endif } /* fpga_count Index: common/Makefile =================================================================== --- common/Makefile (revision 121) +++ common/Makefile (working copy) @@ -95,6 +95,7 @@ COBJS-y += command.o COBJS-y += console.o COBJS-y += cyclon2.o +COBJS-y += stratixII.o COBJS-y += devices.o COBJS-y += dlmalloc.o COBJS-y += docecc.o Index: common/altera.c =================================================================== --- common/altera.c (revision 121) +++ common/altera.c (working copy) @@ -30,6 +30,7 @@ */ #include <common.h> #include <ACEX1K.h> +#include <stratixII.h> /* Define FPGA_DEBUG to get debug printf's */ /* #define FPGA_DEBUG */ @@ -43,7 +44,7 @@ #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) /* Local Static Functions */ -static int altera_validate (Altera_desc * desc, char *fn); +static int altera_validate (Altera_desc * desc, const char *fn); /* ------------------------------------------------------------------------- */ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) @@ -60,7 +61,7 @@ PRINTF ("%s: Launching the ACEX1K Loader...\n", __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); -#elif defined CONFIG_FPGA_CYCLON2 +#elif defined(CONFIG_FPGA_CYCLON2) PRINTF ("%s: Launching the CYCLON II Loader...\n", __FUNCTION__); ret_val = CYC2_load (desc, buf, bsize); @@ -70,6 +71,13 @@ #endif break; +#if defined(CONFIG_FPGA_STRATIX_II) + case Altera_StratixII: + PRINTF ("%s: Launching the Stratix II Loader...\n", + __FUNCTION__); + ret_val = StratixII_load (desc, buf, bsize); + break; +#endif default: printf ("%s: Unsupported family type, %d\n", __FUNCTION__, desc->family); @@ -98,6 +106,13 @@ #endif break; +#if defined(CONFIG_FPGA_STRATIX_II) + case Altera_StratixII: + PRINTF ("%s: Launching the Stratix II Reader...\n", + __FUNCTION__); + ret_val = StratixII_dump (desc, buf, bsize); + break; +#endif default: printf ("%s: Unsupported family type, %d\n", __FUNCTION__, desc->family); @@ -117,10 +132,13 @@ case Altera_ACEX1K: printf ("ACEX1K\n"); break; - /* Add new family types here */ case Altera_CYC2: printf ("CYCLON II\n"); break; + case Altera_StratixII: + printf ("Stratix II\n"); + break; + /* Add new family types here */ default: printf ("Unknown family type, %d\n", desc->family); } @@ -142,6 +160,13 @@ case altera_jtag_mode: /* Not used */ printf ("JTAG Mode\n"); break; + case fast_passive_parallel: + printf ("Fast Passive Parallel (FPP)\n"); + break; + case fast_passive_parallel_security: + printf + ("Fast Passive Parallel with Security (FPPS) \n"); + break; /* Add new interface types here */ default: printf ("Unsupported interface type, %d\n", desc->iface); @@ -166,6 +191,11 @@ __FUNCTION__); #endif break; +#if defined(CONFIG_FPGA_STRATIX_II) + case Altera_StratixII: + StratixII_info (desc); + break; +#endif /* Add new family types here */ default: /* we don't need a message here - we give one up above */ @@ -199,6 +229,11 @@ __FUNCTION__); #endif break; +#if defined(CONFIG_FPGA_STRATIX_II) + case Altera_StratixII: + ret_val = StratixII_reloc (desc, reloc_offset); + break; +#endif case Altera_CYC2: #if defined(CONFIG_FPGA_CYCLON2) ret_val = CYC2_reloc (desc, reloc_offset); @@ -219,7 +254,7 @@ /* ------------------------------------------------------------------------- */ -static int altera_validate (Altera_desc * desc, char *fn) +static int altera_validate (Altera_desc * desc, const char *fn) { int ret_val = FALSE; Index: common/stratixII.c =================================================================== --- common/stratixII.c (revision 0) +++ common/stratixII.c (revision 0) @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2007 + * Eran Liberty, Extricom , eran.liberty(a)gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> /* core U-Boot definitions */ +#include <altera.h> + +#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II) + +int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, + int isSerial, int isSecure); +int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize); + +/****************************************************************/ +/* Stratix II Generic Implementation */ +int StratixII_load (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0); + break; + case fast_passive_parallel: + ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0); + break; + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1); + break; + + /* Add new interface types here */ + default: + printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, + desc->iface); + } + return ret_val; +} + +int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + case fast_passive_parallel: + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_dump (desc, buf, bsize); + break; + /* Add new interface types here */ + default: + printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, + desc->iface); + } + return ret_val; +} + +int StratixII_info (Altera_desc * desc) +{ + return FPGA_SUCCESS; +} + +int StratixII_reloc (Altera_desc * desc, ulong reloc_offset) +{ + int i; + uint32_t dest = (uint32_t) desc & 0xff000000; + + /* we assume a relocated code and non relocated code has different upper 8 bits */ + if (dest != ((uint32_t) desc->iface_fns & 0xff000000)) { + desc->iface_fns = + (void *)((uint32_t) (desc->iface_fns) + reloc_offset); + } + for (i = 0; i < sizeof (altera_board_specific_func) / sizeof (void *); + i++) { + if (dest != + ((uint32_t) (((void **)(desc->iface_fns))[i]) & 0xff000000)) + { + ((void **)(desc->iface_fns))[i] = + (void + *)(((uint32_t) (((void **)(desc->iface_fns))[i])) + + reloc_offset); + } + } + return FPGA_SUCCESS; +} + +int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) +{ + printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); + return FPGA_FAIL; +} + +int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, + int isSerial, int isSecure) +{ + altera_board_specific_func *fns; + int cookie; + int ret_val = FPGA_FAIL; + int bytecount; + char *buff = buf; + int i; + + if (!desc) { + printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__); + return FPGA_FAIL; + } + if (!buff) { + printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__); + return FPGA_FAIL; + } + if (!bsize) { + printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__); + return FPGA_FAIL; + } + if (!desc->iface_fns) { + printf + ("%s(%d) Altera_desc function interface table is missing\n", + __FUNCTION__, __LINE__); + return FPGA_FAIL; + } + fns = (altera_board_specific_func *) (desc->iface_fns); + cookie = desc->cookie; + + if (! + (fns->config && fns->status && fns->done && fns->data + && fns->abort)) { + printf + ("%s(%d) Missing some function in the function interface table\n", + __FUNCTION__, __LINE__); + return FPGA_FAIL; + } + + /* 1. give board specific a chance to do anything before we start */ + if (fns->pre) { + if ((ret_val = fns->pre (cookie)) < 0) { + return ret_val; + } + } + + /* from this point on we must fail gracfully by calling lower layer abort */ + + /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */ + fns->config (0, 1, cookie); + udelay (5); /* nCONFIG low pulse width 2usec */ + fns->config (1, 1, cookie); + udelay (100); /* nCONFIG high to first rising edge on DCLK */ + + /* 3. Start the Data cycle with clk deasserted */ + bytecount = 0; + fns->clk (0, 1, cookie); + + printf ("loading to fpga "); + while (bytecount < bsize) { + /* 3.1 check stratix has not signaled us an error */ + if (fns->status (cookie) != 1) { + printf + ("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n", + __FUNCTION__, __LINE__, bytecount); + fns->abort (cookie); + return FPGA_FAIL; + } + if (isSerial) { + int i; + uint8_t data = buff[bytecount++]; + for (i = 0; i < 8; i++) { + /* 3.2(ps) put data on the bus */ + fns->data ((data >> i) & 1, 1, cookie); + + /* 3.3(ps) clock once */ + fns->clk (1, 1, cookie); + fns->clk (0, 1, cookie); + } + } else { + /* 3.2(fpp) put data on the bus */ + fns->data (buff[bytecount++], 1, cookie); + + /* 3.3(fpp) clock once */ + fns->clk (1, 1, cookie); + fns->clk (0, 1, cookie); + + /* 3.4(fpp) for secure cycle push 3 more clocks */ + for (i = 0; isSecure && i < 3; i++) { + fns->clk (1, 1, cookie); + fns->clk (0, 1, cookie); + } + } + + /* 3.5 while clk is deasserted it is safe to print some progress indication */ + if ((bytecount % (bsize / 100)) == 0) { + printf ("\b\b\b%02d\%", bytecount * 100 / bsize); + } + } + + /* 4. Set one last clock and check conf done signal */ + fns->clk (1, 1, cookie); + udelay (100); + if (!fns->done (cookie)) { + printf (" error!.\n"); + fns->abort (cookie); + return FPGA_FAIL; + } else { + printf ("\b\b\b done.\n"); + } + + /* 5. call lower layer post configuration */ + if (fns->post) { + if ((ret_val = fns->post (cookie)) < 0) { + fns->abort (cookie); + return ret_val; + } + } + + return FPGA_SUCCESS; +} + +#endif /* defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_STRATIX_II) */

1 1

[U-Boot-Users] [PATCH v2 5/7] mx31 litekit support
by Guennadi Liakhovetski 14 Apr '08

14 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds support for the mx31 litekit board Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: removed C++ style comments, disabled CONFIG_FIT, fixed CONFIG_CMD_* macros MAKEALL | 1 + Makefile | 3 + board/imx31_litekit/Makefile | 51 +++++++++++ board/imx31_litekit/config.mk | 2 + board/imx31_litekit/imx31_litekit.c | 66 ++++++++++++++ board/imx31_litekit/lowlevel_init.S | 103 ++++++++++++++++++++++ board/imx31_litekit/u-boot.lds | 59 +++++++++++++ include/configs/imx31_litekit.h | 162 +++++++++++++++++++++++++++++++++++ 8 files changed, 447 insertions(+), 0 deletions(-) create mode 100644 board/imx31_litekit/Makefile create mode 100644 board/imx31_litekit/config.mk create mode 100644 board/imx31_litekit/imx31_litekit.c create mode 100644 board/imx31_litekit/lowlevel_init.S create mode 100644 board/imx31_litekit/u-boot.lds create mode 100644 include/configs/imx31_litekit.h diff --git a/MAKEALL b/MAKEALL index 01573da..5bc2a12 100755 --- a/MAKEALL +++ b/MAKEALL @@ -502,6 +502,7 @@ LIST_ARM11=" \ cp1136 \ omap2420h4 \ apollon \ + imx31_litekit \ " ######################################################################### diff --git a/Makefile b/Makefile index a9f4bd3..62306a4 100644 --- a/Makefile +++ b/Makefile @@ -2595,6 +2595,9 @@ apollon_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk +imx31_litekit_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31 + #======================================================================== # i386 #======================================================================== diff --git a/board/imx31_litekit/Makefile b/board/imx31_litekit/Makefile new file mode 100644 index 0000000..ea8c889 --- /dev/null +++ b/board/imx31_litekit/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := imx31_litekit.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/imx31_litekit/config.mk b/board/imx31_litekit/config.mk new file mode 100644 index 0000000..021f82f --- /dev/null +++ b/board/imx31_litekit/config.mk @@ -0,0 +1,2 @@ +TEXT_BASE = 0x87f00000 + diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c new file mode 100644 index 0000000..8f1672c --- /dev/null +++ b/board/imx31_litekit/imx31_litekit.c @@ -0,0 +1,66 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ + __REG(CSCR_L(0)) = 0xa0330d01; + __REG(CSCR_A(0)) = 0x00220800; + + __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */ + __REG(CSCR_L(4)) = 0x444a4541; + __REG(CSCR_A(4)) = 0x44443302; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); + + gd->bd->bi_arch_number = 447; /* board id for linux */ + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ + + return 0; +} + +int checkboard (void) +{ + printf("Board: i.MX31 Litekit\n"); + return 0; +} + diff --git a/board/imx31_litekit/lowlevel_init.S b/board/imx31_litekit/lowlevel_init.S new file mode 100644 index 0000000..88b5261 --- /dev/null +++ b/board/imx31_litekit/lowlevel_init.S @@ -0,0 +1,103 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +.globl lowlevel_init +lowlevel_init: + + REG IPU_CONF, IPU_CONF_DI_EN + REG CCM_CCMR, 0x074B0BF5 + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS + + REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0) + + REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23) + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + REG 0x43FAC26C, 0 /* SDCLK */ + REG 0x43FAC270, 0 /* CAS */ + REG 0x43FAC274, 0 /* RAS */ + REG 0x43FAC27C, 0x1000 /* CS2 CSD0) */ + REG 0x43FAC284, 0 /* DQM3 */ + REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 0x288..0x2DC) */ + REG 0x43FAC28C, 0 + REG 0x43FAC290, 0 + REG 0x43FAC294, 0 + REG 0x43FAC298, 0 + REG 0x43FAC29C, 0 + REG 0x43FAC2A0, 0 + REG 0x43FAC2A4, 0 + REG 0x43FAC2A8, 0 + REG 0x43FAC2AC, 0 + REG 0x43FAC2B0, 0 + REG 0x43FAC2B4, 0 + REG 0x43FAC2B8, 0 + REG 0x43FAC2BC, 0 + REG 0x43FAC2C0, 0 + REG 0x43FAC2C4, 0 + REG 0x43FAC2C8, 0 + REG 0x43FAC2CC, 0 + REG 0x43FAC2D0, 0 + REG 0x43FAC2D4, 0 + REG 0x43FAC2D8, 0 + REG 0x43FAC2DC, 0 + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x006ac73a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + mov pc, lr diff --git a/board/imx31_litekit/u-boot.lds b/board/imx31_litekit/u-boot.lds new file mode 100644 index 0000000..1460adc --- /dev/null +++ b/board/imx31_litekit/u-boot.lds @@ -0,0 +1,59 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h new file mode 100644 index 0000000..e89d7a3 --- /dev/null +++ b/include/configs/imx31_litekit.h @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff <r-woodruff2(a)ti.com> + * Kshitij Gupta <kshitij(a)ti.com> + * + * Configuration settings for the 242x TI H4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Temporarily disabled */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CFG_MX31_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.23.168 +#define CONFIG_SERVERIP 192.168.23.2 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ + "prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0" + + +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0 /* memtest works on */ +#define CFG_MEMTEST_END 0x10000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0 /* default load address */ + +#define CFG_HZ 32000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE 0xa0000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ + +#define CFG_ENV_ADDR 0xa01f0000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE (64 * 1024) +#define CFG_ENV_SIZE (64 * 1024) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ -- 1.5.4

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