April 2008 - U-Boot

[U-Boot-Users] [PATCH] Add support for AT91RM9200EK board
by Ulf Samuelsson 16 Apr '08

16 Apr '08

Add support for the AT91RM9200EK Board. Signed-off-by: Ulf Samuelsson <ulf(a)atmel.com>

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Re: [U-Boot-Users] drivers MMCplus for at91sam9x
by Ken.Fuchs＠bench.com 15 Apr '08

15 Apr '08

Pierre Savary wrote: > Then my MMC 4GB works with my Linux kernel but if I can't > load my kernel > (located on the first part of this MMC) ... it's not really > interesting :( > So, somebody does already use MMC v4 with U-boot??? Assuming a AT91SAM926x MCI controller: Probably. Given an MMC v2.x compliant U-Boot driver, it would be relatively easy to add support for an MMC v4.x chip. If there is an MMC v4.x compliant Linux driver, it could be ported to U-Boot (Many, if not most, U-Boot drivers are ports from the corresponding Linux driver.) Alternatively, if both an MMC v2.x compliant U-Boot driver and MMC v4.x compliant Linux driver exist, the port would be trivial; just copy the MMC v4.x Linux code into the corresponding places in the MMC v2.2 U-Boot driver until it supports your MMC v4.x chip. Such an MMC v4.x U-Boot AT91SAM926x MCI driver should be able to support any v4.x MMC chip, at least via a one bit MMC bus. (I remain unconvinced that the AT91SAM926x MCI controller can support a 4 bit MMC bus; only a working MCI driver using a 4 bit MMC bus verified by a logic analyzer or similar compliance/debugging device would be convincing enough.) If the Linux AT91SAM926x MCI driver supports a 4 bit MMC bus, then the U-Boot AT91SAM926x MCI driver can borrow the Linux driver's code and support a 4 bit bus also. Sincerely, Ken Fuchs > -----Message d'origine----- > De : u-boot-users-bounces(a)lists.sourceforge.net > [mailto:u-boot-users-bounces@lists.sourceforge.net] De la > part de Pierre > Ossman > Envoyé : samedi 12 avril 2008 11:28 > À : Ken.Fuchs(a)bench.com > Cc : pierre.savary(a)kerlink.fr; u-boot-users(a)lists.sourceforge.net > Objet : Re: [U-Boot-Users] drivers MMCplus for at91sam9x > > On Fri, 11 Apr 2008 13:54:13 -0500 > Ken.Fuchs(a)bench.com wrote: > > > > > The manual for the AT91SAM926x processors clearly states that the > > MCI controller supports MMC 2.2. I asked Atmel whether > this controller > > could support 4 bits to an MMC 4.x chip and they said _no_. > The answer > > is supposedly from their engineering group in France. > > > > What they answered was if Atmel would support such a solution, not if > the hardware would. > > > > > How does one program the MCI controller to send 4 bit > (parallel) data > > an MMC 4.x chip, with or without telling it that it is communicating > > to a 4-bit SD chip? The only way to get 4 bits of data out > of the MCI > > is to tell it that it is connected to a SD (1.0) chip. If > you program > > the MCI to communicate with an MMC chip, it will send data > out only on > > the low order bit. > > You tell it to use all four bits. That's it. The setting isn't MMC/SD, > it's 1-bit/4-bit. > > > Both ends of the communication link must considered. It may not be > > sufficient that the MMC chip is MMC 4.x; The fact that the MCI > > controller is only MMC 2.2 or SD 1.0 compliant, may or may > not impact > > this special handling. > > It does not in the slightest. Remember that these controllers are > extremely dumb. The low level behaviour of the protocol hasn't changed > since the very first specs, so only software needs to be changed to > support even the newest features. > > Rgds > -- > -- Pierre Ossman > > Linux kernel, MMC maintainer http://www.kernel.org > PulseAudio, core developer http://pulseaudio.org > rdesktop, core developer http://www.rdesktop.org > > -------------------------------------------------------------- > ----------- > This SF.net email is sponsored by the 2008 JavaOne(SM) Conference > Don't miss this year's exciting event. There's still time to > save $100. > Use priority code J8TL2D2. > http://ad.doubleclick.net/clk;198757673;13503038;p?http://java .sun.com/javao ne _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] Length and girth competition champion
by lyndel 15 Apr '08

15 Apr '08

It will grown and grown with our new herbal formula http://www.niebagine.com/

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[U-Boot-Users] [PATCH 2/3] RTC driver for MC13783
by Guennadi Liakhovetski 15 Apr '08

15 Apr '08

MC13783 is a multifunction IS with an SPI interface to the host. This driver handles the RTC controller in this chip. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- diff --git a/README b/README index 0a04d73..4556e87 100644 --- a/README +++ b/README @@ -689,6 +689,7 @@ The following options need to be configured: CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC + CONFIG_RTC_MC13783 - use MC13783 RTC Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 800ab99..2e0c118 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -45,6 +45,7 @@ COBJS-y += m41t60.o COBJS-$(CONFIG_RTC_M41T62) += m41t62.o COBJS-y += m48t35ax.o COBJS-y += max6900.o +COBJS-$(CONFIG_RTC_MC13783) += mc13783-rtc.o COBJS-y += mc146818.o COBJS-y += mcfrtc.o COBJS-y += mk48t59.o diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c new file mode 100644 index 0000000..35b1b8b --- /dev/null +++ b/drivers/rtc/mc13783-rtc.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <rtc.h> +#include <spi.h> + +int rtc_get(struct rtc_time *rtc) +{ + u32 day1, day2, time; + u32 reg; + int err, tim, i = 0; + + spi_select(1, 0, SPI_MODE_2 | SPI_CS_HIGH); + + do { + reg = 0x2c000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day1); + + if (err) + return err; + + reg = 0x28000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time); + + if (err) + return err; + + reg = 0x2c000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day2); + + if (err) + return err; + } while (day1 != day2 && i++ < 3); + + tim = day1 * 86400 + time; + to_tm(tim, rtc); + + rtc->tm_yday = 0; + rtc->tm_isdst = 0; + + return 0; +} + +void rtc_set(struct rtc_time *rtc) +{ + u32 time, day, reg; + + time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, + rtc->tm_hour, rtc->tm_min, rtc->tm_sec); + day = time / 86400; + time %= 86400; + + reg = 0x2c000000 | day | 0x80000000; + spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day); + + reg = 0x28000000 | time | 0x80000000; + spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time); +} + +void rtc_reset(void) +{ +}

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Re: [U-Boot-Users] [PATCH 04/13] microblaze: add Emaclite ethernet driver
by Wolfgang Denk 15 Apr '08

15 Apr '08

In message <de470d32d7222874eac8134583889844c80e4bcb.1206711077.git.monstr(a)monstr.eu> you wrote: > From: Michal Simek <monstr(a)monstr.eu> > > > Signed-off-by: Michal Simek <monstr(a)monstr.eu> I see you sneaked this in via your microblaze custodian repo. This was a Bad Thing, and I ask you not to do such things. You were supposed to run this through the Net custodian. Ditto for [PATCH 05/13] microblaze: add Emac ethernet driver Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de You Don't Have To Be 'Damned' To Work Here, But It Helps!!! - Terry Pratchett, _Eric_

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[U-Boot-Users] [PATCH 1/3] New i.MX31 SPI driver
by Guennadi Liakhovetski 15 Apr '08

15 Apr '08

This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- diff --git a/README b/README index 0a04d73..4556e87 100644 --- a/README +++ b/README @@ -1406,6 +1407,11 @@ The following options need to be configured: Currently supported on some MPC8xxx processors. For an example, see include/configs/mpc8349emds.h. + CONFIG_MXC_SPI + + Enables the driver for the SPI controllers on i.MX and MXC + SoCs. Currently only i.MX31 is supported. + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0b7a2df..bc8a104 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-y += mpc8xxx_spi.o +COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c new file mode 100644 index 0000000..da1a9e3 --- /dev/null +++ b/drivers/spi/mxc_spi.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2008 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> + +#ifdef CONFIG_MX27 +/* i.MX27 has a completely wrong register layout and register definitions in the + * datasheet, the correct one is in the Freescale's Linux driver */ + +#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ +"See linux mxc_spi driver from Freescale for details." + +#else + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPIINT 0x0C +#define MXC_CSPIDMA 0x10 +#define MXC_CSPISTAT 0x14 +#define MXC_CSPIPERIOD 0x18 +#define MXC_CSPITEST 0x1C +#define MXC_CSPIRESET 0x00 + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +static unsigned long spi_bases[] = { + 0x43fa4000, + 0x50010000, + 0x53f84000, +}; + +static unsigned long spi_base; + +#endif + +spi_chipsel_type spi_chipsel[] = { + (spi_chipsel_type)0, + (spi_chipsel_type)1, + (spi_chipsel_type)2, + (spi_chipsel_type)3, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +static inline u32 reg_read(unsigned long addr) +{ + return *(volatile unsigned long*)addr; +} + +static inline void reg_write(unsigned long addr, u32 val) +{ + *(volatile unsigned long*)addr = val; +} + +static u32 spi_xchg_single(u32 data, int bitlen) +{ + + unsigned int cfg_reg = reg_read(spi_base + MXC_CSPICTRL); + + if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) { + cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + MXC_CSPICTRL_BITCOUNT(bitlen - 1); + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + } + + reg_write(spi_base + MXC_CSPITXDATA, data); + + cfg_reg |= MXC_CSPICTRL_XCH; + + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + + while (reg_read(spi_base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + ; + + return reg_read(spi_base + MXC_CSPIRXDATA); +} + +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + int n_blks = (bitlen + 31) / 32; + u32 *out_l, *in_l; + int i; + + if ((int)dout & 3 || (int)din & 3) { + printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); + return 1; + } + + if (!spi_base) + spi_select(CONFIG_MXC_SPI_IFACE, (int)chipsel, SPI_MODE_2 | SPI_CS_HIGH); + + for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; + i < n_blks; + i++, in_l++, out_l++, bitlen -= 32) + *in_l = spi_xchg_single(*out_l, bitlen); + + return 0; +} + +void spi_init(void) +{ +} + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode) +{ + unsigned int ctrl_reg; + + if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) || + dev > 3) + return 1; + + spi_base = spi_bases[bus]; + + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(dev) | + MXC_CSPICTRL_BITCOUNT(31) | + MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_EN | + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) + ctrl_reg |= MXC_CSPICTRL_PHA; + if (!(mode & SPI_CPOL)) + ctrl_reg |= MXC_CSPICTRL_POL; + if (mode & SPI_CS_HIGH) + ctrl_reg |= MXC_CSPICTRL_SSPOL; + + reg_write(spi_base + MXC_CSPIRESET, 1); + udelay(1); + reg_write(spi_base + MXC_CSPICTRL, ctrl_reg); + reg_write(spi_base + MXC_CSPIPERIOD, + MXC_CSPIPERIOD_32KHZ); + reg_write(spi_base + MXC_CSPIINT, 0); + + return 0; +} diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index e9c7671..ba9080e 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -37,6 +37,9 @@ #define CCM_UPCTL (CCM_BASE + 0x10) #define CCM_SPCTL (CCM_BASE + 0x18) #define CCM_COSR (CCM_BASE + 0x1C) +#define CCM_CGR0 (CCM_BASE + 0x20) +#define CCM_CGR1 (CCM_BASE + 0x24) +#define CCM_CGR2 (CCM_BASE + 0x28) #define CCMR_MDS (1 << 7) #define CCMR_SBYCS (1 << 4) @@ -118,7 +121,9 @@ #define MUX_CTL_RXD1 0x82 #define MUX_CTL_TXD1 0x83 #define MUX_CTL_CSPI2_MISO 0x84 -/* 0x85 .. 0x8a */ +#define MUX_CTL_CSPI2_SS0 0x85 +#define MUX_CTL_CSPI2_SS1 0x86 +#define MUX_CTL_CSPI2_SS2 0x87 #define MUX_CTL_CSPI2_MOSI 0x8b /* The modes a specific pin can be in diff --git a/include/spi.h b/include/spi.h index 03dc5bc..3a55a68 100644 --- a/include/spi.h +++ b/include/spi.h @@ -24,6 +24,18 @@ #ifndef _SPI_H_ #define _SPI_H_ +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* chipselect active high? */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + /* * The function call pointer type used to drive the chip select. */ @@ -68,6 +80,8 @@ void spi_init(void); * * Returns: 0 on success, not 0 on failure */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode); #endif /* _SPI_H_ */

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Re: [U-Boot-Users] drivers MMCplus for at91sam9x
by Ken.Fuchs＠bench.com 15 Apr '08

15 Apr '08

Pierre Savary wrote: > I use a MMCplus 4GB on my design (with at91sam9260). It's > wired with 4 bits. The MCI controller on the AT91SAM926x family does not support MMCplus. There is no way to support a 4 bit bus, since the MCI controller supports only 1 bit to an MMC chip. The MCI will support a 4 bit SD chip, but I don't think it can be tricked into working with a 4 bit MMC chip (at least not via software alone). The only reasonable solution is switching to a processor that has MMCplus support. Maybe Atmel has been working on one? > Currently U-boot (1.1.5) can't detect correctly the MMC and > so I can't read my Linux kernel Image on the ext3 part of this > MMC. If I use MMC 1GB, it works. Did you add MMCplus commands to the MCI U-Boot driver? You can do this to the extent that these changes do not require the MCI controller to be MMCplus compliant. (The MCI U-Boot driver I'm aware of contains no MMCplus support.) I suggest that you use the u-boot sources available via git. You will get very little support (if any) from the U-Boot ML for two reasons: 1) U-Boot 1.1.5 is extremely old and no one on the list is interested in supporting it. 2) The version of U-Boot 1.1.5 you are using almost certainly has an Atmel patch applied to it that was never accepted into the "official" U-Boot tree. However, ... It appears that someone is working on the AT91SAM9260 within the official U-Boot (git) tree, since the ./include/configs/at91sam9260ek.h file is there. Other file structures like ./cpu/arm926ejs/* seem to be missing some drivers and other support files. I know that the AT91SAM926x specific U-Boot files were never an official part of U-Boot, but that appears to be changing. It is my understanding that the AT91SAM926x support is being completely reworked and integrated with the AT91CAP9 code that has been present in git for over a month already. The AT91CAP9 and AT91SAM926x are very similar and should share a lot of code. Even if the AT91SAM9260 is not quite ready, the AT91CAP9 code should provide the basis of a current U-Boot for the AT91SAM926x family. > Somebody have already use it? Or somebody have already implemented > the ext_csd and high capacity with MMC on another platform? I know that the MCI controller can be used to access 1GB MMCplus chips, but I'm not sure it can be used to access MMCplus chips larger than that. There may be a special MMCplus command that will allow larger chips to be accessed. Try looking for it in your MMCplus chip's manual. Sincerely, Ken Fuchs > -----Original Message----- > From: u-boot-users-bounces(a)lists.sourceforge.net > [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf > Of Pierre Savary > Sent: Tuesday, April 08, 2008 09:32 > To: u-boot-users(a)lists.sourceforge.net > Cc: 'Pierre Ossman' > Subject: [U-Boot-Users] drivers MMCplus for at91sam9x > > > Hi, > I use a MMCplus 4GB on my design (with at91sam9260). It's > wired with 4 bits. > Currently U-boot (1.1.5) can't detect correctly the MMC and > so I can't read > my Linux kernel Image on the ext3 part of this MMC. If I use > MMC 1GB, it > works. > Somebody have already use it? Or somebody have already implemented the > ext_csd and high capacity with MMC on another platform? > I need help. Thanks in advance to help me. > > Regards, > > Pierre > > > -------------------------------------------------------------- > ----------- > This SF.net email is sponsored by the 2008 JavaOne(SM) Conference > Register now and save $200. Hurry, offer ends at 11:59 p.m., > Monday, April 7! Use priority code J8TLD2. > http://ad.doubleclick.net/clk;198757673;13503038;p?http://java .sun.com/javaone _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] How to configure the MPC8313ERDB to support 2x128MB DDR
by Frank Prepelica 15 Apr '08

15 Apr '08

Hi all, I'm using a customized MPC8313ERDB board, which means we replaced the Vitesse switch with a second Marvell PHY and we are using 64MB of NOR flash instead of 8MB. Furthermore we added a second DDR RAM (additional 128MB) on that board. I adapted U-Boot (v1.3.1) to support the 64MB flash memory and the second Marvell PHY. This works really fine. But I got problems when adding the second 128MB RAM module. I just thought I change the value of #define CFG_DDR_SIZE to 256 But after that I see the 128MB of the first RAM module mirrored at address 0x0800 0000. Therefore I guess there's more configuration necessary, of course there is. I don't know where to set the DDRLAWBAR1 to base address 0x0800 0000 because I can't even see DDRLAWBAR0 for the first 128MB RAM module. I found nothing in the MPC8313ERDB.h Could anyone please tell me which defines I have to change or I have to add. Are there further changes necessary in the board specific file sdram.c? Thanks for any hint! Best regards, Frank Prepelica Software Design Engineer Ubidyne GmbH Lise-Meitner-Str.-14 89081 Ulm - Germany Phone: +49 731 88 00 71 58 Fax: +49 731 88 00 71 99 Email: frank.prepelica(a)ubidyne.com Homepage: www.ubidyne.com <http://www.ubidyne.com>

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[U-Boot-Users] [PATCH v2 3/7] add an i2c driver for mx31
by Guennadi Liakhovetski 15 Apr '08

15 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds an i2c driver for Freescale i.MX processors Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- No changes wrt v1 drivers/i2c/Makefile | 1 + drivers/i2c/mxc_i2c.c | 202 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 203 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/mxc_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29d6c03..071ef00 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-y += fsl_i2c.o COBJS-y += omap1510_i2c.o COBJS-y += omap24xx_i2c.o COBJS-y += tsi108_i2c.o +COBJS-y += mxc_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c new file mode 100644 index 0000000..a218329 --- /dev/null +++ b/drivers/i2c/mxc_i2c.c @@ -0,0 +1,202 @@ +/* + * i2c driver for Freescale mx31 + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_HARD_I2C) && defined (CONFIG_I2C_MXC) + +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +#define IADR 0x00 +#define IFDR 0x04 +#define I2CR 0x08 +#define I2SR 0x0c +#define I2DR 0x10 + +#define I2CR_IEN (1 << 7) +#define I2CR_IIEN (1 << 6) +#define I2CR_MSTA (1 << 5) +#define I2CR_MTX (1 << 4) +#define I2CR_TX_NO_AK (1 << 3) +#define I2CR_RSTA (1 << 2) + +#define I2SR_ICF (1 << 7) +#define I2SR_IBB (1 << 5) +#define I2SR_IIF (1 << 1) +#define I2SR_RX_NO_AK (1 << 0) + +#ifdef CFG_I2C_MX31_PORT1 +#define I2C_BASE 0x43f80000 +#elif defined (CFG_I2C_MX31_PORT2) +#define I2C_BASE 0x43f98000 +#elif defined (CFG_I2C_MX31_PORT3) +#define I2C_BASE 0x43f84000 +#else +#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver" +#endif + +#ifdef DEBUG +#define DPRINTF(args...) printf(args) +#else +#define DPRINTF(args...) +#endif + +static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, + 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, + 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; + +void i2c_init(int speed, int unused) +{ + int freq = mx31_get_ipg_clk(); + int i; + + for (i = 0; i < 0x1f; i++) + if (freq / div[i] <= speed) + break; + + DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); + + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + IFDR) = i; + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + __REG16(I2C_BASE + I2SR) = 0; +} + +static int wait_busy(void) +{ + int timeout = 10000; + + while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + udelay(1); + __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + + return timeout; +} + +static int tx_byte(u8 byte) +{ + __REG16(I2C_BASE + I2DR) = byte; + + if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + return -1; + return 0; +} + +static int rx_byte(void) +{ + if (!wait_busy()) + return -1; + + return __REG16(I2C_BASE + I2DR); +} + +int i2c_probe(uchar chip) +{ + int ret; + + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + ret = tx_byte(chip << 1); + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + + return ret; +} + +static int i2c_addr(uchar chip, uint addr, int alen) +{ + __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + + if (tx_byte(chip << 1)) + return -1; + + while (alen--) + if (tx_byte((addr >> (alen * 8)) & 0xff)) + return -1; + return 0; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int timeout = 10000; + int ret; + + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + + if (i2c_addr(chip, addr, alen)) { + printf("i2c_addr failed\n"); + return -1; + } + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + + if (tx_byte(chip << 1 | 1)) + return -1; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); + + ret = __REG16(I2C_BASE + I2DR); + + while (len--) { + if ((ret = rx_byte()) < 0) + return -1; + *buf++ = ret; + if (len <= 1) + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; + } + + wait_busy(); + + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + udelay(1); + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int timeout = 10000; + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + + if (i2c_addr(chip, addr, alen)) + return -1; + + while (len--) + if (tx_byte(*buf++)) + return -1; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + udelay(1); + + return 0; +} + +#endif /* CONFIG_HARD_I2C */ -- 1.5.4

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[U-Boot-Users] [PATCH 3/3] mpc83xx: clean up the readme for 83xx boards
by Dave Liu 15 Apr '08

15 Apr '08

1. correct the typo 2. correct the memory map for 837xerdb board Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- doc/README.mpc8313erdb | 4 ++-- doc/README.mpc8315erdb | 2 +- doc/README.mpc837xemds | 2 +- doc/README.mpc837xerdb | 13 ++++++------- 4 files changed, 10 insertions(+), 11 deletions(-) diff --git a/doc/README.mpc8313erdb b/doc/README.mpc8313erdb index 7ad4cc7..21580f9 100644 --- a/doc/README.mpc8313erdb +++ b/doc/README.mpc8313erdb @@ -3,10 +3,10 @@ Freescale MPC8313ERDB Board 1. Board Switches and Jumpers - SW3 is used to set CFG_RESET_SOURCE. + S3 is used to set CFG_RESET_SOURCE. To boot the image at 0xFE000000 in NOR flash, use these DIP - switche settings for SW3 SW4: + switch settings for S3 S4: +------+ +------+ | | | **** | diff --git a/doc/README.mpc8315erdb b/doc/README.mpc8315erdb index c630cf8..e77eba7 100644 --- a/doc/README.mpc8315erdb +++ b/doc/README.mpc8315erdb @@ -6,7 +6,7 @@ Freescale MPC8315ERDB Board S3 is used to set CFG_RESET_SOURCE. To boot the image at 0xFE000000 in NOR flash, use these DIP - switche settings for S3 S4: + switch settings for S3 S4: +------+ +------+ | | | **** | diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds index 3f0cdf7..7823595 100644 --- a/doc/README.mpc837xemds +++ b/doc/README.mpc837xemds @@ -49,7 +49,7 @@ Freescale MPC837xEMDS Board 0xe010_0000 0xe02f_ffff Empty 2M 0xe030_0000 0xe03f_ffff PCI IO 1M 0xe040_0000 0xe05f_ffff Empty 2M - 0xe060_0000 0xe060_8000 NAND Flash 32K + 0xe060_0000 0xe060_7fff NAND Flash 32K 0xf400_0000 0xf7ff_ffff Empty 64M 0xf800_0000 0xf800_7fff BCSR on CS1 32K 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M diff --git a/doc/README.mpc837xerdb b/doc/README.mpc837xerdb index 8f0192a..510e3bb 100644 --- a/doc/README.mpc837xerdb +++ b/doc/README.mpc837xerdb @@ -1,4 +1,4 @@ -Freescale MPC837xEMDS Board +Freescale MPC837xE-RDB Board ----------------------------------------- 1. Board Description @@ -38,12 +38,11 @@ Freescale MPC837xEMDS Board =========================== ================= ======= ========= 0x0000_0000 0x0fff_ffff DDR 256M 64 0x1000_0000 0x7fff_ffff Empty 1.75G - - 0x8000_0000 0x9fff_ffff PCI1 memory space 512M 32 - 0xa000_0000 0xbfff_ffff PCI2 memory space 512M 32 - 0xc200_0000 0xc2ff_ffff PCI1 I/O space 16M 32 - 0xc300_0000 0xc3ff_ffff PCI2 I/O space 16M 32 + 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32 + 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32 + 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - - 0xe280_0000 0xe47f_ffff NAND Flash 32M 8 + 0xe060_0000 0xe060_7fff NAND Flash 32K 8 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16 @@ -55,7 +54,7 @@ Freescale MPC837xEMDS Board CONFIG_MPC83XX MPC83xx family for both MPC8349 and MPC8360 CONFIG_MPC837X MPC837x specific - CONFIG_MPC837XERDB MPC837XEMDS board specific + CONFIG_MPC837XERDB MPC837xE-RDB board specific 4. Compilation -- 1.5.4.rc4

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