April 2008 - U-Boot

[U-Boot-Users] [PATCH] MPC8610HPCD: Drop -O2 from the build flags
by Kumar Gala 03 May '08

03 May '08

Make the flags use -Os like all other boards Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/freescale/mpc8610hpcd/config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk index 64ac4dc..99e7bd4 100644 --- a/board/freescale/mpc8610hpcd/config.mk +++ b/board/freescale/mpc8610hpcd/config.mk @@ -22,4 +22,4 @@ TEXT_BASE = 0xfff00000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -- 1.5.4.1

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[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
by Stefan Roese 03 May '08

03 May '08

The following changes since commit 76617299358ebba260ecc02d33e8e75d8d13dd3b: Wolfgang Denk (1): Prepare v1.3.3-rc2, again. are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Stefan Roese (2): ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module cpu/ppc4xx/44x_spd_ddr2.c | 7 +++++-- nand_spl/board/amcc/canyonlands/ddr2_fixed.c | 12 +++++++----- 2 files changed, 12 insertions(+), 7 deletions(-)

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[U-Boot-Users] [PATCH] RTC: Fix month offset by one problem in M41T62 RTC driver
by Stefan Roese 03 May '08

03 May '08

This patch fixes a problem with the month being read and written incorrectly (offset by one). This only gets visible by also using the Linux driver (rtc-m41t80). Tested on AMCC Canyonlands. Signed-off-by: Stefan Roese <sr(a)denx.de> --- Wolfgang, could you please apply this for 1.3.3? Thanks. drivers/rtc/m41t62.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index cf2a957..89d4ccd 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -81,7 +81,7 @@ int rtc_get(struct rtc_time *tm) tm->tm_hour = BCD2BIN(buf[M41T62_REG_HOUR] & 0x3f); tm->tm_mday = BCD2BIN(buf[M41T62_REG_DAY] & 0x3f); tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07; - tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f) - 1; + tm->tm_mon = BCD2BIN(buf[M41T62_REG_MON] & 0x1f); /* assume 20YY not 19YY, and ignore the Century Bit */ /* U-Boot needs to add 1900 here */ @@ -119,7 +119,7 @@ void rtc_set(struct rtc_time *tm) buf[M41T62_REG_DAY] = BIN2BCD(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f); buf[M41T62_REG_MON] = - BIN2BCD(tm->tm_mon + 1) | (buf[M41T62_REG_MON] & ~0x1f); + BIN2BCD(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f); /* assume 20YY not 19YY */ buf[M41T62_REG_YEAR] = BIN2BCD(tm->tm_year % 100); -- 1.5.5.1

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[U-Boot-Users] Configuring U-Boot for MPC8349E in little endian mode
by vivek.trivedi＠wipro.com 02 May '08

02 May '08

Hi, We are using MPC8349E based board in big endian mode. It is working fine with U-Boot 1.1.3 . Now due to some reason we have to configure 8349E in little endian mode. I have modified RCW, HID2 and MSR registers for this and built the U-Boot with -mlittle-endian(gcc 3.4.3) and -EL (ld option ). Now code is starting properly in Start.S but it is jumping to alignment vector(0x600) whenever it hits a branch instruction(b , bl). Then it stops at 0x63F in alignment exception vector handler. Has any one tried configuring U-Boot for MPC8349E in little endian mode ...? We have also tried to build U-Boot with -mstrict-align option, but it has not helped us. Are we missing any alignment option in gcc for compiling U-Boot. Any help will be appreciated. Thanks, Vivek Trivedi

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[U-Boot-Users] Memory Size issue @ MPC83xx
by André Schwarz 02 May '08

02 May '08

All, my MPC8343 based system is running fine, but I'm not able to use more than 256MB of memory. Is this a general or known issue ? I'm not quite sure where the problem is since u-boot *seems* to be running fine. Situation : - 2 Micron 16-Bit (2 GBits each) chips soldered down on the board giving 512MByte total. - Connected to CS0 @ 32-Bit memory bus. - memory size defined and recognized correctly - set up CS0_BNDS for 512MB - set up BAT0 + BAT7 for mapping (a single BAT is limited to 256MB). - configure cpu to use high BATs by setting HBE bit in CFG_HID2. - dtb memory size set up correctly and "mtest" works all day from 16M to 500M .... Booting a 2.6.25 kernel crashes during dtb parsing. Limiting memory size to 256MB and skipping BAT7 gives a running system. At first glance this looks like a topic for the linuxppc list. But it *could* also be a u-boot related issue ... Any help is welcome ! regards, André Schwarz MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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[U-Boot-Users] BDI2000 with ppc440epx.
by Leonid 02 May '08

02 May '08

Hi: I have some problem with AMCC PPC440epx CPU when it boots from NAND. I am using sequoia.cfg file. If I do "reset halt" on BDI and then "go", CPU doesn't boot. If I do "reset run" it boots OK. That points on some potential problem in .cfg file. OK, I removed entire [INIT] section, but situation didn't change. Moreover, when I set breakpoint to the function which surely is invoked and do "reset run", I don't hit breakpoint (CPU boots till the end). Do you have any idea what I may be doing wrong? Thanks, Leonid.

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[U-Boot-Users] [PATCH v2] smc911x: add 16 bit support
by Jens Gehrlein 30 Apr '08

30 Apr '08

Incorporated Ben's, Magnus's and Guennadi's proposals. Thank you for reviewing. Signed-off-by: Jens Gehrlein <sew_s(a)tqs.de> --- drivers/net/smc911x.c | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index d22c889..bd82cf7 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -30,6 +30,10 @@ #include <net.h> #include <miiphy.h> +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && defined (CONFIG_DRIVER_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and CONFIG_DRIVER_SMC911X_16_BIT shall be set" +#endif + #ifdef CONFIG_DRIVER_SMC911X_32_BIT static inline u32 reg_read(u32 addr) { @@ -39,9 +43,20 @@ static inline void reg_write(u32 addr, u32 val) { *(volatile u32*)addr = val; } +#elif CONFIG_DRIVER_SMC911X_16_BIT +static inline u32 reg_read(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void reg_write(u32 addr, u32 val) +{ + *(volatile u16*)addr = (u16)val; + *(volatile u16*)(addr + 2) = (u16)(val >> 16); +} #else -#error "SMC911X: Only 32-bit bus is supported" -#endif +#error "SMC911X: undefined buswidth" +#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ #define mdelay(n) udelay((n)*1000)

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[U-Boot-Users] Problems with 1.3.3-rc1 on i.MX31ADS
by Felix Radensky 30 Apr '08

30 Apr '08

Hi, I've installed 1.3.3-rc1 on i.MX31ADS evaluation board and encountered several problems 1. loadaddr environment variable (as reported by printenv) is defined as loadaddr=(0x80000000 + 0x800000) This results in image loaded at address 0x0, and boot gets stuck. Redefining loadaddr as 0x80800000 fixes the problem. 2. dhcp command is undefined, only bootp is available. Thanks for adding i.mx31 support to u-boot. Hopefully i.mx27 support will follow soon. Felix.

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[U-Boot-Users] [PATCH] Fix calculation of I2C clock for some 86xx chips
by Timur Tabi 30 Apr '08

30 Apr '08

Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- Yes, this is ugly and stupid, but the only alternative is to update each board configuration file with another CONFIG_ option. And yes, this does mean that as new 86xx variants are announced, cpu/mpc86xx/speed.c may need to be updated. cpu/mpc86xx/speed.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 7e884f8..da5b58b 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -105,8 +105,20 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + + /* + * The base clock for I2C depends on the actual SOC. Unfortunately, + * there is no pattern that can be used to determine the frequency, so + * the only choice is to look up the actual SOC number and use the value + * for that SOC. This information is taken from application note + * AN2919. + */ +#ifdef CONFIG_MPC8610 gd->i2c1_clk = sys_info.freqSystemBus; - gd->i2c2_clk = sys_info.freqSystemBus; +#else + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#endif + gd->i2c2_clk = gd->i2c1_clk; if (gd->cpu_clk != 0) return 0; -- 1.5.4

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[U-Boot-Users] [PATCH] ColdFire: Fix ethernet hang issue for mcf547x_8x
by Tsi-Chung Liew 30 Apr '08

30 Apr '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> The ethernet hang is caused by receiving buffer in DRAM is not yet ready due to access cycles require longer time in DRAM. Relocate DMA buffer descriptors from DRAM to internal SRAM. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- drivers/net/fsl_mcdmafec.c | 22 +++++++++++++++++++++- include/configs/M5475EVB.h | 1 + include/configs/M5485EVB.h | 1 + 3 files changed, 23 insertions(+), 1 deletions(-) diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 0c876f3..2ef91f2 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -95,7 +95,11 @@ struct fec_info_dma fec_info[] = { 0, /* duplex and speed */ 0, /* phy name */ 0, /* phy name init */ +#ifdef CFG_DMA_USE_INTSRAM + DBUF_LENGTH, /* RX BD */ +#else 0, /* RX BD */ +#endif 0, /* TX BD */ 0, /* rx Index */ 0, /* tx Index */ @@ -164,7 +168,8 @@ static void dbg_fec_regs(struct eth_device *dev) } #endif -static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, int dup_spd) +static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, + int dup_spd) { if ((dup_spd >> 16) == FULL) { /* Set maximum frame length */ @@ -513,6 +518,9 @@ int mcdmafec_initialize(bd_t * bis) { struct eth_device *dev; int i; +#ifdef CFG_DMA_USE_INTSRAM + u32 tmp = CFG_INTSRAM + 0x2000; +#endif for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { @@ -533,6 +541,17 @@ int mcdmafec_initialize(bd_t * bis) dev->recv = fec_recv; /* setup Receive and Transmit buffer descriptor */ +#ifdef CFG_DMA_USE_INTSRAM + fec_info[i].rxbd = (int)fec_info[i].rxbd + tmp; + tmp = fec_info[i].rxbd; + fec_info[i].txbd = + (int)fec_info[i].txbd + tmp + (PKTBUFSRX * sizeof(cbd_t)); + tmp = fec_info[i].txbd; + fec_info[i].txbuf = + (int)fec_info[i].txbuf + tmp + + (CFG_TX_ETH_BUFFER * sizeof(cbd_t)); + tmp = fec_info[i].txbuf; +#else fec_info[i].rxbd = (cbd_t *) memalign(CFG_CACHELINE_SIZE, (PKTBUFSRX * sizeof(cbd_t))); @@ -541,6 +560,7 @@ int mcdmafec_initialize(bd_t * bis) (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); fec_info[i].txbuf = (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); +#endif #ifdef ET_DEBUG printf("rxbd %x txbd %x\n", diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index 6bb4619..fea7551 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -72,6 +72,7 @@ # define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 +# define CFG_DMA_USE_INTSRAM 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 32 # define CFG_TX_ETH_BUFFER 48 diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index cba51c8..454d0a2 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -72,6 +72,7 @@ # define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 +# define CFG_DMA_USE_INTSRAM 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 32 # define CFG_TX_ETH_BUFFER 48 -- 1.5.4.1

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