April 2008 - U-Boot

[U-Boot-Users] --- NAND for AT91RM9200
by Zhukov 18 Apr '08

18 Apr '08

Hello, people! For ARM at91rm9200, I turn on NAND support. Now any request to address 0x40000000 hangs the u-boot while loading. (This happens on calling "NanD_Command" within function "NanD_IdentChip" within cmd_nand.c). U-boot hangs both with and without Nand chip plugged. It looks like something wrong with SMC or EBI, but I didn't see anything suspicious in those registers. Please help, experienced one! Best regards, Andrew

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[U-Boot-Users] Increase your instrument size
by krafft 18 Apr '08

18 Apr '08

Be true to yourself, get your manhood what he needs today, dont wait any longer. http://www.nuueitao.com/

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[U-Boot-Users] I need Help in U-Boot Interrupt support
by U-Boot User 18 Apr '08

18 Apr '08

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[U-Boot-Users] Your bazooka will explode her
by acevez 18 Apr '08

18 Apr '08

Your make device will make her jaw drop http://www.oeiriueeb.com/

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[U-Boot-Users] U-Boot : USB Slave Mode ?
by Neeraj Jayaswal 18 Apr '08

18 Apr '08

Hi, Does U-Boot support USB Slave mode ? I have an ARM926EJS board with USB-OTG. I can configure it in USB Slave mode using some register settings. But I need to run U-Boot on top of it so that I can access the USB Slave functionality. Kindly suggest how I can use U-Boot in USB Slave mode and what configuration changes are required ? Thanks in Advance. Regards, Neeraj The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments contained in it. Contact your Administrator for further information.

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[U-Boot-Users] EHCI USB 2.0 Patch
by Lance Ware 18 Apr '08

18 Apr '08

Hello, I wanted to know how could I get a hold of the USB 2.0 patch for u-boot. I am currently testing a OHCI/EHCI compliant pci usb device. I have the OHCI part working but would like to have use of the EHCI part of the device from the usb device. Thanks, Lance

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[U-Boot-Users] [PATCH] Fix crash on sequoia in ppc_4xx_eth_init
by Anatolij Gustschin 18 Apr '08

18 Apr '08

Currently U-Boot crashes in ppc_4xx_eth_init on sequoia with cache enabled (TLB Parity exeption). This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- cpu/ppc4xx/4xx_enet.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 007cb4f..c40e0ca 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1083,7 +1083,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #ifdef CONFIG_4xx_DCACHE flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); if (!last_used_ea) +#if defined(CFG_MEM_TOP_HIDE) + bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE; +#else bd_uncached = bis->bi_memsize; +#endif else bd_uncached = last_used_ea + MAL_ALLOC_SIZE; -- 1.5.3.3

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[U-Boot-Users] [PATCH] ppc4xx: Fix crash on sequoia with cache enabled
by Anatolij Gustschin 18 Apr '08

18 Apr '08

Currently U-Boot crashes on sequoia board in CPU POST if cache is enabled (CONFIG_4xx_DCACHE defined). The cache won't be disabled by change_tlb before CPU POST because there is an insufficient adress range check since CFG_MEM_TOP_HIDE was introduced. This patch tries to fix this problem. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- cpu/ppc4xx/tlb.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 2bfcba1..f44822d 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -149,7 +149,9 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) /* * Now check the end-address if it's in the range */ - if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) { + if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) || + ((tlb_vaddr < (vaddr + size - 1)) && + ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) { /* * Found a TLB in the range. * Change cache attribute in tlb2 word. -- 1.5.3.3

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[U-Boot-Users] [PATCH][MIPS] Use jr as register jump instruction
by Shinya Kuribayashi 18 Apr '08

18 Apr '08

Current assembler codes are inconsistent in the way of register jump instruction usage; some use jr, some use j. Of course GNU as allows both usages, but as can be expected from `Jump Register' the mnemonic `jr' is more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage at all. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/dbau1x00/lowlevel_init.S | 2 +- board/gth2/lowlevel_init.S | 2 +- board/incaip/lowlevel_init.S | 8 ++++---- board/pb1x00/lowlevel_init.S | 2 +- board/purple/lowlevel_init.S | 2 +- board/qemu-mips/lowlevel_init.S | 2 +- cpu/mips/cache.S | 4 ++-- cpu/mips/incaip_wdt.S | 2 +- cpu/mips/start.S | 6 +++--- 9 files changed, 15 insertions(+), 15 deletions(-) diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 14a7846..27b51f7 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -586,5 +586,5 @@ noCacheJump: sw t1, 0(t0) sync - j ra + jr ra nop diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index eea378a..bf615c1 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -450,7 +450,7 @@ mtc: sw zero, 0(t0) nop nop memtestend: - j ra + jr ra nop memhang: diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index b39f93d..08f7f21 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -105,7 +105,7 @@ __ebu_init: li t2, 0x684143FD sw t2, EBU_BUSCON1(t1) 3: - j ra + jr ra nop .end ebu_init @@ -170,7 +170,7 @@ __cgu_init: li t2, 0x80000001 sw t2, CGU_MUXCR(t1) 5: - j ra + jr ra nop .end cgu_init @@ -266,7 +266,7 @@ __sdram_init: li t2, 0x00000001 sw t2, MC_CTRLENA(t1) - j ra + jr ra nop .end sdram_init @@ -298,7 +298,7 @@ lowlevel_init: nop move ra, t0 - j ra + jr ra nop .end lowlevel_init diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S index e851e2f..98bb394 100644 --- a/board/pb1x00/lowlevel_init.S +++ b/board/pb1x00/lowlevel_init.S @@ -388,5 +388,5 @@ skip_memsetup: */ sync - j ra + jr ra nop diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S index 668124a..b9d03fc 100644 --- a/board/purple/lowlevel_init.S +++ b/board/purple/lowlevel_init.S @@ -33,5 +33,5 @@ lowlevel_init: li t0, MC_IOGP li t1, 0xf24 sw t1, 0(t0) - j ra + jr ra nop diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S index 28166bc..836e027 100644 --- a/board/qemu-mips/lowlevel_init.S +++ b/board/qemu-mips/lowlevel_init.S @@ -37,5 +37,5 @@ lowlevel_init: mtc0 zero, CP0_WIRED nop - j ra + jr ra nop diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index 89ada71..f593968 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -282,7 +282,7 @@ LEAF(dcache_disable) and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG - j ra + jr ra END(dcache_disable) #ifdef CFG_INIT_RAM_LOCK_MIPS @@ -308,7 +308,7 @@ mips_cache_lock: move a1, a2 icacheop(a0,a1,a2,a3,0x1d) - j ra + jr ra .end mips_cache_lock #endif /* CFG_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 71adaa1..2ebcc91 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -68,5 +68,5 @@ disable_incaip_wdt: li t1, WD_WRITE_ENDINIT sw t1, WD_CON0(t0) /* end command */ - j ra + jr ra nop diff --git a/cpu/mips/start.S b/cpu/mips/start.S index baac2ce..6e1a78c 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -286,7 +286,7 @@ reset: la sp, 0(t0) la t9, board_init_f - j t9 + jr t9 nop /* @@ -342,7 +342,7 @@ relocate_code: /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start - j t0 + jr t0 nop .gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */ @@ -387,7 +387,7 @@ in_ram: move a0, a1 la t9, board_init_r - j t9 + jr t9 move a1, a2 /* delay slot */ .end relocate_code

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[U-Boot-Users] [PATCH v2 2/3] RTC driver for MC13783
by Guennadi Liakhovetski 18 Apr '08

18 Apr '08

MC13783 is a multifunction IS with an SPI interface to the host. This driver handles the RTC controller in this chip. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: update to current git HEAD README | 1 + drivers/rtc/Makefile | 1 + drivers/rtc/mc13783-rtc.c | 82 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/mc13783-rtc.c diff --git a/README b/README index d201b92..7c5f9a0 100644 --- a/README +++ b/README @@ -672,6 +672,7 @@ The following options need to be configured: CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC + CONFIG_RTC_MC13783 - use MC13783 RTC CONFIG_RTC_MC146818 - use MC146818 RTC CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 800ab99..2e0c118 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -45,6 +45,7 @@ COBJS-y += m41t60.o COBJS-$(CONFIG_RTC_M41T62) += m41t62.o COBJS-y += m48t35ax.o COBJS-y += max6900.o +COBJS-$(CONFIG_RTC_MC13783) += mc13783-rtc.o COBJS-y += mc146818.o COBJS-y += mcfrtc.o COBJS-y += mk48t59.o diff --git a/drivers/rtc/mc13783-rtc.c b/drivers/rtc/mc13783-rtc.c new file mode 100644 index 0000000..35b1b8b --- /dev/null +++ b/drivers/rtc/mc13783-rtc.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <rtc.h> +#include <spi.h> + +int rtc_get(struct rtc_time *rtc) +{ + u32 day1, day2, time; + u32 reg; + int err, tim, i = 0; + + spi_select(1, 0, SPI_MODE_2 | SPI_CS_HIGH); + + do { + reg = 0x2c000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day1); + + if (err) + return err; + + reg = 0x28000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time); + + if (err) + return err; + + reg = 0x2c000000; + err = spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day2); + + if (err) + return err; + } while (day1 != day2 && i++ < 3); + + tim = day1 * 86400 + time; + to_tm(tim, rtc); + + rtc->tm_yday = 0; + rtc->tm_isdst = 0; + + return 0; +} + +void rtc_set(struct rtc_time *rtc) +{ + u32 time, day, reg; + + time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday, + rtc->tm_hour, rtc->tm_min, rtc->tm_sec); + day = time / 86400; + time %= 86400; + + reg = 0x2c000000 | day | 0x80000000; + spi_xfer(0, 32, (uchar *)&reg, (uchar *)&day); + + reg = 0x28000000 | time | 0x80000000; + spi_xfer(0, 32, (uchar *)&reg, (uchar *)&time); +} + +void rtc_reset(void) +{ +} -- 1.5.4

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