February 2008 - U-Boot

[U-Boot-Users] [PATCH] Flex-OneNAND booting support
by Kyungmin Park 16 Mar '08

16 Mar '08

Flex-OneNAND booting support Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that would otherwise have to use more NOR components. Flex-OneNAND enables users to configure to partition it into SLC and MLC areas in more flexible way. While MLC area of Flex-OneNAND can be used to store data that require low reliability and high density, SLC area of Flex-OneNAND to store data that need high reliability and high performance. Flex-OneNAND can let users take advantage of storing these two different types of data into one chip, which is making Flex-OneNAND more cost- and space-effective. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/Makefile b/Makefile index 9512b71..e9010b6 100644 --- a/Makefile +++ b/Makefile @@ -333,10 +333,12 @@ $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all + $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all $(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk + $(MAKE) -C $(obj)onenand_ipl/board/$(BOARDDIR) all cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin + cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin $(VERSION_FILE): @( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \ @@ -2914,7 +2916,9 @@ clean: @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map @rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \ - $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map + $(obj)onenand_ipl/onenand-ipl-2k.bin \ + $(obj)onenand_ipl/onenand-ipl-4k.bin \ + $(obj)onenand_ipl/onenand-ipl.map @rm -f $(obj)api_examples/demo $(VERSION_FILE) clobber: clean diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index d4003a2..3b828fb 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -1180,6 +1180,12 @@ static int onenand_probe(struct mtd_info *mtd) if (maf_id != bram_maf_id || dev_id != bram_dev_id) return -ENXIO; + /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */ + if (dev_id & (1 << 9)) { + printk("Not yet support Flex-OneNAND\n"); + return -ENXIO; + } + /* Flash device information */ onenand_print_device_info(dev_id, 0); this->device_id = dev_id; diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile index 66a0959..f10ed02 100644 --- a/onenand_ipl/board/apollon/Makefile +++ b/onenand_ipl/board/apollon/Makefile @@ -9,7 +9,7 @@ AFLAGS += -DCONFIG_ONENAND_IPL CFLAGS += -DCONFIG_ONENAND_IPL OBJCLFAGS += --gap-fill=0x00 -SOBJS = start.o low_levelinit.o # _memcpy32.o +SOBJS = start.o low_levelinit.o COBJS = apollon.o onenand_read.o onenand_boot.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -19,13 +19,16 @@ LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) onenandobj := $(OBJTREE)/onenand_ipl/ -ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin +ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin all: $(obj).depend $(ALL) $(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@ +$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@ + $(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S diff --git a/onenand_ipl/onenand_boot.c b/onenand_ipl/onenand_boot.c index f30deae..35668ac 100644 --- a/onenand_ipl/onenand_boot.c +++ b/onenand_ipl/onenand_boot.c @@ -60,7 +60,7 @@ void start_oneboot(void) buf = (uchar *) CFG_LOAD_ADDR; - if (!onenand_read_block(buf, ONENAND_START_BLOCK)) + if (!onenand_read_block0(buf)) buf += ONENAND_BLOCK_SIZE; if (buf == (uchar *)CFG_LOAD_ADDR) diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h index b9c6669..9188b96 100644 --- a/onenand_ipl/onenand_ipl.h +++ b/onenand_ipl/onenand_ipl.h @@ -23,7 +23,6 @@ #include <linux/mtd/onenand_regs.h> -#define ONENAND_START_BLOCK 0 #define ONENAND_BLOCK_SIZE 2048 #ifndef CFG_PRINTF @@ -40,5 +39,5 @@ #define ONENAND_PAGE_SIZE 2048 -extern int onenand_read_block(unsigned char *buf, ulong block); +extern int onenand_read_block0(unsigned char *buf); #endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c index f553220..a0c4acf 100644 --- a/onenand_ipl/onenand_read.c +++ b/onenand_ipl/onenand_read.c @@ -33,8 +33,12 @@ #define onenand_buffer_address() ((1 << 3) << 8) #define onenand_bufferram_address(block) (0) +#ifdef __HAVE_ARCH_MEMCPY32 +extern void *memcpy32(void *dest, void *src, int size); +#endif + /* read a page with ECC */ -static inline int onenand_read_page(ulong block, ulong page, u_char *buf) +static inline int onenand_read_page(ulong block, ulong page, u_char *buf, int pagesize) { unsigned long *base; @@ -46,15 +50,15 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) onenand_writew(onenand_block_address(block), THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + onenand_writew(onenand_bufferram_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + onenand_writew(onenand_sector_address(page), THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); onenand_writew(onenand_buffer_address(), THIS_ONENAND(ONENAND_REG_START_BUFFER)); - onenand_writew(onenand_bufferram_address(block), - THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); - onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); @@ -69,9 +73,9 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) #ifdef __HAVE_ARCH_MEMCPY32 /* 32 bytes boundary memory copy */ - memcpy32(buf, base, ONENAND_PAGE_SIZE); + memcpy32(buf, base, pagesize); #else - for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { + for (offset = 0; offset < (pagesize >> 2); offset++) { value = *(base + offset); *p++ = value; } @@ -87,18 +91,22 @@ static inline int onenand_read_page(ulong block, ulong page, u_char *buf) * onenand_read_block - Read a block data to buf * @return 0 on success */ -int onenand_read_block(unsigned char *buf, ulong block) +int onenand_read_block0(unsigned char *buf) { int page, offset = 0; + int pagesize = ONENAND_PAGE_SIZE; + + /* MLC OneNAND has 4KiB page size */ + if (onenand_readw(THIS_ONENAND(ONENAND_REG_TECHNOLOGY))) + pagesize <<= 1; /* NOTE: you must read page from page 1 of block 0 */ /* read the block page by page*/ for (page = ONENAND_START_PAGE; page < ONENAND_PAGES_PER_BLOCK; page++) { - onenand_read_page(block, page, buf + offset); - - offset += ONENAND_PAGE_SIZE; + onenand_read_page(0, page, buf + offset, pagesize); + offset += pagesize; } return 0;

2 1

[U-Boot-Users] [PATCH] Add support for Intersil isl1208 RTC
by Tor Krill 13 Mar '08

13 Mar '08

Signed-off-by: Tor Krill <tor(a)excito.com> --- README | 1 + drivers/rtc/Makefile | 1 + drivers/rtc/isl1208.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 178 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/isl1208.c diff --git a/README b/README index 491397a..b230fde 100644 --- a/README +++ b/README @@ -669,6 +669,7 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC Note that if the RTC uses I2C, then the I2C interface diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af2bf4..a0d3472 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -53,6 +53,7 @@ COBJS-y += rs5c372.o COBJS-y += rx8025.o COBJS-y += mcfrtc.o COBJS-y += x1205.o +COBJS-y += isl1208.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c new file mode 100644 index 0000000..d52d23d --- /dev/null +++ b/drivers/rtc/isl1208.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2008 + * Tor Krill, Excito Elektronik i Skåne , tor(a)excito.com + * + * Modelled after the ds1337 driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support (no alarms) for Intersil + * ISL1208 Real Time Clock (RTC). + */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> + +#if defined(CONFIG_RTC_ISL1208) && defined(CONFIG_CMD_DATE) + +/*---------------------------------------------------------------------*/ +#undef DEBUG_RTC + +#ifdef DEBUG_RTC +#define DEBUGR(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGR(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/* + * RTC register addresses + */ + +#define RTC_SEC_REG_ADDR 0x0 +#define RTC_MIN_REG_ADDR 0x1 +#define RTC_HR_REG_ADDR 0x2 +#define RTC_DATE_REG_ADDR 0x3 +#define RTC_MON_REG_ADDR 0x4 +#define RTC_YR_REG_ADDR 0x5 +#define RTC_DAY_REG_ADDR 0x6 +#define RTC_STAT_REG_ADDR 0x7 +/* + * RTC control register bits + */ + +/* + * RTC status register bits + */ +#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */ +#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */ +#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */ +#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */ +#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ +#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ + +static uchar rtc_read (uchar reg); +static void rtc_write (uchar reg, uchar val); +static uchar bin2bcd (unsigned int n); +static unsigned bcd2bin (uchar c); + +/* + * Get the current time from the RTC + */ + +void rtc_get (struct rtc_time *tmp) +{ + uchar sec, min, hour, mday, wday, mon, year, status; + + status = rtc_read (RTC_STAT_REG_ADDR); + sec = rtc_read (RTC_SEC_REG_ADDR); + min = rtc_read (RTC_MIN_REG_ADDR); + hour = rtc_read (RTC_HR_REG_ADDR); + wday = rtc_read (RTC_DAY_REG_ADDR); + mday = rtc_read (RTC_DATE_REG_ADDR); + mon = rtc_read (RTC_MON_REG_ADDR); + year = rtc_read (RTC_YR_REG_ADDR); + + DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x status: %02x\n", + year, mon, mday, wday, hour, min, sec, status); + + if (status & RTC_STAT_BIT_RTCF) { + printf ("### Warning: RTC oscillator has stopped\n"); + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF)); + } + + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon & 0x1F); + tmp->tm_year = bcd2bin (year)+2000; + tmp->tm_wday = bcd2bin (wday & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +} + +/* + * Set the RTC + */ +void rtc_set (struct rtc_time *tmp) +{ + DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + /* enable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC); + + rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); + rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); + rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */ + rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + + /* disable write */ + rtc_write(RTC_STAT_REG_ADDR, + rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC); +} + +void rtc_reset (void) +{ +} + +/* + * Helper functions + */ + +static +uchar rtc_read (uchar reg) +{ + return (i2c_reg_read (CFG_I2C_RTC_ADDR, reg)); +} + + +static void rtc_write (uchar reg, uchar val) +{ + i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + + +#endif -- 1.5.3.7

2 2

[U-Boot-Users] [PATCH 0/2] Vitesse VSC7385 firmware patches
by Timur Tabi 12 Mar '08

12 Mar '08

These two patches add the ability to upload firmware to the Vitesse VSC7385 and update some Freescale 83xx board files to use them. These patches are for U-Boot 1.3.3.

4 10

[U-Boot-Users] [PATCH] 83xx: Add support for CFG_I2C_SPEED in fsl_i2c.c
by Timur Tabi 11 Mar '08

11 Mar '08

Add support to fsl_i2c.c for setting and querying the I2C bus speed. Current 83xx boards define the CFG_I2C_SPEED, but fsl_i2c.c ignores the value and uses a conservative value of 0x3F when programming the I2C bus speed. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- Unfortunately, only 83xx calculates and stores the I2C clock frequencies, so this code is compiled on 83xx only. cpu/mpc83xx/cpu.c | 24 +++++++++++ drivers/i2c/fsl_i2c.c | 90 ++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/fsl_i2c.h | 23 ++++++++++ include/configs/MPC832XEMDS.h | 1 + 4 files changed, 137 insertions(+), 1 deletions(-) diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index f1ea17d..51cb1b7 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -716,3 +716,27 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ + +#ifdef CFG_I2C_SPEED +/* + * Map the frequency divider to the FDR. This data is taken from table 17-5 + * of the MPC8349EA reference manual, with duplicates removed. It also applies + * to the 8360. + */ +struct fsl_i2c_speed_map fsl_i2c_speed_map[] = { + {256, 0x20}, {288, 0x21}, {320, 0x22}, {352, 0x23}, + {384, 0x24}, {416, 0x01}, {448, 0x25}, {480, 0x02}, + {512, 0x26}, {576, 0x27}, {640, 0x28}, {704, 0x05}, + {768, 0x29}, {832, 0x06}, {896, 0x2A}, {1024, 0x2B}, + {1152, 0x08}, {1280, 0x2C}, {1536, 0x2D}, {1792, 0x2E}, + {1920, 0x0B}, {2048, 0x2F}, {2304, 0x0C}, {2560, 0x30}, + {3072, 0x31}, {3584, 0x32}, {3840, 0x0F}, {4096, 0x33}, + {4608, 0x10}, {5120, 0x34}, {6144, 0x35}, {7168, 0x36}, + {7680, 0x13}, {8192, 0x37}, {9216, 0x14}, {10240, 0x38}, + {12288, 0x39}, {14336, 0x3A}, {15360, 0x17}, {16384, 0x3B}, + {18432, 0x18}, {20480, 0x3C}, {24576, 0x3D}, {28672, 0x3E}, + {30720, 0x1B}, {32768, 0x3F}, {36864, 0x1C}, {40960, 0x1D}, + {49152, 0x1E}, {61440, 0x1F}, + {-1, 0x1F} +}; +#endif diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 22485ea..bca2c75 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -32,6 +32,8 @@ #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 +DECLARE_GLOBAL_DATA_PTR; + /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 0. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify @@ -43,6 +45,8 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif +static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; + static volatile struct fsl_i2c *i2c_dev[2] = { (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), #ifdef CFG_I2C2_OFFSET @@ -50,6 +54,53 @@ static volatile struct fsl_i2c *i2c_dev[2] = { #endif }; +#ifdef CONFIG_MPC83XX +/* Currently, only 83xx determines and stores the I2C clock frequency */ + +#ifdef CFG_I2C_SPEED +/* Define a default I2C speed map if a real map isn't defined elsewhere */ +#pragma weak fsl_i2c_speed_map = default_fsl_i2c_speed_map + +struct fsl_i2c_speed_map default_fsl_i2c_speed_map[] = { + {0, 0x3F}, {-1, 0x3F} +}; +#endif + +/* + * Get the I2C FDR value for a given I2C clock and a given I2C bus speed + */ +static u8 get_fdr(unsigned int i2c_clk, unsigned int speed) +{ +#ifdef CFG_I2C_SPEED + extern struct fsl_i2c_speed_map fsl_i2c_speed_map[]; + unsigned int d; /* The I2C clock divider */ + unsigned int i = 0; + unsigned int low, high; + + d = i2c_clk / speed; + + /* Scan fsl_i2c_speed_map[] for the closest matching divider.*/ + + while (fsl_i2c_speed_map[i].divider != (unsigned int) -1) { + low = fsl_i2c_speed_map[i].divider; + high = fsl_i2c_speed_map[i+1].divider; + + if ((d >= low) && (d <= high)) { + /* Which one is closer? */ + if ((d - low) < (high - d)) + return fsl_i2c_speed_map[i].fdr; + else + return fsl_i2c_speed_map[i+1].fdr; + break; + } + i++; + } +#endif + + return 0x3F; /* Use a conservative value as the default */ +} +#endif /* CONFIG_MPC83XX */ + void i2c_init(int speed, int slaveadd) { @@ -59,23 +110,37 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + writeb(get_fdr(gd->i2c1_clk, speed), &dev->fdr); /* set bus speed */ +#else writeb(0x3F, &dev->fdr); /* set bus speed */ +#endif writeb(0x3F, &dev->dfsrr); /* set default filter */ writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + i2c_bus_speed[0] = speed; + #ifdef CFG_I2C2_OFFSET dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + writeb(get_fdr(gd->i2c2_clk, speed), &dev->fdr); /* set bus speed */ +#else writeb(0x3F, &dev->fdr); /* set bus speed */ +#endif writeb(0x3F, &dev->dfsrr); /* set default filter */ writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#endif /* CFG_I2C2_OFFSET */ + + i2c_bus_speed[1] = speed; +#endif } static __inline__ int @@ -279,7 +344,23 @@ int i2c_set_bus_num(unsigned int bus) int i2c_set_bus_speed(unsigned int speed) { +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + + unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; + u8 fdr = get_fdr(i2c_clk, speed); + + printf("Writing %x to FDR\n", fdr); + writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ + writeb(fdr, &i2c_dev[i2c_bus_num]->fdr); /* set bus speed */ + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ + + i2c_bus_speed[i2c_bus_num] = speed; + + return 0; +#else return -1; +#endif } unsigned int i2c_get_bus_num(void) @@ -289,7 +370,14 @@ unsigned int i2c_get_bus_num(void) unsigned int i2c_get_bus_speed(void) { +#ifdef CONFIG_MPC83XX + /* Currently, only 83xx determines and stores the I2C clock frequency */ + + return i2c_bus_speed[i2c_bus_num]; +#else return 0; +#endif } + #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ diff --git a/include/asm-ppc/fsl_i2c.h b/include/asm-ppc/fsl_i2c.h index 4f71341..f84a803 100644 --- a/include/asm-ppc/fsl_i2c.h +++ b/include/asm-ppc/fsl_i2c.h @@ -83,4 +83,27 @@ typedef struct fsl_i2c { u8 res6[0xE8]; } fsl_i2c_t; +/* + * Map I2C frequency dividers to FDR values + * + * This structure is used to define the elements of a table that maps I2C + * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be + * programmed into the Frequency Divider Ratio (FDR) register. + * + * The actual table should be defined in the board file, and it must be called + * fsl_i2c_speed_map[]. + * + * The first entry must be {0, X}, where X == fsl_i2c_speed_map[1].fdr. + * + * The last entry of the table must have a value of {-1,x}, where x is same + * FDR value as the second-to-last entry. + * + * The values of the divider must be in increasing numerical order, i.e. + * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. + */ +typedef struct fsl_i2c_speed_map { + unsigned int divider; + u8 fdr; +} fsl_i2c_speed_map_t; + #endif /* _ASM_I2C_H_ */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c9c6d88..d5e588a 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -335,6 +335,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CONFIG_I2C_CMD_TREE /* * Config on-board RTC -- 1.5.2.4

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Re: [U-Boot-Users] Flash write crash on MPC8548CDS
by Andy Fleming 10 Mar '08

10 Mar '08

> It is too late today but tomorrow I will try to write something in Flash > with cp.b and check if this still happens. > > Everything works OK with the old U-Boot that came with CDS though... Ok, I found the problem. Check my tree (u-boot-mpc85xx.git) now. It's got a patch which removes the mappings for INIT_RAM, thus preventing speculative loads from going out on the bus. Andy

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[U-Boot-Users] Regarding Dcache Flush in MPC85xx
by s.balamurugan 04 Mar '08

04 Mar '08

Hi, We are using MPC8555 processor and uboot 1.1.4 both the uboot and linux was up. Now we plan to port QNX, we are facing following issues. 1. Qnx is not jumping to the startup location. After giving go command control is still in the uboot only. 2. When searching in the mailling list we came to know qnx required to flush the Data Cache before disabling it in the uboot level (common/cmd_bootelf.c line no:59) 3. I checked other powerpc architecture like 7xx/74xx, 86xx and 4xx. These architecture has seperate cache.S file ( cpu/mpc86xx/cache.S). That file contains flush_data_cache function to flush the cache before disabling it. But in the MPC85xx flushing the data cache was missing. 4. This is a bug in the 85xx uboot code. Is there any work arround for this? Thanks and Regards S.Balamurugan

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[U-Boot-Users] CramFS endianness
by Laurent Pinchart 04 Mar '08

04 Mar '08

Hi everybody, I recently had a problem with cramfs endianness. cramfs tools generates a host-endian file system, which was incompatible with my big-endian MPC8260 system. I patched mkcramfs to reverse the bit order, and was able to read the cramfs image from Linux. However, even though Linux doesn't do any byte swapping, U-Boot assumes little-endian byte order and swap bytes on big-endian architectures. Why is that ? U-Boot and Linux are clearly not compatible on big-endian architectures, and I'd like to fix the problem in the right place. Laurent Pinchart

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[U-Boot-Users] latest u-boot (1.3.2-rc2) and dataflash vs CFG_NO_FLASH
by Matt Gessner 03 Mar '08

03 Mar '08

Hi, again, OK, I've got a NAND flash, SPI Dataflash, and no "real" flash (NOR, I suppose). If I try to copy from Ram to dataflash, u-boot says "Copy to Flash..." and the CPU pukes; it's detecting what it thinks is flash. If I #define CFG_NO_FLASH, other stuff breaks. If I fix that by changing include/flash.h to remove the #ifndef CFG_NO_FLASH, then everything compiles, but on the link, all of the flash stuff that I DO need (flash_info, flash_erase, etc) isn't defined because of CFG_NO_FLASH. Has this been fixed ANYWHERE in someone's branch? Wolfgang, I know you don't really care much about non-memory flash "devices" but is there some vision as to where all this is supposed to go? Thanks in advance, Matt Gessner mgessner(a)avidyne.com Avidyne Corp Safety Systems Group Columbus, OH

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[U-Boot-Users] 1.3.2-rc2 83xx CONFIG_HAS_ETHX not passing MAC addresses
by Marc Leeman 03 Mar '08

03 Mar '08

When booting an 8347 processor, the MAC addresses (ethaddr and eth1addr) don't seem to get passed anymore. I modified my config to include CONFIG_HAS_ETH0 and CONFIG_HAS_ETH1 and I am entering the code in fdt_fixup_ethernet (common/fdt_support.c) but get stuck at node = fdt_path_offset(fdt, "/aliases"); Once this fails, the MAC addresses are not passed along. Any search on [mleeman@neo linux-2.6.24]$ grep aliases arch/powerpc/boot/dts|wc -l 0 turns up empty for the 2.6.24 kernels, looking for "aliases" in the kernel Documentation does not give a hit that seems relevant for device trees. and the only ref that seems to be on topic is: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/36004 Is this using some dts node that is not yet in the released kernel (2.6.24) [1]? [1] It's probably something I missed since I found this one too: http://patchwork.ozlabs.org/linuxppc/patch?id=12671 -- greetz, marc Human. It's kinda like Sebacean, but we haven't conquered other worlds yet, so we just kick the crap out of each other. Crichton - PK Tech Girl chiana 2.6.18-4-ixp4xx #1 Tue Mar 27 18:01:56 BST 2007 GNU/Linux

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[U-Boot-Users] Contribution: EHCI USB HC driver
by Marcel Moolenaar 03 Mar '08

03 Mar '08

All, Juniper Networks wrote a driver for the EHCI UCB HC and I'd like to contribute that back if there's interest. Besides a new piece of code, this also changes some of the common USB code so that high-speed devices and split-transactions are supported. At this time the EHCI driver is exclusive in that there's no support for having the companion controller active. I presume this is one of the major themes for adding EHCI support, so that's definitely open for discussion. Attached a patch with the common code changes as well as the EHCI driver itself. The patch does not contain any changes to get it built (i.e. included in libusb, etc). A seasoned U-Boot developer should have no problem playing with it, while the details are being worked out for getting this alongside a USB 1.1 HC driver. Comments and suggestions are welcome. Please let me know how best to move forward with adding this to U-Boot, provided there's interest. FYI, -- Marcel Moolenaar marcelm(a)juniper.net

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