February 2008 - U-Boot

[U-Boot-Users] [PATCH] Mark board_init_[fr] as noreturn
by Mike Frysinger 14 Feb '08

14 Feb '08

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- include/common.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/common.h b/include/common.h index 54083f1..bcb8bb9 100644 --- a/include/common.h +++ b/include/common.h @@ -203,8 +203,8 @@ void init_cmd_timeout(void); void reset_cmd_timeout(void); /* lib_$(ARCH)/board.c */ -void board_init_f (ulong); -void board_init_r (gd_t *, ulong); +void board_init_f (ulong) __attribute__ ((noreturn)); +void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); int checkboard (void); int checkflash (void); int checkdram (void); -- 1.5.3.8

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[U-Boot-Users] [PATCH] make the machid configurable via the environment (Was: [PATCH] Changed load address and entry point for uImage to ZRELADDR + 6MB)
by Uwe Kleine-König 14 Feb '08

14 Feb '08

Hello Nicolas, Nicolas Pitre wrote: > > But does U-Boot properly provide machine information to the kernel these > > days? I have been and still being burned by U-Boot hardcoding the > > _wrong_ machine ID, and therefore custom built kernels from k.o simply > > won't boot on those boards without hacking the kernel source. > With "our" U-Boot you can override the compiled-in machid with an > environment variable. I didn't implement this patch but I think it's > not that difficult. I will check tomorrow if I can easily get a patch > out of our scm. It took a bit longer, but here it comes. This is on top of todays u-boot. I didn't tested this patch in that version, but this is how it is done in our version of U-Boot (that is considerable older). Switching the machid is also very convenient because we have modules that can be plugged on different base boards and so can use different machids. Best regards Uwe --->8--- From: Uwe Kleine-König <Uwe.Kleine-Koenig(a)digi.com> make the machid configurable via the environment If the variable "machid" exists, let do_bootm_linux use that instead of bd->bi_arch_number. Signed-off-by: Uwe Kleine-König <Uwe.Kleine-Koenig(a)digi.com> --- lib_arm/armlinux.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index 6d32a41..62185f0 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -78,6 +78,8 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], void (*theKernel)(int zero, int arch, uint params); image_header_t *hdr = &header; bd_t *bd = gd->bd; + int machid = bd->bi_arch_number; + char *s; #ifdef CONFIG_CMDLINE_TAG char *commandline = getenv ("bootargs"); @@ -85,6 +87,12 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep); + s = getenv ("machid"); + if (s) { + machid = simple_strtoul (s, NULL, 16); + printf ("Using machid 0x%x from environment\n", machid); + } + /* * Check if there is an initrd image */ @@ -260,7 +268,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], cleanup_before_linux (); - theKernel (0, bd->bi_arch_number, bd->bi_boot_params); + theKernel (0, machid, bd->bi_boot_params); } -- 1.5.3.8 -- Uwe Kleine-König, Software Engineer Digi International GmbH Branch Breisach, Küferstrasse 8, 79206 Breisach, Germany Tax: 315/5781/0242 / VAT: DE153662976 / Reg. Amtsgericht Dortmund HRB 13962

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[U-Boot-Users] why eeprom vs flash
by Jon Smirl 14 Feb '08

14 Feb '08

I'm new to working on low level code like u-boot. Something I don't understand is why things like the Ethernet address are stored in eeprom instead of flash. Is this something to do with how boards are manufactured? From a high level perspective it doesn't seem to matter if eeprom or flash is used. -- Jon Smirl jonsmirl(a)gmail.com

7 9

[U-Boot-Users] [PATCH] Use #ifdef CONFIG_FSLDMAFEC
by Vlad Lungu 14 Feb '08

14 Feb '08

MCD_tasks.c lacks [subject] so compilation of mips targets (and more, probably) fails Signed-off-by: Vlad Lungu <vlad(a)comsys.ro> --- drivers/dma/MCD_tasks.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c index 694e780..06a2d53 100644 --- a/drivers/dma/MCD_tasks.c +++ b/drivers/dma/MCD_tasks.c @@ -22,6 +22,10 @@ /* Contains task code and structures for Multi-channel DMA */ +#include <common.h> + +#ifdef CONFIG_FSLDMAFEC + #include <MCD_dma.h> u32 MCD_varTab0[]; @@ -2426,3 +2430,5 @@ u32 MCD_ENetXmit_TDT[] = { #ifdef MCD_INCLUDE_EU MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; #endif + +#endif /* CONFIG_FSLDMAFEC */ -- 1.5.2.2

3 2

[U-Boot-Users] [PATCH] common/miiphyutil.c: Cleanup MII_DEBUG and debug()
by Shinya Kuribayashi 14 Feb '08

14 Feb '08

Current MII_DEBUG is confusing in two ways. One is useless define-then- undef at the top of the file. The other is there is only one debug() in this file, and that doesn't seem worthwhile to bother having MII_DEBUG. While there are many useful printf()/puts() debug codes, but they are for DEBUG, not for MII_DEBUG. This patch tries to put them all together into MII_DEBUG and debug(). Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- common/miiphyutil.c | 31 +++++++++---------------------- 1 files changed, 9 insertions(+), 22 deletions(-) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 281f0b2..eac8275 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -36,7 +36,6 @@ #include <net.h> /* local debug macro */ -#define MII_DEBUG #undef MII_DEBUG #undef debug @@ -261,31 +260,25 @@ int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, unsigned short tmp; if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { -#ifdef DEBUG - puts ("PHY ID register 2 read failed\n"); -#endif + debug ("PHY ID register 2 read failed\n"); return (-1); } reg = tmp; -#ifdef DEBUG - printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); -#endif + debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); + if (reg == 0xFFFF) { /* No physical device present at this address */ return (-1); } if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { -#ifdef DEBUG - puts ("PHY ID register 1 read failed\n"); -#endif + debug ("PHY ID register 1 read failed\n"); return (-1); } reg |= tmp << 16; -#ifdef DEBUG - printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); -#endif + debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); + *oui = (reg >> 10); *model = (unsigned char)((reg >> 4) & 0x0000003F); *rev = (unsigned char)(reg & 0x0000000F); @@ -304,15 +297,11 @@ int miiphy_reset (char *devname, unsigned char addr) int loop_cnt; if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) { -#ifdef DEBUG - printf ("PHY status read failed\n"); -#endif + debug ("PHY status read failed\n"); return (-1); } if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) { -#ifdef DEBUG - puts ("PHY reset failed\n"); -#endif + debug ("PHY reset failed\n"); return (-1); } #ifdef CONFIG_PHY_RESET_DELAY @@ -327,9 +316,7 @@ int miiphy_reset (char *devname, unsigned char addr) reg = 0x8000; while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) { -# ifdef DEBUG - puts ("PHY status read failed\n"); -# endif + debug ("PHY status read failed\n"); return (-1); } }

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[U-Boot-Users] [PATCH] OneNAND Initial Program Loader (IPL) support
by Kyungmin Park 14 Feb '08

14 Feb '08

Hi, This patch enables the OneNAND boot within U-Boot. Before this work, we used another OneNAND IPL called X-Loader based on open source. With this work, we can build the oneboot.bin image without other program. The build sequence is simple. First, it compiles the u-boot.bin Second, it compiles OneNAND IPL Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin The mechanism is similar with NAND boot except it boots from itself. Another thing is that you can only use the OneNAND IPL only to work other bootloader such as RedBoot and so on. Any comments are welcome. Thank you, Kyungmin Park Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/Makefile b/Makefile index 1b3d2e6..623138c 100644 --- a/Makefile +++ b/Makefile @@ -277,13 +277,18 @@ NAND_SPL = nand_spl U_BOOT_NAND = $(obj)u-boot-nand.bin endif +ifeq ($(CONFIG_ONENAND_U_BOOT),y) +ONENAND_IPL = onenand_ipl +U_BOOT_ONENAND = $(obj)u-boot-onenand.bin +endif + __OBJS := $(subst $(obj),,$(OBJS)) __LIBS := $(subst $(obj),,$(LIBS)) ######################################################################### ######################################################################### -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) all: $(ALL) @@ -330,6 +335,12 @@ $(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +$(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk + $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all + +$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk + cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin + $(VERSION_FILE): @( echo -n "#define U_BOOT_VERSION \"U-Boot " ; \ echo -n "$(U_BOOT_VERSION)" ; \ @@ -2513,7 +2524,9 @@ omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 apollon_config : unconfig + @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h @$(MKCONFIG) $(@:_config=) arm arm1136 apollon + @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk #======================================================================== # i386 @@ -2797,6 +2810,8 @@ clean: @rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds @rm -f $(obj)include/bmp_logo.h @rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map + @rm -f $(obj)onenand_ipl/onenand-ipl $(obj)onenand_ipl/onenand-ipl.bin \ + $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)onenand_ipl/onenand-ipl.map @rm -f $(obj)api_examples/demo $(VERSION_FILE) clobber: clean @@ -2811,6 +2826,7 @@ clobber: clean @rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f + @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f @[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f ifeq ($(OBJTREE),$(SRCTREE)) diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 064d143..383b064 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -440,7 +440,8 @@ void muxSetupTouchScreen(void) void muxSetupGPMC(void) { /* gpmc_io_dir, MCR */ - writel(0x4800008C, 0x19000000); + volatile unsigned int *MCR = (unsigned int *) 0x4800008C; + *MCR = 0x19000000; /* NOR FLASH CS0 */ /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 17c7a83..8b765f1 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -35,6 +35,25 @@ #endif .globl _start _start: b reset +#ifdef CONFIG_ONENAND_IPL + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -51,6 +70,7 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_ONENAND_IPL */ .global _end_vect _end_vect: @@ -139,7 +159,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ +#ifndef CONFIG_ONENAND_IPL beq stack_setup +#endif /* CONFIG_ONENAND_IPL */ ldr r2, _armboot_start ldr r3, _bss_start @@ -156,26 +178,36 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +#ifdef CONFIG_ONENAND_IPL + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ +#endif /* CONFIG_ONENAND_IPL */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_ONENAND_IPL clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l +#endif ldr pc, _start_armboot +#ifdef CONFIG_ONENAND_IPL +_start_armboot: .word start_oneboot +#else _start_armboot: .word start_armboot +#endif /* @@ -214,6 +246,8 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ + +#ifndef CONFIG_ONENAND_IPL /* ************************************************************************* * @@ -326,10 +360,17 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_ONENAND_IPL */ /* * exception handlers */ +#ifdef CONFIG_ONENAND_IPL + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words about stack */ + bl hang /* hang and never return */ +#else /* !CONFIG_ONENAND IPL */ .align 5 undefined_instruction: get_bad_stack @@ -415,3 +456,4 @@ rstctl: .word PM_RSTCTRL_WKUP #endif +#endif /* CONFIG_ONENAND_IPL */ diff --git a/onenand_ipl/board/apollon/Makefile b/onenand_ipl/board/apollon/Makefile new file mode 100644 index 0000000..66a0959 --- /dev/null +++ b/onenand_ipl/board/apollon/Makefile @@ -0,0 +1,65 @@ + +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk +include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_ONENAND_IPL +CFLAGS += -DCONFIG_ONENAND_IPL +OBJCLFAGS += --gap-fill=0x00 + +SOBJS = start.o low_levelinit.o # _memcpy32.o +COBJS = apollon.o onenand_read.o onenand_boot.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR) + +onenandobj := $(OBJTREE)/onenand_ipl/ + +ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin + +all: $(obj).depend $(ALL) + +$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@ + +$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(onenandobj)onenand-ipl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(onenandobj)onenand-ipl.map \ + -o $(onenandobj)onenand-ipl + +# create symbolic links from common files + +# from cpu directory +$(obj)start.S: + rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/$(CPU)/start.S $(obj)start.S + +# from onenand_ipl directory +$(obj)onenand_ipl.h: + rm -f $(obj)onenand_ipl.h + ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $(obj)onenand_ipl.h + +$(obj)onenand_boot.c: $(obj)onenand_ipl.h + rm -f $(obj)onenand_boot.c + ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $(obj)onenand_boot.c + +$(obj)onenand_read.c: $(obj)onenand_ipl.h + rm -f $(obj)onenand_read.c + ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $(obj)onenand_read.c + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)$.c + $(CC) $(CFLAGS) -c -o $@ $< + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/onenand_ipl/board/apollon/apollon.c b/onenand_ipl/board/apollon/apollon.c new file mode 100644 index 0000000..acf5c29 --- /dev/null +++ b/onenand_ipl/board/apollon/apollon.c @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2005-2008 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/mux.h> + +#define write_config_reg(reg, value) \ +do { \ + writeb(value, reg); \ +} while (0) + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +#ifdef CFG_PRINTF +/* Pin Muxing registers used for UART1 */ +/**************************************** + * Routine: muxSetupUART1 (ostboot) + * Description: Set up uart1 muxing + *****************************************/ +static void muxSetupUART1(void) +{ + /* UART1_CTS pin configuration, PIN = D21 */ + write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); + /* UART1_RTS pin configuration, PIN = H21 */ + write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); + /* UART1_TX pin configuration, PIN = L20 */ + write_config_reg(CONTROL_PADCONF_UART1_TX, 0); + /* UART1_RX pin configuration, PIN = T21 */ + write_config_reg(CONTROL_PADCONF_UART1_RX, 0); +} +#endif + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called at time when only stack is available. + **********************************************************/ +int s_init(int skip) +{ +#ifdef CFG_PRINTF + muxSetupUART1(); +#endif + return 0; +} diff --git a/onenand_ipl/board/apollon/config.mk b/onenand_ipl/board/apollon/config.mk new file mode 100644 index 0000000..fd9c506 --- /dev/null +++ b/onenand_ipl/board/apollon/config.mk @@ -0,0 +1,14 @@ +# +# (C) Copyright 2005-2008 Samsung Electronics +# Kyungmin Park <kyungmin.park(a)samsung.com> +# +# Samsung Apollon board with OMAP2420 (ARM1136) cpu +# +# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0 +# Physical Address: +# 8000'0000 (bank0) +# 8800'0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +TEXT_BASE = 0x00000000 diff --git a/onenand_ipl/board/apollon/low_levelinit.S b/onenand_ipl/board/apollon/low_levelinit.S new file mode 100644 index 0000000..417a5a7 --- /dev/null +++ b/onenand_ipl/board/apollon/low_levelinit.S @@ -0,0 +1,205 @@ +/* + * Board specific setup info + * + * (C) Copyright 2005-2008 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from board/omap2420h4/platform.S + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/omap2420.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> + +#define APOLLON_CS0_BASE 0x00000000 + +#ifdef PRCM_CONFIG_I +#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 +#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 +#define SDRC_RFR_CTRL_0_VAL 0x00044C01 + +/* GPMC */ +#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 +#define APOLLON_GPMC_CONFIG2_0 0x000c1000 +#define APOLLON_GPMC_CONFIG3_0 0x00030400 +#define APOLLON_GPMC_CONFIG4_0 0x0B841006 +#define APOLLON_GPMC_CONFIG5_0 0x020F0C11 +#define APOLLON_GPMC_CONFIG6_0 0x00000000 +#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) + +#elif defined(PRCM_CONFIG_II) +#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 +#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C +#define SDRC_RFR_CTRL_0_VAL 0x00030001 + +/* GPMC */ +#define APOLLON_GPMC_CONFIG1_0 0xe30d1201 +#define APOLLON_GPMC_CONFIG2_0 0x00080E81 +#define APOLLON_GPMC_CONFIG3_0 0x00030400 +#define APOLLON_GPMC_CONFIG4_0 0x08041586 +#define APOLLON_GPMC_CONFIG5_0 0x020C090E +#define APOLLON_GPMC_CONFIG6_0 0x00000000 +#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24)) + +#else +#error "Please configure PRCM schecm" +#endif + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + mov r3, r0 /* save skip information */ + + /* Disable watchdog */ + ldr r0, =WD2_BASE + ldr r1, =WD_UNLOCK1 + str r1, [r0, #WSPR] + + ldr r1, =WD_UNLOCK2 + str r1, [r0, #WSPR] + +#ifdef DEBUG_LED + /* LED0 OFF */ + ldr r0, =0x480000E5 /* ball AA10, mode 3 */ + mov r1, #0x0b + strb r1, [r0] +#endif + + /* Pin muxing for SDRC */ + mov r1, #0x00 + ldr r0, =0x480000A1 /* ball C12, mode 0 */ + strb r1, [r0] + + ldr r0, =0x48000032 /* ball D11, mode 0 */ + strb r1, [r0] + + ldr r0, =0x480000A3 /* ball B13, mode 0 */ + strb r1, [r0] + + /* SDRC setting */ + ldr r0, =OMAP2420_SDRC_BASE + ldr r1, =0x00000010 + str r1, [r0, #0x10] + + ldr r1, =0x00000100 + str r1, [r0, #0x44] + + /* SDRC CS0 configuration */ +#ifdef CONFIG_APOLLON_PLUS + ldr r1, =0x01702011 +#else + ldr r1, =0x00d04011 +#endif + str r1, [r0, #0x80] + + ldr r1, =SDRC_ACTIM_CTRLA_0_VAL + str r1, [r0, #0x9C] + + ldr r1, =SDRC_ACTIM_CTRLB_0_VAL + str r1, [r0, #0xA0] + + ldr r1, =SDRC_RFR_CTRL_0_VAL + str r1, [r0, #0xA4] + + ldr r1, =0x00000041 + str r1, [r0, #0x70] + + /* Manual command sequence */ + ldr r1, =0x00000007 + str r1, [r0, #0xA8] + + ldr r1, =0x00000000 + str r1, [r0, #0xA8] + + ldr r1, =0x00000001 + str r1, [r0, #0xA8] + + ldr r1, =0x00000002 + str r1, [r0, #0xA8] + str r1, [r0, #0xA8] + + /* + * CS0 SDRC Mode register + * Burst length = 4 - DDR memory + * Serial mode + * CAS latency = 3 + */ + ldr r1, =0x00000032 + str r1, [r0, #0x84] + + /* Note: You MUST set EMR values */ + /* EMR1 & EMR2 */ + ldr r1, =0x00000000 + str r1, [r0, #0x88] + str r1, [r0, #0x8C] + +#ifdef OLD_SDRC_DLLA_CTRL + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00007306 + str r1, [r0, #0x60] + + ldr r1, =0x00007303 + str r1, [r0, #0x60] +#else + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x60] + + ldr r1, =0x00000503 + str r1, [r0, #0x60] +#endif + +#ifdef __BROKEN_FEATURE__ + /* SDRC_DLLB_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x68] + + ldr r1, =0x00000503 + str r1, [r0, #0x68] +#endif + + /* little delay after init */ + mov r2, #0x1800 +1: + subs r2, r2, #0x1 + bne 1b + + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + mov r0, r3 /* pass skip info to s_init */ + + bl s_init /* go setup pll,mux,memory */ + + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/onenand_ipl/board/apollon/u-boot.onenand.lds b/onenand_ipl/board/apollon/u-boot.onenand.lds new file mode 100644 index 0000000..5b24380 --- /dev/null +++ b/onenand_ipl/board/apollon/u-boot.onenand.lds @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2005-2008 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from X-loader + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/onenand_ipl/onenand_boot.c b/onenand_ipl/onenand_boot.c new file mode 100644 index 0000000..f30deae --- /dev/null +++ b/onenand_ipl/onenand_boot.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2005-2008 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * Derived from x-loader + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <version.h> + +#include "onenand_ipl.h" + +#ifdef CFG_PRINTF +int print_info(void) +{ + printf(XLOADER_VERSION); + + return 0; +} +#endif + +typedef int (init_fnc_t)(void); + +init_fnc_t *init_sequence[] = { + board_init, /* basic board dependent setup */ +#ifdef CFG_PRINTF + serial_init, /* serial communications setup */ + print_info, +#endif + NULL, +}; + +void start_oneboot(void) +{ + init_fnc_t **init_fnc_ptr; + uchar *buf; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) + hang(); + } + + buf = (uchar *) CFG_LOAD_ADDR; + + if (!onenand_read_block(buf, ONENAND_START_BLOCK)) + buf += ONENAND_BLOCK_SIZE; + + if (buf == (uchar *)CFG_LOAD_ADDR) + hang(); + + /* go run U-Boot and never return */ + printf("Starting OS Bootloader...\n"); + ((init_fnc_t *)CFG_LOAD_ADDR)(); + + /* should never come here */ +} + +void hang(void) +{ + /* if board_hang() returns, hange here */ + printf("X-Loader hangs\n"); + for (;;); +} diff --git a/onenand_ipl/onenand_ipl.h b/onenand_ipl/onenand_ipl.h new file mode 100644 index 0000000..b9c6669 --- /dev/null +++ b/onenand_ipl/onenand_ipl.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2005-2008 Samsung Electronics + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ONENAND_IPL_H +#define _ONENAND_IPL_H + +#include <linux/mtd/onenand_regs.h> + +#define ONENAND_START_BLOCK 0 +#define ONENAND_BLOCK_SIZE 2048 + +#ifndef CFG_PRINTF +#define printf(format, args...) +#endif + +#define onenand_readw(a) readw(a) +#define onenand_writew(v, a) writew(v, a) + +#define THIS_ONENAND(a) (CFG_ONENAND_BASE + (a)) + +#define READ_INTERRUPT() \ + onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT)) + +#define ONENAND_PAGE_SIZE 2048 + +extern int onenand_read_block(unsigned char *buf, ulong block); +#endif diff --git a/onenand_ipl/onenand_read.c b/onenand_ipl/onenand_read.c new file mode 100644 index 0000000..f553220 --- /dev/null +++ b/onenand_ipl/onenand_read.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2005-2008 Samsung Electronis + * Kyungmin Park <kyungmin.park(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <asm/io.h> +#include <asm/string.h> + +#include "onenand_ipl.h" + +#define onenand_block_address(block) (block) +#define onenand_sector_address(page) (page << 2) +#define onenand_buffer_address() ((1 << 3) << 8) +#define onenand_bufferram_address(block) (0) + +/* read a page with ECC */ +static inline int onenand_read_page(ulong block, ulong page, u_char *buf) +{ + unsigned long *base; + +#ifndef __HAVE_ARCH_MEMCPY32 + unsigned int offset, value; + unsigned long *p; +#endif + + onenand_writew(onenand_block_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS1)); + + onenand_writew(onenand_sector_address(page), + THIS_ONENAND(ONENAND_REG_START_ADDRESS8)); + + onenand_writew(onenand_buffer_address(), + THIS_ONENAND(ONENAND_REG_START_BUFFER)); + + onenand_writew(onenand_bufferram_address(block), + THIS_ONENAND(ONENAND_REG_START_ADDRESS2)); + + onenand_writew(ONENAND_INT_CLEAR, THIS_ONENAND(ONENAND_REG_INTERRUPT)); + + onenand_writew(ONENAND_CMD_READ, THIS_ONENAND(ONENAND_REG_COMMAND)); + +#ifndef __HAVE_ARCH_MEMCPY32 + p = (unsigned long *) buf; +#endif + base = (unsigned long *) (CFG_ONENAND_BASE + ONENAND_DATARAM); + + while (!(READ_INTERRUPT() & ONENAND_INT_READ)) + continue; + +#ifdef __HAVE_ARCH_MEMCPY32 + /* 32 bytes boundary memory copy */ + memcpy32(buf, base, ONENAND_PAGE_SIZE); +#else + for (offset = 0; offset < (ONENAND_PAGE_SIZE >> 2); offset++) { + value = *(base + offset); + *p++ = value; + } +#endif + + return 0; +} + +#define ONENAND_START_PAGE 1 +#define ONENAND_PAGES_PER_BLOCK 64 + +/** + * onenand_read_block - Read a block data to buf + * @return 0 on success + */ +int onenand_read_block(unsigned char *buf, ulong block) +{ + int page, offset = 0; + + /* NOTE: you must read page from page 1 of block 0 */ + /* read the block page by page*/ + for (page = ONENAND_START_PAGE; + page < ONENAND_PAGES_PER_BLOCK; page++) { + + onenand_read_page(block, page, buf + offset); + + offset += ONENAND_PAGE_SIZE; + } + + return 0; +}

2 1

[U-Boot-Users] [PATCH] Fix CONFIG_MMC usage in fat code
by Andy Fleming 14 Feb '08

14 Feb '08

A #if statement in fat.c depended on CONFIG_MMC, instead of defined(CONFIG_MMC). This meant CONFIG_MMC needed to be defined as "1" rather than just defined. Now it's better. Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- fs/fat/fat.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index ee8b5fe..c1e5741 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -984,7 +984,7 @@ file_fat_detectfs(void) #if defined(CONFIG_CMD_IDE) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ - (CONFIG_MMC) + defined(CONFIG_MMC) printf("Interface: "); switch(cur_dev->if_type) { case IF_TYPE_IDE : printf("IDE"); break; -- 1.5.0.2.230.gfbe3d-dirty

2 1

[U-Boot-Users] [PATCH v2] ppc: Refactor cache routines, so there is only one common set.
by Rafal Jaworowski 14 Feb '08

14 Feb '08

Signed-off-by: Rafal Jaworowski <raj(a)semihalf.com> --- cpu/mpc512x/start.S | 46 -------------------------------- cpu/mpc83xx/start.S | 34 ------------------------ cpu/mpc85xx/start.S | 45 ------------------------------- cpu/mpc86xx/start.S | 44 ------------------------------- cpu/ppc4xx/start.S | 33 ----------------------- lib_ppc/Makefile | 2 +- lib_ppc/ppccache.S | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 73 insertions(+), 203 deletions(-) create mode 100644 lib_ppc/ppccache.S diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 244c69b..5a9d868 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -479,52 +479,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - /*-------------------------------------------------------------------*/ /* diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 1dfbf62..309eb30 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -840,40 +840,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - .globl ppcDWstore ppcDWstore: lfd 1, 0(r4) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index b489d2f..44b2c7d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -778,51 +778,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /*------------------------------------------------------------------------------*/ /* diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c83310a..fa9736b 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -708,50 +708,6 @@ in32r: blr /* - * Function: ppcDcbf - * Description: Data Cache block flush - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/* - * Function: ppcDcbi - * Description: Data Cache block Invalidate - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/* - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/* - * Function: ppcSync - * Description: Processor Synchronize - * Input: none. - * Output: none. - */ - .globl ppcSync -ppcSync: - sync - blr - -/* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 77c2aa4..c29c87b 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1306,39 +1306,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /* * void relocate_code (addr_sp, gd, addr_moni) * diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile index 2ba034f..afbd5ca 100644 --- a/lib_ppc/Makefile +++ b/lib_ppc/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).a -SOBJS = ppcstring.o ticks.o +SOBJS = ppccache.o ppcstring.o ticks.o COBJS = board.o \ bat_rw.o cache.o extable.o kgdb.o time.o interrupts.o diff --git a/lib_ppc/ppccache.S b/lib_ppc/ppccache.S new file mode 100644 index 0000000..25833ce --- /dev/null +++ b/lib_ppc/ppccache.S @@ -0,0 +1,72 @@ +/* + * Copyright (C) 1998 Dan Malek <dmalek(a)jlc.net> + * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> + * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd(a)denx.de> + * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <ppc_asm.tmpl> + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr -- 1.5.2.2

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Re: [U-Boot-Users] AT91 Bootstrap in U-boot
by Ken.Fuchs＠bench.com 14 Feb '08

14 Feb '08

Ulf Samuelson wrote: > There are no Atmel AT91SAM9 dev boards which uses a parallel flash. This is not quite true. I'm able to boot a AT91SAM9263-EK board via EBI NOR flash and an AT91Bootstrap/Atmel modified U-Boot right now. Did I misunderstand your statement above? One needs only to solder an appropriate EBI NOR chip to the AT91SAM9263-EK board and install the BMS jumper to allow parallel flash booting. Unfortunately, the boards in the AT91SAM9260-EK and AT91SAM9261-EK can't support an EBI NOR flash due to intentional design limitations. Sincerely, Ken Fuchs > -----Original Message----- > From: u-boot-users-bounces(a)lists.sourceforge.net > [mailto:u-boot-users-bounces@lists.sourceforge.net] On Behalf > Of Ulf Samuelsson > Sent: Wednesday, February 13, 2008 15:16 > To: E Robertson; u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] AT91 Bootstrap in U-boot > > > > Hi, > > Is their a reason why the AT91 Bootstrap code was never ported to > > U-boot? > > Yes, Integrating AT91Bootstrap only makes sense if you have a > parallel flash. > > There are no Atmel AT91SAM9 dev boards which uses a parallel flash. > The AT91RM9200 boards uses parallel flash, but they do not > use AT91Bootstrap. > > The SAM9 boards all have an AT45 dataflash which has an SPI interface. > The BMS pin needs to be configured to make the CPU boot from > the internal BootROM. > The BootROM copies the initial application at address 0 of > the dataflash to internal SRAM. > The SRAM can be as small as 4 kB (in the AT91SAM9260) and > that limits the functionality. > U-Boot does not fit, so you have AT91bootstrap. > > AT91bootstrap needs to run BEFORE U-Boot is started. > > > Best Regards > Ulf Samuelsson > > -------------------------------------------------------------- > ----------- > This SF.net email is sponsored by: Microsoft > Defy all challenges. Microsoft(R) Visual Studio 2008. > http://clk.atdmt.com/MRT/go/vse0120000070mrt/direct/01/ > _______________________________________________ > U-Boot-Users mailing list > U-Boot-Users(a)lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/u-boot-users >

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[U-Boot-Users] [PATCH ARM 0/5] AT91CAP9 support
by Stelian Pop 14 Feb '08

14 Feb '08

Hi, This series of patches adds support for Atmel's AT91CAP9 Customizable Microcontrollers family: http://www.atmel.com/products/AT91CAP/Default.asp and more specifically for the AT91CAP9A-DK development kit: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138 The supported features include: - SDRAM - Serial port DBGU - LEDs - SPI - NOR Flash - NAND Flash with ECC soft - DataFlash (through SPI) - Ethernet This patch is to be applied on top of the current u-boot git tree + three small patches I submitted a few days ago but weren't picked up by anyone: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/35306 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/35307 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/35309 This is the fifth submission of the AT91CAP9 support, with some extra cleanup (one whitespace, a few #undefs and bd_info_ext removed). Thanks. Stelian.

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