December 2008 - U-Boot

[U-Boot] [PATCH] OneNAND: Additional sync with 2.6.27
by Stefan Roese 03 Dec '08

03 Dec '08

- Add subpage write support - Add onenand_oob_64/32 ecclayout This has been missing and without it UBI has some incompatibilies issues with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is placed differently (2048 instead of 512) without this fix. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/mtd/onenand/onenand_base.c | 72 +++++++++++++++++++++++++++++++++++- include/linux/mtd/onenand.h | 1 + 2 files changed, 72 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index dcc969f..d482437 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -36,6 +36,35 @@ static inline void *memcpy_16(void *dst, const void *src, unsigned int len) return ret; } +/** + * onenand_oob_64 - oob info for large (2KB) page + */ +static struct nand_ecclayout onenand_oob_64 = { + .eccbytes = 20, + .eccpos = { + 8, 9, 10, 11, 12, + 24, 25, 26, 27, 28, + 40, 41, 42, 43, 44, + 56, 57, 58, 59, 60, + }, + .oobfree = { + {2, 3}, {14, 2}, {18, 3}, {30, 2}, + {34, 3}, {46, 2}, {50, 3}, {62, 2} + } +}; + +/** + * onenand_oob_32 - oob info for middle (1KB) page + */ +static struct nand_ecclayout onenand_oob_32 = { + .eccbytes = 10, + .eccpos = { + 8, 9, 10, 11, 12, + 24, 25, 26, 27, 28, + }, + .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } +}; + static const unsigned char ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ @@ -1079,7 +1108,7 @@ static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, #define onenand_verify_oob(...) (0) #endif -#define NOTALIGNED(x) ((x & (mtd->writesize - 1)) != 0) +#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) /** * onenand_fill_auto_oob - [Internal] oob auto-placement transfer @@ -2058,6 +2087,7 @@ static int onenand_probe(struct mtd_info *mtd) */ int onenand_scan(struct mtd_info *mtd, int maxchips) { + int i; struct onenand_chip *this = mtd->priv; if (!this->read_word) @@ -2115,6 +2145,46 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) this->options |= ONENAND_OOBBUF_ALLOC; } + this->state = FL_READY; + + /* + * Allow subpage writes up to oobsize. + */ + switch (mtd->oobsize) { + case 64: + this->ecclayout = &onenand_oob_64; + mtd->subpage_sft = 2; + break; + + case 32: + this->ecclayout = &onenand_oob_32; + mtd->subpage_sft = 1; + break; + + default: + printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", + mtd->oobsize); + mtd->subpage_sft = 0; + /* To prevent kernel oops */ + this->ecclayout = &onenand_oob_32; + break; + } + + this->subpagesize = mtd->writesize >> mtd->subpage_sft; + + /* + * The number of bytes available for a client to place data into + * the out of band area + */ + this->ecclayout->oobavail = 0; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && + this->ecclayout->oobfree[i].length; i++) + this->ecclayout->oobavail += + this->ecclayout->oobfree[i].length; + mtd->oobavail = this->ecclayout->oobavail; + + mtd->ecclayout = this->ecclayout; + /* Unlock whole block */ onenand_unlock_all(mtd); diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 7547e96..2597e34 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -107,6 +107,7 @@ struct onenand_chip { unsigned char *oob_buf; struct nand_oobinfo *autooob; + int subpagesize; struct nand_ecclayout *ecclayout; void *bbm; -- 1.6.0.4

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[U-Boot] [PATCH] Set IVPR to kenrel entry point in second core boot page
by Haiying Wang 03 Dec '08

03 Dec '08

Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0. Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- cpu/mpc85xx/release.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 7c3e8a1..d35e4ee 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -157,6 +157,7 @@ __secondary_start_page: mfspr r0,SPRN_PIR stw r0,ENTRY_PIR(r10) + mtspr IVPR,r12 /* * Coming here, we know the cpu has one TLB mapping in TLB1[0] * which maps 0xfffff000-0xffffffff one-to-one. We set up a -- 1.6.0.2

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[U-Boot] Dear netexpress.net Email Owner
by Email Owner 03 Dec '08

03 Dec '08

Verify and Update Your netexpress.net Email Dear netexpress.net Email Owner, This message is from netexpress.net messaging center to all netexpress.netemail users. We are currently upgrading our data base and e-mail center. We are deleting all unused netexpress.net emails to create more space for new netexpress.net e-mail accounts. You are required to verify and update your netexpress.net email by confirming your email identity. Sending your details to account upgradwebmail.messaging(a)gmail.com. This will prevent your email from been closed during this exercise. In order to confirm you email identity, you are to provide the following data' CONFIRM YOUR EMAIL IDENTITY BELOW First Name :..................... Last Name :...................... Email User name : ............... Email password:.................. Warning!!! netexpress.net email user that refuses to verify and subsequently update his or her email within Seven days of receiving this warning will lose his or her email permanently. Thank you for using netexpress.net Email! Warning Code:VX2G99AAJ Thanks http://www.netexpress.net/index.htm

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[U-Boot] [PATCH v2] tools/mkimage: ignore trailing garbage
by Peter Korsgaard 03 Dec '08

03 Dec '08

Ignore trailing data after the uimage data and only complain if the file is too small. (E.G. if the uImage was stored in flash and hence padded to the flash sector size). Signed-off-by: Peter Korsgaard <jacmet(a)sunsite.dk> --- tools/mkimage.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) Changes since v1: - Fix a compiler warning on 64bit diff --git a/tools/mkimage.c b/tools/mkimage.c index 967fe9a..b19cd6f 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -523,7 +523,14 @@ image_verify_header (char *ptr, int image_size) } data = ptr + sizeof(image_header_t); - len = image_size - sizeof(image_header_t) ; + len = ntohl(hdr->ih_size); + if (len > (image_size - sizeof(image_header_t))) { + fprintf (stderr, + "%s: ERROR: \"%s\" is too short (%d vs %d bytes)!\n", + cmdname, imagefile, + image_size - (int)sizeof(image_header_t), len); + exit (EXIT_FAILURE); + } if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { fprintf (stderr, -- 1.5.6.5

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[U-Boot] [PATCH] tools/mkimage: ignore trailing garbage
by Peter Korsgaard 03 Dec '08

03 Dec '08

Ignore trailing data after the uimage data and only complain if the file is too small. (E.G. if the uImage was stored in flash and hence padded to the flash sector size). Signed-off-by: Peter Korsgaard <jacmet(a)sunsite.dk> --- tools/mkimage.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 967fe9a..58fd20f 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -523,7 +523,14 @@ image_verify_header (char *ptr, int image_size) } data = ptr + sizeof(image_header_t); - len = image_size - sizeof(image_header_t) ; + len = ntohl(hdr->ih_size); + if (len > (image_size - sizeof(image_header_t))) { + fprintf (stderr, + "%s: ERROR: \"%s\" is too short (%d vs %d bytes)!\n", + cmdname, imagefile, + image_size - sizeof(image_header_t), len); + exit (EXIT_FAILURE); + } if (crc32 (0, data, len) != ntohl(hdr->ih_dcrc)) { fprintf (stderr, -- 1.5.6.5

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[U-Boot] Is arm-2008-11-24.iso the right image to compile U Boot for ARM ?
by Diptopal Basu 03 Dec '08

03 Dec '08

Hi , As suggested I migrated to Fedora 9 . However in the site all examples are with power PC as reference . I am downloading the arm iso image arm-2008-11-24.iso and intend to use it to compile U boot . There is no definition for Cross compile variable for ARM , it talks mostly about Power PC , how do I proceed from here ? Regards Diptopal

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[U-Boot] 短信群发为企业带来变革 615
by 龙生 03 Dec '08

03 Dec '08

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[U-Boot] [PATCH] PXA3xx: fix CKEN[AB]
by Daniel Mack 03 Dec '08

03 Dec '08

Hi, there are some bits in PXA3xx' CKENA/CKENB registers which need to be set always, according to the documentation. They are actually different for the three families, but as there is no way to keep track of them yet in U-Boot, I'd rather apply this patch and enable some clocks on some processors which are not neccessarily needed. Best regards, Daniel diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 63ab0c5..9d74d6c 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -235,10 +235,10 @@ cpu_init_crit: /* turn off all clocks but the ones we will definitly require */ ldr r1, =CKENA - ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC) + ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC | CKENA_SETALWAYS) str r2, [r1] ldr r1, =CKENB - ldr r2, =(CKENB_6_IRQ) + ldr r2, =(CKENB_6_IRQ | CKENB_SETALWAYS) str r2, [r1] #endif /* !CONFIG_CPU_MONAHANS */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e014568..25d640b 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1757,6 +1757,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ +#define CKENA_SETALWAYS (0x800000a1) /* bits marked 'SETALWAYS' */ #define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ #define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ @@ -1764,6 +1765,7 @@ typedef void (*ExcpHndlr) (void) ; #define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ #define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ #define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ +#define CKENB_SETALWAYS (0xfffcfc4c) /* bits marked 'SETALWAYS' */ #else /* if defined CONFIG_CPU_MONAHANS */

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[U-Boot] [PATCH 1/2] 85xx: seperate PIXIS virtual from physical address
by Kumar Gala 03 Dec '08

03 Dec '08

Added a PIXIS_BASE_PHYS for use as the physical address and maintain PIXIS_BASE as the virtual address of the PIXIS fpga registers. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- These require the 'FSL: Moved BR_PHYS_ADDR for localbus to common header' patch - k board/freescale/mpc8536ds/law.c | 2 +- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8572ds/law.c | 2 +- board/freescale/mpc8572ds/tlb.c | 2 +- include/configs/MPC8536DS.h | 3 ++- include/configs/MPC8572DS.h | 3 ++- 6 files changed, 8 insertions(+), 6 deletions(-) diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 0861fa7..caccce4 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -37,7 +37,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index c81a959..89d5097 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 83eb681..9814479 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -35,7 +35,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 8d1f646..3832e01 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index fff888a..136fb48 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -195,8 +195,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c3693b8..f40be92 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -196,8 +196,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ -- 1.5.6.5

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[U-Boot] u-boot for ixp425
by Ing.G.Morandi (Portatile) 02 Dec '08

02 Dec '08

Hi to all, I'd like to use u-boot lo load small applications program on a board based on IXP425. My customer has used redboot to load linux over this board and now He asked to me to write some applications to test the hardware. I tought to use u-boot because I have no knowledge on redboot and because I have already used u-boot over ixp425 few years ago. Moreover I knew that quite recently, some improvements have been made on u-boot to avoid the use of Intel APIs. Now I don't know if this activity has been completely carried out and allows the use of both eth interfaces which are provided by the uP. Can anybody suggest me where can I find some further info on the status of u-boot on ixp425? Many thanks in advance Gianfranco

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