December 2008 - U-Boot

[U-Boot] Please pull u-boot-mpc85xx.git
by Andy Fleming 05 Dec '08

05 Dec '08

are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master Anatolij Gustschin (1): 85xx: socrates: fix DDR SDRAM tlb entry configuration Becky Bruce (1): drivers/fsl_pci_init: Fix inbound window mapping bug Dave Liu (3): 85xx: remove the unused ddr_enable_ecc in the board file 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM case 85xx: fix the wrong DDR settings for MPC8572DS Ed Swarthout (1): fsl ddr skip interleaving if not supported. Jon Loeliger (1): Removed unused CONFIG_L1_INIT_RAM symbol. Kumar Gala (3): FSL: Moved BR_PHYS_ADDR for localbus to common header 85xx: Fix relocation of CCSRBAR 85xx: init gd as early as possible Peter Tyser (2): 85xx: Add CPU 2 errata workaround to all 8548 boards 85xx: Add PORDEVSR_PCI1 define board/atum8548/atum8548.c | 10 --------- board/freescale/mpc8536ds/mpc8536ds.c | 16 +------------ board/freescale/mpc8544ds/mpc8544ds.c | 10 --------- board/freescale/mpc8548cds/mpc8548cds.c | 25 +--------------------- board/freescale/mpc8568mds/mpc8568mds.c | 12 ----------- board/freescale/mpc8572ds/mpc8572ds.c | 16 +------------ board/sbc8548/sbc8548.c | 19 +---------------- board/socrates/tlb.c | 2 + board/tqc/tqm85xx/tqm85xx.c | 2 +- cpu/mpc85xx/cpu_init.c | 34 +++++++++++++++++++++--------- cpu/mpc85xx/pci.c | 2 +- cpu/mpc8xxx/ddr/main.c | 9 ++++++- cpu/mpc8xxx/ddr/options.c | 20 +++++++++--------- drivers/pci/fsl_pci_init.c | 2 +- include/asm-ppc/fsl_lbc.h | 8 +++++++ include/asm-ppc/immap_85xx.h | 3 +- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8536DS.h | 4 +-- include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 4 +-- include/configs/MPC8548CDS.h | 3 +- include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 3 +- include/configs/MPC8572DS.h | 29 ++++++++++++------------- include/configs/MPC8610HPCD.h | 1 - include/configs/MPC8641HPCN.h | 10 --------- include/configs/MVBLM7.h | 1 - include/configs/PM854.h | 1 - include/configs/PM856.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM834x.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/sbc8641d.h | 1 - include/configs/socrates.h | 1 - include/configs/stxgp3.h | 1 - include/configs/stxssa.h | 1 - 43 files changed, 79 insertions(+), 185 deletions(-)

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[U-Boot] Pull request: nand flash
by Scott Wood 05 Dec '08

05 Dec '08

The following changes since commit 2077e348c2a84901022ad95311b47b70361e6daa: Scott Wood (1): NAND: Fix misplaced return statement in nand_{read,write}_skip_bad(). are available in the git repository at: git://git.denx.de/u-boot-nand-flash.git master Stefan Roese (1): OneNAND: Add missing mtd info struct before calling onenand_erase() common/env_onenand.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)

2 1

[U-Boot] Pull requst u-boot-mpc86xx
by Jon Loeliger 05 Dec '08

05 Dec '08

Wolfgang, The following changes since commit 2077e348c2a84901022ad95311b47b70361e6daa: Scott Wood (1): NAND: Fix misplaced return statement in nand_{read,write}_skip_bad(). are available in the git repository at: git://www.denx.de/git/u-boot-mpc86xx.git master Becky Bruce (1): mpc8641: Fix error in README Jon Loeliger (2): 86xx: Fix non-64-bit compilation problems. Removed unused CONFIG_L1_INIT_RAM symbol. doc/README.mpc8641hpcn | 10 +++++----- include/configs/MPC8349EMDS.h | 1 - include/configs/MPC8349ITX.h | 1 - include/configs/MPC8536DS.h | 2 -- include/configs/MPC8540ADS.h | 1 - include/configs/MPC8540EVAL.h | 1 - include/configs/MPC8541CDS.h | 1 - include/configs/MPC8544DS.h | 2 -- include/configs/MPC8548CDS.h | 1 - include/configs/MPC8555CDS.h | 1 - include/configs/MPC8560ADS.h | 1 - include/configs/MPC8568MDS.h | 1 - include/configs/MPC8572DS.h | 2 -- include/configs/MPC8610HPCD.h | 15 ++++++++++++++- include/configs/MPC8641HPCN.h | 1 - include/configs/MVBLM7.h | 1 - include/configs/PM854.h | 1 - include/configs/PM856.h | 1 - include/configs/SBC8540.h | 1 - include/configs/TQM834x.h | 1 - include/configs/TQM85xx.h | 1 - include/configs/sbc8349.h | 1 - include/configs/sbc8548.h | 1 - include/configs/sbc8560.h | 1 - include/configs/sbc8641d.h | 15 ++++++++++++++- include/configs/socrates.h | 1 - include/configs/stxgp3.h | 1 - include/configs/stxssa.h | 1 - 28 files changed, 33 insertions(+), 35 deletions(-)

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[U-Boot] [PATCH] Add secondary CPUs processor frequency for e500 core
by Haiying Wang 05 Dec '08

05 Dec '08

This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang(a)freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang(a)freescale.com> --- This patch has been tested on MPC8572DS board. Two CPU's frequencies showed up correctly, "fdt print" showed clock-frequency was filled in fdt blob correctly. cpu/mpc85xx/cpu.c | 7 +++++-- cpu/mpc85xx/fdt.c | 17 +++++++++++++++-- cpu/mpc85xx/speed.c | 10 ++++++---- include/e500.h | 5 ++++- 4 files changed, 30 insertions(+), 9 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index c780687..ffdda0d 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -91,6 +91,7 @@ int checkcpu (void) #else u32 ddr_ratio = 0; #endif + int i; svr = get_svr(); ver = SVR_SOC_VER(svr); @@ -142,8 +143,10 @@ int checkcpu (void) get_sys_info(&sysinfo); - puts("Clock Configuration:\n"); - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + puts("Clock Configuration:\n "); + for (i = 0; i < CONFIG_NUM_CPUS; i++) + printf("CPU%d:%-4s MHz, ", + i,strmhz(buf1, sysinfo.freqProcessor[i])); printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 59aafb1..4291e94 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -212,6 +212,10 @@ void fdt_add_enet_stashing(void *fdt) void ft_cpu_setup(void *blob, bd_t *bd) { + int off; + int val; + sys_info_t sysinfo; + /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(get_svr())) fdt_fixup_crypto_node(blob, 0); @@ -227,8 +231,17 @@ void ft_cpu_setup(void *blob, bd_t *bd) "timebase-frequency", bd->bi_busfreq / 8, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); + + get_sys_info(&sysinfo); + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]); + fdt_setprop(blob, off, "clock-frequency", &val, 4); + off = fdt_node_offset_by_prop_value(blob, off, "device_type", + "cpu", 4); + } + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); #ifdef CONFIG_QE diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 1e0f483..f123a8a 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -37,17 +37,19 @@ void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint plat_ratio,e500_ratio,half_freqSystemBus; + uint i; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; - e500_ratio = (gur->porpllsr) & 0x003f0000; - e500_ratio >>= 16; /* Divide before multiply to avoid integer * overflow for processor speeds above 2GHz */ half_freqSystemBus = sysInfo->freqSystemBus/2; - sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; + for (i = 0; i < CONFIG_NUM_CPUS; i++) { + e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f; + sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus; + } /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ sysInfo->freqDDRBus = sysInfo->freqSystemBus; @@ -79,7 +81,7 @@ int get_clocks (void) dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); - gd->cpu_clk = sys_info.freqProcessor; + gd->cpu_clk = sys_info.freqProcessor[0]; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; diff --git a/include/e500.h b/include/e500.h index 1971eee..a7f371a 100644 --- a/include/e500.h +++ b/include/e500.h @@ -8,9 +8,12 @@ #ifndef __ASSEMBLY__ +#ifndef CONFIG_NUM_CPUS +#define CONFIG_NUM_CPUS 1 +#endif typedef struct { - unsigned long freqProcessor; + unsigned long freqProcessor[CONFIG_NUM_CPUS]; unsigned long freqSystemBus; unsigned long freqDDRBus; } MPC85xx_SYS_INFO; -- 1.6.0.2

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[U-Boot] [PATCH] IXP425: Add new IXP425 board emPC-A400 Part 1/2
by Stefan Althoefer 04 Dec '08

04 Dec '08

[PATCH] IXP425: Add new IXP425 board emPC-A400 This patch adds support for the emPC-A400 CPU board from Janz Automationssysteme. It will also apply to some of the Janz emVIEW displays which are based on this CPU board. Besides of the board support, the patch includes two features which are (up to now) private to this port but might be of interrest to others. 1. Ability to download microcode to the NPE unit. This code works without using the Intel Library (which makes it smaller). This is good if you do not want to do networking in u-boot, but want boot an NFS-rooted linux system (where linux cannot load the microcode by itself). Refer to boards/empca400/cmd_npe.c 2. Ability to boot the IXP425 Windows-CE kernel. Refer to boards/empca400/cmd_bootce.c. The patch is against "latest" u-boot git-repository Please (still) be patient if style of submission or patches are offending. Signed-off-by: Stefan Althoefer <stefan.althoefer(a)web.de> ---- diff -uprN u-boot-orig//board/empca400/cmd_npeload.c u-boot/board/empca400/cmd_npeload.c --- u-boot-orig//board/empca400/cmd_npeload.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/cmd_npeload.c 2008-12-03 11:53:22.000000000 +0100 @@ -0,0 +1,291 @@ +/* + * cmd_npeload.c - download microcode to the NPE units of IXP4xx cpu + * + * Copyright (C) 2006 Christian Hohnstaedt <chohnstaedt(a)innominate.com> + * Copyright (C) 2006 Stefan Althoefer <as(a)janz.de> + * + * This file is released under the GPLv2 + */ + +/************************************************************************** + * + * Support for downloading microcode into the NPE units of the Intel + * IXP4xx. + * + * Data has to be "microcode.dat", as generated with the IxNpeMicrocode + * utility from Christian Hohnstaedt's IXP4xx network driver. + * + * E.g: + * tftp 0x1000000 microcode.dat + * npeload 0x1000000 + * + ************************************************************************** + */ + +#include <common.h> +#include <command.h> + +#include "npe.h" + + +#define EIO 1 +#define EFAULT 2 +#define ENODEV 3 + + +static struct npe_plat_data npea = { + .name = "NPE A", + .data_size = 0x800, + .inst_size = 0x1000, + .id = 0, +}; + +static struct npe_plat_data npeb = { + .name = "NPE B", + .data_size = 0x800, + .inst_size = 0x800, + .id = 1, + .eth_id = 0, + .rx_id = 4, + .rxfree_id = 27, + .tx_id = 24, + .txdone_id = 31, +}; + +static struct npe_plat_data npec = { + .name = "NPE C", + .data_size = 0x800, + .inst_size = 0x800, + .id = 2, + .eth_id = 1, + .rx_id = 5, + .rxfree_id = 28, + .tx_id = 25, + .txdone_id = 31, +}; + +#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) +#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) +#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) +#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) + +static struct npe_info npe_info[] = { + { + .addr = (void *)IXP4XX_NPEA_BASE_PHYS, + .plat = &npea, + }, + { + .addr = (void *)IXP4XX_NPEB_BASE_PHYS, + .plat = &npeb, + }, + { + .addr = (void *)IXP4XX_NPEC_BASE_PHYS, + .plat = &npec, + } +}; + + + + +#define IXNPE_VERSION "IXP4XX NPE driver Version 0.0.1" + +#define DL_MAGIC 0xfeedf00d + +#define EOF_BLOCK 0xf +#define IMG_SIZE(image) (((image)->size * sizeof(u32)) + \ + sizeof(struct dl_image)) + +#define BT_INSTR 0 +#define BT_DATA 1 + + +struct dl_codeblock { + u32 npe_addr; + u32 size; + u32 data[0]; +}; + +static void npe_stop(struct npe_info *npe) +{ + npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_STOP); + npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); +} +static void npe_reset_active(struct npe_info *npe, u32 reg) +{ + u32 regval; + + regval = npe_read_ecs_reg(npe, reg); + regval &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; + npe_write_ecs_reg(npe, reg, regval); +} + +static void npe_start(struct npe_info *npe) +{ + npe_reset_active(npe, IX_NPEDL_ECS_PRI_1_CTXT_REG_0); + npe_reset_active(npe, IX_NPEDL_ECS_PRI_2_CTXT_REG_0); + npe_reset_active(npe, IX_NPEDL_ECS_DBG_CTXT_REG_0); + + npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); + npe_write_exctl(npe, IX_NPEDL_EXCTL_CMD_NPE_START); +} + +static int +download_block(struct npe_info *npe, struct dl_codeblock *cb, unsigned type) +{ + int i; + int cmd; + + switch (type) { + case BT_DATA: + cmd = IX_NPEDL_EXCTL_CMD_WR_DATA_MEM; + if (cb->npe_addr + cb->size > npe->plat->data_size) { + printf("Data size too large: %d+%d > %d\n", + cb->npe_addr, cb->size, npe->plat->data_size); + return -EIO; + } + break; + case BT_INSTR: + cmd = IX_NPEDL_EXCTL_CMD_WR_INS_MEM; + if (cb->npe_addr + cb->size > npe->plat->inst_size) { + printf("Instr size too large: %d+%d > %d\n", + cb->npe_addr, cb->size, npe->plat->inst_size); + return -EIO; + } + break; + default: + printf("Unknown CMD: %d\n", type); + return -EIO; + } + + for (i=0; i < cb->size; i++) { + npe_write_cmd(npe, cb->npe_addr + i, cb->data[i], cmd); + } + + return 0; +} + +struct npe_info *get_npeptr_by_id(int id) +{ + int i; + + for(i=0; i<sizeof(npe_info)/(sizeof(struct npe_info)); i++){ + if( npe_info[i].plat->id == id ){ + return &npe_info[i]; + } + } + return 0; +} + +static int store_npe_image(struct dl_image *image) +{ + struct dl_block *blk; + struct dl_codeblock *cb; + struct npe_info *npe; + int ret=0; + /*u32 imgid = be32_to_cpu(image->id);*/ + u32 imgid = image->id; + + if (!(npe = get_npeptr_by_id( (imgid >> 24) & 0xf) )) + return -ENODEV; + + if ( npe_status(npe) & IX_NPEDL_EXCTL_STATUS_RUN) { + printf("Cowardly refusing to reload an Image " + "into the running %s\n", npe->plat->name); + return 0; /* indicate success anyway... */ + } + npe_stop(npe); + + for (blk = image->u.block; blk->type != EOF_BLOCK; blk++) { + if (blk->offset > image->size) { + printf("Block offset out of range\n"); + return -EIO; + } + cb = (struct dl_codeblock*)&image->u.data[blk->offset]; + if (blk->offset + cb->size + 2 > image->size) { + printf("Codeblock size out of range\n"); + return -EIO; + } + if ((ret = download_block(npe, cb, blk->type))) + return ret; + } + *(u32*)npe->img_info = imgid; + npe_start(npe); + + printf("Image loaded to %s Func:%x, Rel: %x:%x, Status: %x\n", + npe->plat->name, npe->img_info[1], npe->img_info[2], + npe->img_info[3], npe_status(npe)); + return 0; +} + +int ucode_write(const char *buf) +{ + const char *ppos; + struct dl_image *image; + int ret; + + ppos = buf; + + while (1) { + /* Loop until we have an invalid image */ + image = (struct dl_image *)ppos; + + if (image->magic != DL_MAGIC) { + return -EFAULT; + } + + ppos = ppos + IMG_SIZE(image); + + ret = store_npe_image(image); + if (ret) { + printf("Error in NPE image: %d\n", + image->id); + return ret; + } + } + + return 0; +} + + +static void disable_npe_irq(struct npe_info *npe) +{ + u32 reg; + reg = npe_reg_read(npe, IX_NPEDL_REG_OFFSET_CTL); + reg &= ~(IX_NPEMH_NPE_CTL_OFE | IX_NPEMH_NPE_CTL_IFE); + reg |= IX_NPEMH_NPE_CTL_OFEWE | IX_NPEMH_NPE_CTL_IFEWE; +} + + +/* ---------------------------------------------------------------- */ + +int do_npeload (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + int i; + int *image_data; + + switch (argc) { + case 2: /* fpga <op> */ + image_data = (void *) simple_strtoul (argv[1], NULL, 16); + break; + default: + printf("%s: command error\n", __FUNCTION__); + return 1; + } + + /* Reset all NPEs */ + for (i=0; i<sizeof(npe_info)/(sizeof(struct npe_info)); i++) { + disable_npe_irq(&npe_info[i]); + } + + ucode_write((const char *)image_data); + + return 0; +} + + +U_BOOT_CMD( + npeload, 3, 1, do_npeload, + "npeload - Load microcode to IXP4xx-NPEs\n", + " <addr>\n - load image from 'addr' into the NPEs\n" +); + diff -uprN u-boot-orig//board/empca400/config.mk u-boot/board/empca400/config.mk --- u-boot-orig//board/empca400/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/config.mk 2008-12-03 11:14:56.000000000 +0100 @@ -0,0 +1,4 @@ +# +TEXT_BASE = 0x03f80000 +CONFIG_IXP4XX_NPE_EXT_UCODE_BASE = 0x0 +LOGO_BMP= logos/janz.bmp diff -uprN u-boot-orig//board/empca400/empca400.c u-boot/board/empca400/empca400.c --- u-boot-orig//board/empca400/empca400.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/empca400.c 2008-12-03 12:00:28.000000000 +0100 @@ -0,0 +1,246 @@ +/* + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2008 + * Janz Automationssysteme AG <www.janz.de> + * Stefan Althoefer <as(a)janz.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/ixp425.h> +#include <common.h> +//#include <flash.h> +#include <pci.h> + +/* ------------------------------------------------------------------------- */ + +//extern flash_info_t flash_info[0]; /* FLASH chips info */ + +/* local prototypes */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +/**********************************************************/ + +int board_post_init (void) +{ + return (0); +} + +/**********************************************************/ + +static inline unsigned int mswap32(unsigned int x) +{ + return ( + ((x<<24) & 0xff000000) | + ((x<< 8) & 0x00ff0000) | + ((x>> 8) & 0x0000ff00) | + ((x>>24) & 0x000000ff) ); +} + +#if 0 +/* Left as examples */ +void sm501fixup(void) +{ + pci_dev_t dev; + struct pci_device_id ids; + unsigned int bar1; + unsigned int sm501memconfig; + + /* PCI is already functional here */ + ids.vendor = 0x126f; + ids.device = 0x0501; + dev = pci_find_devices (&ids, 0); + + if( dev == -1 ){ + printf("No SM501\n"); + } else { + pci_read_config_dword (dev, PCI_BASE_ADDRESS_1, &bar1); + printf("SM501base = %x\n", bar1); + + /* Adjust memory size. The board did not set the correct + strapping. */ + sm501memconfig = mswap32( *(unsigned int *)(bar1+0x10) ); + printf("SM501mem = %x\n", sm501memconfig); + sm501memconfig &= ~((0x7)<<13); + sm501memconfig |= (0x1)<<13; + *(unsigned int *)(bar1+0x10) = mswap32(sm501memconfig); + } +} + +void pciirqfixup(void) +{ + pci_dev_t dev; + int i; + + /* JUST A QUICK HACK */ + + /* USB */ + for(i=0; i<7; i++){ + dev = PCI_BDF(0,1,i); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 28); + } + + /* Graphic */ + dev = PCI_BDF(0,2,0); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 27); +} +#endif + + + +/**********************************************************/ + +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of IXDP */ + gd->bd->bi_arch_number = MACH_TYPE_EMPCA400; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + /* Set this value to prevent probing with 8BIT, which will + generate data-abort-error on the IXP expansion bus. */ + //flash_info[0].portwidth = FLASH_CFI_16BIT; + + /* Expansion bus configuration */ + + /* See also setting of EXP_CS0 is empca400.h */ + *IXP425_EXP_CS1 = 0x85013c42; /* CS for upper part of 32MByte FLASH */ + + *IXP425_EXP_CS2 = 0xbfff0002; /* Win-CE want's write to this */ + + *IXP425_EXP_CS3 = 0x95d02c13; /* iX-Bus 8bit */ + + *IXP425_EXP_CS4 = 0x95d02c12; /* iX-Bus 16bit */ + + /**IXP425_EXP_CS5 = 0x84D23C03 ;*/ /* RTC */ + *IXP425_EXP_CS5 = 0x80403C03 ; /* RTC, improved timing */ + + /* These timings are not optimized. They do not need + IORDY yet. */ + *IXP425_EXP_CS6 = 0x86143c02; /* IDE-CS1, Local */ + + *IXP425_EXP_CS7 = 0x86143c02; /* unused */ + + return 0; +} + +/**********************************************************/ + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + if( *IXP425_EXP_CFG0 & (1<<20) ){ + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE_A; + } else { + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE_B; + } + +#if 0 /* TESTCODE */ + sm501fixup(); + pciirqfixup(); +#endif + + return (0); +} + +/**********************************************************/ + +extern struct pci_controller hose; +extern void pci_ixp_init(struct pci_controller * hose); + +void pci_init_board(void) +{ + pci_ixp_init(&hose); + + /* pci_init() (which is calling us) is called by cpu.c. + This is done prior to all other initializations. Therefore, + you cant make any log messages here (not even on a LED) */ +} + + +#define IRQ_IXDP425_PCI_INTA 28 +#define IRQ_IXDP425_PCI_INTB 27 +#define IRQ_IXDP425_PCI_INTC 26 +#define IRQ_IXDP425_PCI_INTD 25 /* not used on emPC-A400 */ + +static int pci_irq_table[4] = { + IRQ_IXDP425_PCI_INTA, + IRQ_IXDP425_PCI_INTB, + IRQ_IXDP425_PCI_INTC, + IRQ_IXDP425_PCI_INTD +}; + + +int pciTranslateIrq(pci_dev_t dev, int intPin) +{ + if (PCI_BUS(dev) == 0) { + return pci_irq_table[(PCI_DEV(dev)+intPin-2)%4] ; + } else { + /* FIXME: Bridge to be implemented */ + } + return 0; +} + +#if defined (CONFIG_CMD_IDE) +/* These are specialized in/out commands for the IDE on the + emPC-A400 board */ +extern ulong ide_bus_offset[]; +void inline ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + *((volatile ushort *)(ATA_CURR_BASE(dev)+port)) = val; + debug ("done"); +} +unsigned char inline ide_inb(int dev, int port) +{ + ushort val; + val = *((volatile ushort *)(ATA_CURR_BASE(dev)+port)); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val&0xff); + debug ("done"); +} + +/* Seems ARM arch does not provide them, but cmd_ide wants them to + compile properly (however they are not used) */ +void outb(unsigned char x, short a) +{ +} +unsigned char inb(short a) +{ + return 0; +} +#endif diff -uprN u-boot-orig//board/empca400/Makefile u-boot/board/empca400/Makefile --- u-boot-orig//board/empca400/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/Makefile 2008-12-02 10:03:44.000000000 +0100 @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := empca400.o cmd_npeload.o cmd_bootce.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff -uprN u-boot-orig//board/empca400/npe.h u-boot/board/empca400/npe.h --- u-boot-orig//board/empca400/npe.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/npe.h 2006-08-21 10:37:05.000000000 +0200 @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2002-2006 Christian Hohnstaedt <chohnstaedt(a)innominate.com> + * + * This file is released under the GPLv2 + */ + +#ifndef NPE_DEVICE_H +#define NPE_DEVICE_H + +#include "npe_regs.h" + +enum blk_type { + instruction, + data, +}; + +struct dl_block { + u32 type; + u32 offset; +}; + +struct dl_image { + u32 magic; + u32 id; + u32 size; + union { + u32 data[0]; + struct dl_block block[0]; + } u; +}; + +struct npe_plat_data { + const char *name; + int data_size; + int inst_size; + int id; /* Node ID */ + int eth_id; /* Physical ID */ + int rx_id; + int rxfree_id; + int tx_id; + int txdone_id; +}; + +struct npe_info { + //struct resource *res; + void *addr; + struct npe_plat_data *plat; + u8 img_info[4]; + u32 exec_count; + u32 ctx_reg2; +}; + + +static inline void npe_reg_write(struct npe_info *npe, u32 reg, u32 val) +{ + *(volatile u32*)((u8*)(npe->addr) + reg) = val; +} + +static inline u32 npe_reg_read(struct npe_info *npe, u32 reg) +{ + return *(volatile u32*)((u8*)(npe->addr) + reg); +} + +static inline u32 npe_status(struct npe_info *npe) +{ + return npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXCTL); +} + +/* ixNpeDlNpeMgrCommandIssue */ +static inline void npe_write_exctl(struct npe_info *npe, u32 cmd) +{ + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd); +} +/* ixNpeDlNpeMgrWriteCommandIssue */ +static inline void +npe_write_cmd(struct npe_info *npe, u32 addr, u32 data, int cmd) +{ + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXDATA, data); + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXAD, addr); + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd); +} +/* ixNpeDlNpeMgrReadCommandIssue */ +static inline u32 +npe_read_cmd(struct npe_info *npe, u32 addr, int cmd) +{ + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXAD, addr); + npe_reg_write(npe, IX_NPEDL_REG_OFFSET_EXCTL, cmd); + /* Intel reads the data twice - so do we... */ + npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXDATA); + return npe_reg_read(npe, IX_NPEDL_REG_OFFSET_EXDATA); +} + +/* ixNpeDlNpeMgrExecAccRegWrite */ +static inline void npe_write_ecs_reg(struct npe_info *npe, u32 addr, u32 data) +{ + npe_write_cmd(npe, addr, data, IX_NPEDL_EXCTL_CMD_WR_ECS_REG); +} +/* ixNpeDlNpeMgrExecAccRegRead */ +static inline u32 npe_read_ecs_reg(struct npe_info *npe, u32 addr) +{ + return npe_read_cmd(npe, addr, IX_NPEDL_EXCTL_CMD_RD_ECS_REG); +} + +extern struct device *get_npe_by_id(int id); + +/* NPE Messages */ +extern int npe_mh_setportaddr(struct npe_info *npe, u8 *macaddr); +extern int npe_mh_disable_firewall(struct npe_info *npe); +int npe_mh_set_rxqid(struct npe_info *npe, int qid); + +#endif diff -uprN u-boot-orig//board/empca400/npe_regs.h u-boot/board/empca400/npe_regs.h --- u-boot-orig//board/empca400/npe_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/npe_regs.h 2006-08-21 09:33:23.000000000 +0200 @@ -0,0 +1,82 @@ +#ifndef NPE_REGS_H +#define NPE_REGS_H + +/* Execution Address */ +#define IX_NPEDL_REG_OFFSET_EXAD 0x00 +/* Execution Data */ +#define IX_NPEDL_REG_OFFSET_EXDATA 0x04 +/* Execution Control */ +#define IX_NPEDL_REG_OFFSET_EXCTL 0x08 +/* Execution Count */ +#define IX_NPEDL_REG_OFFSET_EXCT 0x0C +/* Action Point 0 */ +#define IX_NPEDL_REG_OFFSET_AP0 0x10 +/* Action Point 1 */ +#define IX_NPEDL_REG_OFFSET_AP1 0x14 +/* Action Point 2 */ +#define IX_NPEDL_REG_OFFSET_AP2 0x18 +/* Action Point 3 */ +#define IX_NPEDL_REG_OFFSET_AP3 0x1C +/* Watchpoint FIFO */ +#define IX_NPEDL_REG_OFFSET_WFIFO 0x20 +/* Watch Count */ +#define IX_NPEDL_REG_OFFSET_WC 0x24 +/* Profile Count */ +#define IX_NPEDL_REG_OFFSET_PROFCT 0x28 + +/* Messaging Status */ +#define IX_NPEDL_REG_OFFSET_STAT 0x2C +/* Messaging Control */ +#define IX_NPEDL_REG_OFFSET_CTL 0x30 +/* Mailbox Status */ +#define IX_NPEDL_REG_OFFSET_MBST 0x34 +/* messaging in/out FIFO */ +#define IX_NPEDL_REG_OFFSET_FIFO 0x38 + + +#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 +#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 +#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 + +#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 +#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 +#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 +#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 +#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C +#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 +#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 +#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 +#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 +#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 +#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 + +#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 +#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 +#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 + +#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 +#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 +#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 + +#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C +#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 +#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 + +/* NPE control register bit definitions */ +#define IX_NPEMH_NPE_CTL_OFE (1 << 16) /**< OutFifoEnable */ +#define IX_NPEMH_NPE_CTL_IFE (1 << 17) /**< InFifoEnable */ +#define IX_NPEMH_NPE_CTL_OFEWE (1 << 24) /**< OutFifoEnableWriteEnable */ +#define IX_NPEMH_NPE_CTL_IFEWE (1 << 25) /**< InFifoEnableWriteEnable */ + +/* NPE status register bit definitions */ +#define IX_NPEMH_NPE_STAT_OFNE (1 << 16) /**< OutFifoNotEmpty */ +#define IX_NPEMH_NPE_STAT_IFNF (1 << 17) /**< InFifoNotFull */ +#define IX_NPEMH_NPE_STAT_OFNF (1 << 18) /**< OutFifoNotFull */ +#define IX_NPEMH_NPE_STAT_IFNE (1 << 19) /**< InFifoNotEmpty */ +#define IX_NPEMH_NPE_STAT_MBINT (1 << 20) /**< Mailbox interrupt */ +#define IX_NPEMH_NPE_STAT_IFINT (1 << 21) /**< InFifo interrupt */ +#define IX_NPEMH_NPE_STAT_OFINT (1 << 22) /**< OutFifo interrupt */ +#define IX_NPEMH_NPE_STAT_WFINT (1 << 23) /**< WatchFifo interrupt */ + +#endif + diff -uprN u-boot-orig//board/empca400/u-boot.lds u-boot/board/empca400/u-boot.lds --- u-boot-orig//board/empca400/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/empca400/u-boot.lds 2005-12-16 17:39:27.000000000 +0100 @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -uprN u-boot-orig//common/cmd_ide.c u-boot/common/cmd_ide.c --- u-boot-orig//common/cmd_ide.c 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/common/cmd_ide.c 2008-12-03 09:22:29.000000000 +0100 @@ -900,7 +900,7 @@ input_swap_data(int dev, ulong *sect_buf #ifdef __MIPS__ *dbuf++ = swab16p((u16*)pbuf); *dbuf++ = swab16p((u16*)pbuf); -#elif defined(CONFIG_PCS440EP) +#elif defined(CONFIG_PCS440EP) || defined(CONFIG_EMPCA400) *dbuf++ = *pbuf; *dbuf++ = *pbuf; #else @@ -957,7 +957,25 @@ output_data(int dev, ulong *sect_buf, in } #endif } -#else /* ! __PPC__ */ +#elif defined(CONFIG_EMPCA400) +static void +output_data(int dev, ulong *sect_buf, int words) +{ + ushort *dbuf; + ushort d; + volatile ushort *pbuf; + + pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + dbuf = (ushort *)sect_buf; + words *= 2; + while (words--) { + d = *dbuf; + *pbuf++ = ((d<<8)&0xff00) | ((d>>8)&0x00ff); + } + debug ("output_data (dev= %d) : @ 0x%08lx %d words\n", + dev, (ATA_CURR_BASE(dev)+ATA_DATA_REG), words); +} +#else static void output_data(int dev, ulong *sect_buf, int words) { @@ -1015,6 +1033,47 @@ input_data(int dev, ulong *sect_buf, int } #endif } +#elif defined(CONFIG_EMPCA400) +static void +input_data(int dev, ulong *sect_buf, int words) +{ + /* Data comes swapped with the IXP4xx in big endian mode, + so we need to re-swap it while reading */ + /* Optimized version with 32bit read at a time */ + ulong *dbuf; + uchar *cdbuf; + ulong d; + volatile ulong *pbuf; + + pbuf = (ulong *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); + + debug("input_data (dev= %d) : @ 0x%08lx %d words\n", + dev, pbuf, words); + + if (((long)sect_buf & 0x3) == 0) { + /* If sector buffer is 32bit aligned (hopefully this + is always true) */ + dbuf = (ulong *)sect_buf; + while (words--) { + d = *pbuf; + /* using 0xffff00ff implies that unsigned shift will + shift zeroes into high bits. Compiler specific! */ + *dbuf++ = ((d<<8)&0xff00ffff) | ((d>>8)&0xffff00ff); + } + } else { + cdbuf = (uchar *)sect_buf; + while (words--) { + d = *pbuf; + /* using 0xffff00ff implies that unsigned shift will + shift zeroes into high bits. Compiler specific! */ + d = ((d<<8)&0xff00ffff) | ((d>>8)&0xffff00ff); + *cdbuf++ = (d>>24); + *cdbuf++ = (d>>16); + *cdbuf++ = (d>> 8); + *cdbuf++ = (d>> 0); + } + } +} #else /* ! __PPC__ */ static void input_data(int dev, ulong *sect_buf, int words) @@ -1740,8 +1805,18 @@ input_data_shorts(int dev, ushort *sect_ } #endif } +#elif defined(CONFIG_EMPCA400) +output_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + /* not supported or tested */ +} -#else /* ! __PPC__ */ +static void +input_data_shorts(int dev, ushort *sect_buf, int shorts) +{ + /* not supported or tested */ +} +#else static void output_data_shorts(int dev, ushort *sect_buf, int shorts) { diff -uprN u-boot-orig//cpu/ixp/start.S u-boot/cpu/ixp/start.S --- u-boot-orig//cpu/ixp/start.S 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/cpu/ixp/start.S 2008-12-03 10:27:48.000000000 +0100 @@ -165,7 +165,18 @@ reset: orr r1, r1, #0x80000000 str r1, [r2] #endif + +#if defined(CONFIG_EMPCA400) + /* check for SDRAM size by checking for LA20 + strapping to determine config (see empca400.h) */ + ldr r1, =IXP425_EXP_CFG0 + ldr r2, [r1] + tst r2, #0x100000 + ldrne r1, =CONFIG_SYS_SDR_CONFIG_A + ldreq r1, =CONFIG_SYS_SDR_CONFIG_B +#else mov r1, #CONFIG_SYS_SDR_CONFIG +#endif ldr r2, =IXP425_SDR_CONFIG str r1, [r2] @@ -194,7 +205,11 @@ reset: mov r1, #4 mov r5, #8 111: str r1, [r4] +#if defined(CONFIG_EMPCA400) + DELAY_FOR 0x1000, r0 +#else DELAY_FOR 0x100, r0 +#endif subs r5, r5, #1 bne 111b diff -uprN u-boot-orig//include/configs/empca400.h u-boot/include/configs/empca400.h --- u-boot-orig//include/configs/empca400.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/configs/empca400.h 2008-12-03 10:26:25.000000000 +0100 @@ -0,0 +1,288 @@ +/* + * (C) Copyright 2003 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * Stefan Althoefer, Janz Automationssystem AG + * + * Configuation settings for the emPC-A400 CPU board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_EMPCA400 1 /* On an emPC-A400 board */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_IXP4XX_NPE +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x0 + +#define CONFIG_DISPLAY_CPUINFO + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* Ethernet address can be overwritten once */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_BAUDRATE 9600 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_ELF +#define CONFIG_CMD_PCI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.0.21 +#define CONFIG_SERVERIP 192.168.0.148 +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_BOOTARGS "console=ttyS0,9600" + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 ">" +#define CONFIG_SYS_AUTO_COMPLETE +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ + +#ifdef CONFIG_USE_IRQ +/* Interrupt driven timer wants system tick here */ +#define CONFIG_SYS_HZ 1000 +#else +/* The code in cpu/ixp/timer.c needs timer clock tick in HZ */ +#define CONFIG_SYS_HZ 66666666 +#endif + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*************************************************************** + * Platform/Board specific defines start here. + ***************************************************************/ + +/* + * Hardware drivers + */ + +/* + * I2C configuration + */ +#define CONFIG_SOFT_I2C /* Software I2C support enabled */ +#define CONFIG_SOFT_I2C_INCLUDE <asm/arch-ixp/ixp425.h> + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0xFE +/* + * Software (bit-bang) I2C driver configuration + */ +#define IXP425_SCL (1<<6) +#define IXP425_SDA (1<<7) + +#define I2C_PORT 0 +#define I2C_INIT do { *IXP425_GPIO_GPOER &= ~IXP425_SCL; \ + *IXP425_GPIO_GPOER |= IXP425_SDA; \ + *IXP425_GPIO_GPOUTR &= ~IXP425_SDA; } while(0) +#define I2C_ACTIVE +#define I2C_TRISTATE +#define I2C_READ ((*IXP425_GPIO_GPINR & IXP425_SDA) != 0 ) +#define I2C_SDA(bit) if(bit) (*IXP425_GPIO_GPOER |= IXP425_SDA); \ + else (*IXP425_GPIO_GPOER &= ~IXP425_SDA) +#define I2C_SCL(bit) if(bit) (*IXP425_GPIO_GPOUTR |= IXP425_SCL); \ + else (*IXP425_GPIO_GPOUTR &= ~IXP425_SCL) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CONFIG_ENV_OFFSET 0x010 /* environment starts at offset 10 */ +#define CONFIG_ENV_SIZE 0x500 /* 1280 bytes may be used for env vars */ + /* total size of a CAT24WC32 0x1000 bytes */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x00 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ + +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 11 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +/* + * select serial console configuration + */ +#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 /* we use UART2 for console */ + +/* This should be autodetected */ +#define HAVE64MBYTE + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE_A 0x04000000 /* LA20=high : 64MByte */ +#define PHYS_SDRAM_1_SIZE_B 0x08000000 /* LA20=low : 128MByte */ + +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + + +/* + * Expansion bus settings + */ +/* Old setting */ +/*#define CONFIG_SYS_EXP_CS0 0xbcd23c42*/ + +/* This setting works with 150ns RD/WR pulse */ +/* Setup time (T2) is set to 60ns to accomodate delay + of CS and A24 by the PLD */ +/* See also setting of EXP_CS1 in empca400.c */ +#define CONFIG_SYS_EXP_CS0 0x85013c42 + +/* + * SDRAM settings + */ +#define CONFIG_SYS_SDR_CONFIG_A 0xa /* LA20=high : 64MByte */ +#define CONFIG_SYS_SDR_CONFIG_B 0xc /* LA20=low : 128MByte */ +#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 +#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x40f + +/* + * GPIO settings + */ + +/* + * IDE/ATA settings + */ +#define CONFIG_DOS_PARTITION + +#define CONFIG_SYS_ATA_STRIDE 4 + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x56000000 /* base address */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* ide0 offste */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x20 /* alternate register offset */ + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported... */ +#undef CONFIG_IDE_RESET_ROUTINE +#define CONFIG_SUPPORT_VFAT + + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +/* no byte writes on IXP4xx */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* Addr of Environment Sector */ + +/* Video */ +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_VIDEO_SM501NEW +#define VIDEO_FB_LITTLE_ENDIAN +#undef VIDEO_HW_RECTFILL +#undef VIDEO_HW_BITBLT + + +#endif /* __CONFIG_H */ diff -uprN u-boot-orig//MAKEALL u-boot/MAKEALL --- u-boot-orig//MAKEALL 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/MAKEALL 2008-12-03 11:29:51.000000000 +0100 @@ -573,6 +573,7 @@ LIST_ixp=" \ actux2 \ actux3 \ actux4 \ + empca400 \ ixdp425 \ ixdpg425 \ pdnb3 \ diff -uprN u-boot-orig//Makefile u-boot/Makefile --- u-boot-orig//Makefile 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/Makefile 2008-12-02 18:02:24.000000000 +0100 @@ -2813,6 +2814,9 @@ csb226_config : unconfig delta_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa delta +empca400_config : unconfig + @$(MKCONFIG) $(@:_config=) arm ixp empca400 + innokom_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa innokom

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[U-Boot] [PATCH] IXP425: Changing serial port initialization sequence Part 1/1
by Stefan Althoefer 04 Dec '08

04 Dec '08

[PATCH] IXP425: Changing serial port initialization sequence On my IXP425 board (Janz emPC-A400), the first few characters of the u-boot startup message were missing. I fixed it by enabling the UART before all other initialization. I also enabled (and flushed) the FIFO of the UART. The patch is against "latest" u-boot git-repository Please (still) be patient if style of submission or patches are offending. Signed-off-by: Stefan Althoefer <stefan.althoefer(a)web.de> ---- diff -uprN u-boot-orig//cpu/ixp/serial.c u-boot/cpu/ixp/serial.c --- u-boot-orig//cpu/ixp/serial.c 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/cpu/ixp/serial.c 2008-12-02 22:46:27.000000000 +0100 @@ -50,8 +50,10 @@ void serial_setbrg (void) else hang (); - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ + IER(uart) = IER_UUE; + + /* Enable an clear FIFOs */ + FCR(uart) = FCR_RESETTF | FCR_RESETRF | FCR_TRFIFOE; /* set baud rate */ LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; @@ -63,7 +65,6 @@ void serial_setbrg (void) #else MCR(uart) = 0; /* set RTS inactive */ #endif - IER(uart) = IER_UUE; } /*

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[U-Boot] [PATCH] drivers/fsl_pci_init: Fix inbound window mapping bug
by beckyb＠kernel.crashing.org 04 Dec '08

04 Dec '08

From: Becky Bruce <becky.bruce(a)freescale.com> The current code will cause the creation of a 4GB window starting at 0 if we have more than 4GB of RAM installed, which overlaps with PCI_MEM space and causes pci_bus_to_phys() to return erroneous information. Limit the size to 4GB - 1; which causes the code to create one 2GB and one 1GB window instead. Signed-off-by: Becky Bruce <beckyb(a)kernel.crashing.org> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/pci/fsl_pci_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 7625ccc..e57acba 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -58,7 +58,7 @@ void pciauto_config_init(struct pci_controller *hose); int fsl_pci_setup_inbound_windows(struct pci_region *r) { struct pci_region *rgn_base = r; - u64 sz = min((u64)gd->ram_size, 1ull << 32); + u64 sz = min((u64)gd->ram_size, (1ull << 32) - 1); phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; -- 1.5.6.5

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[U-Boot] [PATCH 3/5] fsl-ddr: make the self refresh idle threshold configurable
by Dave Liu 04 Dec '08

04 Dec '08

Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 ++++++++---- include/asm-ppc/fsl_ddr_sdram.h | 4 ++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index eae794c..292980d 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -755,10 +755,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr) } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) { - unsigned int sr_it = 0; /* Self Refresh Idle Threshold */ - + /* Self Refresh Idle Threshold */ ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; } @@ -861,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, unsigned int i; unsigned int cas_latency; unsigned int additive_latency; + unsigned int sr_it; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -882,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ? popts->additive_latency_override_value : common_dimm->additive_latency; + sr_it = (popts->auto_self_refresh_en) + ? popts->sr_it + : 0; + /* Chip Select Memory Bounds (CSn_BNDS) */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { phys_size_t sa = 0; @@ -1042,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_wrlvl_cntl(ddr); set_ddr_pd_cntl(ddr); - set_ddr_sr_cntr(ddr); + set_ddr_sr_cntr(ddr, sr_it); set_ddr_sdram_rcw_1(ddr); set_ddr_sdram_rcw_2(ddr); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 0006c21..b213af3 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct memctl_options_s { unsigned int bstopre; unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); -- 1.5.4

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[U-Boot] [PATCH 1/5] fsl-ddr: update the bit mask for DDR3 controller
by Dave Liu 04 Dec '08

04 Dec '08

According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 1783e92..d5cdc36 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -185,10 +185,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */ unsigned int cntl_adj = 0; /* Control Adjust */ + /* If the tRAS > 19 MCLK, we use the ext mode */ + if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13) + ext_acttopre = 1; + ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4; ddr->timing_cfg_3 = (0 | ((ext_acttopre & 0x1) << 24) - | ((ext_refrec & 0x7) << 16) + | ((ext_refrec & 0xF) << 16) | ((ext_caslat & 0x1) << 12) | ((cntl_adj & 0x7) << 0) ); @@ -251,12 +255,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps); ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x07) << 28) + | ((pretoact_mclk & 0x0F) << 28) | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0x7) << 20) + | ((acttorw_mclk & 0xF) << 20) | ((caslat_ctrl & 0xF) << 16) | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x07) << 8) + | ((wrrec_mclk & 0x0F) << 8) | ((acttoact_mclk & 0x07) << 4) | ((wrtord_mclk & 0x07) << 0) ); -- 1.5.4

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[U-Boot] [PATCH 2/5] fsl-ddr: clean up the ddr code for DDR3 controller
by Dave Liu 04 Dec '08

04 Dec '08

- The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc8xxx/ddr/ctrl_regs.c | 24 +++++++++++++----------- include/asm-ppc/fsl_ddr_sdram.h | 3 +++ 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index d5cdc36..eae794c 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -167,7 +167,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) | ((trrt_mclk & 0x3) << 26) /* RRT */ | ((twwt_mclk & 0x3) << 24) /* WWT */ | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0x7) << 16) /* PRE_PD_EXIT */ + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ ); @@ -313,13 +313,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps); ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0x7) << 28) + | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) - | ((wr_lat & 0x7) << 19) + | ((wr_lat & 0xf) << 19) | ((rd_to_pre & 0x7) << 13) | ((wr_data_delay & 0x7) << 10) | ((cke_pls & 0x7) << 6) - | ((four_act & 0x1f) << 0) + | ((four_act & 0x3f) << 0) ); debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); } @@ -336,7 +336,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int sdram_type; /* Type of SDRAM */ unsigned int dyn_pwr; /* Dynamic power management mode */ unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be; /* 8-beat burst enable */ + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ unsigned int ncap = 0; /* Non-concurrent auto-precharge */ unsigned int threeT_en; /* Enable 3T timing */ unsigned int twoT_en; /* Enable 2T timing */ @@ -363,7 +363,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, dyn_pwr = popts->dynamic_power; dbw = popts->data_bus_width; - eight_be = 0; /* always 0 for DDR2 */ + /* DDR3 must use 8-beat bursts when using 32-bit bus mode */ + if ((sdram_type == SDRAM_TYPE_DDR3) && (dbw == 0x1)) + eight_be = 1; threeT_en = popts->threeT_en; twoT_en = popts->twoT_en; ba_intlv_ctl = popts->ba_intlv_ctl; @@ -695,10 +697,10 @@ static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr) unsigned int wodt_off = 0; /* Write to ODT off */ ddr->timing_cfg_5 = (0 - | ((rodt_on & 0xf) << 24) - | ((rodt_off & 0xf) << 20) - | ((wodt_on & 0xf) << 12) - | ((wodt_off & 0xf) << 8) + | ((rodt_on & 0x1f) << 24) + | ((rodt_off & 0x7) << 20) + | ((wodt_on & 0x1f) << 12) + | ((wodt_off & 0x7) << 8) ); debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); } @@ -748,7 +750,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr) | ((wrlvl_dqsen & 0x7) << 16) | ((wrlvl_smpl & 0xf) << 12) | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0xF) << 0) + | ((wrlvl_start & 0x1F) << 0) ); } diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c1ea7cd..0006c21 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; #elif defined(CONFIG_FSL_DDR3) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#endif /* #if defined(CONFIG_FSL_DDR1) */ /* define bank(chip select) interleaving mode */ #define FSL_DDR_CS0_CS1 0x40 -- 1.5.4

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