December 2008 - U-Boot

[U-Boot] Increase command line size
by Paulo Flabiano Smorigo 09 Dec '08

09 Dec '08

Hi everybody, I want to know how to increase the command line size to more than 255 characters. I want to set the bootargs parameter with more than 300 chars... Thanks in advance, Paulo Flabiano Smorigo

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[U-Boot] Lost of data in board info before relocating U-Boot in SDRAM
by Gregory Medwed 09 Dec '08

09 Dec '08

Hi everybody, I'm porting U-Boot 2008.10 to a new board based on AMCC PPC460EX processor. I took AMCC canyonlands board as starting point. I port U-Boot and have the prompt and most basic commands are working fine. But, all info passed to bd_t (board info) before relocation of U-Boot are lost. Any advices ? Best regards Gregory Medwed

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[U-Boot] [PATCH v5] ppc4xx: Add GDsys PowerPC 440 ETX board support.
by Dirk Eibach 09 Dec '08

09 Dec '08

Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Depends on [PATCH v3] ppc4xx: Improve DDR autodetect More whitespace rework. MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/gdsys/gdppc440etx/Makefile | 51 +++++ board/gdsys/gdppc440etx/config.mk | 44 +++++ board/gdsys/gdppc440etx/gdppc440etx.c | 325 +++++++++++++++++++++++++++++++++ board/gdsys/gdppc440etx/init.S | 75 ++++++++ board/gdsys/gdppc440etx/u-boot.lds | 144 +++++++++++++++ include/configs/gdppc440etx.h | 194 ++++++++++++++++++++ 9 files changed, 838 insertions(+), 0 deletions(-) create mode 100644 board/gdsys/gdppc440etx/Makefile create mode 100644 board/gdsys/gdppc440etx/config.mk create mode 100644 board/gdsys/gdppc440etx/gdppc440etx.c create mode 100644 board/gdsys/gdppc440etx/init.S create mode 100644 board/gdsys/gdppc440etx/u-boot.lds create mode 100644 include/configs/gdppc440etx.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b..b836263 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Dirk Eibach <eibach(a)gdsys.de> + gdppc440etx PPC440EP/GR neo PPC405EP Dave Ellis <DGE(a)sixnetio.com> diff --git a/MAKEALL b/MAKEALL index dbed268..3789bb9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -188,6 +188,7 @@ LIST_4xx=" \ EXBITGEN \ fx12mm \ G2000 \ + gdppc440etx \ glacier \ haleakala \ haleakala_nand \ diff --git a/Makefile b/Makefile index befb608..d77ab3a 100644 --- a/Makefile +++ b/Makefile @@ -1315,6 +1315,9 @@ fx12mm_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +gdppc440etx_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys + hcu4_config: unconfig @mkdir -p $(obj)board/netstal/common @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile new file mode 100644 index 0000000..b93f2c3 --- /dev/null +++ b/board/gdsys/gdppc440etx/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk new file mode 100644 index 0000000..045f3e9 --- /dev/null +++ b/board/gdsys/gdppc440etx/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# G&D 440EP/GR ETX-Module +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 0000000..e1890ff --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on board/amcc/yosemite/yosemite.c + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +int board_early_init_f(void) +{ + register uint reg; + + /* + * Setup the external bus controller/chip selects + */ + mfebc(xbcfg, reg); + mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + + /* + * Setup the GPIO pins + */ + + /* setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); + + /* setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /* UART0 and UART1*/ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); + + /* disable boot-eeprom WP */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); + out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /* + * Setup other serial configuration + */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + return 0; +} + +int misc_init_r(void) +{ + uint pbcr; + int size_val; + uint sz; + + /* Re-do sizing to get full correct info */ + mfebc(pb0cr, pbcr); + + if (gd->bd->bi_flashsize > 0x08000000) + panic("Max. flash banksize is 128 MB!\n"); + + for (sz = gd->bd->bi_flashsize, size_val = 7; + ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) + sz <<= 1; + + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + u8 rev; + u8 val; + + printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /* + * Set priority for all PLB4 devices to 0. + */ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /* + * Set Nebula PLB4 arbiter to fair mode. + */ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + /* enable 66 MHz ext. Clock */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); + out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF + * ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); + out32r(PCIX0_PTM1LA, 0); + out32r(PCIX0_PTM2MS, 0); + out32r(PCIX0_PTM2LA, 0); + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ + +/* + * pci_master_init + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ + +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + */ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S new file mode 100644 index 0000000..0bbd45a --- /dev/null +++ b/board/gdsys/gdppc440etx/init.S @@ -0,0 +1,75 @@ +/* +* (C) Copyright 2008 +* Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de +* +* based on board/amcc/yosemite/init.S +* original Copyright not specified there +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use + * the speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, + 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, + 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, + 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, + 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds new file mode 100644 index 0000000..1df817b --- /dev/null +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/gdsys/gdppc440etx/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 0000000..701a6fb --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#endif /* __CONFIG_H */ -- 1.5.6.5

3 3

[U-Boot] [PATCH v4] ppc4xx: Add GDsys PowerPC 440 ETX board support.
by Dirk Eibach 09 Dec '08

09 Dec '08

Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Depends on [PATCH v3] ppc4xx: Improve DDR autodetect Removed legacy includes in board/gdsys/gdppc440etx/gdppc440etx.c. Used mfebc()/mtebc() in board/gdsys/gdppc440etx/gdppc440etx.c. Identation with tabs instead of spaces in include/configs/gdppc440etx.h. MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/gdsys/gdppc440etx/Makefile | 51 +++++ board/gdsys/gdppc440etx/config.mk | 44 +++++ board/gdsys/gdppc440etx/gdppc440etx.c | 325 +++++++++++++++++++++++++++++++++ board/gdsys/gdppc440etx/init.S | 75 ++++++++ board/gdsys/gdppc440etx/u-boot.lds | 144 +++++++++++++++ include/configs/gdppc440etx.h | 194 ++++++++++++++++++++ 9 files changed, 838 insertions(+), 0 deletions(-) create mode 100644 Makefile create mode 100644 board/gdsys/gdppc440etx/config.mk create mode 100644 board/gdsys/gdppc440etx/gdppc440etx.c create mode 100644 board/gdsys/gdppc440etx/init.S create mode 100644 board/gdsys/gdppc440etx/u-boot.lds create mode 100644 include/configs/gdppc440etx.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b..b836263 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Dirk Eibach <eibach(a)gdsys.de> + gdppc440etx PPC440EP/GR neo PPC405EP Dave Ellis <DGE(a)sixnetio.com> diff --git a/MAKEALL b/MAKEALL index dbed268..3789bb9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -188,6 +188,7 @@ LIST_4xx=" \ EXBITGEN \ fx12mm \ G2000 \ + gdppc440etx \ glacier \ haleakala \ haleakala_nand \ diff --git a/Makefile b/Makefile index befb608..d77ab3a 100644 --- a/Makefile +++ b/Makefile @@ -1315,6 +1315,9 @@ fx12mm_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +gdppc440etx_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys + hcu4_config: unconfig @mkdir -p $(obj)board/netstal/common @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile new file mode 100644 index 0000000..b93f2c3 --- /dev/null +++ b/board/gdsys/gdppc440etx/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk new file mode 100644 index 0000000..045f3e9 --- /dev/null +++ b/board/gdsys/gdppc440etx/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# G&D 440EP/GR ETX-Module +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 0000000..e1890ff --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on board/amcc/yosemite/yosemite.c + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +int board_early_init_f(void) +{ + register uint reg; + + /* + * Setup the external bus controller/chip selects + */ + mfebc(xbcfg, reg); + mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + + /* + * Setup the GPIO pins + */ + + /* setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); + + /* setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /* UART0 and UART1*/ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); + + /* disable boot-eeprom WP */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); + out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /* + * Setup other serial configuration + */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + return 0; +} + +int misc_init_r(void) +{ + uint pbcr; + int size_val; + uint sz; + + /* Re-do sizing to get full correct info */ + mfebc(pb0cr, pbcr); + + if (gd->bd->bi_flashsize > 0x08000000) + panic("Max. flash banksize is 128 MB!\n"); + + for (sz = gd->bd->bi_flashsize, size_val = 7; + ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) + sz <<= 1; + + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + u8 rev; + u8 val; + + printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /* + * Set priority for all PLB4 devices to 0. + */ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /* + * Set Nebula PLB4 arbiter to fair mode. + */ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + /* enable 66 MHz ext. Clock */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); + out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF + * ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); + out32r(PCIX0_PTM1LA, 0); + out32r(PCIX0_PTM2MS, 0); + out32r(PCIX0_PTM2LA, 0); + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ + +/* + * pci_master_init + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ + +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + */ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S new file mode 100644 index 0000000..0bbd45a --- /dev/null +++ b/board/gdsys/gdppc440etx/init.S @@ -0,0 +1,75 @@ +/* +* (C) Copyright 2008 +* Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de +* +* based on board/amcc/yosemite/init.S +* original Copyright not specified there +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use + * the speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, + 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, + 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, + 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, + 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds new file mode 100644 index 0000000..1df817b --- /dev/null +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/gdsys/gdppc440etx/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 0000000..edee177 --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#endif /* __CONFIG_H */ -- 1.5.6.5

2 1

[U-Boot] [PATCH 1/1] Make FAT code comply to coding rules.
by Remy Böhmer 09 Dec '08

09 Dec '08

Currently the fat code is messy related to Coding rules. Signed-off-by: Remy Bohmer <linux(a)bohmer.net> --- fs/fat/fat.c | 1004 ++++++++++++++++++++++++++++----------------------------- fs/fat/file.c | 65 ++-- include/fat.h | 7 +- 3 files changed, 518 insertions(+), 558 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 06eabc3..0d4942a 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -34,8 +34,7 @@ /* * Convert a string to lowercase. */ -static void -downcase(char *str) +static void downcase(char *str) { while (*str != '\0') { TOLOWER(*str); @@ -43,7 +42,7 @@ downcase(char *str) } } -static block_dev_desc_t *cur_dev = NULL; +static block_dev_desc_t *cur_dev = NULL; static unsigned long part_offset = 0; static int cur_part = 1; @@ -51,21 +50,18 @@ static int cur_part = 1; #define DOS_PART_MAGIC_OFFSET 0x1fe #define DOS_FS_TYPE_OFFSET 0x36 -int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) +static int disk_read(__u32 startblock, __u32 nofblocks, __u8 *bufptr) { startblock += part_offset; if (cur_dev == NULL) return -1; - if (cur_dev->block_read) { - return cur_dev->block_read (cur_dev->dev - , startblock, getsize, (unsigned long *)bufptr); - } + if (cur_dev->block_read) + return cur_dev->block_read(cur_dev->dev, startblock, nofblocks, + (unsigned long *)bufptr); return -1; } - -int -fat_register_device(block_dev_desc_t *dev_desc, int part_no) +int fat_register_device(block_dev_desc_t *dev_desc, int part_no) { unsigned char buffer[SECTOR_SIZE]; disk_partition_t info; @@ -74,22 +70,22 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) return -1; cur_dev = dev_desc; /* check if we have a MBR (on floppies we have only a PBR) */ - if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { - printf ("** Can't read from device %d **\n", dev_desc->dev); + if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)buffer) != 1) { + printf("** Can't read from device %d **\n", dev_desc->dev); return -1; } if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || - buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { + buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) /* no signature found */ return -1; - } + #if (defined(CONFIG_CMD_IDE) || \ defined(CONFIG_CMD_SCSI) || \ defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) /* First we assume, there is a MBR */ - if (!get_partition_info (dev_desc, part_no, &info)) { + if (!get_partition_info(dev_desc, part_no, &info)) { part_offset = info.start; cur_part = part_no; } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { @@ -97,13 +93,13 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) cur_part = 1; part_offset = 0; } else { - printf ("** Partition %d not valid on device %d **\n", - part_no, dev_desc->dev); + printf("** Partition %d not valid on device %d **\n", + part_no, dev_desc->dev); return -1; } #else - if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { /* ok, we assume we are on a PBR only */ cur_part = 1; part_offset = 0; @@ -121,37 +117,34 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) return 0; } - /* * Get the first occurence of a directory delimiter ('/' or '\') in a string. * Return index into string if found, -1 otherwise. */ -static int -dirdelim(char *str) +static int dirdelim(char *str) { char *start = str; while (*str != '\0') { - if (ISDIRDELIM(*str)) return str - start; + if (ISDIRDELIM(*str)) + return str - start; str++; } return -1; } - /* * Match volume_info fs_type strings. * Return 0 on match, -1 otherwise. */ -static int -compare_sign(char *str1, char *str2) +static int compare_sign(char *str1, char *str2) { - char *end = str1+SIGNLEN; + char *end = str1 + SIGNLEN; while (str1 != end) { - if (*str1 != *str2) { + if (*str1 != *str2) return -1; - } + str1++; str2++; } @@ -159,15 +152,14 @@ compare_sign(char *str1, char *str2) return 0; } - /* * Extract zero terminated short name from a directory entry. */ -static void get_name (dir_entry *dirent, char *s_name) +static void get_name(dir_entry *dirent, char *s_name) { char *ptr; - memcpy (s_name, dirent->name, 8); + memcpy(s_name, dirent->name, 8); s_name[8] = '\0'; ptr = s_name; while (*ptr && *ptr != ' ') @@ -175,7 +167,7 @@ static void get_name (dir_entry *dirent, char *s_name) if (dirent->ext[0] && dirent->ext[0] != ' ') { *ptr = '.'; ptr++; - memcpy (ptr, dirent->ext, 3); + memcpy(ptr, dirent->ext, 3); ptr[3] = '\0'; while (*ptr && *ptr != ' ') ptr++; @@ -185,19 +177,20 @@ static void get_name (dir_entry *dirent, char *s_name) *s_name = '\0'; else if (*s_name == aRING) *s_name = DELETED_FLAG; - downcase (s_name); + downcase(s_name); } /* * Get the entry at index 'entry' in a FAT (12/16/32) table. * On failure 0x00 is returned. */ -static __u32 -get_fatent(fsdata *mydata, __u32 entry) +static __u32 get_fatent(fsdata *mydata, __u32 entry) { __u32 bufnum; __u32 offset; __u32 ret = 0x00; + __u32 off16; + __u16 val1, val2; switch (mydata->fatsize) { case 32: @@ -220,7 +213,7 @@ get_fatent(fsdata *mydata, __u32 entry) /* Read a new block of FAT entries into the cache. */ if (bufnum != mydata->fatbufnum) { - int getsize = FATBUFSIZE/FS_BLOCK_SIZE; + int nofblocks = FATBUFSIZE / FS_BLOCK_SIZE; __u8 *bufptr = mydata->fatbuf; __u32 fatlength = mydata->fatlength; __u32 startblock = bufnum * FATBUFBLOCKS; @@ -228,8 +221,9 @@ get_fatent(fsdata *mydata, __u32 entry) fatlength *= SECTOR_SIZE; /* We want it in bytes now */ startblock += mydata->fat_sect; /* Offset from start of disk */ - if (getsize > fatlength) getsize = fatlength; - if (disk_read(startblock, getsize, bufptr) < 0) { + if (nofblocks > (fatlength / FS_BLOCK_SIZE)) + nofblocks = fatlength / FS_BLOCK_SIZE; + if (disk_read(startblock, nofblocks, bufptr) < 0) { FAT_DPRINT("Error reading FAT blocks\n"); return ret; } @@ -239,96 +233,89 @@ get_fatent(fsdata *mydata, __u32 entry) /* Get the actual entry from the table */ switch (mydata->fatsize) { case 32: - ret = FAT2CPU32(((__u32*)mydata->fatbuf)[offset]); + ret = FAT2CPU32(((__u32 *) mydata->fatbuf)[offset]); break; case 16: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[offset]); + ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[offset]); break; - case 12: { - __u32 off16 = (offset*3)/4; - __u16 val1, val2; + case 12: + off16 = (offset * 3) / 4; switch (offset & 0x3) { case 0: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]); ret &= 0xfff; break; case 1: - val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]); val1 &= 0xf000; - val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16 + 1]); val2 &= 0x00ff; ret = (val2 << 4) | (val1 >> 12); break; case 2: - val1 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]); + val1 = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]); val1 &= 0xff00; - val2 = FAT2CPU16(((__u16*)mydata->fatbuf)[off16+1]); + val2 = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16 + 1]); val2 &= 0x000f; ret = (val2 << 8) | (val1 >> 8); break; case 3: - ret = FAT2CPU16(((__u16*)mydata->fatbuf)[off16]);; + ret = FAT2CPU16(((__u16 *) mydata->fatbuf)[off16]); ret = (ret & 0xfff0) >> 4; break; default: break; } - } - break; + break; } FAT_DPRINT("ret: %d, offset: %d\n", ret, offset); return ret; } - /* * Read at most 'size' bytes from the specified cluster into 'buffer'. * Return 0 on success, -1 otherwise. */ -static int -get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) +static int get_cluster(fsdata *mydata, __u32 clustnum, + __u8 *buffer, unsigned long size_bytes) { int idx = 0; __u32 startsect; - if (clustnum > 0) { - startsect = mydata->data_begin + clustnum*mydata->clust_size; - } else { + if (clustnum > 0) + startsect = mydata->data_begin + clustnum * mydata->clust_size; + else startsect = mydata->rootdir_sect; - } FAT_DPRINT("gc - clustnum: %d, startsect: %d\n", clustnum, startsect); - if (disk_read(startsect, size/FS_BLOCK_SIZE , buffer) < 0) { + if (disk_read(startsect, size_bytes / FS_BLOCK_SIZE, buffer) < 0) { FAT_DPRINT("Error reading data\n"); return -1; } - if(size % FS_BLOCK_SIZE) { + if (size_bytes % FS_BLOCK_SIZE) { __u8 tmpbuf[FS_BLOCK_SIZE]; - idx= size/FS_BLOCK_SIZE; + idx = size_bytes / FS_BLOCK_SIZE; if (disk_read(startsect + idx, 1, tmpbuf) < 0) { FAT_DPRINT("Error reading data\n"); return -1; } - buffer += idx*FS_BLOCK_SIZE; + buffer += idx * FS_BLOCK_SIZE; - memcpy(buffer, tmpbuf, size % FS_BLOCK_SIZE); + memcpy(buffer, tmpbuf, size_bytes % FS_BLOCK_SIZE); return 0; } - return 0; } - /* * Read at most 'maxsize' bytes from the file associated with 'dentptr' * into 'buffer'. * Return the number of bytes read or -1 on fatal errors. */ -static long -get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, - unsigned long maxsize) +static long get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, + unsigned long maxsize) { unsigned long filesize = FAT2CPU32(dentptr->size), gotsize = 0; unsigned int bytesperclust = mydata->clust_size * SECTOR_SIZE; @@ -338,25 +325,44 @@ get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, FAT_DPRINT("Filesize: %ld bytes\n", filesize); - if (maxsize > 0 && filesize > maxsize) filesize = maxsize; + if (maxsize > 0 && filesize > maxsize) + filesize = maxsize; FAT_DPRINT("Reading: %ld bytes\n", filesize); - actsize=bytesperclust; - endclust=curclust; - do { + actsize = bytesperclust; + endclust = curclust; + for (;;) { /* search for consecutive clusters */ - while(actsize < filesize) { + while (actsize < filesize) { newclust = get_fatent(mydata, endclust); - if((newclust -1)!=endclust) - goto getit; + if ((newclust - 1) != endclust) { + if (get_cluster(mydata, curclust, buffer, + (int)actsize) != 0) { + FAT_ERROR("Error reading cluster\n"); + return -1; + } + gotsize += (int)actsize; + filesize -= actsize; + buffer += actsize; + curclust = get_fatent(mydata, endclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + FAT_DPRINT("curclust: 0x%x\n", + curclust); + FAT_ERROR("Invalid FAT entry\n"); + return gotsize; + } + actsize = bytesperclust; + endclust = curclust; + continue; + } if (CHECK_CLUST(newclust, mydata->fatsize)) { FAT_DPRINT("curclust: 0x%x\n", newclust); FAT_DPRINT("Invalid FAT entry\n"); return gotsize; } - endclust=newclust; - actsize+= bytesperclust; + endclust = newclust; + actsize += bytesperclust; } /* actsize >= file size */ actsize -= bytesperclust; @@ -369,90 +375,75 @@ get_contents(fsdata *mydata, dir_entry *dentptr, __u8 *buffer, gotsize += (int)actsize; filesize -= actsize; buffer += actsize; - actsize= filesize; + actsize = filesize; if (get_cluster(mydata, endclust, buffer, (int)actsize) != 0) { FAT_ERROR("Error reading cluster\n"); return -1; } - gotsize+=actsize; + gotsize += actsize; return gotsize; -getit: - if (get_cluster(mydata, curclust, buffer, (int)actsize) != 0) { - FAT_ERROR("Error reading cluster\n"); - return -1; - } - gotsize += (int)actsize; - filesize -= actsize; - buffer += actsize; - curclust = get_fatent(mydata, endclust); - if (CHECK_CLUST(curclust, mydata->fatsize)) { - FAT_DPRINT("curclust: 0x%x\n", curclust); - FAT_ERROR("Invalid FAT entry\n"); - return gotsize; - } - actsize=bytesperclust; - endclust=curclust; - } while (1); + } } - #ifdef CONFIG_SUPPORT_VFAT /* * Extract the file name information from 'slotptr' into 'l_name', * starting at l_name[*idx]. * Return 1 if terminator (zero byte) is found, 0 otherwise. */ -static int -slot2str(dir_slot *slotptr, char *l_name, int *idx) +static int slot2str(dir_slot *slotptr, char *l_name, int *idx) { int j; for (j = 0; j <= 8; j += 2) { l_name[*idx] = slotptr->name0_4[j]; - if (l_name[*idx] == 0x00) return 1; + if (l_name[*idx] == 0x00) + return 1; (*idx)++; } for (j = 0; j <= 10; j += 2) { l_name[*idx] = slotptr->name5_10[j]; - if (l_name[*idx] == 0x00) return 1; + if (l_name[*idx] == 0x00) + return 1; (*idx)++; } for (j = 0; j <= 2; j += 2) { l_name[*idx] = slotptr->name11_12[j]; - if (l_name[*idx] == 0x00) return 1; + if (l_name[*idx] == 0x00) + return 1; (*idx)++; } return 0; } - /* * Extract the full long filename starting at 'retdent' (which is really * a slot) into 'l_name'. If successful also copy the real directory entry * into 'retdent' * Return 0 on success, -1 otherwise. */ -__u8 get_vfatname_block[MAX_CLUSTSIZE]; -static int -get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, - dir_entry *retdent, char *l_name) +static __u8 get_vfatname_block[MAX_CLUSTSIZE]; + +static int get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, + dir_entry *retdent, char *l_name) { dir_entry *realdent; - dir_slot *slotptr = (dir_slot*) retdent; - __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE; - __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff; + dir_slot *slotptr = (dir_slot *) retdent; + __u8 *nextclust = cluster + mydata->clust_size * SECTOR_SIZE; + __u8 counter = (slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff; int idx = 0; - while ((__u8*)slotptr < nextclust) { - if (counter == 0) break; + while ((__u8 *) slotptr < nextclust) { + if (counter == 0) + break; if (((slotptr->id & ~LAST_LONG_ENTRY_MASK) & 0xff) != counter) return -1; slotptr++; counter--; } - if ((__u8*)slotptr >= nextclust) { + if ((__u8 *) slotptr >= nextclust) { dir_slot *slotptr2; slotptr--; @@ -467,29 +458,32 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, FAT_DPRINT("Error: reading directory block\n"); return -1; } - slotptr2 = (dir_slot*) get_vfatname_block; + slotptr2 = (dir_slot *) get_vfatname_block; while (slotptr2->id > 0x01) { slotptr2++; } /* Save the real directory entry */ - realdent = (dir_entry*)slotptr2 + 1; - while ((__u8*)slotptr2 >= get_vfatname_block) { + realdent = (dir_entry *) slotptr2 + 1; + while ((__u8 *) slotptr2 >= get_vfatname_block) { slot2str(slotptr2, l_name, &idx); slotptr2--; } } else { /* Save the real directory entry */ - realdent = (dir_entry*)slotptr; + realdent = (dir_entry *) slotptr; } do { slotptr--; - if (slot2str(slotptr, l_name, &idx)) break; + if (slot2str(slotptr, l_name, &idx)) + break; } while (!(slotptr->id & LAST_LONG_ENTRY_MASK)); l_name[idx] = '\0'; - if (*l_name == DELETED_FLAG) *l_name = '\0'; - else if (*l_name == aRING) *l_name = DELETED_FLAG; + if (*l_name == DELETED_FLAG) + *l_name = '\0'; + else if (*l_name == aRING) + *l_name = DELETED_FLAG; downcase(l_name); /* Return the real directory entry */ @@ -498,174 +492,181 @@ get_vfatname(fsdata *mydata, int curclust, __u8 *cluster, return 0; } - /* Calculate short name checksum */ -static __u8 -mkcksum(const char *str) +static __u8 mkcksum(const char *str) { int i; __u8 ret = 0; - for (i = 0; i < 11; i++) { - ret = (((ret&1)<<7)|((ret&0xfe)>>1)) + str[i]; - } + for (i = 0; i < 11; i++) + ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + str[i]; return ret; } #endif - -/* - * Get the directory entry associated with 'filename' from the directory - * starting at 'startsect' - */ -__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; -static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, - char *filename, dir_entry * retdent, - int dols) +/* Returns 0 on illegal vfat entry, 1 on valid vfat entry */ +static int valid_vfat(fsdata *mydata, dir_entry *dentptr, __u16 *prevcksum, + int curclust, char *l_name, int dols, int *dirs, + int *files, __u8 *read_block) { - __u16 prevcksum = 0xffff; - __u32 curclust = START (retdent); - int files = 0, dirs = 0; - - FAT_DPRINT ("get_dentfromdir: %s\n", filename); - while (1) { - dir_entry *dentptr; - int i; - - if (get_cluster (mydata, curclust, get_dentfromdir_block, - mydata->clust_size * SECTOR_SIZE) != 0) { - FAT_DPRINT ("Error: reading directory block\n"); - return NULL; - } - dentptr = (dir_entry *) get_dentfromdir_block; - for (i = 0; i < DIRENTSPERCLUST; i++) { - char s_name[14], l_name[256]; - - l_name[0] = '\0'; - if (dentptr->name[0] == DELETED_FLAG) { - dentptr++; - continue; - } - if ((dentptr->attr & ATTR_VOLUME)) { #ifdef CONFIG_SUPPORT_VFAT - if ((dentptr->attr & ATTR_VFAT) && - (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { - prevcksum = ((dir_slot *) dentptr) - ->alias_checksum; - get_vfatname (mydata, curclust, get_dentfromdir_block, - dentptr, l_name); - if (dols) { + if ((dentptr->attr & ATTR_VFAT) && + (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { + *prevcksum = ((dir_slot *) dentptr)->alias_checksum; + if (get_vfatname(mydata, curclust, read_block, dentptr, l_name)) + return 0; + + if (dols != LS_NO) { int isdir = (dentptr->attr & ATTR_DIR); char dirc; int doit = 0; if (isdir) { - dirs++; - dirc = '/'; - doit = 1; - } else { - dirc = ' '; - if (l_name[0] != 0) { - files++; + (*dirs)++; + dirc = '/'; doit = 1; - } + } else { + dirc = ' '; + if (l_name[0] != 0) { + (*files)++; + doit = 1; + } } if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), - l_name, dirc); - } else { - printf (" %s%c\n", l_name, dirc); - } + if (dirc == ' ') + printf(" %8ld %s%c\n", (long)FAT2CPU32 + (dentptr->size), l_name, dirc); + else + printf(" %s%c\n", l_name, + dirc); } - dentptr++; - continue; - } - FAT_DPRINT ("vfatname: |%s|\n", l_name); - } else -#endif - { - /* Volume label or VFAT entry */ - dentptr++; - continue; } - } - if (dentptr->name[0] == 0) { - if (dols) { - printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); + FAT_DPRINT("Rootvfatname: |%s|\n", l_name); + return 1; + } +#endif + /* Probably just a Volume label */ + return 0; +} + +/* + * Get the directory entry associated with 'filename' from the directory + * starting at 'startsect' + */ +static __u8 get_dentfromdir_block[MAX_CLUSTSIZE]; + +static dir_entry *get_dentfromdir(fsdata *mydata, int startsect, + char *filename, dir_entry *retdent, int dols) +{ + __u16 prevcksum = 0xffff; + __u32 curclust = START(retdent); + int files = 0, dirs = 0; + + FAT_DPRINT("get_dentfromdir: %s\n", filename); + for (;;) { + dir_entry *dentptr; + int i; + + if (get_cluster(mydata, curclust, get_dentfromdir_block, + mydata->clust_size * SECTOR_SIZE) != 0) { + FAT_DPRINT("Error: reading directory block\n"); + return NULL; } - FAT_DPRINT ("Dentname == NULL - %d\n", i); - return NULL; - } + dentptr = (dir_entry *) get_dentfromdir_block; + for (i = 0; i < DIRENTSPERCLUST; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if (dentptr->name[0] == DELETED_FLAG) { + dentptr++; + continue; + } + if ((dentptr->attr & ATTR_VOLUME) && + !valid_vfat(mydata, dentptr, &prevcksum, curclust, + l_name, dols, &dirs, &files, + get_dentfromdir_block)) { + /* Ignore volume labels */ + dentptr++; + continue; + } + + if (dentptr->name[0] == 0) { + if (dols != LS_NO) + printf("\n%d file(s), %d dir(s)\n\n", + files, dirs); + + FAT_DPRINT("Dentname == NULL - %d\n", i); + return NULL; + } #ifdef CONFIG_SUPPORT_VFAT - if (dols && mkcksum (dentptr->name) == prevcksum) { - dentptr++; - continue; - } + if ((dols != LS_NO) && + (mkcksum(dentptr->name) == prevcksum)) { + dentptr++; + continue; + } #endif - get_name (dentptr, s_name); - if (dols) { - int isdir = (dentptr->attr & ATTR_DIR); - char dirc; - int doit = 0; - - if (isdir) { - dirs++; - dirc = '/'; - doit = 1; - } else { - dirc = ' '; - if (s_name[0] != 0) { - files++; - doit = 1; - } + get_name(dentptr, s_name); + if (dols != LS_NO) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirs++; + dirc = '/'; + doit = 1; + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') + printf(" %8ld %s%c\n", (long) + FAT2CPU32(dentptr->size), + s_name, dirc); + else + printf(" %s%c\n", + s_name, dirc); + } + dentptr++; + continue; + } + if (strcmp(filename, s_name) + && strcmp(filename, l_name)) { + FAT_DPRINT("Mismatch: |%s|%s|\n", s_name, + l_name); + dentptr++; + continue; + } + memcpy(retdent, dentptr, sizeof(dir_entry)); + + FAT_DPRINT("DentName: %s", s_name); + FAT_DPRINT(", start: 0x%x", START(dentptr)); + FAT_DPRINT(", size: 0x%x %s\n", + FAT2CPU32(dentptr->size), + (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); + + return retdent; } - if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), s_name, - dirc); - } else { - printf (" %s%c\n", s_name, dirc); - } + curclust = get_fatent(mydata, curclust); + if (CHECK_CLUST(curclust, mydata->fatsize)) { + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return NULL; } - dentptr++; - continue; - } - if (strcmp (filename, s_name) && strcmp (filename, l_name)) { - FAT_DPRINT ("Mismatch: |%s|%s|\n", s_name, l_name); - dentptr++; - continue; - } - memcpy (retdent, dentptr, sizeof (dir_entry)); - - FAT_DPRINT ("DentName: %s", s_name); - FAT_DPRINT (", start: 0x%x", START (dentptr)); - FAT_DPRINT (", size: 0x%x %s\n", - FAT2CPU32 (dentptr->size), - (dentptr->attr & ATTR_DIR) ? "(DIR)" : ""); - - return retdent; - } - curclust = get_fatent (mydata, curclust); - if (CHECK_CLUST(curclust, mydata->fatsize)) { - FAT_DPRINT ("curclust: 0x%x\n", curclust); - FAT_ERROR ("Invalid FAT entry\n"); - return NULL; } - } - - return NULL; + return NULL; } - /* * Read boot sector and volume info from a FAT filesystem */ -static int -read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) +static int read_bootsectandvi(boot_sector *bs, volume_info *volinfo, + int *fatsize) { __u8 block[FS_BLOCK_SIZE]; volume_info *vistart; @@ -676,27 +677,27 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) } memcpy(bs, block, sizeof(boot_sector)); - bs->reserved = FAT2CPU16(bs->reserved); - bs->fat_length = FAT2CPU16(bs->fat_length); - bs->secs_track = FAT2CPU16(bs->secs_track); - bs->heads = FAT2CPU16(bs->heads); -#if 0 /* UNUSED */ - bs->hidden = FAT2CPU32(bs->hidden); + bs->reserved = FAT2CPU16(bs->reserved); + bs->fat_length = FAT2CPU16(bs->fat_length); + bs->secs_track = FAT2CPU16(bs->secs_track); + bs->heads = FAT2CPU16(bs->heads); +#if 0 /* UNUSED */ + bs->hidden = FAT2CPU32(bs->hidden); #endif - bs->total_sect = FAT2CPU32(bs->total_sect); + bs->total_sect = FAT2CPU32(bs->total_sect); /* FAT32 entries */ if (bs->fat_length == 0) { /* Assume FAT32 */ bs->fat32_length = FAT2CPU32(bs->fat32_length); - bs->flags = FAT2CPU16(bs->flags); + bs->flags = FAT2CPU16(bs->flags); bs->root_cluster = FAT2CPU32(bs->root_cluster); - bs->info_sector = FAT2CPU16(bs->info_sector); - bs->backup_boot = FAT2CPU16(bs->backup_boot); - vistart = (volume_info*) (block + sizeof(boot_sector)); + bs->info_sector = FAT2CPU16(bs->info_sector); + bs->backup_boot = FAT2CPU16(bs->backup_boot); + vistart = (volume_info *) (block + sizeof(boot_sector)); *fatsize = 32; } else { - vistart = (volume_info*) &(bs->fat32_length); + vistart = (volume_info *)&(bs->fat32_length); *fatsize = 0; } memcpy(volinfo, vistart, sizeof(volume_info)); @@ -706,9 +707,8 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) vistart->fs_type[8] = '\0'; if (*fatsize == 32) { - if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { + if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) return 0; - } } else { if (compare_sign(FAT12_SIGN, vistart->fs_type) == 0) { *fatsize = 12; @@ -724,258 +724,228 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } +static __u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ -__u8 do_fat_read_block[MAX_CLUSTSIZE]; /* Block buffer */ -long -do_fat_read (const char *filename, void *buffer, unsigned long maxsize, - int dols) +long do_fat_read(const char *filename, void *buffer, + unsigned long maxsize, int dols) { -#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ - static +#if CONFIG_NIOS /* NIOS CPU cannot access big automatic arrays */ + static #endif - char fnamecopy[2048]; - boot_sector bs; - volume_info volinfo; - fsdata datablock; - fsdata *mydata = &datablock; - dir_entry *dentptr; - __u16 prevcksum = 0xffff; - char *subname = ""; - int rootdir_size, cursect; - int idx, isdir = 0; - int files = 0, dirs = 0; - long ret = 0; - int firsttime; - - if (read_bootsectandvi (&bs, &volinfo, &mydata->fatsize)) { - FAT_DPRINT ("Error: reading boot sector\n"); - return -1; - } - if (mydata->fatsize == 32) { - mydata->fatlength = bs.fat32_length; - } else { - mydata->fatlength = bs.fat_length; - } - mydata->fat_sect = bs.reserved; - cursect = mydata->rootdir_sect - = mydata->fat_sect + mydata->fatlength * bs.fats; - mydata->clust_size = bs.cluster_size; - if (mydata->fatsize == 32) { - rootdir_size = mydata->clust_size; - mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ - - (mydata->clust_size * 2); - } else { - rootdir_size = ((bs.dir_entries[1] * (int) 256 + bs.dir_entries[0]) - * sizeof (dir_entry)) / SECTOR_SIZE; - mydata->data_begin = mydata->rootdir_sect + rootdir_size - - (mydata->clust_size * 2); - } - mydata->fatbufnum = -1; - - FAT_DPRINT ("FAT%d, fatlength: %d\n", mydata->fatsize, - mydata->fatlength); - FAT_DPRINT ("Rootdir begins at sector: %d, offset: %x, size: %d\n" - "Data begins at: %d\n", - mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, - rootdir_size, mydata->data_begin); - FAT_DPRINT ("Cluster size: %d\n", mydata->clust_size); - - /* "cwd" is always the root... */ - while (ISDIRDELIM (*filename)) - filename++; - /* Make a copy of the filename and convert it to lowercase */ - strcpy (fnamecopy, filename); - downcase (fnamecopy); - if (*fnamecopy == '\0') { - if (!dols) - return -1; - dols = LS_ROOT; - } else if ((idx = dirdelim (fnamecopy)) >= 0) { - isdir = 1; - fnamecopy[idx] = '\0'; - subname = fnamecopy + idx + 1; - /* Handle multiple delimiters */ - while (ISDIRDELIM (*subname)) - subname++; - } else if (dols) { - isdir = 1; - } - - while (1) { - int i; - - if (disk_read (cursect, mydata->clust_size, do_fat_read_block) < 0) { - FAT_DPRINT ("Error: reading rootdir block\n"); - return -1; + char fnamecopy[2048]; + boot_sector bs; + volume_info volinfo; + fsdata datablock; + fsdata *mydata = &datablock; + dir_entry *dentptr; + __u16 prevcksum = 0xffff; + char *subname = ""; + int rootdir_size, cursect; + int idx, isdir = 0; + int files = 0, dirs = 0; + long ret = 0; + int firsttime; + + if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) { + FAT_DPRINT("Error: reading boot sector\n"); + return -1; } - dentptr = (dir_entry *) do_fat_read_block; - for (i = 0; i < DIRENTSPERBLOCK; i++) { - char s_name[14], l_name[256]; - - l_name[0] = '\0'; - if ((dentptr->attr & ATTR_VOLUME)) { -#ifdef CONFIG_SUPPORT_VFAT - if ((dentptr->attr & ATTR_VFAT) && - (dentptr->name[0] & LAST_LONG_ENTRY_MASK)) { - prevcksum = ((dir_slot *) dentptr)->alias_checksum; - get_vfatname (mydata, 0, do_fat_read_block, dentptr, l_name); - if (dols == LS_ROOT) { - int isdir = (dentptr->attr & ATTR_DIR); - char dirc; - int doit = 0; - - if (isdir) { - dirs++; - dirc = '/'; - doit = 1; - } else { - dirc = ' '; - if (l_name[0] != 0) { - files++; - doit = 1; - } + if (mydata->fatsize == 32) + mydata->fatlength = bs.fat32_length; + else + mydata->fatlength = bs.fat_length; + + mydata->fat_sect = bs.reserved; + cursect = mydata->rootdir_sect = mydata->fat_sect + + (mydata->fatlength * bs.fats); + mydata->clust_size = bs.cluster_size; + if (mydata->fatsize == 32) { + rootdir_size = mydata->clust_size; + mydata->data_begin = mydata->rootdir_sect /* + rootdir_size */ + - (mydata->clust_size * 2); + } else { + rootdir_size = ((bs.dir_entries[1] * (int)256 + + bs.dir_entries[0]) * sizeof(dir_entry)) / SECTOR_SIZE; + mydata->data_begin = mydata->rootdir_sect + rootdir_size + - (mydata->clust_size * 2); + } + mydata->fatbufnum = -1; + + FAT_DPRINT("FAT%d, fatlength: %d\n", mydata->fatsize, + mydata->fatlength); + FAT_DPRINT("Rootdir begins at sector: %d, offset: %x, size: %d\n" + "Data begins at: %d\n", + mydata->rootdir_sect, mydata->rootdir_sect * SECTOR_SIZE, + rootdir_size, mydata->data_begin); + FAT_DPRINT("Cluster size: %d\n", mydata->clust_size); + + /* "cwd" is always the root... */ + while (ISDIRDELIM(*filename)) + filename++; + /* Make a copy of the filename and convert it to lowercase */ + strcpy(fnamecopy, filename); + downcase(fnamecopy); + if (*fnamecopy == '\0') { + if (dols == LS_NO) + return -1; + dols = LS_ROOT; + } else if ((idx = dirdelim(fnamecopy)) >= 0) { + isdir = 1; + fnamecopy[idx] = '\0'; + subname = fnamecopy + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM(*subname)) + subname++; + } else if (dols != LS_NO) + isdir = 1; + + for (;;) { + int i; + + if (disk_read(cursect, 1, do_fat_read_block) < 0) { + FAT_DPRINT("Error: reading rootdir block\n"); + return -1; + } + dentptr = (dir_entry *) do_fat_read_block; + for (i = 0; i < DIRENTSPERBLOCK; i++) { + char s_name[14], l_name[256]; + + l_name[0] = '\0'; + if (dentptr->name[0] == DELETED_FLAG) { + /* Ignore deleted entries */ + dentptr++; + continue; } - if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), - l_name, dirc); - } else { - printf (" %s%c\n", l_name, dirc); - } + if ((dentptr->attr & ATTR_VOLUME) && + !valid_vfat(mydata, dentptr, &prevcksum, 0, l_name, + dols, &dirs, &files, + do_fat_read_block)) { + /* Ignore volume labels */ + dentptr++; + continue; + } + if (dentptr->name[0] == 0) { + FAT_DPRINT("RootDentname == NULL - %d\n", i); + if (dols == LS_ROOT) { + printf("\n%d file(s), %d dir(s)\n\n", + files, dirs); + return 0; + } + return -1; } - dentptr++; - continue; - } - FAT_DPRINT ("Rootvfatname: |%s|\n", l_name); - } else -#endif - { - /* Volume label or VFAT entry */ - dentptr++; - continue; - } - } else if (dentptr->name[0] == 0) { - FAT_DPRINT ("RootDentname == NULL - %d\n", i); - if (dols == LS_ROOT) { - printf ("\n%d file(s), %d dir(s)\n\n", files, dirs); - return 0; - } - return -1; - } #ifdef CONFIG_SUPPORT_VFAT - else if (dols == LS_ROOT - && mkcksum (dentptr->name) == prevcksum) { - dentptr++; - continue; - } + if (dols == LS_ROOT && + mkcksum(dentptr->name) == prevcksum) { + dentptr++; + continue; + } #endif - get_name (dentptr, s_name); - if (dols == LS_ROOT) { - int isdir = (dentptr->attr & ATTR_DIR); - char dirc; - int doit = 0; - - if (isdir) { - dirc = '/'; - if (s_name[0] != 0) { - dirs++; - doit = 1; - } - } else { - dirc = ' '; - if (s_name[0] != 0) { - files++; - doit = 1; - } - } - if (doit) { - if (dirc == ' ') { - printf (" %8ld %s%c\n", - (long) FAT2CPU32 (dentptr->size), s_name, - dirc); - } else { - printf (" %s%c\n", s_name, dirc); - } - } - dentptr++; - continue; - } - if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) { - FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name); - dentptr++; - continue; - } - if (isdir && !(dentptr->attr & ATTR_DIR)) - return -1; + get_name(dentptr, s_name); + if (dols == LS_ROOT) { + int isdir = (dentptr->attr & ATTR_DIR); + char dirc; + int doit = 0; + + if (isdir) { + dirc = '/'; + if (s_name[0] != 0) { + dirs++; + doit = 1; + } + } else { + dirc = ' '; + if (s_name[0] != 0) { + files++; + doit = 1; + } + } + if (doit) { + if (dirc == ' ') + printf(" %8ld %s%c\n", (long) + FAT2CPU32(dentptr->size), + s_name, dirc); + else + printf(" %s%c\n", + s_name, dirc); + } + dentptr++; + continue; + } + if (strcmp(fnamecopy, s_name) + && strcmp(fnamecopy, l_name)) { + FAT_DPRINT("RootMismatch: |%s|%s|\n", s_name, + l_name); + dentptr++; + continue; + } + if (isdir && !(dentptr->attr & ATTR_DIR)) + return -1; - FAT_DPRINT ("RootName: %s", s_name); - FAT_DPRINT (", start: 0x%x", START (dentptr)); - FAT_DPRINT (", size: 0x%x %s\n", - FAT2CPU32 (dentptr->size), isdir ? "(DIR)" : ""); + FAT_DPRINT("RootName: %s", s_name); + FAT_DPRINT(", start: 0x%x", START(dentptr)); + FAT_DPRINT(", size: 0x%x %s\n", + FAT2CPU32(dentptr->size), + isdir ? "(DIR)" : ""); - goto rootdir_done; /* We got a match */ - } - cursect++; - } - rootdir_done: - - firsttime = 1; - while (isdir) { - int startsect = mydata->data_begin - + START (dentptr) * mydata->clust_size; - dir_entry dent; - char *nextname = NULL; - - dent = *dentptr; - dentptr = &dent; - - idx = dirdelim (subname); - if (idx >= 0) { - subname[idx] = '\0'; - nextname = subname + idx + 1; - /* Handle multiple delimiters */ - while (ISDIRDELIM (*nextname)) - nextname++; - if (dols && *nextname == '\0') - firsttime = 0; - } else { - if (dols && firsttime) { - firsttime = 0; - } else { - isdir = 0; - } - } + goto rootdir_done; /* We got a match */ + } + cursect++; + } +rootdir_done: + + firsttime = 1; + while (isdir) { + int startsect = mydata->data_begin + + START(dentptr) * mydata->clust_size; + dir_entry dent; + char *nextname = NULL; + + dent = *dentptr; + dentptr = &dent; + + idx = dirdelim(subname); + if (idx >= 0) { + subname[idx] = '\0'; + nextname = subname + idx + 1; + /* Handle multiple delimiters */ + while (ISDIRDELIM(*nextname)) + nextname++; + if (dols != LS_NO && *nextname == '\0') + firsttime = 0; + } else { + if (dols != LS_NO && firsttime) + firsttime = 0; + else + isdir = 0; + } - if (get_dentfromdir (mydata, startsect, subname, dentptr, - isdir ? 0 : dols) == NULL) { - if (dols && !isdir) - return 0; - return -1; - } + if (get_dentfromdir(mydata, startsect, subname, dentptr, + isdir ? 0 : dols) == NULL) { + if (dols != LS_NO && !isdir) + return 0; + return -1; + } - if (idx >= 0) { - if (!(dentptr->attr & ATTR_DIR)) - return -1; - subname = nextname; + if (idx >= 0) { + if (!(dentptr->attr & ATTR_DIR)) + return -1; + subname = nextname; + } } - } - ret = get_contents (mydata, dentptr, buffer, maxsize); - FAT_DPRINT ("Size: %d, got: %ld\n", FAT2CPU32 (dentptr->size), ret); + ret = get_contents(mydata, dentptr, buffer, maxsize); + FAT_DPRINT("Size: %d, got: %ld\n", FAT2CPU32(dentptr->size), ret); - return ret; + return ret; } - -int -file_fat_detectfs(void) +int file_fat_detectfs(void) { - boot_sector bs; - volume_info volinfo; - int fatsize; - char vol_label[12]; + boot_sector bs; + volume_info volinfo; + int fatsize; + char vol_label[12]; - if(cur_dev==NULL) { + if (cur_dev == NULL) { printf("No current device\n"); return 1; } @@ -984,41 +954,37 @@ file_fat_detectfs(void) defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) printf("Interface: "); - switch(cur_dev->if_type) { + switch (cur_dev->if_type) { case IF_TYPE_IDE : printf("IDE"); break; case IF_TYPE_SCSI : printf("SCSI"); break; case IF_TYPE_ATAPI : printf("ATAPI"); break; case IF_TYPE_USB : printf("USB"); break; case IF_TYPE_DOC : printf("DOC"); break; case IF_TYPE_MMC : printf("MMC"); break; - default : printf("Unknown"); + default : printf("Unknown"); break; } - printf("\n Device %d: ",cur_dev->dev); + printf("\n Device %d: ", cur_dev->dev); dev_print(cur_dev); #endif - if(read_bootsectandvi(&bs, &volinfo, &fatsize)) { + if (read_bootsectandvi(&bs, &volinfo, &fatsize)) { printf("\nNo valid FAT fs found\n"); return 1; } - memcpy (vol_label, volinfo.volume_label, 11); + memcpy(vol_label, volinfo.volume_label, 11); vol_label[11] = '\0'; - volinfo.fs_type[5]='\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n" - ,cur_part,volinfo.fs_type,vol_label); + volinfo.fs_type[5] = '\0'; + printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part, + volinfo.fs_type, vol_label); return 0; } - -int -file_fat_ls(const char *dir) +int file_fat_ls(const char *dir) { return do_fat_read(dir, NULL, 0, LS_YES); } - -long -file_fat_read(const char *filename, void *buffer, unsigned long maxsize) +long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) { - printf("reading %s\n",filename); + printf("reading %s\n", filename); return do_fat_read(filename, buffer, maxsize, LS_NO); } diff --git a/fs/fat/file.c b/fs/fat/file.c index e870734..e300ff7 100644 --- a/fs/fat/file.c +++ b/fs/fat/file.c @@ -34,8 +34,9 @@ /* Supported filesystems */ static const struct filesystem filesystems[] = { - { file_fat_detectfs, file_fat_ls, file_fat_read, "FAT" }, + {file_fat_detectfs, file_fat_ls, file_fat_read, "FAT"}, }; + #define NUM_FILESYS (sizeof(filesystems)/sizeof(struct filesystem)) /* The filesystem which was last detected */ @@ -43,56 +44,54 @@ static int current_filesystem = FSTYPE_NONE; /* The current working directory */ #define CWD_LEN 511 -char file_cwd[CWD_LEN+1] = "/"; +char file_cwd[CWD_LEN + 1] = "/"; -const char * -file_getfsname(int idx) +const char *file_getfsname(int idx) { - if (idx < 0 || idx >= NUM_FILESYS) return NULL; + if (idx < 0 || idx >= NUM_FILESYS) + return NULL; return filesystems[idx].name; } - -static void -pathcpy(char *dest, const char *src) +static void pathcpy(char *dest, const char *src) { char *origdest = dest; - do { - if (dest-file_cwd >= CWD_LEN) { + for (;;) { + if (dest - file_cwd >= CWD_LEN) { *dest = '\0'; return; } *(dest) = *(src); if (*src == '\0') { - if (dest-- != origdest && ISDIRDELIM(*dest)) { + if (dest-- != origdest && ISDIRDELIM(*dest)) *dest = '\0'; - } + return; } ++dest; - if (ISDIRDELIM(*src)) { - while (ISDIRDELIM(*src)) src++; - } else { + if (ISDIRDELIM(*src)) + while (ISDIRDELIM(*src)) + src++; + else src++; - } - } while (1); + } } - -int -file_cd(const char *path) +int file_cd(const char *path) { if (ISDIRDELIM(*path)) { - while (ISDIRDELIM(*path)) path++; - strncpy(file_cwd+1, path, CWD_LEN-1); + while (ISDIRDELIM(*path)) + path++; + strncpy(file_cwd + 1, path, CWD_LEN - 1); } else { const char *origpath = path; char *tmpstr = file_cwd; int back = 0; - while (*tmpstr != '\0') tmpstr++; + while (*tmpstr != '\0') + tmpstr++; do { tmpstr--; } while (ISDIRDELIM(*tmpstr)); @@ -108,7 +107,8 @@ file_cd(const char *path) back = 0; break; } - while (ISDIRDELIM(*path)) path++; + while (ISDIRDELIM(*path)) + path++; origpath = path; } @@ -123,7 +123,8 @@ file_cd(const char *path) break; } /* Skip delimiters */ - while (ISDIRDELIM(*tmpstr)) tmpstr--; + while (ISDIRDELIM(*tmpstr)) + tmpstr--; } tmpstr++; if (*path == '\0') { @@ -135,15 +136,13 @@ file_cd(const char *path) return 0; } *tmpstr = '/'; - pathcpy(tmpstr+1, path); + pathcpy(tmpstr + 1, path); } return 0; } - -int -file_detectfs(void) +int file_detectfs(void) { int i; @@ -160,9 +159,7 @@ file_detectfs(void) return current_filesystem; } - -int -file_ls(const char *dir) +int file_ls(const char *dir) { char fullpath[1024]; const char *arg; @@ -181,9 +178,7 @@ file_ls(const char *dir) return filesystems[current_filesystem].ls(arg); } - -long -file_read(const char *filename, void *buffer, unsigned long maxsize) +long file_read(const char *filename, void *buffer, unsigned long maxsize) { char fullpath[1024]; const char *arg; diff --git a/include/fat.h b/include/fat.h index c8b9493..be7023a 100644 --- a/include/fat.h +++ b/include/fat.h @@ -49,7 +49,6 @@ #define FAT16BUFSIZE (FATBUFSIZE/2) #define FAT32BUFSIZE (FATBUFSIZE/4) - /* Filesystem identifiers */ #define FAT12_SIGN "FAT12 " #define FAT16_SIGN "FAT16 " @@ -140,8 +139,7 @@ typedef struct boot_sector { __u16 reserved2[6]; /* Unused */ } boot_sector; -typedef struct volume_info -{ +typedef struct volume_info { __u8 drive_number; /* BIOS drive number */ __u8 reserved; /* Unused */ __u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */ @@ -188,7 +186,8 @@ typedef struct { __u16 fat_sect; /* Starting sector of the FAT */ __u16 rootdir_sect; /* Start sector of root directory */ __u16 clust_size; /* Size of clusters in sectors */ - short data_begin; /* The sector of the first cluster, can be negative */ + short data_begin; /* The sector of the first cluster, + * can be negative */ int fatbufnum; /* Used by get_fatent, init to -1 */ } fsdata; -- 1.5.6.3

3 3

[U-Boot] [PATCH] mgcoge make ether_scc.c work with CONFIG_NET_MULTI
by Gary Jennejohn 09 Dec '08

09 Dec '08

This change is needed for mgcoge because it uses two ethernet drivers. Add a check for the presence of the PIGGY board on mgcoge. Without this board networking cannot work and the initialization must be aborted. Only allocate rtx once to prevent DPRAM exhaustion. Initialize ether_scc.c and the keymile-specific HDLC driver (to be added soon) in eth.c. Signed-off-by: Gary Jennejohn <garyj(a)denx.de> --- I ran "MAKEALL ppc" and no errors were caused by this patch. cpu/mpc8260/ether_scc.c | 56 +++++++++++++++++++++++++++++++++++++++++------ net/eth.c | 8 ++++++ 2 files changed, 57 insertions(+), 7 deletions(-) diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index c65f0e0..537cd39 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -10,6 +10,12 @@ * Advent Networks, Inc. <http://www.adventnetworks.com> * Jay Monkman <jtm(a)smoothsmoothie.com> * + * Modified so that it plays nicely when more than one ETHERNET interface + * is in use a la ether_fcc.c. + * (C) Copyright 2008 + * DENX Software Engineerin GmbH + * Gary Jennejohn <garyj(a)denx.de> + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,12 +38,17 @@ #include <common.h> #include <asm/cpm_8260.h> #include <mpc8260.h> +#include <malloc.h> #include <net.h> #include <command.h> #include <config.h> #if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET) +#ifndef CONFIG_NET_MULTI +#error "CONFIG_NET_MULTI must be defined." +#endif + #if (CONFIG_ETHER_INDEX == 1) # define PROFF_ENET PROFF_SCC1 # define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE @@ -100,7 +111,7 @@ typedef volatile struct CommonBufferDescriptor { static RTXBD *rtx; -int eth_send(volatile void *packet, int length) +int sec_send(struct eth_device *dev, volatile void *packet, int length) { int i; int result = 0; @@ -137,7 +148,7 @@ int eth_send(volatile void *packet, int length) } -int eth_rx(void) +int sec_rx(struct eth_device *dev) { int length; @@ -184,19 +195,32 @@ int eth_rx(void) * *************************************************************/ -int eth_init(bd_t *bis) +int sec_init(struct eth_device *dev, bd_t *bis) { int i; volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; scc_enet_t *pram_ptr; uint dpaddr; +#if defined(CONFIG_CHECK_ETHERNET_PRESENT) + if (ethernet_present (CONFIG_ETHER_INDEX) == 0) { + printf("Ethernet index: %d not present.\n", + CONFIG_ETHER_INDEX); + return -1; + } +#endif + rxIdx = 0; txIdx = 0; - /* assign static pointer to BD area */ - dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); - rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; + /* + * Assign static pointer to BD area. + * Avoid exhausting DPRAM, which would cause a panic. + */ + if (rtx == NULL) { + dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16); + rtx = (RTXBD *)&immr->im_dprambase[dpaddr]; + } /* 24.21 - (1-3): ioports have been set up already */ @@ -338,7 +362,7 @@ int eth_init(bd_t *bis) } -void eth_halt(void) +void sec_halt(struct eth_device *dev) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR | @@ -354,4 +378,22 @@ void restart(void) } #endif +int sec_initialize(bd_t *bis) +{ + struct eth_device *dev; + + dev = (struct eth_device *) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "SCC ETHERNET"); + dev->init = sec_init; + dev->halt = sec_halt; + dev->send = sec_send; + dev->recv = sec_rx; + + eth_register(dev); + + return 1; +} + #endif diff --git a/net/eth.c b/net/eth.c index ccd871a..5fe8b83 100644 --- a/net/eth.c +++ b/net/eth.c @@ -48,6 +48,8 @@ extern int ppc_4xx_eth_initialize(bd_t *); extern int scc_initialize(bd_t*); extern int npe_initialize(bd_t *); extern int uec_initialize(int); +extern int sec_initialize(bd_t *); +extern int keymile_hdlc_enet_initialize(bd_t *); #ifdef CONFIG_API extern void (*push_packet)(volatile void *, int); @@ -196,6 +198,12 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_IXP4XX_NPE) npe_initialize(bis); #endif +#if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_MPC8260) + sec_initialize(bis); +#endif +#if defined(CONFIG_KEYMILE_HDLC_ENET) + keymile_hdlc_enet_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); show_boot_progress (-64); -- 1.5.4.3 --- Gary Jennejohn ********************************************************************* DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de *********************************************************************

3 9

[U-Boot] [PATCH v2] ppc4xx: Improve DDR autodetect
by Dirk Eibach 09 Dec '08

09 Dec '08

Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Cleaned up whitespace issues cpu/ppc4xx/sdram.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 50 insertions(+), 5 deletions(-) diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 6d5f8d6..b1d82f8 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -259,6 +259,7 @@ phys_size_t initdram(int board_type) #ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ + {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ }; #else @@ -269,6 +270,18 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #define CONFIG_SYS_SDRAM0_TR0 0x41094012 #endif +#ifndef CONFIG_SYS_SDRAM0_WDDCTR +#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_RTR +#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_CFG0 +#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */ +#endif + #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #define NUM_TRIES 64 @@ -378,7 +391,7 @@ phys_size_t initdram(int board_type) mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* @@ -387,31 +400,63 @@ phys_size_t initdram(int board_type) mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ + mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR); mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { + phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); + + /* + * OK, size detected. Enable second bank if + * defined (assumes same type as bank 0) + */ +#ifdef CONFIG_SDRAM_BANK1 + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + + /* + * Check if 2nd bank is really available. + * If the size not equal to the size of the first + * bank, then disable the 2nd bank completely. + */ + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) + != mb0cf[i].size) { + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, 0); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + } else { + /* + * We have two identical banks, so the size + * is twice the bank size + */ + size = 2 * size; + } +#endif + #ifdef CONFIG_SDRAM_ECC - ecc_init(0, mb0cf[i].size); + ecc_init(0, size); #endif /* * OK, size detected -> all done */ - return mb0cf[i].size; + return size; } } -- 1.5.6.5

2 1

[U-Boot] [PATCH v3] ppc4xx: Add GDsys PowerPC 440 ETX board support.
by Dirk Eibach 09 Dec '08

09 Dec '08

Board support for the Guntermann & Drunck PowerPC 440 ETX module. Based on the AMCC Yosemite board support by Stefan Roese. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- Cleaned up copyright and whitespace issues. Depends on [PATCH v2] ppc4xx-Improve-DDR-autodetect. MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/gdsys/gdppc440etx/Makefile | 51 +++++ board/gdsys/gdppc440etx/config.mk | 44 +++++ board/gdsys/gdppc440etx/gdppc440etx.c | 331 +++++++++++++++++++++++++++++++++ board/gdsys/gdppc440etx/init.S | 75 ++++++++ board/gdsys/gdppc440etx/u-boot.lds | 144 ++++++++++++++ include/configs/gdppc440etx.h | 203 ++++++++++++++++++++ 9 files changed, 853 insertions(+), 0 deletions(-) create mode 100644 board/gdsys/gdppc440etx/Makefile create mode 100644 board/gdsys/gdppc440etx/config.mk create mode 100644 board/gdsys/gdppc440etx/gdppc440etx.c create mode 100644 board/gdsys/gdppc440etx/init.S create mode 100644 board/gdsys/gdppc440etx/u-boot.lds create mode 100644 include/configs/gdppc440etx.h diff --git a/MAINTAINERS b/MAINTAINERS index 127604b..b836263 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Dirk Eibach <eibach(a)gdsys.de> + gdppc440etx PPC440EP/GR neo PPC405EP Dave Ellis <DGE(a)sixnetio.com> diff --git a/MAKEALL b/MAKEALL index dbed268..3789bb9 100755 --- a/MAKEALL +++ b/MAKEALL @@ -188,6 +188,7 @@ LIST_4xx=" \ EXBITGEN \ fx12mm \ G2000 \ + gdppc440etx \ glacier \ haleakala \ haleakala_nand \ diff --git a/Makefile b/Makefile index befb608..d77ab3a 100644 --- a/Makefile +++ b/Makefile @@ -1315,6 +1315,9 @@ fx12mm_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +gdppc440etx_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys + hcu4_config: unconfig @mkdir -p $(obj)board/netstal/common @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile new file mode 100644 index 0000000..b93f2c3 --- /dev/null +++ b/board/gdsys/gdppc440etx/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk new file mode 100644 index 0000000..045f3e9 --- /dev/null +++ b/board/gdsys/gdppc440etx/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# G&D 440EP/GR ETX-Module +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 0000000..d9982cd --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,331 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on board/amcc/yosemite/yosemite.c + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +int board_early_init_f(void) +{ + register uint reg; + + /* + * Setup the external bus controller/chip selects + */ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + /* + * Setup the GPIO pins + */ + + /* setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); + + /* setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART0 and UART1*/ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); + + /* disable boot-eeprom WP */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); + out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /* + * Setup other serial configuration + */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + return 0; +} + +int misc_init_r(void) +{ + uint pbcr; + int size_val; + uint sz; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + + if (gd->bd->bi_flashsize > 0x08000000) + panic("Max. flash banksize is 128 MB!\n"); + + for (sz = gd->bd->bi_flashsize, size_val = 7; + ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) + sz <<= 1; + + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + u8 rev; + u8 val; + + printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /* + * Set priority for all PLB4 devices to 0. + */ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /* + * Set Nebula PLB4 arbiter to fair mode. + */ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + /* enable 66 MHz ext. Clock */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); + out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF + * ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); + out32r(PCIX0_PTM1LA, 0); + out32r(PCIX0_PTM2MS, 0); + out32r(PCIX0_PTM2LA, 0); + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ + +/* + * pci_master_init + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ + +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + */ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S new file mode 100644 index 0000000..0bbd45a --- /dev/null +++ b/board/gdsys/gdppc440etx/init.S @@ -0,0 +1,75 @@ +/* +* (C) Copyright 2008 +* Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de +* +* based on board/amcc/yosemite/init.S +* original Copyright not specified there +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use + * the speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, + 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, + 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, + 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, + 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds new file mode 100644 index 0000000..1df817b --- /dev/null +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/gdsys/gdppc440etx/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 0000000..17ce0a4 --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,203 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach(a)gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#define CONFIG_SYS_EBC_PB1AP 0 +#define CONFIG_SYS_EBC_PB1CR 0 +#define CONFIG_SYS_EBC_PB2AP 0 +#define CONFIG_SYS_EBC_PB2CR 0 +#define CONFIG_SYS_EBC_PB3AP 0 +#define CONFIG_SYS_EBC_PB3CR 0 +#define CONFIG_SYS_EBC_PB4AP 0 +#define CONFIG_SYS_EBC_PB4CR 0 + +#endif /* __CONFIG_H */ -- 1.5.6.5

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[U-Boot] [PATCH v2 1/2] ppc4xx: Add 440EPx SPI driver
by Steven A. Falco 09 Dec '08

09 Dec '08

This patch adds an SPI driver for the 440EPx processor. Tested on Sequoia. Signed-off-by: Steven A. Falco <sfalco(a)harris.com> --- Regarding Ben's comments: First, thanks for reviewing. You gave me two different approaches to consider, 1) using in/out functions, and 2) using a structure. So, for this version, I've followed the style of the example you gave, using the structure approach. This driver may be applicable to other 4xx chips, but after looking at the 405gp and 440gp, neither have a SPI hw device. So, I'm making this one exclusive to the 440epx until someone else wants it on another processor. At that point, it can be adapted as needed. Regarding Stefan's comments: I've renamed the file, and cleaned up the nits. Given that I've used the structure approach, I believe the in/out calls are not applicable. Regarding Wolfgang's comments: It is not for the fun of it. We are planning a custom board which will use the SPI port. We are entering layout now, and the hardware won't appear for at least a few months. However, the Sequoia board does have a connector for the SPI port, and I have connected a device to that connector for prototyping purposes. Other purchasers of the Sequoia may well have a similar need. You are certainly welcome to reject this driver if you feel that is insufficient grounds for "usage". Please let me know, so I don't bother the list with it. drivers/spi/Makefile | 1 + drivers/spi/ppc4xx_spi.c | 119 +++++++++++++++++++++++++++++++++++++++++++++ lude/asm-ppc/ppc4xx_spi.h | 62 +++++++++++++++++++++++ 3 files changed, 182 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/ppc4xx_spi.c create mode 100644 include/asm-ppc/ppc4xx_spi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 15e0f7a..7dbba5d 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libspi.a COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o +COBJS-$(CONFIG_PPC440EPX_SPI) += ppc4xx_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS := $(COBJS-y) diff --git a/drivers/spi/ppc4xx_spi.c b/drivers/spi/ppc4xx_spi.c new file mode 100644 index 0000000..156b056 --- /dev/null +++ b/drivers/spi/ppc4xx_spi.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2008 Harris Corporation + * Author: Steven A. Falco <sfalco(a)harris.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <malloc.h> + +#include <asm/io.h> +#include <asm/ppc4xx_spi.h> + +void spi_init (void) +{ + volatile spi4xx_t *spi = (volatile spi4xx_t *) SPI_BASE_ADDR; + + spi->cdm = 0; /* Default to "go fast" */ + spi->mode = SPI_MODE_SPE; /* Enable port */ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + volatile spi4xx_t *spi = (volatile spi4xx_t *) SPI_BASE_ADDR; + + ulong opb = get_OPB_freq(); + ulong divisor; + struct spi_slave *s; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + divisor = ((opb + (max_hz * 4) - 1) / (max_hz * 4)) - 1; + if (divisor > 255) + return NULL; + + spi->cdm = divisor; + + if (!(s = malloc(sizeof(struct spi_slave)))) + return NULL; + + if (mode & SPI_CPHA) + spi->mode &= ~SPI_MODE_SCP; + else + spi->mode |= SPI_MODE_SCP; + + if (mode & SPI_CPOL) + spi->mode |= SPI_MODE_CI; + else + spi->mode &= ~SPI_MODE_CI; + + s->bus = bus; + s->cs = cs; + + return s; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +#define GO spi->cr = SPI_CR_STR +#define TXWAIT while(spi->sr & SPI_SR_BSY) +#define RXWAIT while(!(spi->sr & SPI_SR_RBR)) + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + volatile spi4xx_t *spi = (volatile spi4xx_t *) SPI_BASE_ADDR; + + const u8 *txd = dout; + u8 *rxd = din; + int ii; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* Do a byte at a time */ + for (ii = 0; ii < ((bitlen + 7) / 8); ii++) { + TXWAIT; + spi->txd = *txd++; + GO; + RXWAIT; + *rxd++ = spi->rxd; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/include/asm-ppc/ppc4xx_spi.h b/include/asm-ppc/ppc4xx_spi.h new file mode 100644 index 0000000..135c9e6 --- /dev/null +++ b/include/asm-ppc/ppc4xx_spi.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2008 Harris Corporation + * Author: Steven A. Falco <sfalco(a)harris.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _4xx_spi_h_ +#define _4xx_spi_h_ + +#include <asm/types.h> + +#if defined(CONFIG_440EPX) +#define SPI_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000900) +#endif + +/* Bits in the command register */ +#define SPI_CR_STR 0x01 + +/* Bits in the status register */ +#define SPI_SR_RBR 0x01 +#define SPI_SR_BSY 0x02 + +/* Bits in the mode register */ +#define SPI_MODE_IL 0x01 +#define SPI_MODE_CI 0x02 +#define SPI_MODE_RD 0x04 +#define SPI_MODE_SPE 0x08 +#define SPI_MODE_SCP 0x10 + +#if defined(CONFIG_440EPX) || \ + defined(CONFIG_440GRX) + +typedef struct spi4xx { + u8 mode; /* mode register */ + u8 rxd; /* receive register */ + u8 txd; /* transmit register */ + u8 cr; /* command register */ + u8 sr; /* status register */ + u8 res0; /* reserved */ + u8 cdm; /* clock divisor */ +} spi4xx_t; + +#endif + +#endif /* _4xx_spi_h_ */ -- 1.6.0.2

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[U-Boot] Interrupts in standalone application
by kishore choudhari 09 Dec '08

09 Dec '08

Hi all, Iam unable to haandle ,The interrupts in standalone applications for GCC compiler. I want to know if there anything possible to do like this and how , thanks in advance . Regards, kishore.

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