December 2008 - U-Boot

[U-Boot] [PATCH 2/6] usb : musb : Adding host controller driver for Mentor USB controller
by Thomas Abraham 16 Dec '08

16 Dec '08

Adding Mentor USB core functionality and Mentor USB Host controller functionality for Mentor USB OTG controller (musbhdrc). Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- drivers/usb/Makefile | 1 + drivers/usb/musb_core.c | 158 +++++++++++ drivers/usb/musb_core.h | 322 +++++++++++++++++++++ drivers/usb/musb_hcd.c | 707 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/musb_hcd.h | 49 ++++ 5 files changed, 1237 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/musb_core.c create mode 100644 drivers/usb/musb_core.h create mode 100644 drivers/usb/musb_hcd.c create mode 100644 drivers/usb/musb_hcd.h diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 856f51a..d93be2b 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_USB_OHCI_NEW) += usb_ohci.o COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o +COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o # device ifdef CONFIG_USB_DEVICE diff --git a/drivers/usb/musb_core.c b/drivers/usb/musb_core.c new file mode 100644 index 0000000..4f3aff3 --- /dev/null +++ b/drivers/usb/musb_core.c @@ -0,0 +1,158 @@ +/* + * Mentor USB OTG Core functionality common for both host and Device + * functionality. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#include <common.h> + +#if defined(CONFIG_MUSB_HCD) || defined(CONFIG_MUSB_DEVICE) +#include "musb_core.h" + +/* + * program the mentor core to start (enable interrupts, dma, etc.) + */ +void musb_start(void) +{ + u8 devctl; + + /* disable all interrupts */ + musb_writew(MUSB_INTRTXE, 0); + musb_writew(MUSB_INTRRXE, 0); + musb_writeb(MUSB_INTRUSBE, 0); + musb_writeb(MUSB_TESTMODE, 0); + + /* put into basic highspeed mode and start session */ + musb_writeb(MUSB_POWER, MUSB_POWER_HSENAB); +#if defined(CONFIG_MUSB_HCD) + devctl = musb_readb(MUSB_DEVCTL); + musb_writeb(MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION); +#endif +} + +/* + * This function configures the endpoint configuration. The musb hcd or musb + * device implementation can use this function to configure the Endpoints + * and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints + * should not be more than the available FIFO size. + * + * epinfo - Pointer to EP configuration table + * cnt - Number of entries in the EP conf table. + */ +void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) +{ + u16 csr; + u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ + u32 fifosize; + u8 idx; + + while (cnt--) { + /* prepare fifosize to write to register */ + fifosize = epinfo->epsize >> 3; + idx = ffs(fifosize) - 1; + + musb_writeb(MUSB_INDEX, epinfo->epnum); + if (epinfo->epdir) { + /* Configure fifo size and fifo base address */ + musb_writeb(MUSB_TXFIFOSZ, idx); + musb_writew(MUSB_TXFIFOADD, fifoaddr >> 3); + +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_CLRDATATOG); +#endif + + /* Flush fifo if required */ + if (csr & MUSB_TXCSR_TXPKTRDY) { + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_FLUSHFIFO); + } + } else { + /* Configure fifo size and fifo base address */ + musb_writeb(MUSB_RXFIFOSZ, idx); + musb_writew(MUSB_RXFIFOADD, fifoaddr >> 3); + +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr | MUSB_RXCSR_CLRDATATOG); +#endif + + /* Flush fifo if required */ + if (csr & MUSB_RXCSR_RXPKTRDY) { + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr | MUSB_RXCSR_FLUSHFIFO); + } + } + fifoaddr += epinfo->epsize; + epinfo++; + } +} + +/* + * This function writes data to endpoint fifo + * + * ep - Endpoint number + * length - Number of bytes to write to FIFO + * fifo_data - Pointer to data buffer that contains the data to write + */ +void write_fifo(u8 ep, u32 length, void *fifo_data) +{ + u32 address; + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + musb_writeb(MUSB_INDEX, ep); + address = MUSB_FIFO_OFFSET(ep); + + /* write the data to the fifo */ + while (length--) + musb_writeb(address, *data++); +} + +/* + * This function reads data from endpoint fifo + * + * ep - Endpoint number + * length - Number of bytes to read from FIFO + * fifo_data - Pointer to data buffer into which data is read + */ +void read_fifo(u8 ep, u32 length, void *fifo_data) +{ + u32 address; + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + musb_writeb(MUSB_INDEX, ep); + address = MUSB_FIFO_OFFSET(ep); + + /* read the data to the fifo */ + while (length--) + *data++ = musb_readb(address); +} + +#endif /* CONFIG_MUSB_HCD */ + + + diff --git a/drivers/usb/musb_core.h b/drivers/usb/musb_core.h new file mode 100644 index 0000000..d5fba54 --- /dev/null +++ b/drivers/usb/musb_core.h @@ -0,0 +1,322 @@ +/****************************************************************** + * Copyright 2005 Mentor Graphics Corporation + * Copyright (C) 2005-2006 by Texas Instruments + * + * This file is part of the Inventra Controller Driver for Linux. + * + * The Inventra Controller Driver for Linux is free software; you + * can redistribute it and/or modify it under the terms of the GNU + * General Public License version 2 as published by the Free Software + * Foundation. + * + * The Inventra Controller Driver for Linux is distributed in + * the hope that it will be useful, but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with The Inventra Controller Driver for Linux ; if not, + * write to the Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION + * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE + * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS + * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. + * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT + * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR + * GRAPHICS SUPPORT CUSTOMER. + ******************************************************************/ + +#ifndef __MUSB_HDRC_DEFS_H__ +#define __MUSB_HDRC_DEFS_H__ + +#include <usb.h> +#include <usb_defs.h> + +#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ + +/* + * Common USB registers + */ + +#define MUSB_FADDR 0x00 /* 8-bit */ +#define MUSB_POWER 0x01 /* 8-bit */ + +#define MUSB_INTRTX 0x02 /* 16-bit */ +#define MUSB_INTRRX 0x04 +#define MUSB_INTRTXE 0x06 +#define MUSB_INTRRXE 0x08 +#define MUSB_INTRUSB 0x0A /* 8 bit */ +#define MUSB_INTRUSBE 0x0B /* 8 bit */ +#define MUSB_FRAME 0x0C +#define MUSB_INDEX 0x0E /* 8 bit */ +#define MUSB_TESTMODE 0x0F /* 8 bit */ + +/* Get offset for a given FIFO from musb->mregs */ +#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4)) + +/* + * Additional Control Registers + */ +#define MUSB_DEVCTL 0x60 /* 8 bit */ + +/* These are always controlled through the INDEX register */ +#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ +#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ +#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ +#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ + +/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ +#define MUSB_HWVERS 0x6C /* 8 bit */ + +#define MUSB_EPINFO 0x78 /* 8 bit */ +#define MUSB_RAMINFO 0x79 /* 8 bit */ +#define MUSB_LINKINFO 0x7a /* 8 bit */ +#define MUSB_VPLEN 0x7b /* 8 bit */ +#define MUSB_HS_EOF1 0x7c /* 8 bit */ +#define MUSB_FS_EOF1 0x7d /* 8 bit */ +#define MUSB_LS_EOF1 0x7e /* 8 bit */ + +/* Offsets to endpoint registers */ +#define MUSB_TXMAXP 0x00 +#define MUSB_TXCSR 0x02 +#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ +#define MUSB_RXMAXP 0x04 +#define MUSB_RXCSR 0x06 +#define MUSB_RXCOUNT 0x08 +#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ +#define MUSB_TXTYPE 0x0A +#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ +#define MUSB_TXINTERVAL 0x0B +#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ +#define MUSB_RXTYPE 0x0C +#define MUSB_RXINTERVAL 0x0D +#define MUSB_FIFOSIZE 0x0F +#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ + +/* Offsets to endpoint registers in indexed model (using INDEX register) */ +#define MUSB_INDEXED_OFFSET(_offset) \ + (0x10 + (_offset)) + +/* Offsets to endpoint registers in flat models */ +#define MUSB_FLAT_OFFSET(_epnum, _offset) \ + (0x100 + (0x10*(_epnum)) + (_offset)) + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +#define MUSB_TXFUNCADDR 0x00 +#define MUSB_TXHUBADDR 0x02 +#define MUSB_TXHUBPORT 0x03 + +#define MUSB_RXFUNCADDR 0x04 +#define MUSB_RXHUBADDR 0x06 +#define MUSB_RXHUBPORT 0x07 + +#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ + (0x80 + (8*(_epnum)) + (_offset)) + +/* + * MUSB Register bits + */ + +/* POWER */ +#define MUSB_POWER_ISOUPDATE 0x80 +#define MUSB_POWER_SOFTCONN 0x40 +#define MUSB_POWER_HSENAB 0x20 +#define MUSB_POWER_HSMODE 0x10 +#define MUSB_POWER_RESET 0x08 +#define MUSB_POWER_RESUME 0x04 +#define MUSB_POWER_SUSPENDM 0x02 +#define MUSB_POWER_ENSUSPEND 0x01 +#define MUSB_POWER_HSMODE_SHIFT 4 + + +/* INTRUSB */ +#define MUSB_INTR_SUSPEND 0x01 +#define MUSB_INTR_RESUME 0x02 +#define MUSB_INTR_RESET 0x04 +#define MUSB_INTR_BABBLE 0x04 +#define MUSB_INTR_SOF 0x08 +#define MUSB_INTR_CONNECT 0x10 +#define MUSB_INTR_DISCONNECT 0x20 +#define MUSB_INTR_SESSREQ 0x40 +#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ + +/* DEVCTL */ +#define MUSB_DEVCTL_BDEVICE 0x80 +#define MUSB_DEVCTL_FSDEV 0x40 +#define MUSB_DEVCTL_LSDEV 0x20 +#define MUSB_DEVCTL_VBUS 0x18 +#define MUSB_DEVCTL_VBUS_SHIFT 3 +#define MUSB_DEVCTL_HM 0x04 +#define MUSB_DEVCTL_HR 0x02 +#define MUSB_DEVCTL_SESSION 0x01 + +/* TESTMODE */ +#define MUSB_TEST_FORCE_HOST 0x80 +#define MUSB_TEST_FIFO_ACCESS 0x40 +#define MUSB_TEST_FORCE_FS 0x20 +#define MUSB_TEST_FORCE_HS 0x10 +#define MUSB_TEST_PACKET 0x08 +#define MUSB_TEST_K 0x04 +#define MUSB_TEST_J 0x02 +#define MUSB_TEST_SE0_NAK 0x01 + +/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ +#define MUSB_FIFOSZ_DPB 0x10 +/* Allocation size (8, 16, 32, ... 4096) */ +#define MUSB_FIFOSZ_SIZE 0x0f + +/* CSR0 */ +#define MUSB_CSR0_FLUSHFIFO 0x0100 +#define MUSB_CSR0_TXPKTRDY 0x0002 +#define MUSB_CSR0_RXPKTRDY 0x0001 + +/* CSR0 in Peripheral mode */ +#define MUSB_CSR0_P_SVDSETUPEND 0x0080 +#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 +#define MUSB_CSR0_P_SENDSTALL 0x0020 +#define MUSB_CSR0_P_SETUPEND 0x0010 +#define MUSB_CSR0_P_DATAEND 0x0008 +#define MUSB_CSR0_P_SENTSTALL 0x0004 + +/* CSR0 in Host mode */ +#define MUSB_CSR0_H_DIS_PING 0x0800 +#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ +#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ +#define MUSB_CSR0_H_NAKTIMEOUT 0x0080 +#define MUSB_CSR0_H_STATUSPKT 0x0040 +#define MUSB_CSR0_H_REQPKT 0x0020 +#define MUSB_CSR0_H_ERROR 0x0010 +#define MUSB_CSR0_H_SETUPPKT 0x0008 +#define MUSB_CSR0_H_RXSTALL 0x0004 + +/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_CSR0_P_WZC_BITS \ + (MUSB_CSR0_P_SENTSTALL) +#define MUSB_CSR0_H_WZC_BITS \ + (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ + | MUSB_CSR0_RXPKTRDY) + +/* TxType/RxType */ +#define MUSB_TYPE_SPEED 0xc0 +#define MUSB_TYPE_SPEED_SHIFT 6 +#define MUSB_TYPE_SPEED_HIGH 1 +#define MUSB_TYPE_SPEED_FULL 2 +#define MUSB_TYPE_SPEED_LOW 3 +#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_SHIFT 4 +#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_BULK 2 + +/* CONFIGDATA */ +#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ +#define MUSB_CONFIGDATA_BIGENDIAN 0x20 +#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ +#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ +#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ +#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ +#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ + +/* TXCSR in Peripheral and Host mode */ +#define MUSB_TXCSR_AUTOSET 0x8000 +#define MUSB_TXCSR_MODE 0x2000 +#define MUSB_TXCSR_DMAENAB 0x1000 +#define MUSB_TXCSR_FRCDATATOG 0x0800 +#define MUSB_TXCSR_DMAMODE 0x0400 +#define MUSB_TXCSR_CLRDATATOG 0x0040 +#define MUSB_TXCSR_FLUSHFIFO 0x0008 +#define MUSB_TXCSR_FIFONOTEMPTY 0x0002 +#define MUSB_TXCSR_TXPKTRDY 0x0001 + +/* TXCSR in Peripheral mode */ +#define MUSB_TXCSR_P_ISO 0x4000 +#define MUSB_TXCSR_P_INCOMPTX 0x0080 +#define MUSB_TXCSR_P_SENTSTALL 0x0020 +#define MUSB_TXCSR_P_SENDSTALL 0x0010 +#define MUSB_TXCSR_P_UNDERRUN 0x0004 + +/* TXCSR in Host mode */ +#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 +#define MUSB_TXCSR_H_DATATOGGLE 0x0100 +#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 +#define MUSB_TXCSR_H_RXSTALL 0x0020 +#define MUSB_TXCSR_H_ERROR 0x0004 +#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 + + +/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_TXCSR_P_WZC_BITS \ + (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ + | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) +#define MUSB_TXCSR_H_WZC_BITS \ + (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ + | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) + +/* RXCSR in Peripheral and Host mode */ +#define MUSB_RXCSR_AUTOCLEAR 0x8000 +#define MUSB_RXCSR_DMAENAB 0x2000 +#define MUSB_RXCSR_DISNYET 0x1000 +#define MUSB_RXCSR_PID_ERR 0x1000 +#define MUSB_RXCSR_DMAMODE 0x0800 +#define MUSB_RXCSR_INCOMPRX 0x0100 +#define MUSB_RXCSR_CLRDATATOG 0x0080 +#define MUSB_RXCSR_FLUSHFIFO 0x0010 +#define MUSB_RXCSR_DATAERROR 0x0008 +#define MUSB_RXCSR_FIFOFULL 0x0002 +#define MUSB_RXCSR_RXPKTRDY 0x0001 + +/* RXCSR in Peripheral mode */ +#define MUSB_RXCSR_P_ISO 0x4000 +#define MUSB_RXCSR_P_SENTSTALL 0x0040 +#define MUSB_RXCSR_P_SENDSTALL 0x0020 +#define MUSB_RXCSR_P_OVERRUN 0x0004 + +/* RXCSR in Host mode */ +#define MUSB_RXCSR_H_AUTOREQ 0x4000 +#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 +#define MUSB_RXCSR_H_DATATOGGLE 0x0200 +#define MUSB_RXCSR_H_RXSTALL 0x0040 +#define MUSB_RXCSR_H_REQPKT 0x0020 +#define MUSB_RXCSR_H_ERROR 0x0004 +#define MUSB_S_RXCSR_H_DATATOGGLE 9 + +/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_RXCSR_P_WZC_BITS \ + (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ + | MUSB_RXCSR_RXPKTRDY) +#define MUSB_RXCSR_H_WZC_BITS \ + (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ + | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) + +/* HUBADDR */ +#define MUSB_HUBADDR_MULTI_TT 0x80 + +/* Endpoint configuration information. Note: The value of endpoint fifo size + * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other + * values are not supported + */ +struct musb_epinfo { + u8 epnum; /* Endpoint number */ + u8 epdir; /* Endpoint direction */ + u16 epsize; /* Endpoint FIFO size */ +}; + +/* exported functions */ +extern void musb_start(void); +extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); +extern void write_fifo(u8 ep, u32 length, void *fifo_data); +extern void read_fifo(u8 ep, u32 length, void *fifo_data); + +/* extern functions */ +extern inline void musb_writew(u32 offset, u16 value); +extern inline void musb_writeb(u32 offset, u8 value); +extern inline u16 musb_readw(u32 offset); +extern inline u8 musb_readb(u32 offset); + +#endif /* __MUSB_HDRC_DEFS_H__ */ + diff --git a/drivers/usb/musb_hcd.c b/drivers/usb/musb_hcd.c new file mode 100644 index 0000000..ebe36d4 --- /dev/null +++ b/drivers/usb/musb_hcd.c @@ -0,0 +1,707 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#include <common.h> + +#ifdef CONFIG_MUSB_HCD +#include "musb_hcd.h" + +/* MSC control transfers */ +#define USB_MSC_BBB_RESET 0xFF +#define USB_MSC_BBB_GET_MAX_LUN 0xFE + +/* speed negotiated with the connected device */ +static u8 musb_speed; + +/* Endpoint configuration information */ +static struct musb_epinfo epinfo[2] = { + {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ + {MUSB_BULK_EP, 0, 512} /* EP1 - Bluk In - 512 Bytes */ +}; + +/* + * This function writes the data toggle value. + */ +static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) +{ + u16 toggle = usb_gettoggle(dev, ep, dir_out); + u16 csr; + + if (dir_out) { + if (!toggle) + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + MUSB_TXCSR_CLRDATATOG); + else { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + csr |= MUSB_TXCSR_H_WR_DATATOGGLE; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), csr); + csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), csr); + } + } else { + if (!toggle) + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + MUSB_RXCSR_CLRDATATOG); + else { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + csr |= MUSB_RXCSR_H_WR_DATATOGGLE; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + } + } +} + +/* + * This function checks if RxStall has occured on the endpoint. If a RxStall + * has occured, the RxStall is cleared and 1 is returned. If RxStall has + * not occured, 0 is returned. + */ +static u8 check_stall(u8 ep, u8 dir_out) +{ + u16 csr; + + /* For endpoint 0 */ + if (!ep) { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + if (csr & MUSB_CSR0_H_RXSTALL) { + csr &= ~MUSB_CSR0_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + return 1; + } + } else { /* For non-ep0 */ + if (dir_out) { /* is it tx ep */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + if (csr & MUSB_TXCSR_H_RXSTALL) { + csr &= ~MUSB_TXCSR_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr); + return 1; + } + } else { /* is it rx ep */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + if (csr & MUSB_RXCSR_H_RXSTALL) { + csr &= ~MUSB_RXCSR_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr); + return 1; + } + } + } + return 0; +} + + +/* + * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout + * error and -2 for stall. + */ +static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) +{ + u16 csr; + int result = 1; + + while (result > 0) { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + if (csr & MUSB_CSR0_H_ERROR) { + csr &= ~MUSB_CSR0_H_ERROR; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + dev->status = USB_ST_CRC_ERR; + result = -1; + break; + } + + switch (bit_mask) { + case MUSB_CSR0_TXPKTRDY: + if (!(csr & MUSB_CSR0_TXPKTRDY)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + + case MUSB_CSR0_RXPKTRDY: + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + if (csr & MUSB_CSR0_RXPKTRDY) + result = 0; + break; + + case MUSB_CSR0_H_REQPKT: + if (!(csr & MUSB_CSR0_H_REQPKT)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + } + } + return result; +} + +/* + * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 1)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + if (csr & MUSB_TXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (csr & MUSB_TXCSR_TXPKTRDY); + return 1; +} + +/* + * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 0)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + if (csr & MUSB_RXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (!(csr & MUSB_RXCSR_RXPKTRDY)); + return 1; +} + +/* + * This function performs the setup phase of the control transfer + */ +static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) +{ + int result; + u16 csr; + + /* write the control request to ep0 fifo */ + write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); + + /* enable transfer of setup packet */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* wait until the setup packet is transmitted */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + dev->act_len = 0; + return result; +} + +/* + * This function handles the control transfer in data phase + */ +static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 rxlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *rxbuff = (u8 *)buffer; + u8 rxedlength; + int result; + + while (rxlen < len) { + /* Determine the next read length */ + nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); + + /* Set the ReqPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), + csr | MUSB_CSR0_H_REQPKT); + + result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); + if (result < 0) + return result; + + /* Actual number of bytes received by usb */ + rxedlength = musb_readb(MUSB_INDEXED_OFFSET(MUSB_COUNT0)); + + /* Read the data from the RxFIFO */ + read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); + + /* Clear the RxPktRdy Bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr &= ~MUSB_CSR0_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* short packet? */ + if (rxedlength != nextlen) { + dev->act_len += rxedlength; + break; + } + rxlen += nextlen; + dev->act_len = rxlen; + } + return 0; +} + +/* + * This function handles the control transfer out data phase + */ +static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *txbuff = (u8 *)buffer; + int result = 0; + + while (txlen < len) { + /* Determine the next write length */ + nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); + + /* Load the data to send in FIFO */ + write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); + + /* Set TXPKTRDY bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), + csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY); + + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + if (result < 0) + break; + + txlen += nextlen; + dev->act_len = txlen; + } + return result; +} + + +/* + * This function handles the control transfer out status phase + */ +static int ctrlreq_out_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | + MUSB_CSR0_H_STATUSPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* Wait until TXPKTRDY bit is cleared */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + return result; +} + + +/* + * This function handles the control transfer in status phase + */ +static int ctrlreq_in_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit and ReqPkt bit */ + csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); + + /* clear StatusPkt bit and RxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + return result; +} + + +/* + * determines the speed of the device (High/Full/Slow) + */ +static u8 get_dev_speed(struct usb_device *dev) +{ + return (dev->high) ? MUSB_TYPE_SPEED_HIGH : + ((dev->slow) ? MUSB_TYPE_SPEED_LOW : MUSB_TYPE_SPEED_FULL); +} + +/* + * configure the hub address and the port address. + */ +static void config_hub_port(struct usb_device *dev, u8 ep) +{ + u8 chid; + u8 hub; + + /* Find out the nearest parent which is high speed */ + while (dev->parent->parent != NULL) + if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) + dev = dev->parent; + else + break; + + /* determine the port address at that hub */ + hub = dev->parent->devnum; + for (chid = 0; chid < USB_MAXCHILDREN; chid++) + if (dev->parent->children[chid] == dev) + break; + + /* configure the hub address and the port address */ + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_TXHUBADDR), hub); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_TXHUBPORT), (chid + 1)); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_RXHUBADDR), hub); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_RXHUBPORT), (chid + 1)); +} + +/* + * do a control transfer + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + u16 csr; + u8 devspeed; + + /* select control endpoint */ + musb_writeb(MUSB_INDEX, MUSB_CONTROL_EP); + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + + /* target addr and (for multipoint) hub addr/port */ + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, MUSB_TXFUNCADDR), + devnum); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, MUSB_RXFUNCADDR), + devnum); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + config_hub_port(dev, MUSB_CONTROL_EP); + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TYPE0), devspeed << 6); + } else { + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TYPE0), musb_speed << 6); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_TXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_TXHUBPORT), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_RXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_RXHUBPORT), 0); + } + + /* Control transfer setup phase */ + if (ctrlreq_setup_phase(dev, setup) < 0) + return 0; + + switch (setup->request) { + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_GET_STATUS: + case USB_MSC_BBB_GET_MAX_LUN: + /* control transfer in-data-phase */ + if (ctrlreq_in_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer out-status-phase */ + if (ctrlreq_out_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_INTERFACE: + case USB_REQ_CLEAR_FEATURE: + case USB_MSC_BBB_RESET: + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_DESCRIPTOR: + /* control transfer out data phase */ + if (ctrlreq_out_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + default: + /* unhandled control transfer */ + return -1; + } + + dev->status = 0; + dev->act_len = len; + return len; +} + +/* + * do a bulk transfer + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select bulk endpoint */ + musb_writeb(MUSB_INDEX, MUSB_BULK_EP); + + /* write the address of the device */ + if (dir_out) + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXFUNCADDR), devnum); + else + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXFUNCADDR), devnum); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_BULK_EP); + } else { + if (dir_out) { + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXHUBPORT), 0); + } else { + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXHUBPORT), 0); + } + devspeed = musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (dir_out) { /* bulk-out transfer */ + /* Program the TxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TXTYPE), type); + + /* Write maximum packet size to the TxMaxp register */ + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXMAXP), + dev->epmaxpacketout[ep]); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? + (len-txlen) : dev->epmaxpacketout[ep]; + + /* Write the data to the FIFO */ + write_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Set the TxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_TXPKTRDY); + + /* Wait until the TxPktRdy bit is cleared */ + if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + csr = musb_readw( + MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + dev->act_len = txlen; + return 0; + } + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + } else { /* bulk-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_RXTYPE), type); + + /* Write the maximum packet size to the RxMaxp register */ + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXMAXP), + dev->epmaxpacketin[ep]); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + MUSB_RXCSR_H_REQPKT); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + csr = musb_readw( + MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr); + dev->act_len = txlen; + return 0; + } + + /* Read the data from the FIFO */ + read_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + csr &= ~MUSB_RXCSR_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* bulk transfer is complete */ + dev->status = 0; + dev->act_len = len; + return 0; +} + +/* + * This function initializes the usb controller module. + */ +int usb_lowlevel_init(void) +{ + u8 power; + u32 timeout; + + if (musb_platform_init() == -1) + return -1; + + /* Configure all the endpoint FIFO's and start usb controller */ + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + musb_start(); + + /* + * Wait until musb is enabled in host mode with a timeout. There + * should be a usb device connected. + */ + timeout = MUSB_HCD_TIMEOUT; + while (timeout--) + if (musb_readb(MUSB_DEVCTL) & MUSB_DEVCTL_HM) + break; + + /* if musb core is not in host mode, then return */ + if (!timeout) + return -1; + + /* start usb bus reset */ + power = musb_readb(MUSB_POWER); + musb_writeb(MUSB_POWER, power | MUSB_POWER_RESET); + + /* After initiating a usb reset, wait for about 20ms to 30ms */ + udelay(30000); + + /* stop usb bus reset */ + power = musb_readb(MUSB_POWER); + power &= ~MUSB_POWER_RESET; + musb_writeb(MUSB_POWER, power); + + /* Determine if the connected device is a high/full/low speed device */ + musb_speed = (musb_readb(MUSB_POWER) & MUSB_POWER_HSMODE) ? + MUSB_TYPE_SPEED_HIGH : + ((musb_readb(MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ? + MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); + return 0; +} + +/* + * This function stops the operation of the davinci usb module. + */ +int usb_lowlevel_stop(void) +{ + /* Reset the USB module */ + musb_platform_deinit(); + musb_writeb(MUSB_DEVCTL, 0); + return 0; +} + +/* + * This function supports usb interrupt transfers. Currently, usb interrupt + * transfers are not supported. + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len, int interval) +{ + return -1; +} + +#endif /* CONFIG_MUSB_HCD */ + + + diff --git a/drivers/usb/musb_hcd.h b/drivers/usb/musb_hcd.h new file mode 100644 index 0000000..a561e54 --- /dev/null +++ b/drivers/usb/musb_hcd.h @@ -0,0 +1,49 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#ifndef __MUSB_HCD_H__ +#define __MUSB_HCD_H__ + +#include "musb_core.h" + +/* The controller driver polls for changes in the state. This defines a timeout + for cases where the states do not change so the appropriate error can be + returned. */ +#define MUSB_HCD_TIMEOUT 0x3FFFFFF + +/* This defines the endpoint number used for control transfers */ +#define MUSB_CONTROL_EP 0 + +/* This defines the endpoint number used for bulk transfer */ +#define MUSB_BULK_EP 1 + +/* Determine the operating speed of MUSB core */ +#define musb_ishighspeed() \ + ((musb_readb(MUSB_POWER) & MUSB_POWER_HSMODE) \ + >> MUSB_POWER_HSMODE_SHIFT) + +/* extern functions */ +extern int musb_platform_init(void); +extern void musb_platform_deinit(void); + +#endif /* __MUSB_HCD_H__ */ -- 1.5.6

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[U-Boot] MPC5121 MSCAN Peripheral in U-Boot
by Matteo Canella 16 Dec '08

16 Dec '08

Hi sirs, I'm implementing a driver for the MSCAN peripheral of the mpc5121 in Das U-Boot. I'm wondering if there's anyone who has already done some work on it. Thank you Matteo Canella Digitek

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[U-Boot] [PATCH] MIPS: Add VCT board series support (Part 1/3)
by Stefan Roese 16 Dec '08

16 Dec '08

This patch adds support for the Micronas VCT board series. Currently the following platforms are supported: vct_premium vct_premium_small vct_premium_onenand vct_premium_onenand_small vct_platinum vct_platinum_small vct_platinum_onenand vct_platinum_onenand_small vct_platinumavc vct_platinumavc_small vct_platinumavc_onenand vct_platinumavc_onenand_small One speciality of the VCT board is that it can't access NOR FLASH memory-mapped. It has to use special access functions for this. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/micronas/vct/Makefile | 56 +++++ board/micronas/vct/config.mk | 31 +++ board/micronas/vct/ebi.c | 48 +++++ board/micronas/vct/ebi_nor_flash.c | 131 ++++++++++++ board/micronas/vct/ebi_onenand.c | 168 +++++++++++++++ board/micronas/vct/ebi_smc911x.c | 94 +++++++++ board/micronas/vct/gpio.c | 88 ++++++++ board/micronas/vct/smc_eeprom.c | 394 ++++++++++++++++++++++++++++++++++++ board/micronas/vct/top.c | 289 ++++++++++++++++++++++++++ board/micronas/vct/u-boot.lds | 70 +++++++ board/micronas/vct/vct.c | 117 +++++++++++ 11 files changed, 1486 insertions(+), 0 deletions(-) create mode 100644 board/micronas/vct/Makefile create mode 100644 board/micronas/vct/config.mk create mode 100644 board/micronas/vct/ebi.c create mode 100644 board/micronas/vct/ebi_nor_flash.c create mode 100644 board/micronas/vct/ebi_onenand.c create mode 100644 board/micronas/vct/ebi_smc911x.c create mode 100644 board/micronas/vct/gpio.c create mode 100644 board/micronas/vct/smc_eeprom.c create mode 100644 board/micronas/vct/top.c create mode 100644 board/micronas/vct/u-boot.lds create mode 100644 board/micronas/vct/vct.c diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile new file mode 100644 index 0000000..2f8ece6 --- /dev/null +++ b/board/micronas/vct/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-y += ebi.o +COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o +COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o +COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o +COBJS-y += gpio.o +COBJS-y += top.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk new file mode 100644 index 0000000..2a71dad --- /dev/null +++ b/board/micronas/vct/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# vct_xxx boards with MIPS 4Kc CPU core +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0x87000000 +endif diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c new file mode 100644 index 0000000..8e93f69 --- /dev/null +++ b/board/micronas/vct/ebi.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +int ebi_initialize(void) +{ +#if defined(CONFIG_VCT_NOR) + if (ebi_init_nor_flash()) + return -1; +#endif + +#if defined(CONFIG_VCT_ONENAND) + if (ebi_init_onenand()) + return -1; +#endif + +#if defined(CONFIG_DRIVER_SMC911X) + if (ebi_init_smc911x()) + return -1; +#endif + + reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); + + ebi_wait(); + + return 0; +} diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c new file mode 100644 index 0000000..ae87643 --- /dev/null +++ b/board/micronas/vct/ebi_nor_flash.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +static u32 ebi_read(u32 addr) +{ + addr &= ~0xFC000000; + + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); +} + +static int ebi_write_u16(u32 addr, u32 data, int fetchIO) +{ + u32 val = (data << 16); + + addr &= ~0xFC000000; + + ebi_wait(); + + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr); + ebi_wait(); + + if (fetchIO) { + u32 counter = 0; + while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { + if (counter++ > 0xFFFFFF) + return 1; + } + } + + return 0; +} + +static u16 ebi_read_u16(u32 addr) +{ + return ((ebi_read(addr) >> 16) & 0xFFFF); +} + +static u8 ebi_read_u8(u32 addr) +{ + u32 val = ebi_read(addr) >> 16; + + if (addr & 0x1) + return val & 0xff; + else + return (val >> 8) & 0xff; +} + +/* + * EBI initialization for NOR FLASH access + */ +int ebi_init_nor_flash(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/mtd/cfi_flash.c + */ +void flash_write8(u8 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +void flash_write16(u16 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +u8 flash_read8(void *addr) +{ + return ebi_read_u8((u32)addr); +} + +u16 flash_read16(void *addr) +{ + return ebi_read_u16((u32)addr); +} + +u32 flash_read32(void *addr) +{ + return ((u32)ebi_read_u16((u32)addr) << 16) | + ebi_read_u16((u32)addr + 2); +} + +void *board_flash_read_memcpy(void *dest, const void *src, size_t count) +{ + u16 *tmp = (u16 *)dest, *s = (u16 *)src; + int i; + + for (i = 0; i < count; i += 2) + *tmp++ = flash_read16(s++); + + return dest; +} diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c new file mode 100644 index 0000000..5da59b5 --- /dev/null +++ b/board/micronas/vct/ebi_onenand.c @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include "vct.h" + +static u16 ebi_nand_read_word(void __iomem *addr) +{ + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; +} + +static void ebi_nand_write_word(u16 data, void __iomem * addr) +{ + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); + ebi_wait(); +} + +/* + * EBI initialization for OneNAND FLASH access + */ +int ebi_init_onenand(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); + reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); + reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); + + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + /* prepare DMA configuration for EBI */ + reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); + + /* READ only no byte order change, TAG 1 used */ + reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); + + reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ + reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); + reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); + reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); + + return 0; +} + +static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + *d++ = ebi_nand_read_word(s++); + + return ret; +} + +static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + ebi_nand_write_word(*s++, d++); + + return ret; +} + +static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { + if (area == ONENAND_DATARAM) + return mtd->writesize; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } + + return 0; +} + +static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy_16_from_onenand(buffer, bufferram + offset, count); + + return 0; +} + +static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy_16_to_onenand(bufferram + offset, buffer, count); + + return 0; +} + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *chip = mtd->priv; + + /* + * Insert board specific OneNAND access functions + */ + chip->read_word = ebi_nand_read_word; + chip->write_word = ebi_nand_write_word; + + chip->read_bufferram = ebi_read_bufferram; + chip->read_spareram = ebi_read_bufferram; + chip->write_bufferram = ebi_write_bufferram; +} diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c new file mode 100644 index 0000000..e1b67a0 --- /dev/null +++ b/board/micronas/vct/ebi_smc911x.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +/* + * EBI initialization for SMC911x access + */ +int ebi_init_smc911x(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + + reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); + reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); + + reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); + reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/net/smc911x.c + */ +u32 smc911x_reg_read(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return (data); +} + +void smc911x_reg_write(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); +} + +void pkt_data_push(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); + + return; +} + +u32 pkt_data_pull(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return data; +} diff --git a/board/micronas/vct/gpio.c b/board/micronas/vct/gpio.c new file mode 100644 index 0000000..2c113be --- /dev/null +++ b/board/micronas/vct/gpio.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +/* + * Find out to which of the 2 gpio modules the pin specified in the + * argument belongs: + * GPIO_MODULE yields 0 for pins 0 to 31, + * 1 for pins 32 to 63 + */ +#define GPIO_MODULE(pin) ((pin) >> 5) + +/* + * Bit position within a 32-bit peripheral register (where every + * bit is one bitslice) + */ +#define MASK(pin) (1 << ((pin) & 0x1F)) +#define BASE_ADDR(mod) module_base[mod] + +/* + * Lookup table for transforming gpio module number 0 to 2 to + * address offsets + */ +static u32 module_base[] = { + GPIO1_BASE, + GPIO2_BASE +}; + +static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask) +{ + reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); +} + +int vct_gpio_dir(int pin, int dir) +{ + u32 gpio_base; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + + if (dir == 0) + clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); + else + clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); + + return 0; +} + +void vct_gpio_set(int pin, int val) +{ + u32 gpio_base; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + + if (val == 0) + clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); + else + clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); +} + +int vct_gpio_get(int pin) +{ + u32 gpio_base; + u32 value; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + value = reg_read(GPIO_EXT_PORTA(gpio_base)); + + return ((value & MASK(pin)) ? 1 : 0); +} diff --git a/board/micronas/vct/smc_eeprom.c b/board/micronas/vct/smc_eeprom.c new file mode 100644 index 0000000..2bc7ad4 --- /dev/null +++ b/board/micronas/vct/smc_eeprom.c @@ -0,0 +1,394 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright 2005, Seagate Technology LLC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#undef DEBUG + +#include <common.h> +#include <command.h> +#include <config.h> +#include <net.h> + +#include "vct.h" + +#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE +#define BYTE_TEST (SMSC9118_BASE + 0x64) +#define GPIO_CFG (SMSC9118_BASE + 0x88) +#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY (0x80000000) +#define MAC_CSR_CMD_RNW (0x40000000) +#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW)) +#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY)) +#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8) +#define E2P_CMD (SMSC9118_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */ +#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */ +#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */ +#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */ +#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */ +#define E2P_DATA (SMSC9118_BASE + 0xB4) + +#define MAC_ADDRH (0x2) +#define MAC_ADDRL (0x3) + +#define MAC_TIMEOUT 200 + +#define HIBYTE(word) ((u8)(((u16)(word)) >> 8)) +#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU)) +#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16)) +#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL)) + +static int mac_busy(int req_to) +{ + int timeout = req_to; + + while (timeout--) { + if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)) + goto done; + } + return 1; /* Timeout */ + +done: + return 0; /* No timeout */ +} + +static ulong get_mac_reg(int reg) +{ + ulong reg_val = 0xffffffff; + + if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) { + printf("get_mac_reg: previous command not complete\n"); + goto done; + } + + smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg)); + udelay(10000); + + if (mac_busy(MAC_TIMEOUT) == 1) { + printf("get_mac_reg: timeout waiting for response from MAC\n"); + goto done; + } + + reg_val = smc911x_reg_read(MAC_CSR_DATA); + +done: + return (reg_val); +} + +static ulong eeprom_enable_access(void) +{ + ulong gpio; + + gpio = smc911x_reg_read(GPIO_CFG); + debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio, + (gpio & 0xFF0FFFFFUL)); + + smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL)); + return gpio; +} + +static void eeprom_disable_access(ulong gpio) +{ + debug("%s: gpio= 0x%08lx\n", __func__, gpio); + smc911x_reg_write(GPIO_CFG, gpio); +} + +static int eeprom_is_mac_address_loaded(void) +{ + int ret; + + ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_; + debug("%s: ret = %x\n", __func__, ret); + + return ret; +} + +static int eeprom_read_location(unchar address, u8 *data) +{ + ulong timeout = 100000; + ulong temp = 0; + + if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp); + return 0; + } + + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ | + ((ulong) address))); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout\n"); + return 0; + } + (*data) = (unchar) (smc911x_reg_read(E2P_DATA)); + debug("%s: ret = %x\n", __func__, (*data)); + + return 1; +} + +static int eeprom_enable_erase_and_write(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[1]\n"); + return 0; + } + + return 1; +} + +static int eeprom_disable_erase_and_write(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[2]\n"); + return 0; + } + + return 1; +} + +static int eeprom_write_location(unchar address, unchar data) +{ + ulong timeout = 100000; + + debug("%s: address: %x data = %x\n", __func__, address, data); + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + + smc911x_reg_write(E2P_DATA, ((ulong) data)); + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ | + ((ulong) address))); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[3]\n"); + return 0; + } + + return 1; +} + +static int eeprom_erase_all(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[4]\n"); + return 0; + } + + return 1; +} + +static int eeprom_reload(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return -1; + } + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) + return 0; + + return 1; +} + +static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32) +{ + int result = 0; + + debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32); + + if (!eeprom_enable_erase_and_write()) + goto DONE; + if (!eeprom_erase_all()) + goto DONE; + if (!eeprom_write_location(0, 0xA5)) + goto DONE; + if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16)))) + goto DONE; + if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16)))) + goto DONE; + if (!eeprom_disable_erase_and_write()) + goto DONE; + + result = 1; + +DONE: + return result; +} + +static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unchar data = 0, index = 0; + ulong gpio_old_val; + + gpio_old_val = eeprom_enable_access(); + + printf("EEPROM content: \n"); + for (index = 0; index < 8; index++) { + if (eeprom_read_location(index, &data)) + printf("%02x ", data); + else + printf("FAILED"); + } + + eeprom_disable_access(gpio_old_val); + printf("\n"); + + return 0; +} + +static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + eeprom_erase_all(); + + return 0; +} + +static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong hi16, lo32; + unchar ethaddr[6], i; + ulong gpio; + char *tmp, *end; + + tmp = argv[1]; + for (i = 0; i < 6; i++) { + ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end + 1 : end; + } + + hi16 = (ethaddr[5] << 8) | (ethaddr[4]); + lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) | + (ethaddr[1] << 8) | (ethaddr[0]); + + gpio = eeprom_enable_access(); + + eeprom_save_mac_address(hi16, lo32); + + eeprom_reload(); + + /* Check new values */ + if (eeprom_is_mac_address_loaded()) { + ulong mac_hi16, mac_lo32; + + mac_hi16 = get_mac_reg(MAC_ADDRH); + mac_lo32 = get_mac_reg(MAC_ADDRL); + printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32); + } else { + printf("Address is not reloaded \n"); + } + eeprom_disable_access(gpio); + + return 0; +} + +U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all, + "smcee - Erase content of SMC EEPROM\n",); + +U_BOOT_CMD(smced, 1, 0, do_eeprom_dump, + "smced - Dump content of SMC EEPROM\n",); + +U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac, + "smcew - Write MAC address to SMC EEPROM\n", + "aa:bb:cc:dd:ee:ff new mac address\n"); diff --git a/board/micronas/vct/top.c b/board/micronas/vct/top.c new file mode 100644 index 0000000..0923954 --- /dev/null +++ b/board/micronas/vct/top.c @@ -0,0 +1,289 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include "vct.h" + +typedef union _TOP_PINMUX_t +{ + u32 reg; + struct { + u32 res : 24; /* reserved */ + u32 drive : 2; /* Driver strength */ + u32 slew : 1; /* Slew rate */ + u32 strig : 1; /* Schmitt trigger input*/ + u32 pu_pd : 2; /* Pull up/ pull down */ + u32 funsel : 2; /* Pin function */ + } Bits; +} TOP_PINMUX_t; + +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + +static TOP_PINMUX_t top_read_pin(int pin) +{ + TOP_PINMUX_t reg; + + switch (pin) { + case 2: + case 3: + case 6: + case 9: + reg.reg = 0xdeadbeef; + break; + case 4: + reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); + break; + case 5: + reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); + break; + case 7: + reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); + break; + case 8: + reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + + ((pin - 10) * 4)); + break; + default: + reg.reg = reg_read(TOP_BASE + (pin * 4)); + break; + } + + return reg; +} + +static void top_write_pin(int pin, TOP_PINMUX_t reg) +{ + + switch (pin) { + case 4: + reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); + break; + case 5: + reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); + break; + case 7: + reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); + break; + case 8: + reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + + ((pin - 10) * 4), reg.reg); + break; + default: + reg_write(TOP_BASE + (pin * 4), reg.reg); + break; + } +} + +int top_set_pin(int pin, int func) +{ + TOP_PINMUX_t reg; + + /* check global range */ + if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) + return -1; /* pin number or function out of valid range */ + + /* check undefined values; */ + if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9)) + return -1; /* pin number out of valid range */ + + reg = top_read_pin(pin); + reg.Bits.funsel = func; + top_write_pin(pin, reg); + + return 0; +} + +#endif + +#if defined(CONFIG_VCT_PLATINUMAVC) + +int top_set_pin(int pin, int func) +{ + TOP_PINMUX_t reg; + + /* check global range */ + if ((pin < 0) || (pin > 158)) + return -1; /* pin number or function out of valid range */ + + reg.reg = reg_read(TOP_BASE + (pin * 4)); + reg.Bits.funsel = func; + reg_write(TOP_BASE + (pin * 4), reg.reg); + + return 0; +} + +#endif + +void vct_pin_mux_initialize(void) +{ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + top_set_pin(34, 01); /* EBI_CS0 */ + top_set_pin(33, 01); /* EBI_CS1 */ + top_set_pin(32, 01); /* EBI_CS2 */ + top_set_pin(100, 02); /* EBI_CS3 */ + top_set_pin(101, 02); /* EBI_CS4 */ + top_set_pin(102, 02); /* EBI_CS5 */ + top_set_pin(103, 02); /* EBI_CS6 */ + top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(35, 01); /* EBI_ALE */ + top_set_pin(36, 01); /* EBI_ADDR15 */ + top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ + top_set_pin(38, 01); /* EBI_ADDR13 */ + top_set_pin(39, 01); /* EBI_ADDR12 */ + top_set_pin(40, 01); /* EBI_ADDR11 */ + top_set_pin(41, 01); /* EBI_ADDR10 */ + top_set_pin(42, 01); /* EBI_ADDR9 */ + top_set_pin(43, 01); /* EBI_ADDR8 */ + top_set_pin(44, 01); /* EBI_ADDR7 */ + top_set_pin(45, 01); /* EBI_ADDR6 */ + top_set_pin(46, 01); /* EBI_ADDR5 */ + top_set_pin(47, 01); /* EBI_ADDR4 */ + top_set_pin(48, 01); /* EBI_ADDR3 */ + top_set_pin(49, 01); /* EBI_ADDR2 */ + top_set_pin(50, 01); /* EBI_ADDR1 */ + top_set_pin(51, 01); /* EBI_ADDR0 */ + top_set_pin(52, 01); /* EBI_DIR */ + top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ + top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ + top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ + top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ + top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ + top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ + top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ + top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ + top_set_pin(61, 01); /* EBI_DAT7 */ + top_set_pin(62, 01); /* EBI_DAT6 */ + top_set_pin(63, 01); /* EBI_DAT5 */ + top_set_pin(64, 01); /* EBI_DAT4 */ + top_set_pin(65, 01); /* EBI_DAT3 */ + top_set_pin(66, 01); /* EBI_DAT2 */ + top_set_pin(67, 01); /* EBI_DAT1 */ + top_set_pin(68, 01); /* EBI_DAT0 */ + top_set_pin(69, 01); /* EBI_IORD */ + top_set_pin(70, 01); /* EBI_IOWR */ + top_set_pin(71, 01); /* EBI_WE */ + top_set_pin(72, 01); /* EBI_OE */ + top_set_pin(73, 01); /* EBI_IORDY */ + top_set_pin(95, 02); /* EBI_EBI_DMACK*/ + top_set_pin(112, 02); /* EBI_IRQ0 */ + top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ + top_set_pin(107, 02); /* EBI_IRQ2 */ + top_set_pin(108, 02); /* EBI_IRQ3 */ + top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ + top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ + top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ + top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ + top_set_pin(110, 02); /* EBI_BURST_CLK */ +#endif + +#if defined(CONFIG_VCT_PLATINUMAVC) + top_set_pin(19, 01); /* EBI_CS0 */ + top_set_pin(18, 01); /* EBI_CS1 */ + top_set_pin(17, 01); /* EBI_CS2 */ + top_set_pin(92, 02); /* EBI_CS3 */ + top_set_pin(93, 02); /* EBI_CS4 */ + top_set_pin(95, 02); /* EBI_CS6 */ + top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(20, 01); /* EBI_ALE */ + top_set_pin(21, 01); /* EBI_ADDR15 */ + top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ + top_set_pin(23, 01); /* EBI_ADDR13 */ + top_set_pin(24, 01); /* EBI_ADDR12 */ + top_set_pin(25, 01); /* EBI_ADDR11 */ + top_set_pin(26, 01); /* EBI_ADDR10 */ + top_set_pin(27, 01); /* EBI_ADDR9 */ + top_set_pin(28, 01); /* EBI_ADDR8 */ + top_set_pin(29, 01); /* EBI_ADDR7 */ + top_set_pin(30, 01); /* EBI_ADDR6 */ + top_set_pin(31, 01); /* EBI_ADDR5 */ + top_set_pin(32, 01); /* EBI_ADDR4 */ + top_set_pin(33, 01); /* EBI_ADDR3 */ + top_set_pin(34, 01); /* EBI_ADDR2 */ + top_set_pin(35, 01); /* EBI_ADDR1 */ + top_set_pin(36, 01); /* EBI_ADDR0 */ + top_set_pin(37, 01); /* EBI_DIR */ + top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ + top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ + top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ + top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ + top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ + top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ + top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ + top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ + top_set_pin(46, 01); /* EBI_DAT7 */ + top_set_pin(47, 01); /* EBI_DAT6 */ + top_set_pin(48, 01); /* EBI_DAT5 */ + top_set_pin(49, 01); /* EBI_DAT4 */ + top_set_pin(50, 01); /* EBI_DAT3 */ + top_set_pin(51, 01); /* EBI_DAT2 */ + top_set_pin(52, 01); /* EBI_DAT1 */ + top_set_pin(53, 01); /* EBI_DAT0 */ + top_set_pin(54, 01); /* EBI_IORD */ + top_set_pin(55, 01); /* EBI_IOWR */ + top_set_pin(56, 01); /* EBI_WE */ + top_set_pin(57, 01); /* EBI_OE */ + top_set_pin(58, 01); /* EBI_IORDY */ + top_set_pin(87, 02); /* EBI_EBI_DMACK*/ + top_set_pin(106, 02); /* EBI_IRQ0 */ + top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ + top_set_pin(101, 02); /* EBI_IRQ2 */ + top_set_pin(102, 02); /* EBI_IRQ3 */ + top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ + top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ + top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ + top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ + top_set_pin(104, 02); /* EBI_BURST_CLK */ +#endif + + /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */ + top_set_pin(0, 2); /* SCL2 on GPIO 11 */ + top_set_pin(1, 2); /* SDA2 on GPIO 10 */ + + /* UART pins */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + top_set_pin(141, 1); + top_set_pin(143, 1); +#endif +#if defined(CONFIG_VCT_PLATINUMAVC) + top_set_pin(107, 1); + top_set_pin(109, 1); +#endif +} diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds new file mode 100644 index 0000000..1e1c559 --- /dev/null +++ b/board/micronas/vct/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* +OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") +*/ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + .sdata : { *(.sdata) } + + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss (NOLOAD) : { *(.sbss) } + .bss (NOLOAD) : { *(.bss) } + uboot_end = .; +} diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c new file mode 100644 index 0000000..61af14a --- /dev/null +++ b/board/micronas/vct/vct.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr(a)denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include "vct.h" + +#if defined(CONFIG_VCT_PREMIUM) +#define BOARD_NAME "PremiumD" +#elif defined(CONFIG_VCT_PLATINUM) +#define BOARD_NAME "PlatinumD" +#elif defined(CONFIG_VCT_PLATINUMAVC) +#define BOARD_NAME "PlatinumAVC" +#else +#error "vct: No board variant defined!" +#endif + +#if defined(CONFIG_VCT_ONENAND) +#define BOARD_NAME_ADD " OneNAND" +#else +#define BOARD_NAME_ADD "" +#endif + +int board_early_init_f(void) +{ + /* + * First initialize the PIN mulitplexing + */ + vct_pin_mux_initialize(); + + /* + * Init the EBI very early so that FLASH can be accessed + */ + ebi_initialize(); + + return 0; +} + +void _machine_restart(void) +{ + reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT); + reg_write(WDT_TORR(WDT_BASE), 0x00); + reg_write(WDT_CR(WDT_BASE), 0x1D); + + /* + * Now wait for the watchdog to trigger the reset + */ + udelay(1000000); +} + +/* + * SDRAM is already configured by the bootstrap code, only return the + * auto-detected size here + */ +phys_size_t initdram(int board_type) +{ + return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_MBYTES_SDRAM << 20); +} + +int checkboard(void) +{ + u32 config0 = read_c0_prid(); + char *s = getenv("serial#"); + + if ((config0 & 0xff0000) == PRID_COMP_LEGACY + && (config0 & 0xff00) == PRID_IMP_LX4280) { + puts("Board: MDED \n"); + printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else if ((config0 & 0xff0000) == PRID_COMP_MIPS + && (config0 & 0xff00) == PRID_IMP_VGC) { + u32 jedec_id = *((u32 *) 0xBEBC71A0); + if ((((jedec_id) >> 12) & 0xFF) == 0x40) { + puts("Board: VGCA \n"); + } else if ((((jedec_id) >> 12) & 0xFF) == 0x48 + || (((jedec_id) >> 12) & 0xFF) == 0x49) { + puts("Board: VGCB \n"); + } + printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else if (config0 == 0x19378) { + printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else { + printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24, + config0); + } + + printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} -- 1.6.0.5

2 2

[U-Boot] [PATCH 1/3] 85xx: Fix the boot window issue
by Dave Liu 16 Dec '08

16 Dec '08

If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc85xx/start.S | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 8fa0ff7..80f9677 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -184,19 +184,19 @@ _start_e500: mtspr DBCR0,r0 #endif - /* create a temp mapping in AS=1 to the boot window */ + /* create a temp mapping in AS=1 to the 4M boot window */ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l - /* Align the mapping to 16MB */ - lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l + lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l - lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l mtspr MAS0,r6 mtspr MAS1,r7 -- 1.5.4

1 0

[U-Boot] sectoff in asm
by youhello youhello 16 Dec '08

16 Dec '08

hi all: i am a u-boot beginner, i found a line code "li r0,__got2_entries@sectoff@l" in almost all mpc start.s.i have tried to delete sectoff and i got same result of uboot with "li r0,__got2_entries@l". could you tell me what difference between "li r0,__got2_entries@sectoff@l" and "li r0,__got2_entries@l" and why the author use "li r0,__got2_entries@sectoff@l" but not "li r0,__got2_entries@l".thank very much.

1 0

[U-Boot] [PATCH v4 0/3]Support for XPedite5370 and misc GPIO
by Peter Tyser 16 Dec '08

16 Dec '08

Hello, This patch series adds support for the XPedite5370 SBC. Its an MPC8572-based VPX card with a PMC/XMC site. The XPedite5370 includes a significant number of I2C GPIO devices (5) which are used for board configuration. I added support for 2 new I2C gpio devices in a new drivers/gpio directory. I'm not sure if this is the preferred location/method, so let me know if others have have different preferences. It'd be nice to have a more generic GPIO framework (like Linux's) at some point, but figured this was a step in the right direction by providing a place for generic GPIO devices in drivers/gpio. Thanks, Peter Changes since v1: - Rebased to u-boot-mpc85xx tree - Updated NOR flash remapping method - Added CONFIG_SYS_I2C2_OFFSET define to XPEDITE5370.h - Removed CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE from XPEDITE5370.h Changes since v2: pca953x.c: - Use cmd_tbl_t for subcommand parsing - Made 'info' command dependent on CONFIG_CMD_PCA953X_INFO - Removed chip command parameters, added 'device' subcommand ds4510.c: - Use cmd_tbl_t for subcommand parsing - Made 'info' command dependent on CONFIG_CMD_DS4510_INFO - Made memory commands dependent on CONFIG_CMD_DS4510_MEM - Made 'rst' command dependent on CONFIG_CMD_DS4510_RST - Removed chip command parameters, added 'device' subcommand - Fixed multiline comment style - moved to drivers/misc xpedite5370: - Changed alignment by spaces to alignment by tabs - Fixed gur->devdisr typo for PCIe2 - Fixed some lines over 80 chars - Fixed multiline comment style - Cleaned up environment defines Changes since v3: - Removed CONFIG_L1_INIT_RAM reference Peter Tyser (3): Add support for PCA953x I2C gpio devices Add support for Maxim's DS4510 I2C device XPedite5370 board support MAINTAINERS | 3 + MAKEALL | 1 + Makefile | 5 + README | 13 + board/xes/common/Makefile | 56 ++++ board/xes/common/fsl_8572_clk.c | 51 +++ board/xes/common/fsl_85xx_ddr.c | 93 ++++++ board/xes/common/fsl_85xx_pci.c | 265 ++++++++++++++++ board/xes/xpedite5370/Makefile | 45 +++ board/xes/xpedite5370/config.mk | 35 ++ board/xes/xpedite5370/ddr.c | 270 ++++++++++++++++ board/xes/xpedite5370/law.c | 54 ++++ board/xes/xpedite5370/tlb.c | 94 ++++++ board/xes/xpedite5370/u-boot.lds | 145 +++++++++ board/xes/xpedite5370/xpedite5370.c | 128 ++++++++ drivers/gpio/Makefile | 47 +++ drivers/gpio/pca953x.c | 218 +++++++++++++ drivers/misc/Makefile | 1 + drivers/misc/ds4510.c | 400 ++++++++++++++++++++++++ include/configs/XPEDITE5370.h | 589 +++++++++++++++++++++++++++++++++++ include/gpio/ds4510.h | 75 +++++ include/gpio/pca953x.h | 39 +++ 22 files changed, 2627 insertions(+), 0 deletions(-) create mode 100644 board/xes/common/Makefile create mode 100644 board/xes/common/fsl_8572_clk.c create mode 100644 board/xes/common/fsl_85xx_ddr.c create mode 100644 board/xes/common/fsl_85xx_pci.c create mode 100644 board/xes/xpedite5370/Makefile create mode 100644 board/xes/xpedite5370/config.mk create mode 100644 board/xes/xpedite5370/ddr.c create mode 100644 board/xes/xpedite5370/law.c create mode 100644 board/xes/xpedite5370/tlb.c create mode 100644 board/xes/xpedite5370/u-boot.lds create mode 100644 board/xes/xpedite5370/xpedite5370.c create mode 100644 drivers/gpio/Makefile create mode 100644 drivers/gpio/pca953x.c create mode 100644 drivers/misc/ds4510.c create mode 100644 include/configs/XPEDITE5370.h create mode 100644 include/gpio/ds4510.h create mode 100644 include/gpio/pca953x.h

3 7

[U-Boot] [PATCH] common: Iteration limit for memory test.
by Dirk Eibach 16 Dec '08

16 Dec '08

We want to use mtest for production memory test (though I know it is not recommended). I implemented an iteration limit, so expect can parse the results. The iteration limit is passed to mtest as a fourth parameter: [start [end [pattern [iterations]]]] If no fourth parameter is supplied, there is no iteration limit and the test will loop forever. Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- - Modified original patch title "Added optional iteration limit for alternative memory test." - Iteration limit is now implemented for both original and alternative memory test. common/cmd_mem.c | 29 +++++++++++++++++++++++++---- 1 files changed, 25 insertions(+), 4 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index d7666c2..f87170c 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -672,6 +672,8 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong val; ulong readback; int rcode = 0; + int iterations = 1; + int iteration_limit; #if defined(CONFIG_SYS_ALT_MEMTEST) vu_long len; @@ -687,7 +689,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) vu_long *dummy = 0; /* yes, this is address 0x0, not NULL */ #endif int j; - int iterations = 1; static const ulong bitpattern[] = { 0x00000001, /* single bit */ @@ -722,6 +723,12 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) pattern = 0; } + if (argc > 4) { + iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16); + } else { + iteration_limit = 0; + } + #if defined(CONFIG_SYS_ALT_MEMTEST) printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end); PRINTF("%s:%d: start 0x%p end 0x%p\n", @@ -733,6 +740,13 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + + if (iteration_limit && iterations > iteration_limit) { + printf ("Tested %d iteration(s) without errors.\n", + iterations-1); + return 0; + } + printf("Iteration: %6d\r", iterations); PRINTF("Iteration: %6d\n", iterations); iterations++; @@ -926,6 +940,13 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + if (iteration_limit && iterations > iteration_limit) { + printf ("Tested %d iteration(s) without errors.\n", + iterations-1); + return 0; + } + ++iterations; + printf ("\rPattern %08lX Writing..." "%12s" "\b\b\b\b\b\b\b\b\b\b", @@ -1277,9 +1298,9 @@ U_BOOT_CMD( #endif /* CONFIG_LOOPW */ U_BOOT_CMD( - mtest, 4, 1, do_mem_mtest, - "mtest - simple RAM test\n", - "[start [end [pattern]]]\n" + mtest, 5, 1, do_mem_mtest, + "mtest - simple RAM test\n", + "[start [end [pattern [iterations]]]]\n" " - simple RAM read/write test\n" ); -- 1.5.6.5

2 1

[U-Boot] [PATCH] spi/stmicro: fix debug() display of cmd
by Mike Frysinger 16 Dec '08

16 Dec '08

The stmicro_wait_ready() func tries to show the actual opcode that was sent to the device, but instead it displays the array pointer. Fix it to pull out the opcode from the start of the array. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/mtd/spi/stmicro.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index b8b835a..86324e4 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -137,7 +137,7 @@ static int stmicro_wait_ready(struct spi_flash *flash, unsigned long timeout) ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); if (ret) { - debug("SF: Failed to send command %02x: %d\n", cmd, ret); + debug("SF: Failed to send command %02x: %d\n", cmd[0], ret); return ret; } -- 1.6.0.4

2 1

[U-Boot] [PATCH] env_sf: support embedded environments
by Mike Frysinger 16 Dec '08

16 Dec '08

If both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE are defined, and the sect size is larger than the env size, then it means the env is embedded in a block. So we have to save/restore the part of the sector which is not the environment. Previously, saving the environment in SPI flash in this setup would probably brick the board as the rest of the sector tends to contain actual U-Boot data/code. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/env_sf.c | 41 ++++++++++++++++++++++++++++++++++++----- 1 files changed, 36 insertions(+), 5 deletions(-) diff --git a/common/env_sf.c b/common/env_sf.c index 1bbf93f..2f52e25 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -27,6 +27,7 @@ */ #include <common.h> #include <environment.h> +#include <malloc.h> #include <spi_flash.h> #ifndef CONFIG_ENV_SPI_BUS @@ -60,13 +61,30 @@ uchar env_get_char_spec(int index) int saveenv(void) { + u32 saved_size, saved_offset; + char *saved_buffer = NULL; u32 sector = 1; + int ret; if (!env_flash) { puts("Environment SPI flash not initialized\n"); return 1; } + /* Is the sector larger than the env (i.e. embedded) */ + if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { + saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE; + saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE; + saved_buffer = malloc(saved_size); + if (!saved_buffer) { + ret = 1; + goto done; + } + ret = spi_flash_read(env_flash, saved_offset, saved_size, saved_buffer); + if (ret) + goto done; + } + if (CONFIG_ENV_SIZE > CONFIG_ENV_SECT_SIZE) { sector = CONFIG_ENV_SIZE / CONFIG_ENV_SECT_SIZE; if (CONFIG_ENV_SIZE % CONFIG_ENV_SECT_SIZE) @@ -74,15 +92,28 @@ int saveenv(void) } puts("Erasing SPI flash..."); - if (spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE)) - return 1; + ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, sector * CONFIG_ENV_SECT_SIZE); + if (ret) + goto done; puts("Writing to SPI flash..."); - if (spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr)) - return 1; + ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr); + if (ret) + goto done; + + if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { + ret = spi_flash_write(env_flash, saved_offset, saved_size, saved_buffer); + if (ret) + goto done; + } + ret = 0; puts("done\n"); - return 0; + + done: + if (saved_buffer) + free(saved_buffer); + return ret; } void env_relocate_spec(void) -- 1.6.0.4

3 2

[U-Boot] [PATCH] smc911x_eeprom: new example app for managing newer SMC parts
by Mike Frysinger 16 Dec '08

16 Dec '08

A forward port of the last version to work with the newer smc911x driver. A bunch of simple functions/defines had to be split out of the smc911x driver to avoid ugly code duplication in the eeprom programmer. I only have a board with a LAN9218 part on it, so that is the only one I've tested. But there isn't anything in this that would make it terribly chip specific afaik. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- drivers/net/smc911x.c | 452 +----------------------------------------- drivers/net/smc911x.h | 486 +++++++++++++++++++++++++++++++++++++++++++++ examples/.gitignore | 1 + examples/Makefile | 7 +- examples/smc911x_eeprom.c | 381 +++++++++++++++++++++++++++++++++++ 5 files changed, 874 insertions(+), 453 deletions(-) create mode 100644 drivers/net/smc911x.h create mode 100644 examples/smc911x_eeprom.c diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 648c94c..192bd96 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -27,35 +27,7 @@ #include <net.h> #include <miiphy.h> -#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ - defined (CONFIG_DRIVER_SMC911X_16_BIT) -#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ - CONFIG_DRIVER_SMC911X_16_BIT shall be set" -#endif - -#if defined (CONFIG_DRIVER_SMC911X_32_BIT) -static inline u32 reg_read(u32 addr) -{ - return *(volatile u32*)addr; -} -static inline void reg_write(u32 addr, u32 val) -{ - *(volatile u32*)addr = val; -} -#elif defined (CONFIG_DRIVER_SMC911X_16_BIT) -static inline u32 reg_read(u32 addr) -{ - volatile u16 *addr_16 = (u16 *)addr; - return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); -} -static inline void reg_write(u32 addr, u32 val) -{ - *(volatile u16*)addr = (u16)val; - *(volatile u16*)(addr + 2) = (u16)(val >> 16); -} -#else -#error "SMC911X: undefined bus width" -#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ +#include "smc911x.h" u32 pkt_data_pull(u32 addr) \ __attribute__ ((weak, alias ("reg_read"))); @@ -64,368 +36,6 @@ void pkt_data_push(u32 addr, u32 val) \ #define mdelay(n) udelay((n)*1000) -/* Below are the register offsets and bit definitions - * of the Lan911x memory space - */ -#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) - -#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) -#define TX_CMD_A_INT_ON_COMP 0x80000000 -#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 -#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 -#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 -#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 -#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 -#define TX_CMD_A_INT_FIRST_SEG 0x00002000 -#define TX_CMD_A_INT_LAST_SEG 0x00001000 -#define TX_CMD_A_BUF_SIZE 0x000007FF -#define TX_CMD_B_PKT_TAG 0xFFFF0000 -#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 -#define TX_CMD_B_DISABLE_PADDING 0x00001000 -#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF - -#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) -#define RX_STS_PKT_LEN 0x3FFF0000 -#define RX_STS_ES 0x00008000 -#define RX_STS_BCST 0x00002000 -#define RX_STS_LEN_ERR 0x00001000 -#define RX_STS_RUNT_ERR 0x00000800 -#define RX_STS_MCAST 0x00000400 -#define RX_STS_TOO_LONG 0x00000080 -#define RX_STS_COLL 0x00000040 -#define RX_STS_ETH_TYPE 0x00000020 -#define RX_STS_WDOG_TMT 0x00000010 -#define RX_STS_MII_ERR 0x00000008 -#define RX_STS_DRIBBLING 0x00000004 -#define RX_STS_CRC_ERR 0x00000002 -#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) -#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) -#define TX_STS_TAG 0xFFFF0000 -#define TX_STS_ES 0x00008000 -#define TX_STS_LOC 0x00000800 -#define TX_STS_NO_CARR 0x00000400 -#define TX_STS_LATE_COLL 0x00000200 -#define TX_STS_MANY_COLL 0x00000100 -#define TX_STS_COLL_CNT 0x00000078 -#define TX_STS_MANY_DEFER 0x00000004 -#define TX_STS_UNDERRUN 0x00000002 -#define TX_STS_DEFERRED 0x00000001 -#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) -#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) -#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ -#define ID_REV_REV_ID 0x0000FFFF /* RO */ - -#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) -#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ -#define INT_CFG_INT_DEAS_CLR 0x00004000 -#define INT_CFG_INT_DEAS_STS 0x00002000 -#define INT_CFG_IRQ_INT 0x00001000 /* RO */ -#define INT_CFG_IRQ_EN 0x00000100 /* R/W */ -#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ -#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ - -#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) -#define INT_STS_SW_INT 0x80000000 /* R/WC */ -#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ -#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ -#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ -#define INT_STS_RXDF_INT 0x00400000 /* R/WC */ -#define INT_STS_TX_IOC 0x00200000 /* R/WC */ -#define INT_STS_RXD_INT 0x00100000 /* R/WC */ -#define INT_STS_GPT_INT 0x00080000 /* R/WC */ -#define INT_STS_PHY_INT 0x00040000 /* RO */ -#define INT_STS_PME_INT 0x00020000 /* R/WC */ -#define INT_STS_TXSO 0x00010000 /* R/WC */ -#define INT_STS_RWT 0x00008000 /* R/WC */ -#define INT_STS_RXE 0x00004000 /* R/WC */ -#define INT_STS_TXE 0x00002000 /* R/WC */ -/*#define INT_STS_ERX 0x00001000*/ /* R/WC */ -#define INT_STS_TDFU 0x00000800 /* R/WC */ -#define INT_STS_TDFO 0x00000400 /* R/WC */ -#define INT_STS_TDFA 0x00000200 /* R/WC */ -#define INT_STS_TSFF 0x00000100 /* R/WC */ -#define INT_STS_TSFL 0x00000080 /* R/WC */ -/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ -#define INT_STS_RDFO 0x00000040 /* R/WC */ -#define INT_STS_RDFL 0x00000020 /* R/WC */ -#define INT_STS_RSFF 0x00000010 /* R/WC */ -#define INT_STS_RSFL 0x00000008 /* R/WC */ -#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ -#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ -#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ -#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) -#define INT_EN_SW_INT_EN 0x80000000 /* R/W */ -#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ -#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ -#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ -/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ -#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ -#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ -#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ -#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ -#define INT_EN_PME_INT_EN 0x00020000 /* R/W */ -#define INT_EN_TXSO_EN 0x00010000 /* R/W */ -#define INT_EN_RWT_EN 0x00008000 /* R/W */ -#define INT_EN_RXE_EN 0x00004000 /* R/W */ -#define INT_EN_TXE_EN 0x00002000 /* R/W */ -/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ -#define INT_EN_TDFU_EN 0x00000800 /* R/W */ -#define INT_EN_TDFO_EN 0x00000400 /* R/W */ -#define INT_EN_TDFA_EN 0x00000200 /* R/W */ -#define INT_EN_TSFF_EN 0x00000100 /* R/W */ -#define INT_EN_TSFL_EN 0x00000080 /* R/W */ -/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ -#define INT_EN_RDFO_EN 0x00000040 /* R/W */ -#define INT_EN_RDFL_EN 0x00000020 /* R/W */ -#define INT_EN_RSFF_EN 0x00000010 /* R/W */ -#define INT_EN_RSFL_EN 0x00000008 /* R/W */ -#define INT_EN_GPIO2_INT 0x00000004 /* R/W */ -#define INT_EN_GPIO1_INT 0x00000002 /* R/W */ -#define INT_EN_GPIO0_INT 0x00000001 /* R/W */ - -#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) -#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) -#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ -#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ -#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ -#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ - -#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) -#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ -#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ -#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ -#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ -#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ -#define RX_CFG_RX_DUMP 0x00008000 /* R/W */ -#define RX_CFG_RXDOFF 0x00001F00 /* R/W */ -/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ - -#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) -/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ -/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ -#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ -#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ -#define TX_CFG_TXSAO 0x00000004 /* R/W */ -#define TX_CFG_TX_ON 0x00000002 /* R/W */ -#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ - -#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) -#define HW_CFG_TTM 0x00200000 /* R/W */ -#define HW_CFG_SF 0x00100000 /* R/W */ -#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ -#define HW_CFG_TR 0x00003000 /* R/W */ -#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ -#define HW_CFG_SMI_SEL 0x00000010 /* R/W */ -#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ -#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ -#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ -#define HW_CFG_SRST_TO 0x00000002 /* RO */ -#define HW_CFG_SRST 0x00000001 /* Self Clearing */ - -#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) -#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ -#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ - -#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) -#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ -#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ - -#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) -#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ -#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ - -#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) -#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ -#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ -#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ -#define PMT_CTRL_ED_EN 0x00000100 /* R/W */ -#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ -#define PMT_CTRL_WUPS 0x00000030 /* R/WC */ -#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ -#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ -#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ -#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ -#define PMT_CTRL_PME_IND 0x00000008 /* R/W */ -#define PMT_CTRL_PME_POL 0x00000004 /* R/W */ -#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ -#define PMT_CTRL_READY 0x00000001 /* RO */ - -#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) -#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ -#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ -#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ -#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ -#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ -#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ -#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ -#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ -#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ -#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ -#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ -#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ -#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ -#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ -#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ -#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ -#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ -#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ - -#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) -#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ -#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ - -#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) -#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ - -#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) -#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) -#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) -#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) -#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ -#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ -#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ - -#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) -#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) -#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ -#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ -#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ -#define AFC_CFG_FCMULT 0x00000008 /* R/W */ -#define AFC_CFG_FCBRD 0x00000004 /* R/W */ -#define AFC_CFG_FCADD 0x00000002 /* R/W */ -#define AFC_CFG_FCANY 0x00000001 /* R/W */ - -#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) -#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ -#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ -#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ -#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ -#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ -#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ -#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ -#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ -#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ -#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ -#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ -#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ -#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ - -#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) -#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ -/* end of LAN register offsets and bit definitions */ - -/* MAC Control and Status registers */ -#define MAC_CR 0x01 /* R/W */ - -/* MAC_CR - MAC Control Register */ -#define MAC_CR_RXALL 0x80000000 -/* TODO: delete this bit? It is not described in the data sheet. */ -#define MAC_CR_HBDIS 0x10000000 -#define MAC_CR_RCVOWN 0x00800000 -#define MAC_CR_LOOPBK 0x00200000 -#define MAC_CR_FDPX 0x00100000 -#define MAC_CR_MCPAS 0x00080000 -#define MAC_CR_PRMS 0x00040000 -#define MAC_CR_INVFILT 0x00020000 -#define MAC_CR_PASSBAD 0x00010000 -#define MAC_CR_HFILT 0x00008000 -#define MAC_CR_HPFILT 0x00002000 -#define MAC_CR_LCOLL 0x00001000 -#define MAC_CR_BCAST 0x00000800 -#define MAC_CR_DISRTY 0x00000400 -#define MAC_CR_PADSTR 0x00000100 -#define MAC_CR_BOLMT_MASK 0x000000C0 -#define MAC_CR_DFCHK 0x00000020 -#define MAC_CR_TXEN 0x00000008 -#define MAC_CR_RXEN 0x00000004 - -#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ -#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ -#define HASHH 0x04 /* R/W */ -#define HASHL 0x05 /* R/W */ - -#define MII_ACC 0x06 /* R/W */ -#define MII_ACC_PHY_ADDR 0x0000F800 -#define MII_ACC_MIIRINDA 0x000007C0 -#define MII_ACC_MII_WRITE 0x00000002 -#define MII_ACC_MII_BUSY 0x00000001 - -#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ - -#define FLOW 0x08 /* R/W */ -#define FLOW_FCPT 0xFFFF0000 -#define FLOW_FCPASS 0x00000004 -#define FLOW_FCEN 0x00000002 -#define FLOW_FCBSY 0x00000001 - -#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ -#define VLAN1_VTI1 0x0000ffff - -#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ -#define VLAN2_VTI2 0x0000ffff - -#define WUFF 0x0B /* WO */ - -#define WUCSR 0x0C /* R/W */ -#define WUCSR_GUE 0x00000200 -#define WUCSR_WUFR 0x00000040 -#define WUCSR_MPR 0x00000020 -#define WUCSR_WAKE_EN 0x00000004 -#define WUCSR_MPEN 0x00000002 - -/* Chip ID values */ -#define CHIP_9115 0x115 -#define CHIP_9116 0x116 -#define CHIP_9117 0x117 -#define CHIP_9118 0x118 -#define CHIP_9215 0x115a -#define CHIP_9216 0x116a -#define CHIP_9217 0x117a -#define CHIP_9218 0x118a - -struct chip_id { - u16 id; - char *name; -}; - -static const struct chip_id chip_ids[] = { - { CHIP_9115, "LAN9115" }, - { CHIP_9116, "LAN9116" }, - { CHIP_9117, "LAN9117" }, - { CHIP_9118, "LAN9118" }, - { CHIP_9215, "LAN9215" }, - { CHIP_9216, "LAN9216" }, - { CHIP_9217, "LAN9217" }, - { CHIP_9218, "LAN9218" }, - { 0, NULL }, -}; - -#define DRIVERNAME "smc911x" - -u32 smc911x_get_mac_csr(u8 reg) -{ - while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); - while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - - return reg_read(MAC_CSR_DATA); -} - -void smc911x_set_mac_csr(u8 reg, u32 data) -{ - while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; - reg_write(MAC_CSR_DATA, data); - reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); - while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) - ; -} - static int smx911x_handle_mac_address(bd_t *bd) { unsigned long addrh, addrl; @@ -536,48 +146,6 @@ err_out: printf(DRIVERNAME ": autonegotiation timed out\n"); } -static void smc911x_reset(void) -{ - int timeout; - - /* Take out of PM setting first */ - if (reg_read(PMT_CTRL) & PMT_CTRL_READY) { - /* Write to the bytetest will take out of powerdown */ - reg_write(BYTE_TEST, 0x0); - - timeout = 10; - - while (timeout-- && !(reg_read(PMT_CTRL) & PMT_CTRL_READY)) - udelay(10); - if (!timeout) { - printf(DRIVERNAME - ": timeout waiting for PM restore\n"); - return; - } - } - - /* Disable interrupts */ - reg_write(INT_EN, 0); - - reg_write(HW_CFG, HW_CFG_SRST); - - timeout = 1000; - while (timeout-- && reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) - udelay(10); - - if (!timeout) { - printf(DRIVERNAME ": reset timeout\n"); - return; - } - - /* Reset the FIFO level and flow control settings */ - smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); - reg_write(AFC_CFG, 0x0050287F); - - /* Set to LED outputs */ - reg_write(GPIO_CFG, 0x70070000); -} - static void smc911x_enable(void) { /* Enable TX */ @@ -596,26 +164,10 @@ static void smc911x_enable(void) int eth_init(bd_t *bd) { - unsigned long val, i; - printf(DRIVERNAME ": initializing\n"); - val = reg_read(BYTE_TEST); - if (val != 0x87654321) { - printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + if (!smc911x_detect_chip()) goto err_out; - } - - val = reg_read(ID_REV) >> 16; - for (i = 0; chip_ids[i].id != 0; i++) { - if (chip_ids[i].id == val) break; - } - if (!chip_ids[i].id) { - printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); - goto err_out; - } - - printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); smc911x_reset(); diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h new file mode 100644 index 0000000..24cbaaa --- /dev/null +++ b/drivers/net/smc911x.h @@ -0,0 +1,486 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SMC911X_H_ +#define _SMC911X_H_ + +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ + defined (CONFIG_DRIVER_SMC911X_16_BIT) +#error "SMC911X: Only one of CONFIG_DRIVER_SMC911X_32_BIT and \ + CONFIG_DRIVER_SMC911X_16_BIT shall be set" +#endif + +#if defined (CONFIG_DRIVER_SMC911X_32_BIT) +static inline u32 reg_read(u32 addr) +{ + return *(volatile u32*)addr; +} +static inline void reg_write(u32 addr, u32 val) +{ + *(volatile u32*)addr = val; +} +#elif defined (CONFIG_DRIVER_SMC911X_16_BIT) +static inline u32 reg_read(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16)); +} +static inline void reg_write(u32 addr, u32 val) +{ + *(volatile u16*)addr = (u16)val; + *(volatile u16*)(addr + 2) = (u16)(val >> 16); +} +#else +#error "SMC911X: undefined bus width" +#endif /* CONFIG_DRIVER_SMC911X_16_BIT */ + +/* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +#define RX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x00) + +#define TX_DATA_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x20) +#define TX_CMD_A_INT_ON_COMP 0x80000000 +#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000 +#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000 +#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000 +#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000 +#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000 +#define TX_CMD_A_INT_FIRST_SEG 0x00002000 +#define TX_CMD_A_INT_LAST_SEG 0x00001000 +#define TX_CMD_A_BUF_SIZE 0x000007FF +#define TX_CMD_B_PKT_TAG 0xFFFF0000 +#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000 +#define TX_CMD_B_DISABLE_PADDING 0x00001000 +#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF + +#define RX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x40) +#define RX_STS_PKT_LEN 0x3FFF0000 +#define RX_STS_ES 0x00008000 +#define RX_STS_BCST 0x00002000 +#define RX_STS_LEN_ERR 0x00001000 +#define RX_STS_RUNT_ERR 0x00000800 +#define RX_STS_MCAST 0x00000400 +#define RX_STS_TOO_LONG 0x00000080 +#define RX_STS_COLL 0x00000040 +#define RX_STS_ETH_TYPE 0x00000020 +#define RX_STS_WDOG_TMT 0x00000010 +#define RX_STS_MII_ERR 0x00000008 +#define RX_STS_DRIBBLING 0x00000004 +#define RX_STS_CRC_ERR 0x00000002 +#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) +#define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) +#define TX_STS_TAG 0xFFFF0000 +#define TX_STS_ES 0x00008000 +#define TX_STS_LOC 0x00000800 +#define TX_STS_NO_CARR 0x00000400 +#define TX_STS_LATE_COLL 0x00000200 +#define TX_STS_MANY_COLL 0x00000100 +#define TX_STS_COLL_CNT 0x00000078 +#define TX_STS_MANY_DEFER 0x00000004 +#define TX_STS_UNDERRUN 0x00000002 +#define TX_STS_DEFERRED 0x00000001 +#define TX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x4C) +#define ID_REV (CONFIG_DRIVER_SMC911X_BASE + 0x50) +#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */ +#define ID_REV_REV_ID 0x0000FFFF /* RO */ + +#define INT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x54) +#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */ +#define INT_CFG_INT_DEAS_CLR 0x00004000 +#define INT_CFG_INT_DEAS_STS 0x00002000 +#define INT_CFG_IRQ_INT 0x00001000 /* RO */ +#define INT_CFG_IRQ_EN 0x00000100 /* R/W */ +#define INT_CFG_IRQ_POL 0x00000010 /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_TYPE 0x00000001 /* R/W Not Affected by SW Reset */ + +#define INT_STS (CONFIG_DRIVER_SMC911X_BASE + 0x58) +#define INT_STS_SW_INT 0x80000000 /* R/WC */ +#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */ +#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */ +#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */ +#define INT_STS_RXDF_INT 0x00400000 /* R/WC */ +#define INT_STS_TX_IOC 0x00200000 /* R/WC */ +#define INT_STS_RXD_INT 0x00100000 /* R/WC */ +#define INT_STS_GPT_INT 0x00080000 /* R/WC */ +#define INT_STS_PHY_INT 0x00040000 /* RO */ +#define INT_STS_PME_INT 0x00020000 /* R/WC */ +#define INT_STS_TXSO 0x00010000 /* R/WC */ +#define INT_STS_RWT 0x00008000 /* R/WC */ +#define INT_STS_RXE 0x00004000 /* R/WC */ +#define INT_STS_TXE 0x00002000 /* R/WC */ +/*#define INT_STS_ERX 0x00001000*/ /* R/WC */ +#define INT_STS_TDFU 0x00000800 /* R/WC */ +#define INT_STS_TDFO 0x00000400 /* R/WC */ +#define INT_STS_TDFA 0x00000200 /* R/WC */ +#define INT_STS_TSFF 0x00000100 /* R/WC */ +#define INT_STS_TSFL 0x00000080 /* R/WC */ +/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */ +#define INT_STS_RDFO 0x00000040 /* R/WC */ +#define INT_STS_RDFL 0x00000020 /* R/WC */ +#define INT_STS_RSFF 0x00000010 /* R/WC */ +#define INT_STS_RSFL 0x00000008 /* R/WC */ +#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */ +#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */ +#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */ +#define INT_EN (CONFIG_DRIVER_SMC911X_BASE + 0x5C) +#define INT_EN_SW_INT_EN 0x80000000 /* R/W */ +#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */ +#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */ +#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */ +/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */ +#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */ +#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */ +#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */ +#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */ +#define INT_EN_PME_INT_EN 0x00020000 /* R/W */ +#define INT_EN_TXSO_EN 0x00010000 /* R/W */ +#define INT_EN_RWT_EN 0x00008000 /* R/W */ +#define INT_EN_RXE_EN 0x00004000 /* R/W */ +#define INT_EN_TXE_EN 0x00002000 /* R/W */ +/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */ +#define INT_EN_TDFU_EN 0x00000800 /* R/W */ +#define INT_EN_TDFO_EN 0x00000400 /* R/W */ +#define INT_EN_TDFA_EN 0x00000200 /* R/W */ +#define INT_EN_TSFF_EN 0x00000100 /* R/W */ +#define INT_EN_TSFL_EN 0x00000080 /* R/W */ +/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */ +#define INT_EN_RDFO_EN 0x00000040 /* R/W */ +#define INT_EN_RDFL_EN 0x00000020 /* R/W */ +#define INT_EN_RSFF_EN 0x00000010 /* R/W */ +#define INT_EN_RSFL_EN 0x00000008 /* R/W */ +#define INT_EN_GPIO2_INT 0x00000004 /* R/W */ +#define INT_EN_GPIO1_INT 0x00000002 /* R/W */ +#define INT_EN_GPIO0_INT 0x00000001 /* R/W */ + +#define BYTE_TEST (CONFIG_DRIVER_SMC911X_BASE + 0x64) +#define FIFO_INT (CONFIG_DRIVER_SMC911X_BASE + 0x68) +#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */ +#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */ +#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */ +#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */ + +#define RX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x6C) +#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */ +#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */ +#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */ +#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */ +#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */ +#define RX_CFG_RX_DUMP 0x00008000 /* R/W */ +#define RX_CFG_RXDOFF 0x00001F00 /* R/W */ +/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */ + +#define TX_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x70) +/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */ +/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/ /* R/W Self Clearing */ +#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */ +#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */ +#define TX_CFG_TXSAO 0x00000004 /* R/W */ +#define TX_CFG_TX_ON 0x00000002 /* R/W */ +#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */ + +#define HW_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x74) +#define HW_CFG_TTM 0x00200000 /* R/W */ +#define HW_CFG_SF 0x00100000 /* R/W */ +#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ +#define HW_CFG_TR 0x00003000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ +#define HW_CFG_SMI_SEL 0x00000010 /* R/W */ +#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ +#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ +#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */ +#define HW_CFG_SRST_TO 0x00000002 /* RO */ +#define HW_CFG_SRST 0x00000001 /* Self Clearing */ + +#define RX_DP_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x78) +#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */ +#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */ + +#define RX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x7C) +#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */ +#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */ + +#define TX_FIFO_INF (CONFIG_DRIVER_SMC911X_BASE + 0x80) +#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */ +#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */ + +#define PMT_CTRL (CONFIG_DRIVER_SMC911X_BASE + 0x84) +#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */ +#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */ +#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */ +#define PMT_CTRL_ED_EN 0x00000100 /* R/W */ +#define PMT_CTRL_PME_TYPE 0x00000040 /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_WUPS 0x00000030 /* R/WC */ +#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */ +#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */ +#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */ +#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */ +#define PMT_CTRL_PME_IND 0x00000008 /* R/W */ +#define PMT_CTRL_PME_POL 0x00000004 /* R/W */ +#define PMT_CTRL_PME_EN 0x00000002 /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_READY 0x00000001 /* RO */ + +#define GPIO_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x88) +#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */ +#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */ +#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */ +#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */ +#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */ +#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */ +#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */ +#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */ +#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */ +#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */ +#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */ +#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */ +#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */ +#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */ +#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */ +#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */ +#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */ +#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */ + +#define GPT_CFG (CONFIG_DRIVER_SMC911X_BASE + 0x8C) +#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */ +#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */ + +#define GPT_CNT (CONFIG_DRIVER_SMC911X_BASE + 0x90) +#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */ + +#define ENDIAN (CONFIG_DRIVER_SMC911X_BASE + 0x98) +#define FREE_RUN (CONFIG_DRIVER_SMC911X_BASE + 0x9C) +#define RX_DROP (CONFIG_DRIVER_SMC911X_BASE + 0xA0) +#define MAC_CSR_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */ +#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */ +#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */ + +#define MAC_CSR_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xA8) +#define AFC_CFG (CONFIG_DRIVER_SMC911X_BASE + 0xAC) +#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */ +#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */ +#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */ +#define AFC_CFG_FCMULT 0x00000008 /* R/W */ +#define AFC_CFG_FCBRD 0x00000004 /* R/W */ +#define AFC_CFG_FCADD 0x00000002 /* R/W */ +#define AFC_CFG_FCANY 0x00000001 /* R/W */ + +#define E2P_CMD (CONFIG_DRIVER_SMC911X_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */ +#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */ +#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */ +#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */ +#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */ + +#define E2P_DATA (CONFIG_DRIVER_SMC911X_BASE + 0xB4) +#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */ +/* end of LAN register offsets and bit definitions */ + +/* MAC Control and Status registers */ +#define MAC_CR 0x01 /* R/W */ + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL 0x80000000 +/* TODO: delete this bit? It is not described in the data sheet. */ +#define MAC_CR_HBDIS 0x10000000 +#define MAC_CR_RCVOWN 0x00800000 +#define MAC_CR_LOOPBK 0x00200000 +#define MAC_CR_FDPX 0x00100000 +#define MAC_CR_MCPAS 0x00080000 +#define MAC_CR_PRMS 0x00040000 +#define MAC_CR_INVFILT 0x00020000 +#define MAC_CR_PASSBAD 0x00010000 +#define MAC_CR_HFILT 0x00008000 +#define MAC_CR_HPFILT 0x00002000 +#define MAC_CR_LCOLL 0x00001000 +#define MAC_CR_BCAST 0x00000800 +#define MAC_CR_DISRTY 0x00000400 +#define MAC_CR_PADSTR 0x00000100 +#define MAC_CR_BOLMT_MASK 0x000000C0 +#define MAC_CR_DFCHK 0x00000020 +#define MAC_CR_TXEN 0x00000008 +#define MAC_CR_RXEN 0x00000004 + +#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */ +#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */ +#define HASHH 0x04 /* R/W */ +#define HASHL 0x05 /* R/W */ + +#define MII_ACC 0x06 /* R/W */ +#define MII_ACC_PHY_ADDR 0x0000F800 +#define MII_ACC_MIIRINDA 0x000007C0 +#define MII_ACC_MII_WRITE 0x00000002 +#define MII_ACC_MII_BUSY 0x00000001 + +#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */ + +#define FLOW 0x08 /* R/W */ +#define FLOW_FCPT 0xFFFF0000 +#define FLOW_FCPASS 0x00000004 +#define FLOW_FCEN 0x00000002 +#define FLOW_FCBSY 0x00000001 + +#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */ +#define VLAN1_VTI1 0x0000ffff + +#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */ +#define VLAN2_VTI2 0x0000ffff + +#define WUFF 0x0B /* WO */ + +#define WUCSR 0x0C /* R/W */ +#define WUCSR_GUE 0x00000200 +#define WUCSR_WUFR 0x00000040 +#define WUCSR_MPR 0x00000020 +#define WUCSR_WAKE_EN 0x00000004 +#define WUCSR_MPEN 0x00000002 + +/* Chip ID values */ +#define CHIP_9115 0x115 +#define CHIP_9116 0x116 +#define CHIP_9117 0x117 +#define CHIP_9118 0x118 +#define CHIP_9215 0x115a +#define CHIP_9216 0x116a +#define CHIP_9217 0x117a +#define CHIP_9218 0x118a + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { 0, NULL }, +}; + +#define DRIVERNAME "smc911x" + +static u32 smc911x_get_mac_csr(u8 reg) +{ + while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg); + while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + + return reg_read(MAC_CSR_DATA); +} + +static void smc911x_set_mac_csr(u8 reg, u32 data) +{ + while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; + reg_write(MAC_CSR_DATA, data); + reg_write(MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg); + while (reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) + ; +} + +static bool smc911x_detect_chip(void) +{ + unsigned long val, i; + + val = reg_read(BYTE_TEST); + if (val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val); + return false; + } + + val = reg_read(ID_REV) >> 16; + for (i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04lx\n", val); + return false; + } + + printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + + return true; +} + +static void smc911x_reset(void) +{ + int timeout; + + /* Take out of PM setting first */ + if (reg_read(PMT_CTRL) & PMT_CTRL_READY) { + /* Write to the bytetest will take out of powerdown */ + reg_write(BYTE_TEST, 0x0); + + timeout = 10; + + while (timeout-- && !(reg_read(PMT_CTRL) & PMT_CTRL_READY)) + udelay(10); + if (!timeout) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + reg_write(INT_EN, 0); + + reg_write(HW_CFG, HW_CFG_SRST); + + timeout = 1000; + while (timeout-- && reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) + udelay(10); + + if (!timeout) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); + reg_write(AFC_CFG, 0x0050287F); + + /* Set to LED outputs */ + reg_write(GPIO_CFG, 0x70070000); +} + +#endif diff --git a/examples/.gitignore b/examples/.gitignore index 806425f..0d1864c 100644 --- a/examples/.gitignore +++ b/examples/.gitignore @@ -6,5 +6,6 @@ /timer /sched /smc91111_eeprom +/smc911x_eeprom *.bin *.srec diff --git a/examples/Makefile b/examples/Makefile index b0a8853..962ca8a 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -101,9 +101,10 @@ BIN += sched.bin endif ifeq ($(ARCH),blackfin) -ELF += smc91111_eeprom -SREC += smc91111_eeprom.srec -BIN += smc91111_eeprom.bin +BFIN_BIN = smc91111_eeprom smc911x_eeprom +ELF += $(BFIN_BIN) +SREC += $(addsuffix .srec,$(BFIN_BIN)) +BIN += $(addsuffix .bin,$(BFIN_BIN)) endif # The following example is pretty 8xx specific... diff --git a/examples/smc911x_eeprom.c b/examples/smc911x_eeprom.c new file mode 100644 index 0000000..3dac4d3 --- /dev/null +++ b/examples/smc911x_eeprom.c @@ -0,0 +1,381 @@ +/* + * smc911x_eeprom.c - EEPROM interface to SMC911x parts. + * Only tested on SMSC9118 though ... + * + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + * + * Based on smc91111_eeprom.c which: + * Heavily borrowed from the following peoples GPL'ed software: + * - Wolfgang Denk, DENX Software Engineering, wd(a)denx.de + * Das U-boot + * - Ladislav Michl ladis(a)linux-mips.org + * A rejected patch on the U-Boot mailing list + */ + +#include <common.h> +#include <exports.h> + +#ifdef CONFIG_DRIVER_SMC911X + +#include "../drivers/net/smc911x.h" + +/** + * smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?) + */ +static int smsc_ctrlc(void) +{ + return (tstc() && getc() == 0x03); +} + +/** + * usage - dump usage information + */ +static void usage(void) +{ + puts( + "MAC/EEPROM Commands:\n" + " P : Print the MAC addresses\n" + " D : Dump the EEPROM contents\n" + " M : Dump the MAC contents\n" + " C : Copy the MAC address from the EEPROM to the MAC\n" + " W : Write a register in the EEPROM or in the MAC\n" + " Q : Quit\n" + "\n" + "Some commands take arguments:\n" + " W <E|M> <register> <value>\n" + " E: EEPROM M: MAC\n" + ); +} + +/** + * dump_regs - dump the MAC registers + * + * Registers 0x00 - 0x50 are FIFOs. The 0x50+ are the control registers + * and they're all 32bits long. 0xB8+ are reserved, so don't bother. + */ +static void dump_regs(void) +{ + u8 i, j = 0; + for (i = 0x50; i < 0xB8; i += sizeof(u32)) + printf("%02x: 0x%08x %c", i, reg_read(CONFIG_DRIVER_SMC911X_BASE + i), + (j++ % 2 ? '\n' : ' ')); +} + +/** + * do_eeprom_cmd - handle eeprom communication + */ +static int do_eeprom_cmd(int cmd, u8 reg) +{ + if (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) { + printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n", + reg_read(E2P_CMD)); + return -1; + } + + reg_write(E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg); + + while (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) + if (smsc_ctrlc()) { + printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n", + reg_read(E2P_CMD)); + return -1; + } + + return 0; +} + +/** + * read_eeprom_reg - read specified register in EEPROM + */ +static u8 read_eeprom_reg(u8 reg) +{ + int ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_READ, reg); + return (ret ? : reg_read(E2P_DATA)); +} + +/** + * write_eeprom_reg - write specified value into specified register in EEPROM + */ +static int write_eeprom_reg(u8 value, u8 reg) +{ + int ret; + + /* enable erasing/writing */ + ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWEN, reg); + if (ret) + goto done; + + /* erase the eeprom reg */ + ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_ERASE, reg); + if (ret) + goto done; + + /* write the eeprom reg */ + reg_write(E2P_DATA, value); + ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_WRITE, reg); + if (ret) + goto done; + + /* disable erasing/writing */ + ret = do_eeprom_cmd(E2P_CMD_EPC_CMD_EWDS, reg); + + done: + return ret; +} + +/** + * skip_space - find first non-whitespace in given pointer + */ +static char *skip_space(char *buf) +{ + while (buf[0] == ' ' || buf[0] == '\t') + ++buf; + return buf; +} + +/** + * write_stuff - handle writing of MAC registers / eeprom + */ +static void write_stuff(char *line) +{ + char dest; + char *endp; + u8 reg; + u32 value; + + /* Skip over the "W " part of the command */ + line = skip_space(line + 1); + + /* Figure out destination */ + switch (line[0]) { + case 'E': + case 'M': + dest = line[0]; + break; + default: + invalid_usage: + printf("ERROR: Invalid write usage\n"); + usage(); + return; + } + + /* Get the register to write */ + line = skip_space(line + 1); + reg = simple_strtoul(line, &endp, 16); + if (line == endp) + goto invalid_usage; + + /* Get the value to write */ + line = skip_space(endp); + value = simple_strtoul(line, &endp, 16); + if (line == endp) + goto invalid_usage; + + /* Check for trailing cruft */ + line = skip_space(endp); + if (line[0]) + goto invalid_usage; + + /* Finally, execute the command */ + if (dest == 'E') { + printf("Writing EEPROM register %02x with %02x\n", reg, value); + write_eeprom_reg(value, reg); + } else { + printf("Writing MAC register %02x with %08x\n", reg, value); + reg_write(CONFIG_DRIVER_SMC911X_BASE + reg, value); + } +} + +/** + * copy_from_eeprom - copy MAC address in eeprom to address registers + */ +static void copy_from_eeprom(void) +{ + ulong addrl = + read_eeprom_reg(0x01) | + read_eeprom_reg(0x02) << 8 | + read_eeprom_reg(0x03) << 16 | + read_eeprom_reg(0x04) << 24; + ulong addrh = + read_eeprom_reg(0x05) | + read_eeprom_reg(0x06) << 8; + smc911x_set_mac_csr(ADDRL, addrl); + smc911x_set_mac_csr(ADDRH, addrh); + puts("EEPROM contents copied to MAC\n"); +} + +/** + * print_macaddr - print MAC address registers and MAC address in eeprom + */ +static void print_macaddr(void) +{ + puts("Current MAC Address in MAC: "); + ulong addrl = smc911x_get_mac_csr(ADDRL); + ulong addrh = smc911x_get_mac_csr(ADDRH); + printf("%02x:%02x:%02x:%02x:%02x:%02x\n", + (u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16), + (u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8)); + + puts("Current MAC Address in EEPROM: "); + int i; + for (i = 1; i < 6; ++i) + printf("%02x:", read_eeprom_reg(i)); + printf("%02x\n", read_eeprom_reg(i)); +} + +/** + * dump_eeprom - dump the whole content of the EEPROM + */ +static void dump_eeprom(void) +{ + int i; + puts("EEPROM:\n"); + for (i = 0; i < 7; ++i) + printf("%02x: 0x%02x\n", i, read_eeprom_reg(i)); +} + +/** + * smc911x_init - get the MAC/EEPROM up and ready for use + */ +static int smc911x_init(void) +{ + /* See if there is anything there */ + if (!smc911x_detect_chip()) + return 1; + + smc911x_reset(); + + /* Make sure we set EEDIO/EECLK to the EEPROM */ + if (reg_read(GPIO_CFG) & GPIO_CFG_EEPR_EN) { + while (reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY) + if (smsc_ctrlc()) { + printf("init: timeout (E2P_CMD = 0x%08x)\n", reg_read(E2P_CMD)); + return 1; + } + reg_write(GPIO_CFG, reg_read(GPIO_CFG) & ~GPIO_CFG_EEPR_EN); + } + + return 0; +} + +/** + * getline - consume a line of input and handle some escape sequences + */ +static char *getline(void) +{ + static char buffer[100]; + char c; + size_t i; + + i = 0; + while (1) { + buffer[i] = '\0'; + while (!tstc()) + continue; + + c = getc(); + /* Convert to uppercase */ + if (c >= 'a' && c <= 'z') + c -= ('a' - 'A'); + + switch (c) { + case '\r': /* Enter/Return key */ + case '\n': + puts("\n"); + return buffer; + + case 0x03: /* ^C - break */ + return NULL; + + case 0x5F: + case 0x08: /* ^H - backspace */ + case 0x7F: /* DEL - backspace */ + if (i) { + puts("\b \b"); + i--; + } + break; + + default: + /* Ignore control characters */ + if (c < 0x20) + break; + /* Queue up all other characters */ + buffer[i++] = c; + printf("%c", c); + break; + } + } +} + +/** + * smc911x_eeprom - our application's main() function + */ +int smc911x_eeprom(int argc, char *argv[]) +{ + /* Print the ABI version */ + app_startup(argv); + if (XF_VERSION != get_version()) { + printf("Expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %lu\n", get_version()); + printf("Can't run\n\n"); + return 1; + } + + /* Initialize the MAC/EEPROM somewhat */ + puts("\n"); + if (smc911x_init()) + return 1; + + /* Dump helpful usage information */ + puts("\n"); + usage(); + puts("\n"); + + while (1) { + char *line; + + /* Send the prompt and wait for a line */ + puts("eeprom> "); + line = getline(); + + /* Got a ctrl+c */ + if (!line) + return 0; + + /* Eat leading space */ + line = skip_space(line); + + /* Empty line, try again */ + if (!line[0]) + continue; + + /* Only accept 1 letter commands */ + if (line[0] && line[1] && line[1] != ' ' && line[1] != '\t') + goto unknown_cmd; + + /* Now parse the command */ + switch (line[0]) { + case 'W': write_stuff(line); break; + case 'D': dump_eeprom(); break; + case 'M': dump_regs(); break; + case 'C': copy_from_eeprom(); break; + case 'P': print_macaddr(); break; + unknown_cmd: + default: puts("ERROR: Unknown command!\n\n"); + case '?': + case 'H': usage(); break; + case 'Q': return 0; + } + } +} + +#else +int smc911x_eeprom(int argc, char *argv[]) +{ + puts("Not supported for this board\n"); + return 1; +} +#endif -- 1.6.0.4

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