November 2008 - U-Boot

[U-Boot] [PATCH/RFC] Some speed improvements to U-Boot JFFS2 code
by Ilya Yanok 11 Nov '08

11 Nov '08

Hello everybody, here is a set of changes we made to improve U-Boot JFFS2 code performance. We still can't reach Linux's performance but improvements are significant. Any comments are welcome. Regards, Ilya.

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[U-Boot] [PATCH 0/9] MPC8641 memory map changes/cleanup/36-bit
by Becky Bruce 11 Nov '08

11 Nov '08

board/freescale/mpc8641hpcn/config.mk | 2 +- board/freescale/mpc8641hpcn/law.c | 30 ++-- cpu/mpc86xx/cpu_init.c | 4 + cpu/mpc86xx/start.S | 90 +++++++----- include/configs/MPC8610HPCD.h | 9 + include/configs/MPC8641HPCN.h | 260 ++++++++++++++++++++++----------- include/configs/sbc8641d.h | 9 + 7 files changed, 267 insertions(+), 137 deletions(-) This is the remainer of the patches required to get 36-bit physical addressing working on 8641HPCN. This patch series consists of: - Various cleanup patches for 8641 - Getting rid of the nonexistent second flash bank - A new 32-bit memory map to make the layout more like 85xx - A new 36-bit memory map and the ability to enable CONFIG_PHYS_64BIT to turn on locating devices in high physical address space. Note: With these changes, an updated device tree is required to boot Linux; I will be pushing that to Linux shortly. Cheers, Becky

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[U-Boot] MAKEALL ml507_flash return "Not enough room for program headers" error
by Benny Chen 11 Nov '08

11 Nov '08

Hi there, I am trying to build a U-Boot image for the ML507 board running from FLASH and got the "Not enough room for program headers" error. The main difference for my setup is the toolchain. I am using the powerpc-eabi-ld linker from Xilinx's EDK tool chain to build the ml507_flash design for U-Boot. I have seen a patch on the linker script for the mpc8555cds board and tried adding the patch to the Xilinx/ppc440-generic/u-boot-rom.lds but got the "relocation truncated to fit R_PPC_REL24" error. Before going further with debugging this problem, I would like to check if this problem is due to the powerpc-eabi tool chain from Xilinx? Thanks for your help. Regards, Benny $ ./MAKEALL ml507_flash Configuring for ml507 board... powerpc-eabi-ld: u-boot: Not enough room for program headers (allocated 2, need 5) powerpc-eabi-ld: final link failed: Bad value make: *** [u-boot] Error 1 size: './u-boot': No such file

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[U-Boot] U-Boot bootstrap solution on the ML507 board.
by Benny Chen 11 Nov '08

11 Nov '08

Hi Guys, I have been chasing my tail on this one. But I just want to make sure others don't have to go through this process. Below is a solution that works for me. 1. When using the ml507_flash design you need to map your onboard NOR FLASH at 0xFE000000 to 0xFFFFFFFF. More precisely you need to have the end of your FLASH memory butting up against 0xFFFFFFFF. This is because the initial boot code needs to reside in the last 4K of memory from address 0xFFFFFFFC. 2. Because of point 1, you cannot have your EDK application program (E.g. bootloop or your custom bootloader program) running when U-Boot is installed and boot from FLASH. This is because the EDK application program also needs to install its boot.o boot code in the same address space. There are ways at which you can do this but you will need to do a bit of linking magic and break up your application into separate memory address range making sure they will work for both your application and u-boot. 3. Personally, I find the easiest way to have both your EDK application program and U-Boot cohabit on your embedded system is to: a) Have a BRAM block butting up to 0xffffffff b) Install your EDK application code in the BRAM c) Build a RAM based U-Boot image b) Install your U-Boot image in FLASH e) Use your EDK application to load the U-Boot image from FLASH to RAM f) Branch to it to boot strap your U-Boot kernel. There should be plenty of other alternatives to do this. Cheers, Benny

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Re: [U-Boot] [PATCH] mpc83xx: New board support SIMPC8313
by Ron Madrid 10 Nov '08

10 Nov '08

> > > > +Ron Madrid > > > > > > hmm..I'm not sure if this email address is acceptable. > > > > > > > What are acceptable email addresses if this one in fact is not? > > I would think ones that are more likely to be directly associated with > a human being that is familiar with u-boot, e.g.: > > Ron Madrid > While my familiarity with u-boot is still up for debate, what would happen should I no longer be employed by my current employer. I would not want to continue to be listed as a maintainer for a u-boot project that I am not associated with, or much less begin to receive email regarding the project. BTW, a work email address is not a possibility. Ron

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Re: [U-Boot] [PATCH] mpc83xx: New board support SIMPC8313
by Ron Madrid 10 Nov '08

10 Nov '08

Kim, Thank you for the feedback. I am in the process of implementing the appropriate changes, however I have a couple of questions/ concerns about your review. > > ...NAND...Configuring for SIMPC8313 board... > In file included from simpc8313.c:32: > /home/kim/git/u-boot/include/ns16550.h:108:2: error: #error "Please define > NS16550 registers size." I have this line in my board config file: #define CFG_NS16550_REG_SIZE 1 So I don't know where this error would come from as I did not see it when I performed my builds > > +Ron Madrid <info(a)sheldoninst.com> > > hmm..I'm not sure if this email address is acceptable. > What are acceptable email addresses if this one in fact is not?

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[U-Boot] [PATCH v2] ARM: OMAP: Convert IO macros
by dirk.behme＠googlemail.com 10 Nov '08

10 Nov '08

Convert IO macros to readx/writex. Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in v2: - Do only IO macro conversion, don't mix with coding style. v2 version of this patch previous patch v1 obsolete. Note: Patch is against U-Boot master commit 1378174a1351c0285736863a665ab758fe8d5f71 "Merge branch 'master' of /home/wd/git/u-boot/custodians" --- drivers/i2c/omap24xx_i2c.c | 131 +++++++++++++++++++++------------------------ 1 files changed, 64 insertions(+), 67 deletions(-) Index: u-boot-main/drivers/i2c/omap24xx_i2c.c =================================================================== --- u-boot-main.orig/drivers/i2c/omap24xx_i2c.c +++ u-boot-main/drivers/i2c/omap24xx_i2c.c @@ -25,9 +25,6 @@ #include <asm/arch/i2c.h> #include <asm/io.h> -#define inw(a) __raw_readw(a) -#define outw(a,v) __raw_writew(a,v) - static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); @@ -36,32 +33,32 @@ void i2c_init (int speed, int slaveadd) { u16 scl; - outw(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ udelay(1000); - outw(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, I2C_SYSC); /* will probably self clear but */ - if (inw (I2C_CON) & I2C_CON_EN) { - outw (0, I2C_CON); + if (readw (I2C_CON) & I2C_CON_EN) { + writew (0, I2C_CON); udelay (50000); } /* 12MHz I2C module clock */ - outw (0, I2C_PSC); + writew (0, I2C_PSC); speed = speed/1000; /* 100 or 400 */ scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - outw (scl, I2C_SCLL); - outw (scl, I2C_SCLH); + writew (scl, I2C_SCLL); + writew (scl, I2C_SCLH); /* own address */ - outw (slaveadd, I2C_OA); - outw (I2C_CON_EN, I2C_CON); + writew (slaveadd, I2C_OA); + writew (I2C_CON_EN, I2C_CON); /* have to enable intrrupts or OMAP i2c module doesn't work */ - outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); udelay (1000); flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + writew (0xFFFF, I2C_STAT); + writew (0, I2C_CNT); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -73,19 +70,19 @@ static int i2c_read_byte (u8 devaddr, u8 wait_for_bb (); /* one byte only */ - outw (1, I2C_CNT); + writew (1, I2C_CNT); /* set slave address */ - outw (devaddr, I2C_SA); + writew (devaddr, I2C_SA); /* no stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - *(volatile u8 *) (I2C_DATA) = regoffset; + writeb (regoffset, I2C_DATA); udelay (20000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -94,42 +91,42 @@ static int i2c_read_byte (u8 devaddr, u8 if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - outw (0, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + writew (0, I2C_CON); + while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - outw (0xFFFF, I2C_STAT); + writew (0xFFFF, I2C_STAT); } wait_for_bb (); /* set slave address */ - outw (devaddr, I2C_SA); + writew (devaddr, I2C_SA); /* read one byte from slave */ - outw (1, I2C_CNT); + writew (1, I2C_CNT); /* need stop bit here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { - *value = inw (I2C_DATA); + *value = readw (I2C_DATA); udelay (20000); } else { i2c_error = 1; } if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) - || (inw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, I2C_CON); + while (readw (I2C_STAT) + || (readw (I2C_CON) & I2C_CON_MST)) { udelay (10000); - outw (0xFFFF, I2C_STAT); + writew (0xFFFF, I2C_STAT); } } } flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + writew (0xFFFF, I2C_STAT); + writew (0, I2C_CNT); return i2c_error; } @@ -142,22 +139,22 @@ static int i2c_write_byte (u8 devaddr, u wait_for_bb (); /* two bytes */ - outw (2, I2C_CNT); + writew (2, I2C_CNT); /* set slave address */ - outw (devaddr, I2C_SA); + writew (devaddr, I2C_SA); /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* send out two bytes */ - outw ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, I2C_DATA); /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -167,18 +164,18 @@ static int i2c_write_byte (u8 devaddr, u if (!i2c_error) { int eout = 200; - outw (I2C_CON_EN, I2C_CON); - while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, I2C_CON); + while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - outw (0xFFFF, I2C_STAT); + writew (0xFFFF, I2C_STAT); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + writew (0xFFFF, I2C_STAT); + writew (0, I2C_CNT); return i2c_error; } @@ -189,10 +186,10 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = inw(I2C_STAT); + stat = readw(I2C_STAT); if(stat == I2C_STAT_RRDY){ - inw(I2C_DATA); - outw(I2C_STAT_RRDY,I2C_STAT); + readw(I2C_DATA); + writew(I2C_STAT_RRDY,I2C_STAT); udelay(1000); }else break; @@ -203,7 +200,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == inw (I2C_OA)) { + if (chip == readw (I2C_OA)) { return res; } @@ -211,27 +208,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - outw (1, I2C_CNT); + writew (1, I2C_CNT); /* set slave address */ - outw (chip, I2C_SA); + writew (chip, I2C_SA); /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); /* enough delay for the NACK bit set */ udelay (50000); - if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - outw(0xFFFF, I2C_STAT); + writew(0xFFFF, I2C_STAT); } else { - outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ - outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ + writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - outw(0xFFFF, I2C_STAT); + writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, I2C_STAT); return res; } @@ -290,17 +287,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - outw(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - outw (stat, I2C_STAT); + writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ + while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + writew (stat, I2C_STAT); udelay (50000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); + readw (I2C_STAT)); } - outw(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -310,7 +307,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = inw (I2C_STAT); + status = readw (I2C_STAT); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -318,8 +315,8 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); - outw(0xFFFF, I2C_STAT); + readw (I2C_STAT)); + writew(0xFFFF, I2C_STAT); } return status; }

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Re: [U-Boot] [PATCH-OMAP3] OMAP3: Remove BITx magic
by Dirk Behme 10 Nov '08

10 Nov '08

Dear Wolfgang, Wolfgang Denk wrote: > Dear dirk.behme(a)googlemail.com, > > In message <49172e4a.0b38560a.42bc.ffffb794(a)mx.google.com> you wrote: > >>Subject: [PATCH-OMAP3] OMAP3: Remove BITx magic >> >>From: Dirk Behme <dirk.behme(a)gmail.com> >> >>Remove bits.h and it's macros usage. Requested by Wolfgang Denk. >> >>Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> > > ... > >> /* device type */ >>-#define DEVICE_MASK (BIT8 | BIT9 | BIT10) >>+#define DEVICE_MASK (0x7 << 8) > > > That's a funny way to make code difficult to read. Why do you prefer > "(0x7 << 8)" instead of "0x700" (which looks more obvious to me) ? > > >>-#define DLL_NO_FILTER_MASK (BIT8 | BIT9) >>+#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) > > Ditto here - why not simply 0x300 ? For my taste the << style makes it easier to create macros from TRM and later to review code against TRM. Maybe 0x700 and 0x300 are easy cases, but for e.g 0x34B03C00 I need a sheet of paper or calculator to get an idea which bits are exactly set in register. And then later re-calculate twice to be sure I'm correct ;) Having a TRM, looking at a register description and then wanting to set Bits 29 & 28 & 26 & 23 & 21 & 20 & 13 & 12 & 11 & 10 using something like (1 << 29) | (1 << 28) | (1 << 26) | (1 << 23) | (1 << 21) | (1 << 20) | (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) makes it more obvious for me. Then using preprocessor/compiler to create 0x34B03C00 I'm on the safe side from my point of view. >>-#define GPT_EN ((0 << 2) | BIT1 | BIT0) >>+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) > > > Why not 0x3 ? > > Note: especially the "(0x0 << 2) | " part in the expression i really > bogus. Again, from TRM point of view, above style makes it clear that bit 2 is intentionally set to zero. Best regards Dirk

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Re: [U-Boot] [PATCH 11/13 v5] ARM: OMAP3: Add EVM board
by Dirk Behme 10 Nov '08

10 Nov '08

Dear Wolfgang, Wolfgang Denk wrote: > Dear Jean-Christophe PLAGNIOL-VILLARD, > > In message <20081109150321.GF25307(a)game.jcrosoft.org> you wrote: > >>>+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); >>>+#endif >>>+ >>>+#if defined(CONFIG_CMD_NET) >>>+ setup_net_chip(); >>>+#endif >>>+ >>>+ return 0; >>>+} >>>+ >>>+/****************************************************************************** >>>+ * Routine: set_muxconf_regs >>>+ * Description: Setting up the configuration Mux registers specific to the >>>+ * hardware. Many pins need to be moved from protect to primary >>>+ * mode. >>>+ *****************************************************************************/ >>>+void set_muxconf_regs(void) >>>+{ >>>+ MUX_EVM(); >>>+} >>>+ >>>+/****************************************************************************** >>>+ * Routine: setup_net_chip >>>+ * Description: Setting up the configuration GPMC registers specific to the >>>+ * Ethernet hardware. Pin Muxing for the SMC9118 is initialized >>>+ * here. >>>+ *****************************************************************************/ >>>+static int setup_net_chip(void) >>>+{ >> >>in this function please add some blank line to make the code more readable >> >>>+ int i = 0; >>>+ >>>+ /* Configure GPMC registers */ >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF; >>>+ (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c; >>>+ >>>+ /* Configure PIN MUX registers */ >>>+ /* Enable GPMC Pin Mux Registers */ >>>+ /* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000; >>>+ /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018; >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8; >>>+ /* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00; >>>+ /* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00; >>>+ /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000; >>>+ >>>+ /* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and >>>+ configuring the mux mode to 0 */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018; >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8; >>>+ /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018; >>>+ /* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018; >>>+ /* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018; >>>+ /* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018; >>>+ /* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018; >>>+ /* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */ >>>+ (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018; > > > And please use accessor functions / macros to access the registers. > Access through volatile pointers is considered a Bad Thing (TM). Sorry for not mentioning this earlier, but you don't have to comment on a) readx/writex accessor functions / macros b) hardcoded values vs. speaking macros These are known issues of OMAP3 patch set I will fix step by step. Once we send the "final" OMAP3 patch set to the mailing list, if I missed something, then you are welcome to comment on it, though ;) Thanks for your review and best regards Dirk

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[U-Boot] [PATCH 04/13 v5] ARM: OMAP3: Add lowlevel init and sys_info common files
by dirk.behme＠googlemail.com 10 Nov '08

10 Nov '08

Subject: [PATCH 04/13 v5] ARM: OMAP3: Add lowlevel init and sys_info common files From: Dirk Behme <dirk.behme(a)gmail.com> Add assembly lowlevel init and sys_info common files Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v3: - Add detection and support for 128MB/256MB RAM by Mans Rullgard Changes in version v2: - Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang. cpu/arm_cortexa8/omap3/Makefile | 46 ++++ cpu/arm_cortexa8/omap3/config.mk | 36 +++ cpu/arm_cortexa8/omap3/lowlevel_init.S | 359 +++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/omap3/sys_info.c | 334 ++++++++++++++++++++++++++++++ 4 files changed, 775 insertions(+) Index: u-boot-main/cpu/arm_cortexa8/omap3/Makefile =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS := lowlevel_init.o +COBJS := sys_info.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### Index: u-boot-main/cpu/arm_cortexa8/omap3/config.mk =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +# Make ARMv5 to allow more compilers to work, even though its v7a. +PLATFORM_CPPFLAGS += -march=armv5 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) Index: u-boot-main/cpu/arm_cortexa8/omap3/lowlevel_init.S =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -0,0 +1,359 @@ +/* + * Board specific setup info + * + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Initial Code by: + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks_omap3.h> + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3 - r10} /* copy from source address [r0] */ + stmia r1!, {r3 - r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* *************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this + * code runs from flash before SDR is init so that should be ok. + ****************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4 - r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4 - r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE, 0x07, 0x05, 0x01 +/* ES2 */ +.word 0x0FA, 0x05, 0x07, 0x01 +/* 3410 */ +.word 0x085, 0x05, 0x07, 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D, 0x0C, 0x03, 0x01 +/* ES2 */ +.word 0x1F4, 0x0C, 0x03, 0x01 +/* 3410 */ +.word 0x10A, 0x0C, 0x03, 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179, 0x12, 0x04, 0x01 +/* ES2 */ +.word 0x271, 0x17, 0x03, 0x01 +/* 3410 */ +.word 0x14C, 0x17, 0x03, 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D, 0x19, 0x03, 0x01 +/* ES2 */ +.word 0x0FA, 0x0C, 0x07, 0x01 +/* 3410 */ +.word 0x085, 0x0C, 0x07, 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA, 0x32, 0x03, 0x01 +/* ES2 */ +.word 0x271, 0x2F, 0x03, 0x01 +/* 3410 */ +.word 0x14C, 0x2F, 0x03, 0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D, 0x05, 0x07, 0x01 +/* ES2 */ +.word 0x0B4, 0x05, 0x07, 0x01 +/* 3410 */ +.word 0x085, 0x05, 0x07, 0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA, 0x0C, 0x03, 0x01 +/* ES2 */ +.word 0x168, 0x0C, 0x03, 0x01 +/* 3410 */ +.word 0x10A, 0x0C, 0x03, 0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082, 0x09, 0x07, 0x01 +/* ES2 */ +.word 0x0E1, 0x0B, 0x06, 0x01 +/* 3410 */ +.word 0x14C, 0x17, 0x03, 0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D, 0x0C, 0x07, 0x01 +/* ES2 */ +.word 0x0B4, 0x0C, 0x07, 0x01 +/* 3410 */ +.word 0x085, 0x0C, 0x07, 0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F, 0x30, 0x03, 0x01 +/* ES2 */ +.word 0x0E1, 0x17, 0x06, 0x01 +/* 3410 */ +.word 0x14C, 0x2F, 0x03, 0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1, M_12_ES1, FSL_12_ES1, M2_12_ES1 +/* ES2 */ +.word M_12, N_12, FSEL_12, M2_12 +/* 3410 */ +.word M_12, N_12, FSEL_12, M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1, N_13_ES1, FSL_13_ES1, M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1, N_19p2_ES1, FSL_19p2_ES1, M2_19p2_ES1 +/* ES2 */ +.word M_19p2, N_19p2, FSEL_19p2, M2_19p2 +/* 3410 */ +.word M_19p2, N_19p2, FSEL_19p2, M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1, N_26_ES1, FSL_26_ES1, M2_26_ES1 +/* ES2 */ +.word M_26, N_26, FSEL_26, M2_26 +/* 3410 */ +.word M_26, N_26, FSEL_26, M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1, N_38p4_ES1, FSL_38p4_ES1, M2_38p4_ES1 +/* ES2 */ +.word M_38p4, N_38p4, FSEL_38p4, M2_38p4 +/* 3410 */ +.word M_38p4, N_38p4, FSEL_38p4, M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8, 0x05, 0x07, 0x09 + +/* 13MHz */ +.word 0x1B0, 0x0C, 0x03, 0x09 + +/* 19.2MHz */ +.word 0xE1, 0x09, 0x07, 0x09 + +/* 26MHz */ +.word 0xD8, 0x0C, 0x07, 0x09 + +/* 38.4MHz */ +.word 0xE1, 0x13, 0x07, 0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr Index: u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c @@ -0,0 +1,334 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Manikandan Pillai <mani.pillai(a)ti.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> /* get mem tables */ +#include <asm/arch/sys_proto.h> +#include <i2c.h> + +extern omap3_sysinfo sysinfo; +static u32 *gpmc_base = (u32 *)GPMC_BASE; + +/************************************************************************** + * get_gpmc0_type() + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ +#if defined(CONFIG_ENV_IS_IN_ONENAND) + return 1; /* OneNAND */ +#else + return 2; /* NAND */ +#endif +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + /* fixme, need to get register defines for OMAP3 */ + return CPU_3430; +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 cpuid = 0; + /* On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate + * between ES2.0 and ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid)); + if ((cpuid & 0xf) == 0x0) + return CPU_3430_ES1; + else + return CPU_3430_ES2; + +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *) (SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return 1; + return 0; +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ +#if defined(CONFIG_OMAP3_BEAGLE) || defined(CONFIG_OVERO) + return DDR_STACKED; +#else + return DDR_DISCRETE; +#endif +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return size; +} + +/*********************************************************************** + * get_sdr_cs_offset() - get offset of cs from cs0 start + ************************************************************************/ +u32 get_sdr_cs_offset(u32 cs) +{ + u32 offset; + + if (!cs) + return 0; + + offset = readl(SDRC_CS_CFG); + offset = (offset & 15) << 27 | (offset & 0x30) >> 17; + + return offset; +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + ************************************************************************/ +u32 get_board_type(void) +{ + if (get_cpu_rev() == CPU_3430_ES2) + return sysinfo.board_type_v2; + else + return sysinfo.board_type_v1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return 0x0000003F & readl(CONTROL_STATUS); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = readl(gpmc_base + OFFS(GPMC_CONFIG7)); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return b; +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return WIDTH_16BIT; +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + return 0x20; +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONENAND", + "NAND", + "P2a", + "NOR", + "NOR", + "P2a", + "P2b", + }; + u32 brev = get_board_rev(); + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "LPDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + char p_l3[] = "165"; + char p_cpu[] = "2"; + + char *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", sysinfo.cpu_string, + sec_s, rev, p_cpu, p_l3); + printf("%s + %s/%s\n", sysinfo.board_string, + mem_s, bootmode[get_gpmc0_type()]); + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return val; +} + +/******************************************************** + * is_running_in_flash() - tell if currently running in + * FLASH. + *******************************************************/ +u32 is_running_in_flash(void) +{ + if (get_base() < 4) + return 1; /* in FLASH */ + + return 0; /* running in SRAM or SDRAM */ +} + +/******************************************************** + * is_running_in_sram() - tell if currently running in + * SRAM. + *******************************************************/ +u32 is_running_in_sram(void) +{ + if (get_base() == 4) + return 1; /* in SRAM */ + + return 0; /* running in FLASH or SDRAM */ +} + +/******************************************************** + * is_running_in_sdram() - tell if currently running in + * SDRAM. + *******************************************************/ +u32 is_running_in_sdram(void) +{ + if (get_base() > 4) + return 1; /* in SDRAM */ + + return 0; /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + + mode = readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +}

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