January 2008 - U-Boot

[U-Boot-Users] resend #4: [PATCH 2/5]: add AcTux-1 board support
by Michael Schwingen 15 Jan '08

15 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/board/actux1/Makefile b/board/actux1/Makefile new file mode 100644 index 0000000..83611e7 --- /dev/null +++ b/board/actux1/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux1.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c new file mode 100644 index 0000000..e9acf02 --- /dev/null +++ b/board/actux1/actux1.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> +#include <asm/io.h> +#include <miiphy.h> + +#include "actux1_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + + /* Setup GPIO's for PCI INTA */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA); + + /* Setup GPIO's for 33MHz clock output */ + GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + /* CS5: Debug port */ + *IXP425_EXP_CS5 = 0x9d520003; + /* CS6: HwRel */ + *IXP425_EXP_CS6 = 0x81860001; + /* CS7: LEDs */ + *IXP425_EXP_CS7 = 0x80900003; + + udelay (533); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + + ACTUX1_LED1 (2); + ACTUX1_LED2 (2); + ACTUX1_LED3 (0); + ACTUX1_LED4 (0); + ACTUX1_LED5 (0); + ACTUX1_LED6 (0); + ACTUX1_LED7 (0); + + ACTUX1_HS (ACTUX1_HS_DCD); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard (void) +{ + char revision; + char *s = getenv ("serial#"); + + puts ("Board: AcTux-1 rev."); + putc (ACTUX1_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev (void) +{ + return ACTUX1_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) +extern struct pci_controller hose; +extern void pci_ixp_init (struct pci_controller *hose); + +void pci_init_board (void) +{ + extern void pci_ixp_init (struct pci_controller *hose); + pci_ixp_init (&hose); +} +#endif + +void reset_phy (void) +{ + u16 id1, id2; + + /* initialize the PHY */ + miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2); + + id2 &= 0xFFF0; /* mask out revision bits */ + + if (id1 == 0x13 && id2 == 0x78e0) { + /* + * LXT971/LXT972 PHY: set LED outputs: + * LED1(green) = Link/ACT, + * LED2 (unused) = LINK, + * LED3(red) = Coll + */ + miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); + } else if (id1 == 0x143 && id2 == 0xbc30) { + /* BCM5241: default values are OK */ + } else + printf ("unknown ethernet PHY ID: %x %x\n", id1, id2); +} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h new file mode 100644 index 0000000..bb3b7f9 --- /dev/null +++ b/board/actux1/actux1_hw.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX1_HW_H +#define _ACTUX1_HW_H + +/* 0 = LED off,1 = green, 2 = red, 3 = orange */ +#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) +#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) +#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) +#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) +#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) +#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) +#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) +#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) +#define ACTUX1_HS_DCD 0x01 +#define ACTUX1_HS_DSR 0x02 + +#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS +#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) + +/* GPIO settings */ +#define CFG_GPIO_PCI1_INTA 2 +#define CFG_GPIO_PCI2_INTA 3 +#define CFG_GPIO_I2C_SDA 4 +#define CFG_GPIO_I2C_SCL 5 +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 /* Out */ +#define CFG_GPIO_PCI_CLK 14 /* Out */ +#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ + +#endif diff --git a/board/actux1/config.mk b/board/actux1/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux1/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds new file mode 100644 index 0000000..0de78d3 --- /dev/null +++ b/board/actux1/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + cpu/ixp/start.o(.text) + lib_generic/string.o(.text) + lib_generic/vsprintf.o(.text) + lib_arm/board.o(.text) + common/dlmalloc.o(.text) + cpu/ixp/cpu.o(.text) + . = env_offset; + common/environment.o(.ppcenv) + * (.text) + } + + . = ALIGN (4); + .rodata : { + *(.rodata) + } + . = ALIGN (4); + .data : { + *(.data) + } + . = ALIGN (4); + .got : { + *(.got) + } + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + __bss_start =.; + .bss (NOLOAD): { + *(.bss) + } + _end =.; +} diff --git a/include/configs/actux1.h b/include/configs/actux1.h new file mode 100644 index 0000000..4c4b1d1 --- /dev/null +++ b/include/configs/actux1.h @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* 1: modified board with 32MB DRAM */ +#define CONFIG_ACTUX1_32MB 0 +/* 1: 2*2MB FLASH (standard) */ +#define CONFIG_ACTUX1_FLASH2X2 1 +/* 1: 1*8MB FLASH (upgraded boards) */ +#define CONFIG_ACTUX1_FLASH1X8 0 + +#define CONFIG_IXP425 1 +#define CONFIG_ACTUX1 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +/* max number of command args */ +#define CFG_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00800000 + +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* spec says 66.666 MHz, but it appears to be 33 */ +#define CFG_HZ 3333333 + +/* default load address */ +#define CFG_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Expansion bus settings */ +#define CFG_EXP_CS0 0xbd113842 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CFG_DRAM_BASE 0x00000000 + +#if CONFIG_ACTUX1_32MB +# define CFG_SDR_CONFIG 0x18 +# define PHYS_SDRAM_1_SIZE 0x02000000 +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x02000000 +#else /* 16MB SDRAM */ +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 +#endif + +/* FLASH organization */ +#if CONFIG_ACTUX1_FLASH2X2 +# define CFG_MAX_FLASH_BANKS 2 +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT 40 +# define PHYS_FLASH_1 0x50000000 +# define PHYS_FLASH_2 0x50200000 +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#endif +#if CONFIG_ACTUX1_FLASH1X8 +# define CFG_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT 140 +# define PHYS_FLASH_1 0x50000000 +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } +#endif + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +/* use separate flash sector with ucode images */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 +#define CONFIG_RESET_PHY_R 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 32 + +/* + * environment organization: + * one flash sector, embedded in uboot area (bottom bootblock flash) + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff;" \ + " protect off 50006000 5003ffff;" \ + " erase 50000000 50003fff;" \ + " erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000;" \ + " cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff;" \ + " erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +#endif /* __CONFIG_H */

1 0

[U-Boot-Users] resend #4: [PATCH 1/5]: add AcTux board support (common)
by Michael Schwingen 15 Jan '08

15 Jan '08

Hi, resend of the previous patch set with formatting fixed (hopefully). The patch adds 4 boards, called AcTux-1 .. AcTux-4. This patch contains the files that contain changes for multiple boards, the board-specific files follow as separate patches. cu Michael Signed-off-by: Michael Schwingen <michael(a)schwingen.org> (patch compressed due to size)

1 0

[U-Boot-Users] [PATCH] ColdFire: Add MCF5227x cpu and M52277EVB support-3
by Tsi-Chung Liew 15 Jan '08

15 Jan '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- include/asm-m68k/m5227x.h | 796 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 796 insertions(+), 0 deletions(-) create mode 100644 include/asm-m68k/m5227x.h diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h new file mode 100644 index 0000000..afd31ba --- /dev/null +++ b/include/asm-m68k/m5227x.h @@ -0,0 +1,796 @@ +/* + * MCF5227x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MCF5227X__ +#define __MCF5227X__ + +/********************************************************************* +* Interrupt Controller (INTC) +*********************************************************************/ +#define INT0_LO_RSVD0 (0) +#define INT0_LO_EPORT1 (1) +#define INT0_LO_EPORT4 (4) +#define INT0_LO_EPORT7 (7) +#define INT0_LO_EDMA_00 (8) +#define INT0_LO_EDMA_01 (9) +#define INT0_LO_EDMA_02 (10) +#define INT0_LO_EDMA_03 (11) +#define INT0_LO_EDMA_04 (12) +#define INT0_LO_EDMA_05 (13) +#define INT0_LO_EDMA_06 (14) +#define INT0_LO_EDMA_07 (15) +#define INT0_LO_EDMA_08 (16) +#define INT0_LO_EDMA_09 (17) +#define INT0_LO_EDMA_10 (18) +#define INT0_LO_EDMA_11 (19) +#define INT0_LO_EDMA_12 (20) +#define INT0_LO_EDMA_13 (21) +#define INT0_LO_EDMA_14 (22) +#define INT0_LO_EDMA_15 (23) +#define INT0_LO_EDMA_ERR (24) +#define INT0_LO_SCM_CWIC (25) +#define INT0_LO_UART0 (26) +#define INT0_LO_UART1 (27) +#define INT0_LO_UART2 (28) +#define INT0_LO_I2C (30) +#define INT0_LO_DSPI (31) +#define INT0_HI_DTMR0 (32) +#define INT0_HI_DTMR1 (33) +#define INT0_HI_DTMR2 (34) +#define INT0_HI_DTMR3 (35) +#define INT0_HI_SCMIR (62) +#define INT0_HI_RTC_ISR (63) + +#define INT1_HI_CAN_BOFFINT (1) +#define INT1_HI_CAN_ERRINT (3) +#define INT1_HI_CAN_BUF0I (4) +#define INT1_HI_CAN_BUF1I (5) +#define INT1_HI_CAN_BUF2I (6) +#define INT1_HI_CAN_BUF3I (7) +#define INT1_HI_CAN_BUF4I (8) +#define INT1_HI_CAN_BUF5I (9) +#define INT1_HI_CAN_BUF6I (10) +#define INT1_HI_CAN_BUF7I (11) +#define INT1_HI_CAN_BUF8I (12) +#define INT1_HI_CAN_BUF9I (13) +#define INT1_HI_CAN_BUF10I (14) +#define INT1_HI_CAN_BUF11I (15) +#define INT1_HI_CAN_BUF12I (16) +#define INT1_HI_CAN_BUF13I (17) +#define INT1_HI_CAN_BUF14I (18) +#define INT1_HI_CAN_BUF15I (19) +#define INT1_HI_PIT0_PIF (43) +#define INT1_HI_PIT1_PIF (44) +#define INT1_HI_USBOTG_STS (47) +#define INT1_HI_SSI_ISR (49) +#define INT1_HI_PWM_INT (50) +#define INT1_HI_LCDC_ISR (51) +#define INT1_HI_CCM_UOCSR (53) +#define INT1_HI_DSPI_EOQF (54) +#define INT1_HI_DSPI_TFFF (55) +#define INT1_HI_DSPI_TCF (56) +#define INT1_HI_DSPI_TFUF (57) +#define INT1_HI_DSPI_RFDF (58) +#define INT1_HI_DSPI_RFOF (59) +#define INT1_HI_DSPI_RFOF_TFUF (60) +#define INT1_HI_TOUCH_ADC (61) +#define INT1_HI_PLL_LOCKS (62) + +/* Bit definitions and macros for IPRH */ +#define INTC_IPRH_INT32 (0x00000001) +#define INTC_IPRH_INT33 (0x00000002) +#define INTC_IPRH_INT34 (0x00000004) +#define INTC_IPRH_INT35 (0x00000008) +#define INTC_IPRH_INT36 (0x00000010) +#define INTC_IPRH_INT37 (0x00000020) +#define INTC_IPRH_INT38 (0x00000040) +#define INTC_IPRH_INT39 (0x00000080) +#define INTC_IPRH_INT40 (0x00000100) +#define INTC_IPRH_INT41 (0x00000200) +#define INTC_IPRH_INT42 (0x00000400) +#define INTC_IPRH_INT43 (0x00000800) +#define INTC_IPRH_INT44 (0x00001000) +#define INTC_IPRH_INT45 (0x00002000) +#define INTC_IPRH_INT46 (0x00004000) +#define INTC_IPRH_INT47 (0x00008000) +#define INTC_IPRH_INT48 (0x00010000) +#define INTC_IPRH_INT49 (0x00020000) +#define INTC_IPRH_INT50 (0x00040000) +#define INTC_IPRH_INT51 (0x00080000) +#define INTC_IPRH_INT52 (0x00100000) +#define INTC_IPRH_INT53 (0x00200000) +#define INTC_IPRH_INT54 (0x00400000) +#define INTC_IPRH_INT55 (0x00800000) +#define INTC_IPRH_INT56 (0x01000000) +#define INTC_IPRH_INT57 (0x02000000) +#define INTC_IPRH_INT58 (0x04000000) +#define INTC_IPRH_INT59 (0x08000000) +#define INTC_IPRH_INT60 (0x10000000) +#define INTC_IPRH_INT61 (0x20000000) +#define INTC_IPRH_INT62 (0x40000000) +#define INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for IPRL */ +#define INTC_IPRL_INT0 (0x00000001) +#define INTC_IPRL_INT1 (0x00000002) +#define INTC_IPRL_INT2 (0x00000004) +#define INTC_IPRL_INT3 (0x00000008) +#define INTC_IPRL_INT4 (0x00000010) +#define INTC_IPRL_INT5 (0x00000020) +#define INTC_IPRL_INT6 (0x00000040) +#define INTC_IPRL_INT7 (0x00000080) +#define INTC_IPRL_INT8 (0x00000100) +#define INTC_IPRL_INT9 (0x00000200) +#define INTC_IPRL_INT10 (0x00000400) +#define INTC_IPRL_INT11 (0x00000800) +#define INTC_IPRL_INT12 (0x00001000) +#define INTC_IPRL_INT13 (0x00002000) +#define INTC_IPRL_INT14 (0x00004000) +#define INTC_IPRL_INT15 (0x00008000) +#define INTC_IPRL_INT16 (0x00010000) +#define INTC_IPRL_INT17 (0x00020000) +#define INTC_IPRL_INT18 (0x00040000) +#define INTC_IPRL_INT19 (0x00080000) +#define INTC_IPRL_INT20 (0x00100000) +#define INTC_IPRL_INT21 (0x00200000) +#define INTC_IPRL_INT22 (0x00400000) +#define INTC_IPRL_INT23 (0x00800000) +#define INTC_IPRL_INT24 (0x01000000) +#define INTC_IPRL_INT25 (0x02000000) +#define INTC_IPRL_INT26 (0x04000000) +#define INTC_IPRL_INT27 (0x08000000) +#define INTC_IPRL_INT28 (0x10000000) +#define INTC_IPRL_INT29 (0x20000000) +#define INTC_IPRL_INT30 (0x40000000) +#define INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for IMRH */ +#define INTC_IMRH_INT_MASK32 (0x00000001) +#define INTC_IMRH_INT_MASK33 (0x00000002) +#define INTC_IMRH_INT_MASK34 (0x00000004) +#define INTC_IMRH_INT_MASK35 (0x00000008) +#define INTC_IMRH_INT_MASK36 (0x00000010) +#define INTC_IMRH_INT_MASK37 (0x00000020) +#define INTC_IMRH_INT_MASK38 (0x00000040) +#define INTC_IMRH_INT_MASK39 (0x00000080) +#define INTC_IMRH_INT_MASK40 (0x00000100) +#define INTC_IMRH_INT_MASK41 (0x00000200) +#define INTC_IMRH_INT_MASK42 (0x00000400) +#define INTC_IMRH_INT_MASK43 (0x00000800) +#define INTC_IMRH_INT_MASK44 (0x00001000) +#define INTC_IMRH_INT_MASK45 (0x00002000) +#define INTC_IMRH_INT_MASK46 (0x00004000) +#define INTC_IMRH_INT_MASK47 (0x00008000) +#define INTC_IMRH_INT_MASK48 (0x00010000) +#define INTC_IMRH_INT_MASK49 (0x00020000) +#define INTC_IMRH_INT_MASK50 (0x00040000) +#define INTC_IMRH_INT_MASK51 (0x00080000) +#define INTC_IMRH_INT_MASK52 (0x00100000) +#define INTC_IMRH_INT_MASK53 (0x00200000) +#define INTC_IMRH_INT_MASK54 (0x00400000) +#define INTC_IMRH_INT_MASK55 (0x00800000) +#define INTC_IMRH_INT_MASK56 (0x01000000) +#define INTC_IMRH_INT_MASK57 (0x02000000) +#define INTC_IMRH_INT_MASK58 (0x04000000) +#define INTC_IMRH_INT_MASK59 (0x08000000) +#define INTC_IMRH_INT_MASK60 (0x10000000) +#define INTC_IMRH_INT_MASK61 (0x20000000) +#define INTC_IMRH_INT_MASK62 (0x40000000) +#define INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for IMRL */ +#define INTC_IMRL_INT_MASK0 (0x00000001) +#define INTC_IMRL_INT_MASK1 (0x00000002) +#define INTC_IMRL_INT_MASK2 (0x00000004) +#define INTC_IMRL_INT_MASK3 (0x00000008) +#define INTC_IMRL_INT_MASK4 (0x00000010) +#define INTC_IMRL_INT_MASK5 (0x00000020) +#define INTC_IMRL_INT_MASK6 (0x00000040) +#define INTC_IMRL_INT_MASK7 (0x00000080) +#define INTC_IMRL_INT_MASK8 (0x00000100) +#define INTC_IMRL_INT_MASK9 (0x00000200) +#define INTC_IMRL_INT_MASK10 (0x00000400) +#define INTC_IMRL_INT_MASK11 (0x00000800) +#define INTC_IMRL_INT_MASK12 (0x00001000) +#define INTC_IMRL_INT_MASK13 (0x00002000) +#define INTC_IMRL_INT_MASK14 (0x00004000) +#define INTC_IMRL_INT_MASK15 (0x00008000) +#define INTC_IMRL_INT_MASK16 (0x00010000) +#define INTC_IMRL_INT_MASK17 (0x00020000) +#define INTC_IMRL_INT_MASK18 (0x00040000) +#define INTC_IMRL_INT_MASK19 (0x00080000) +#define INTC_IMRL_INT_MASK20 (0x00100000) +#define INTC_IMRL_INT_MASK21 (0x00200000) +#define INTC_IMRL_INT_MASK22 (0x00400000) +#define INTC_IMRL_INT_MASK23 (0x00800000) +#define INTC_IMRL_INT_MASK24 (0x01000000) +#define INTC_IMRL_INT_MASK25 (0x02000000) +#define INTC_IMRL_INT_MASK26 (0x04000000) +#define INTC_IMRL_INT_MASK27 (0x08000000) +#define INTC_IMRL_INT_MASK28 (0x10000000) +#define INTC_IMRL_INT_MASK29 (0x20000000) +#define INTC_IMRL_INT_MASK30 (0x40000000) +#define INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for INTFRCH */ +#define INTC_INTFRCH_INTFRC32 (0x00000001) +#define INTC_INTFRCH_INTFRC33 (0x00000002) +#define INTC_INTFRCH_INTFRC34 (0x00000004) +#define INTC_INTFRCH_INTFRC35 (0x00000008) +#define INTC_INTFRCH_INTFRC36 (0x00000010) +#define INTC_INTFRCH_INTFRC37 (0x00000020) +#define INTC_INTFRCH_INTFRC38 (0x00000040) +#define INTC_INTFRCH_INTFRC39 (0x00000080) +#define INTC_INTFRCH_INTFRC40 (0x00000100) +#define INTC_INTFRCH_INTFRC41 (0x00000200) +#define INTC_INTFRCH_INTFRC42 (0x00000400) +#define INTC_INTFRCH_INTFRC43 (0x00000800) +#define INTC_INTFRCH_INTFRC44 (0x00001000) +#define INTC_INTFRCH_INTFRC45 (0x00002000) +#define INTC_INTFRCH_INTFRC46 (0x00004000) +#define INTC_INTFRCH_INTFRC47 (0x00008000) +#define INTC_INTFRCH_INTFRC48 (0x00010000) +#define INTC_INTFRCH_INTFRC49 (0x00020000) +#define INTC_INTFRCH_INTFRC50 (0x00040000) +#define INTC_INTFRCH_INTFRC51 (0x00080000) +#define INTC_INTFRCH_INTFRC52 (0x00100000) +#define INTC_INTFRCH_INTFRC53 (0x00200000) +#define INTC_INTFRCH_INTFRC54 (0x00400000) +#define INTC_INTFRCH_INTFRC55 (0x00800000) +#define INTC_INTFRCH_INTFRC56 (0x01000000) +#define INTC_INTFRCH_INTFRC57 (0x02000000) +#define INTC_INTFRCH_INTFRC58 (0x04000000) +#define INTC_INTFRCH_INTFRC59 (0x08000000) +#define INTC_INTFRCH_INTFRC60 (0x10000000) +#define INTC_INTFRCH_INTFRC61 (0x20000000) +#define INTC_INTFRCH_INTFRC62 (0x40000000) +#define INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for INTFRCL */ +#define INTC_INTFRCL_INTFRC0 (0x00000001) +#define INTC_INTFRCL_INTFRC1 (0x00000002) +#define INTC_INTFRCL_INTFRC2 (0x00000004) +#define INTC_INTFRCL_INTFRC3 (0x00000008) +#define INTC_INTFRCL_INTFRC4 (0x00000010) +#define INTC_INTFRCL_INTFRC5 (0x00000020) +#define INTC_INTFRCL_INTFRC6 (0x00000040) +#define INTC_INTFRCL_INTFRC7 (0x00000080) +#define INTC_INTFRCL_INTFRC8 (0x00000100) +#define INTC_INTFRCL_INTFRC9 (0x00000200) +#define INTC_INTFRCL_INTFRC10 (0x00000400) +#define INTC_INTFRCL_INTFRC11 (0x00000800) +#define INTC_INTFRCL_INTFRC12 (0x00001000) +#define INTC_INTFRCL_INTFRC13 (0x00002000) +#define INTC_INTFRCL_INTFRC14 (0x00004000) +#define INTC_INTFRCL_INTFRC15 (0x00008000) +#define INTC_INTFRCL_INTFRC16 (0x00010000) +#define INTC_INTFRCL_INTFRC17 (0x00020000) +#define INTC_INTFRCL_INTFRC18 (0x00040000) +#define INTC_INTFRCL_INTFRC19 (0x00080000) +#define INTC_INTFRCL_INTFRC20 (0x00100000) +#define INTC_INTFRCL_INTFRC21 (0x00200000) +#define INTC_INTFRCL_INTFRC22 (0x00400000) +#define INTC_INTFRCL_INTFRC23 (0x00800000) +#define INTC_INTFRCL_INTFRC24 (0x01000000) +#define INTC_INTFRCL_INTFRC25 (0x02000000) +#define INTC_INTFRCL_INTFRC26 (0x04000000) +#define INTC_INTFRCL_INTFRC27 (0x08000000) +#define INTC_INTFRCL_INTFRC28 (0x10000000) +#define INTC_INTFRCL_INTFRC29 (0x20000000) +#define INTC_INTFRCL_INTFRC30 (0x40000000) +#define INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for ICONFIG */ +#define INTC_ICONFIG_EMASK (0x0020) +#define INTC_ICONFIG_ELVLPRI1 (0x0200) +#define INTC_ICONFIG_ELVLPRI2 (0x0400) +#define INTC_ICONFIG_ELVLPRI3 (0x0800) +#define INTC_ICONFIG_ELVLPRI4 (0x1000) +#define INTC_ICONFIG_ELVLPRI5 (0x2000) +#define INTC_ICONFIG_ELVLPRI6 (0x4000) +#define INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for SIMR */ +#define INTC_SIMR_SIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CIMR */ +#define INTC_CIMR_CIMR(x) (((x)&0x7F)) + +/* Bit definitions and macros for CLMASK */ +#define INTC_CLMASK_CLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for SLMASK */ +#define INTC_SLMASK_SLMASK(x) (((x)&0x0F)) + +/* Bit definitions and macros for ICR group */ +#define INTC_ICR_IL(x) (((x)&0x07)) + +/********************************************************************* +* Reset Controller Module (RCM) +*********************************************************************/ + +/* Bit definitions and macros for RCR */ +#define RCM_RCR_FRCRSTOUT (0x40) +#define RCM_RCR_SOFTRST (0x80) + +/* Bit definitions and macros for RSR */ +#define RCM_RSR_LOL (0x01) +#define RCM_RSR_WDR_CORE (0x02) +#define RCM_RSR_EXT (0x04) +#define RCM_RSR_POR (0x08) +#define RCM_RSR_SOFT (0x20) + +/********************************************************************* +* Chip Configuration Module (CCM) +*********************************************************************/ + +/* Bit definitions and macros for CCR */ +#define CCM_CCR_DRAMSEL (0x0100) +#define CCM_CCR_CSC_MASK (0xFF3F) +#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0) +#define CCM_CCR_CSC_FBCS5_A22 (0x0080) +#define CCM_CCR_CSC_FB_A23_A22 (0x0040) +#define CCM_CCR_LIMP (0x0020) +#define CCM_CCR_LOAD (0x0010) +#define CCM_CCR_BOOTPS_MASK (0xFFF3) +#define CCM_CCR_BOOTPS_PS16 (0x0008) +#define CCM_CCR_BOOTPS_PS8 (0x0004) +#define CCM_CCR_BOOTPS_PS32 (0x0000) +#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002) + +/* Bit definitions and macros for RCON */ +#define CCM_RCON_CSC_MASK (0xFF3F) +#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0) +#define CCM_RCON_CSC_FBCS5_A22 (0x0080) +#define CCM_RCON_CSC_FB_A23_A22 (0x0040) +#define CCM_RCON_LIMP (0x0020) +#define CCM_RCON_LOAD (0x0010) +#define CCM_RCON_BOOTPS_MASK (0xFFF3) +#define CCM_RCON_BOOTPS_PS16 (0x0008) +#define CCM_RCON_BOOTPS_PS8 (0x0004) +#define CCM_RCON_BOOTPS_PS32 (0x0000) +#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002) + +/* Bit definitions and macros for CIR */ +#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */ +#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */ +#define CCM_CIR_PIN_MASK (0xFFC0) +#define CCM_CIR_PRN_MASK (0x003F) +#define CCM_CIR_PIN_MCF52277 (0x0000) + +/* Bit definitions and macros for MISCCR */ +#define CCM_MISCCR_RTCSRC (0x4000) +#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */ +#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */ + +#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */ +#define CCM_MISCCR_BMT_65536 (0) +#define CCM_MISCCR_BMT_32768 (1) +#define CCM_MISCCR_BMT_16384 (2) +#define CCM_MISCCR_BMT_8192 (3) +#define CCM_MISCCR_BMT_4096 (4) +#define CCM_MISCCR_BMT_2048 (5) +#define CCM_MISCCR_BMT_1024 (6) +#define CCM_MISCCR_BMT_512 (7) + +#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */ +#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */ +#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */ +#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */ +#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */ +#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */ +#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */ + +/* Bit definitions and macros for CDR */ +#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12) +#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */ +#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */ + +/* Bit definitions and macros for UOCSR */ +#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */ +#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */ +#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */ +#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */ +#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */ +#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */ +#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */ +#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */ +#define CCM_UOCSR_SEND (0x0010) /* Session end */ +#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */ +#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */ +#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */ + +/********************************************************************* +* General Purpose I/O Module (GPIO) +*********************************************************************/ +/* Bit definitions and macros for PAR_BE */ +#define GPIO_PAR_BE_MASK (0x0F) +#define GPIO_PAR_BE_BE3_BE3 (0x08) +#define GPIO_PAR_BE_BE3_GPIO (0x00) +#define GPIO_PAR_BE_BE2_BE2 (0x04) +#define GPIO_PAR_BE_BE2_GPIO (0x00) +#define GPIO_PAR_BE_BE1_BE1 (0x02) +#define GPIO_PAR_BE_BE1_GPIO (0x00) +#define GPIO_PAR_BE_BE0_BE0 (0x01) +#define GPIO_PAR_BE_BE0_GPIO (0x00) + +/* Bit definitions and macros for PAR_CS */ +#define GPIO_PAR_CS_CS3 (0x10) +#define GPIO_PAR_CS_CS2 (0x08) +#define GPIO_PAR_CS_CS1_FBCS1 (0x06) +#define GPIO_PAR_CS_CS1_SDCS1 (0x04) +#define GPIO_PAR_CS_CS1_GPIO (0x00) +#define GPIO_PAR_CS_CS0 (0x01) + +/* Bit definitions and macros for PAR_FBCTL */ +#define GPIO_PAR_FBCTL_OE (0x80) +#define GPIO_PAR_FBCTL_TA (0x40) +#define GPIO_PAR_FBCTL_RW (0x20) +#define GPIO_PAR_FBCTL_TS_MASK (0xE7) +#define GPIO_PAR_FBCTL_TS_FBTS (0x18) +#define GPIO_PAR_FBCTL_TS_DMAACK (0x10) +#define GPIO_PAR_FBCTL_TS_GPIO (0x00) + +/* Bit definitions and macros for PAR_FECI2C */ +#define GPIO_PAR_I2C_SCL_MASK (0xF3) +#define GPIO_PAR_I2C_SCL_SCL (0x0C) +#define GPIO_PAR_I2C_SCL_CANTXD (0x08) +#define GPIO_PAR_I2C_SCL_U2TXD (0x04) +#define GPIO_PAR_I2C_SCL_GPIO (0x00) + +#define GPIO_PAR_I2C_SDA_MASK (0xFC) +#define GPIO_PAR_I2C_SDA_SDA (0x03) +#define GPIO_PAR_I2C_SDA_CANRXD (0x02) +#define GPIO_PAR_I2C_SDA_U2RXD (0x01) +#define GPIO_PAR_I2C_SDA_GPIO (0x00) + +/* Bit definitions and macros for PAR_UART */ +#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF) +#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000) +#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000) +#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000) +#define GPIO_PAR_UART_U1CTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF) +#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000) +#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000) +#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000) +#define GPIO_PAR_UART_U1RTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF) +#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00) +#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800) +#define GPIO_PAR_UART_U1RXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF) +#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300) +#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200) +#define GPIO_PAR_UART_U1TXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F) +#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0) +#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080) +#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040) +#define GPIO_PAR_UART_U0CTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF) +#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030) +#define GPIO_PAR_UART_U0RTS_T1IN (0x0020) +#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010) +#define GPIO_PAR_UART_U0RTS_GPIO (0x0000) + +#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3) +#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C) +#define GPIO_PAR_UART_U0RXD_CANRX (0x0008) +#define GPIO_PAR_UART_U0RXD_GPIO (0x0000) + +#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC) +#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003) +#define GPIO_PAR_UART_U0TXD_CANTX (0x0002) +#define GPIO_PAR_UART_U0TXD_GPIO (0x0000) + +/* Bit definitions and macros for PAR_DSPI */ +#define GPIO_PAR_DSPI_PCS0_MASK (0x3F) +#define GPIO_PAR_DSPI_PCS0_PCS0 (0x80) +#define GPIO_PAR_DSPI_PCS0_U2RTS (0x40) +#define GPIO_PAR_DSPI_PCS0_GPIO (0x00) +#define GPIO_PAR_DSPI_SIN_MASK (0xCF) +#define GPIO_PAR_DSPI_SIN_SIN (0x30) +#define GPIO_PAR_DSPI_SIN_U2RXD (0x20) +#define GPIO_PAR_DSPI_SIN_GPIO (0x00) +#define GPIO_PAR_DSPI_SOUT_MASK (0xF3) +#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C) +#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08) +#define GPIO_PAR_DSPI_SOUT_GPIO (0x00) +#define GPIO_PAR_DSPI_SCK_MASK (0xFC) +#define GPIO_PAR_DSPI_SCK_SCK (0x03) +#define GPIO_PAR_DSPI_SCK_U2CTS (0x02) +#define GPIO_PAR_DSPI_SCK_GPIO (0x00) + +/* Bit definitions and macros for PAR_TIMER */ +#define GPIO_PAR_TIMER_T3IN_MASK (0x3F) +#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0) +#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80) +#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40) +#define GPIO_PAR_TIMER_T3IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T2IN_MASK (0xCF) +#define GPIO_PAR_TIMER_T2IN_T2IN (0x30) +#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20) +#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10) +#define GPIO_PAR_TIMER_T2IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T1IN_MASK (0xF3) +#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C) +#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08) +#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04) +#define GPIO_PAR_TIMER_T1IN_GPIO (0x00) +#define GPIO_PAR_TIMER_T0IN_MASK (0xFC) +#define GPIO_PAR_TIMER_T0IN_T0IN (0x03) +#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02) +#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01) +#define GPIO_PAR_TIMER_T0IN_GPIO (0x00) + +/* Bit definitions and macros for GPIO_PAR_LCDCTL */ +#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7) +#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18) +#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10) +#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00) +#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04) +#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02) +#define GPIO_PAR_LCDCTL_LSCLK (0x01) + +/* Bit definitions and macros for PAR_IRQ */ +#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3) +#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C) +#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08) +#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00) +#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC) +#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03) +#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02) +#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01) +#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00) + +/* Bit definitions and macros for GPIO_PAR_LCDH */ +#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00) +#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800) +#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300) +#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200) +#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F) +#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0) +#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080) +#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF) +#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030) +#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020) +#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3) +#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C) +#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008) +#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000) + +#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC) +#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003) +#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002) +#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000) + +/* Bit definitions and macros for GPIO_PAR_LCDL */ +#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF) +#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000) +#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000) +#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF) +#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000) +#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000) +#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF) +#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000) +#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000) +#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF) +#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000) +#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000) +#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF) +#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000) +#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000) +#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF) +#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000) +#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000) +#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF) +#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000) +#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000) +#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF) +#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000) +#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000) +#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF) +#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000) +#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000) +#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF) +#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000) +#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000) +#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF) +#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00) +#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800) +#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000) + +#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF) +#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300) +#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200) +#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000) + +/* Bit definitions and macros for MSCR_FB */ +#define GPIO_MSCR_FB_DUPPER_MASK (0xCF) +#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30) +#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20) +#define GPIO_MSCR_FB_DUPPER_OD (0x10) +#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00) + +#define GPIO_MSCR_FB_DLOWER_MASK (0xF3) +#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C) +#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08) +#define GPIO_MSCR_FB_DLOWER_OD (0x04) +#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00) + +#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC) +#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03) +#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02) +#define GPIO_MSCR_FB_ADDRCTL_OD (0x01) +#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00) + +/* Bit definitions and macros for MSCR_SDRAM */ +#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF) +#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30) +#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20) +#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10) +#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00) + +#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3) +#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C) +#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08) +#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04) +#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00) + +#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC) +#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03) +#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02) +#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01) +#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00) + +/* Bit definitions and macros for Drive Strength Control */ +#define DSCR_LOAD_50PF (0x03) +#define DSCR_LOAD_30PF (0x02) +#define DSCR_LOAD_20PF (0x01) +#define DSCR_LOAD_10PF (0x00) + +/********************************************************************* +* SDRAM Controller (SDRAMC) +*********************************************************************/ + +/* Bit definitions and macros for SDMR */ +#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */ +#define SDRAMC_SDMR_CMD (0x00010000) /* Command */ +#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */ +#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */ +#define SDRAMC_SDMR_BK_LMR (0x00000000) +#define SDRAMC_SDMR_BK_LEMR (0x40000000) + +/* Bit definitions and macros for SDCR */ +#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */ +#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */ +#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */ +#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */ +#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */ +#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */ +#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */ +#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */ +#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */ +#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */ +#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */ +#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */ +#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */ +#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000) + +/* Bit definitions and macros for SDCFG1 */ +#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */ +#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */ +#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */ +#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */ +#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */ +#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */ +#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */ + +/* Bit definitions and macros for SDCFG2 */ +#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */ +#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */ +#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */ +#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */ + +/* Bit definitions and macros for SDCS group */ +#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */ +#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */ +#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000) +#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* +* Phase Locked Loop (PLL) +*********************************************************************/ + +/* Bit definitions and macros for PCR */ +#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */ +#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */ +#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */ +#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */ +#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */ +#define PLL_PCR_PFDR_MASK (0x000F0000) +#define PLL_PCR_OUTDIV5_MASK (0x000F0000) +#define PLL_PCR_OUTDIV3_MASK (0x00000F00) +#define PLL_PCR_OUTDIV2_MASK (0x000000F0) +#define PLL_PCR_OUTDIV1_MASK (0x0000000F) + +/* Bit definitions and macros for PSR */ +#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */ +#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */ +#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */ +#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */ + +/********************************************************************/ + +#endif /* __MCF5227X__ */ -- 1.5.2

1 0

[U-Boot-Users] [PATCH] ColdFire: Add MCF5227x cpu and MCF52277EVB support-2
by Tsi-Chung Liew 15 Jan '08

15 Jan '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- cpu/mcf5227x/Makefile | 48 ++++++ cpu/mcf5227x/config.mk | 31 ++++ cpu/mcf5227x/cpu.c | 75 +++++++++ cpu/mcf5227x/cpu_init.c | 146 ++++++++++++++++ cpu/mcf5227x/interrupts.c | 52 ++++++ cpu/mcf5227x/speed.c | 120 ++++++++++++++ cpu/mcf5227x/start.S | 356 ++++++++++++++++++++++++++++++++++++++++ include/asm-m68k/immap_5227x.h | 343 ++++++++++++++++++++++++++++++++++++++ 8 files changed, 1171 insertions(+), 0 deletions(-) create mode 100644 cpu/mcf5227x/Makefile create mode 100644 cpu/mcf5227x/config.mk create mode 100644 cpu/mcf5227x/cpu.c create mode 100644 cpu/mcf5227x/cpu_init.c create mode 100644 cpu/mcf5227x/interrupts.c create mode 100644 cpu/mcf5227x/speed.c create mode 100644 cpu/mcf5227x/start.S create mode 100644 include/asm-m68k/immap_5227x.h diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile new file mode 100644 index 0000000..d0e9b45 --- /dev/null +++ b/cpu/mcf5227x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk new file mode 100644 index 0000000..8d60fd6 --- /dev/null +++ b/cpu/mcf5227x/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner(a)telex.de> +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC +else +PLATFORM_CPPFLAGS += -m5307 -fPIC +endif diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c new file mode 100644 index 0000000..5792a1c --- /dev/null +++ b/cpu/mcf5227x/cpu.c @@ -0,0 +1,75 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + udelay(1000); + rcm->rcr |= RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x6c: + id = 52277; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000), + (int)(gd->flb_clk / 1000000)); + printf(" INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); + } + + return 0; +} diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c new file mode 100644 index 0000000..71b053d --- /dev/null +++ b/cpu/mcf5227x/cpu_init.c @@ -0,0 +1,146 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> + +#include <asm/immap.h> +#include <asm/rtc.h> + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Workaround, must place before fbcs */ + pll->psr = 0x12; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + scm1->pacri = 0; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFTMR + volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + u32 oscillator = CFG_RTC_OSCILLATOR; + + rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart &= + (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart &= + (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + case 2: + gpio->par_dspi &= + (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); + gpio->par_dspi = + (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); + break; + } +} diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c new file mode 100644 index 0000000..9572a7b --- /dev/null +++ b/cpu/mcf5227x/interrupts.c @@ -0,0 +1,52 @@ +/* + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include <common.h> +#include <asm/immap.h> + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c new file mode 100644 index 0000000..78c946f --- /dev/null +++ b/cpu/mcf5227x/speed.c @@ -0,0 +1,120 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Low Power Divider specifications + */ +#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ + +#define CLOCK_PLL_FVCO_MAX 540000000 +#define CLOCK_PLL_FVCO_MIN 300000000 + +#define CLOCK_PLL_FSYS_MAX 266666666 +#define CLOCK_PLL_FSYS_MIN 100000000 +#define MHZ 1000000 + +void clock_enter_limp(int lpdiv) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + int i, j; + + /* Check bounds of divider */ + if (lpdiv < CLOCK_LPD_MIN) + lpdiv = CLOCK_LPD_MIN; + if (lpdiv > CLOCK_LPD_MAX) + lpdiv = CLOCK_LPD_MAX; + + /* Round divider down to nearest power of two */ + for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; + + /* Apply the divider to the system clock */ + ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + + /* Enable Limp Mode */ + ccm->misccr |= CCM_MISCCR_LIMP; +} + +/* + * brief Exit Limp mode + * warning The PLL should be set and locked prior to exiting Limp mode + */ +void clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Exit Limp mode */ + ccm->misccr &= ~CCM_MISCCR_LIMP; + + /* Wait for the PLL to lock */ + while (!(pll->psr & PLL_PSR_LOCK)) ; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + int vco, temp, pcrvalue, pfdr; + u8 bootmode; + + bootmode = (ccm->ccr & 0x000C) >> 2; + + pcrvalue = pll->pcr & 0xFF0F0FFF; + pfdr = pcrvalue >> 24; + + if (pfdr != 0x1E) { + /* serial mode */ + } else { + /* Normal Mode */ + vco = pfdr * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; + } + + if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + /* Limp mode */ + } else { + gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + + temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + gd->flb_clk = vco / temp; /* flexbus clock */ + gd->bus_clk = gd->flb_clk; + } + + return (0); +} diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S new file mode 100644 index 0000000..0e2db12 --- /dev/null +++ b/cpu/mcf5227x/start.S @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner(a)telex.de> + * Based on code from Bernhard Kuhn <bkuhn(a)metrowerks.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l #(CACR_STATUS), %a3 /* CACR */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01200000, %d0 /* Invalid cache */ + movec %d0, %CACR + + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + movec %d0, %ACR0 + + move.l #0x81600610, %d0 /* Enable cache */ + movec %d0, %CACR + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x01F00000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + clr.l %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x80600610, %d0 /* Invalidate icache */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #0x01200000, %d0 /* Invalid cache */ + movec %d0, %CACR + + move.l #0x81300610, %d0 + movec %d0, %CACR + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #0x81600610, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_invalid +dcache_invalid: + move.l #0x81100610, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h new file mode 100644 index 0000000..1d1e6f1 --- /dev/null +++ b/include/asm-m68k/immap_5227x.h @@ -0,0 +1,343 @@ +/* + * MCF5227x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5227X__ +#define __IMMAP_5227X__ + +/* Module Base Addresses */ +#define MMAP_SCM1 (CFG_MBAR + 0x00000000) +#define MMAP_XBS (CFG_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_MBAR + 0x00008000) +#define MMAP_CAN (CFG_MBAR + 0x00020000) +#define MMAP_RTC (CFG_MBAR + 0x0003C000) +#define MMAP_SCM2 (CFG_MBAR + 0x00040010) +#define MMAP_SCM3 (CFG_MBAR + 0x00040070) +#define MMAP_EDMA (CFG_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_MBAR + 0x0004C000) +#define MMAP_IACK (CFG_MBAR + 0x00054000) +#define MMAP_I2C (CFG_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_MBAR + 0x00084000) +#define MMAP_PWM (CFG_MBAR + 0x00090000) +#define MMAP_EPORT (CFG_MBAR + 0x00094000) +#define MMAP_RCM (CFG_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_MBAR + 0x000A4000) +#define MMAP_ADC (CFG_MBAR + 0x000A8000) +#define MMAP_LCD (CFG_MBAR + 0x000AC000) +#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800) +#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00) +#define MMAP_USBHW (CFG_MBAR + 0x000B0000) +#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100) +#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140) +#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0) +#define MMAP_SDRAM (CFG_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_MBAR + 0x000C0000) + +#include <asm/coldfire/crossbar.h> +#include <asm/coldfire/dspi.h> +#include <asm/coldfire/edma.h> +#include <asm/coldfire/flexbus.h> +#include <asm/coldfire/lcd.h> +#include <asm/coldfire/ssi.h> + +/* Interrupt Controller (INTC) */ +typedef struct int0_ctrl { + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt ack */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt ack */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt ack */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt ack */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt ack */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt ack */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt ack */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt ack */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt ack */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt ack */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt ack */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt ack */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt ack */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt ack */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt ack */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt ack */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +/* Global Interrupt Acknowledge (IACK) */ +typedef struct iack { + u8 resv0[0xE0]; + u8 gswiack; + u8 resv1[0x3]; + u8 gl1iack; + u8 resv2[0x3]; + u8 gl2iack; + u8 resv3[0x3]; + u8 gl3iack; + u8 resv4[0x3]; + u8 gl4iack; + u8 resv5[0x3]; + u8 gl5iack; + u8 resv6[0x3]; + u8 gl6iack; + u8 resv7[0x3]; + u8 gl7iack; +} iack_t; + +/* Edge Port Module (EPORT) */ +typedef struct eport { + u16 eppar; + u8 epddr; + u8 epier; + u8 epdr; + u8 eppdr; + u8 epfr; +} eport_t; + +/* Reset Controller Module (RCM) */ +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/* Chip Configuration Module (CCM) */ +typedef struct ccm { + u16 ccr; /* Chip Configuration (Rd-only) */ + u16 resv1; + u16 rcon; /* Reset Configuration (Rd-only) */ + u16 cir; /* Chip Identification (Rd-only) */ + u32 resv2; + u16 misccr; /* Miscellaneous Control */ + u16 cdr; /* Clock Divider */ + u16 uocsr; /* USB On-the-Go Controller Status */ + u16 resv4; + u16 sbfsr; /* Serial Boot Status */ + u16 sbfcr; /* Serial Boot Control */ +} ccm_t; + +/* General Purpose I/O Module (GPIO) */ +typedef struct gpio { + /* Port Output Data Registers */ + u8 podr_be; /* 0x00 */ + u8 podr_cs; /* 0x01 */ + u8 podr_fbctl; /* 0x02 */ + u8 podr_i2c; /* 0x03 */ + u8 rsvd1; /* 0x04 */ + u8 podr_uart; /* 0x05 */ + u8 podr_dspi; /* 0x06 */ + u8 podr_timer; /* 0x07 */ + u8 podr_lcdctl; /* 0x08 */ + u8 podr_lcddatah; /* 0x09 */ + u8 podr_lcddatam; /* 0x0A */ + u8 podr_lcddatal; /* 0x0B */ + + /* Port Data Direction Registers */ + u8 pddr_be; /* 0x0C */ + u8 pddr_cs; /* 0x0D */ + u8 pddr_fbctl; /* 0x0E */ + u8 pddr_i2c; /* 0x0F */ + u8 rsvd2; /* 0x10 */ + u8 pddr_uart; /* 0x11 */ + u8 pddr_dspi; /* 0x12 */ + u8 pddr_timer; /* 0x13 */ + u8 pddr_lcdctl; /* 0x14 */ + u8 pddr_lcddatah; /* 0x15 */ + u8 pddr_lcddatam; /* 0x16 */ + u8 pddr_lcddatal; /* 0x17 */ + + /* Port Pin Data/Set Data Registers */ + u8 ppdsdr_be; /* 0x18 */ + u8 ppdsdr_cs; /* 0x19 */ + u8 ppdsdr_fbctl; /* 0x1A */ + u8 ppdsdr_i2c; /* 0x1B */ + u8 rsvd3; /* 0x1C */ + u8 ppdsdr_uart; /* 0x1D */ + u8 ppdsdr_dspi; /* 0x1E */ + u8 ppdsdr_timer; /* 0x1F */ + u8 ppdsdr_lcdctl; /* 0x20 */ + u8 ppdsdr_lcddatah; /* 0x21 */ + u8 ppdsdr_lcddatam; /* 0x22 */ + u8 ppdsdr_lcddatal; /* 0x23 */ + + /* Port Clear Output Data Registers */ + u8 pclrr_be; /* 0x24 */ + u8 pclrr_cs; /* 0x25 */ + u8 pclrr_fbctl; /* 0x26 */ + u8 pclrr_i2c; /* 0x27 */ + u8 rsvd4; /* 0x28 */ + u8 pclrr_uart; /* 0x29 */ + u8 pclrr_dspi; /* 0x2A */ + u8 pclrr_timer; /* 0x2B */ + u8 pclrr_lcdctl; /* 0x2C */ + u8 pclrr_lcddatah; /* 0x2D */ + u8 pclrr_lcddatam; /* 0x2E */ + u8 pclrr_lcddatal; /* 0x2F */ + + /* Pin Assignment Registers */ + u8 par_be; /* 0x30 */ + u8 par_cs; /* 0x31 */ + u8 par_fbctl; /* 0x32 */ + u8 par_i2c; /* 0x33 */ + u16 par_uart; /* 0x34 */ + u8 par_dspi; /* 0x36 */ + u8 par_timer; /* 0x37 */ + u8 par_lcdctl; /* 0x38 */ + u8 par_irq; /* 0x39 */ + u16 rsvd6; /* 0x3A - 0x3B */ + u32 par_lcdh; /* 0x3C */ + u32 par_lcdl; /* 0x40 */ + + /* Mode select control registers */ + u8 mscr_fb; /* 0x44 */ + u8 mscr_sdram; /* 0x45 */ + + u16 rsvd7; /* 0x46 - 0x47 */ + u8 dscr_dspi; /* 0x48 */ + u8 dscr_timer; /* 0x49 */ + u8 dscr_i2c; /* 0x4A */ + u8 dscr_lcd; /* 0x4B */ + u8 dscr_debug; /* 0x4C */ + u8 dscr_clkrst; /* 0x4D */ + u8 dscr_irq; /* 0x4E */ + u8 dscr_uart; /* 0x4F */ +} gpio_t; + +/* SDRAM Controller (SDRAMC) */ +typedef struct sdramc { + u32 sdmr; /* Mode/Extended Mode */ + u32 sdcr; /* Control */ + u32 sdcfg1; /* Configuration 1 */ + u32 sdcfg2; /* Chip Select */ + u8 resv0[0x100]; + u32 sdcs0; /* Mode/Extended Mode */ + u32 sdcs1; /* Mode/Extended Mode */ +} sdramc_t; + +/* Phase Locked Loop (PLL) */ +typedef struct pll { + u32 pcr; /* PLL Control */ + u32 psr; /* PLL Status */ +} pll_t; + +/* System Control Module register */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 */ + u32 pacrb; /* 0x24 */ + u32 pacrc; /* 0x28 */ + u32 pacrd; /* 0x2C */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 */ + u32 pacrf; /* 0x44 */ + u32 pacrg; /* 0x48 */ + u32 rsvd3; + u32 pacri; /* 0x50 */ +} scm1_t; + +typedef struct scm2_ctrl { + u8 res1[3]; /* 0x00 - 0x02 */ + u8 wcr; /* 0x03 wakeup control */ + u16 res2; /* 0x04 - 0x05 */ + u16 cwcr; /* 0x06 Core Watchdog Control */ + u8 res3[3]; /* 0x08 - 0x0A */ + u8 cwsr; /* 0x0B Core Watchdog Service */ + u8 res4[2]; /* 0x0C - 0x0D */ + u8 scmisr; /* 0x0F Interrupt Status */ + u32 res5; /* 0x20 */ + u32 bcr; /* 0x24 Burst Configuration */ +} scm2_t; + +typedef struct scm3_ctrl { + u32 cfadr; /* 0x00 Core Fault Address */ + u8 res7; /* 0x04 */ + u8 cfier; /* 0x05 Core Fault Interrupt Enable */ + u8 cfloc; /* 0x06 Core Fault Location */ + u8 cfatr; /* 0x07 Core Fault Attributes */ + u32 cfdtr; /* 0x08 Core Fault Data */ +} scm3_t; + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5227X__ */ -- 1.5.2

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[U-Boot-Users] [PATCH] ColdFire: Add MCF5227x cpu and M52277EVB support-1
by Tsi-Chung Liew 15 Jan '08

15 Jan '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + README | 1 + board/freescale/m52277evb/Makefile | 44 ++++++ board/freescale/m52277evb/config.mk | 25 ++++ board/freescale/m52277evb/m52277evb.c | 86 +++++++++++ board/freescale/m52277evb/u-boot.lds | 145 +++++++++++++++++++ doc/README.m52277evb | 237 +++++++++++++++++++++++++++++++ include/asm-m68k/global_data.h | 3 + include/asm-m68k/immap.h | 34 +++++ include/configs/M52277EVB.h | 251 +++++++++++++++++++++++++++++++++ lib_m68k/board.c | 10 ++ 13 files changed, 841 insertions(+), 0 deletions(-) create mode 100644 board/freescale/m52277evb/Makefile create mode 100644 board/freescale/m52277evb/config.mk create mode 100644 board/freescale/m52277evb/m52277evb.c create mode 100644 board/freescale/m52277evb/u-boot.lds create mode 100644 doc/README.m52277evb create mode 100644 include/configs/M52277EVB.h diff --git a/MAINTAINERS b/MAINTAINERS index 02698c8..477da87 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -627,6 +627,7 @@ Zachary P. Landau <zachary.landau(a)labxtechnologies.com> TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> + M52277EVB mcf5227x M5235EVB mcf52x2 M5329EVB mcf532x M5373EVB mcf532x diff --git a/MAKEALL b/MAKEALL index 1f59532..37e1104 100755 --- a/MAKEALL +++ b/MAKEALL @@ -635,6 +635,7 @@ LIST_coldfire=" \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ idmr \ + M52277EVB \ M5235EVB \ M5249EVB \ M5253EVB \ diff --git a/Makefile b/Makefile index f541392..023ae52 100644 --- a/Makefile +++ b/Makefile @@ -1721,6 +1721,9 @@ ZPC1900_config: unconfig ## Coldfire ######################################################################### +M52277EVB_config: unconfig + @$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale + M5235EVB_config \ M5235EVB_Flash16_config \ M5235EVB_Flash32_config: unconfig diff --git a/README b/README index 57fc01a..4962c7a 100644 --- a/README +++ b/README @@ -136,6 +136,7 @@ Directory Hierarchy: - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs + - mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - mips Files specific to MIPS CPUs diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile new file mode 100644 index 0000000..981763d --- /dev/null +++ b/board/freescale/m52277evb/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk new file mode 100644 index 0000000..ce014ed --- /dev/null +++ b/board/freescale/m52277evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn(a)metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c new file mode 100644 index 0000000..98424c8 --- /dev/null +++ b/board/freescale/m52277evb/m52277evb.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M52277 EVB\n"); + return 0; +}; + +long int initdram(int board_type) +{ + volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CFG_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->sdcs0 = (CFG_SDRAM_BASE | i); + + sdram->sdcfg1 = CFG_SDRAM_CFG1; + sdram->sdcfg2 = CFG_SDRAM_CFG2; + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Issue LEMR */ + /*sdram->sdmr = CFG_SDRAM_EMOD; */ + sdram->sdmr = CFG_SDRAM_MODE; + + udelay(1000); + + /* Issue PALL */ + sdram->sdcr = CFG_SDRAM_CTRL | 2; + + /* Perform two refresh cycles */ + sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CFG_SDRAM_CTRL | 4; + + sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + + udelay(100); + + return (dramsize); +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds new file mode 100644 index 0000000..9125bfc --- /dev/null +++ b/board/freescale/m52277evb/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5227x/start.o (.text) + cpu/mcf5227x/libmcf5227x.a (.text) + lib_m68k/libm68k.a (.text) + lib_generic/libgeneric.a (.text) + common/cmd_mem.o (.text) + common/main.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/doc/README.m52277evb b/doc/README.m52277evb new file mode 100644 index 0000000..de1daba --- /dev/null +++ b/doc/README.m52277evb @@ -0,0 +1,237 @@ +Freescale MCF52277EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew(a)freescale.com) +Created Jan 8, 2008 +=========================================== + + +Changed files: +============== + +- board/freescale/m52277evb/m52277evb.c Dram setup +- board/freescale/m52277evb/Makefile Makefile +- board/freescale/m52277evb/config.mk config make +- board/freescale/m52277evb/u-boot.lds Linker description + +- cpu/mcf5227x/cpu.c cpu specific code +- cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- cpu/mcf5227x/interrupts.c cpu specific interrupt support +- cpu/mcf5227x/speed.c system, flexbus, and cpu clock +- cpu/mcf5227x/Makefile Makefile +- cpu/mcf5227x/config.mk config make +- cpu/mcf5227x/start.S start up assembly code + +- doc/README.m52277evb This readme file + +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/crossbar.h CrossBar structure and definition +- include/asm-m68k/dspi.h DSPI structure and definition +- include/asm-m68k/edma.h eDMA structure and definition +- include/asm-m68k/flexbus.h FlexBus structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_5227x.h mcf5227x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/lcd.h LCD structure and definition +- include/asm-m68k/m5227x.h mcf5227x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/ssi.h SSI structure and definition +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M52277EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +1 MCF52277 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in this coldfire family + +1.2 Configuration settings for M52277EVB Development Board +CONFIG_MCF5227x -- define for all MCF5227x CPUs +CONFIG_M52277 -- define for all Freescale MCF52277 CPUs +CONFIG_M52277EVB -- define for M52277EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CFG_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_SDRAM_BASE -- defines the DRAM Base + +CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot, +update will be provided at later time + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (64MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M52277EVB_config + make + +4. SCREEN DUMP +============== +4.1 M52277EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.1 (Jan 8 2008 - 12:44:08) + +CPU: Freescale MCF52277 (Mask:6c Version:0) + CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ + INP CLK 16 Mhz VCO CLK 480 Mhz +Board: Freescale 52277 EVB +I2C: ready +DRAM: 64 MB +FLASH: 16 MB +In: serial +Out: serial +Err: serial +-> print +baudrate=115200 +hostname=M52277EVB +inpclk=16000000 +loadaddr=(0x40000000 + 0x10000) +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save +u-boot=u-boot.bin +stdin=serial +stdout=serial +stderr=serial +mem=65024k + +Environment size: 280/32764 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x04000000 +flashstart = 0x00000000 +flashsize = 0x01000000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +flbfreq = 80 Mhz +inpfreq = 16 Mhz +vcofreq = 480 Mhz + +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +version - print monitor version +-> diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index 9d9894b..1e26eb0 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -53,6 +53,9 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long have_console; /* serial_init() was called */ +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) + unsigned long fb_base; /* Base addr of framebuffer memory */ +#endif #ifdef CONFIG_BOARD_TYPES unsigned long board_type; #endif diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 852d941..9dd9707 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -26,6 +26,40 @@ #ifndef __IMMAP_H #define __IMMAP_H +#ifdef CONFIG_M52277 +#include <asm/immap_5227x.h> +#include <asm/m5227x.h> + +#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000)) + +#define CFG_MCFRTC_BASE (MMAP_RTC) + +#ifdef CONFIG_LCD +#define CFG_LCD_BASE (MMAP_LCD) +#endif + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CFG_UDELAY_BASE (MMAP_DTMR0) +#define CFG_TMR_BASE (MMAP_DTMR1) +#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0) +#define CFG_TMRINTR_NO (INT0_HI_DTMR1) +#define CFG_TMRINTR_MASK (INTC_IPRH_INT33) +#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK) +#define CFG_TMRINTR_PRI (6) +#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif + +#ifdef CONFIG_MCFPIT +#define CFG_UDELAY_BASE (MMAP_PIT0) +#define CFG_PIT_BASE (MMAP_PIT1) +#define CFG_PIT_PRESCALE (6) +#endif + +#define CFG_INTR_BASE (MMAP_INTC0) +#define CFG_NUM_IRQS (128) +#endif /* CONFIG_M52277 */ + #ifdef CONFIG_M5235 #include <asm/immap_5235.h> #include <asm/m5235.h> diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h new file mode 100644 index 0000000..ab574d5 --- /dev/null +++ b/include/configs/M52277EVB.h @@ -0,0 +1,251 @@ +/* + * Configuation settings for the Freescale MCF52277 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M52277EVB_H +#define _M52277EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5227x /* define processor family */ +#define CONFIG_M52277 /* define processor type */ +#define CONFIG_M52277EVB /* M52277EVB board */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#define CONFIG_CMD_REGINFO +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_BMP + +#define CONFIG_HOSTNAME M52277EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 0x3ffff;" \ + "era 0 3ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +/* LCD */ +#ifdef CONFIG_CMD_BMP +#define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_LCD_LOGO +#define CONFIG_SHARP_LQ035Q7DH06 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#define CFG_USB_EHCI_REGS_BASE 0xFC0B0000 +#define CFG_USB_EHCI_CPU_INIT +#endif + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CFG_INPUT_CLKSRC 16000000 + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x21 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x43711630 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x81810000 +#define CFG_SDRAM_MODE 0x00CD0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_BASE CFG_CS0_BASE +#define CFG_FLASH0_BASE CFG_CS0_BASE +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000) +#define CFG_ENV_SECT_SIZE 0x8000 + +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CONFIG_CMD_JFFS2 +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x40000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ + +#define CFG_CS0_BASE 0x00000000 +#define CFG_CS0_MASK 0x00FF0001 +#define CFG_CS0_CTRL 0x00001FA0 + +#endif /* _M52277EVB_H */ diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 43f97c4..9159206 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -313,6 +313,16 @@ board_init_f (ulong bootflag) debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); #endif /* CONFIG_PRAM */ + /* round down to next 4 kB limit */ + addr &= ~(4096 - 1); + debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + +#ifdef CONFIG_LCD + /* reserve memory for LCD display (always full pages) */ + addr = lcd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_LCD */ + /* * reserve memory for U-Boot code, data & bss * round down to next 4 kB limit -- 1.5.2

1 0

[U-Boot-Users] [PATCH] ColdFire: Add M5373EVB platform support - 2
by Tsi-Chung Liew 15 Jan '08

15 Jan '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- MAINTAINERS | 1 + MAKEALL | 3 +- Makefile | 10 ++ cpu/mcf532x/cpu.c | 20 +++- doc/README.m5373evb | 333 +++++++++++++++++++++++++++++++++++++++++ include/asm-m68k/immap.h | 4 +- include/asm-m68k/immap_5329.h | 89 +++++++++--- include/asm-m68k/m5329.h | 5 + include/configs/M5373EVB.h | 267 +++++++++++++++++++++++++++++++++ 9 files changed, 708 insertions(+), 24 deletions(-) create mode 100644 doc/README.m5373evb create mode 100644 include/configs/M5373EVB.h diff --git a/MAINTAINERS b/MAINTAINERS index 2ef2f5c..02698c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -629,6 +629,7 @@ TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> M5235EVB mcf52x2 M5329EVB mcf532x + M5373EVB mcf532x M54455EVB mcf5445x Hayden Fraser <Hayden.Fraser(a)freescale.com> diff --git a/MAKEALL b/MAKEALL index ebc5a22..1f59532 100755 --- a/MAKEALL +++ b/MAKEALL @@ -641,7 +641,8 @@ LIST_coldfire=" \ M5271EVB \ M5272C3 \ M5282EVB \ - M5329EVB \ + M5329AFEE \ + M5373EVB \ M54455EVB \ r5200 \ TASREG \ diff --git a/Makefile b/Makefile index 1983ca0..f541392 100644 --- a/Makefile +++ b/Makefile @@ -1793,6 +1793,16 @@ M5329BFEE_config : unconfig fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale +M5373EVB_config : unconfig + @case "$@" in \ + M5373EVB_config) NAND=16;; \ + esac; \ + >include/config.h ; \ + if [ "$${NAND}" != "0" ] ; then \ + echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale + M54455EVB_config \ M54455EVB_atmel_config \ M54455EVB_intel_config \ diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 89cc8ad..61541ab 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -64,6 +64,18 @@ int checkcpu(void) case 0x61: id = 5327; break; + case 0x65: + id = 5373; + break; + case 0x68: + id = 53721; + break; + case 0x69: + id = 5372; + break; + case 0x6B: + id = 5372; + break; } if (id) { @@ -84,6 +96,7 @@ void watchdog_reset(void) volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); wdp->sr = 0x5555; /* Count register */ + wdp->sr = 0xAAAA; /* Count register */ } int watchdog_disable(void) @@ -104,8 +117,11 @@ int watchdog_init(void) /* set timeout and enable watchdog */ wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); - wdog_module |= (wdog_module / 8192); - wdp->mr = wdog_module; +#ifdef CONFIG_M5329 + wdp->mr = (wdog_module / 8192); +#else + wdp->mr = (wdog_module / 4096); +#endif wdp->cr = WTM_WCR_EN; puts("WATCHDOG:enabled\n"); diff --git a/doc/README.m5373evb b/doc/README.m5373evb new file mode 100644 index 0000000..4f33b7d --- /dev/null +++ b/doc/README.m5373evb @@ -0,0 +1,333 @@ +Freescale MCF5373EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew(a)freescale.com) +Created 11/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m5373evb/m5373evb.c Dram setup +- board/freescale/m5373evb/mii.c Mii access +- board/freescale/m5373evb/Makefile Makefile +- board/freescale/m5373evb/config.mk config make +- board/freescale/m5373evb/u-boot.lds Linker description + +- cpu/mcf532x/cpu.c cpu specific code +- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- cpu/mcf532x/interrupts.c cpu specific interrupt support +- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf532x/Makefile Makefile +- cpu/mcf532x/config.mk config make +- cpu/mcf532x/start.S start up assembly code + +- doc/README.m5373evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_532x.h mcf532x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf532x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M5373EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +1 MCF5373 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M5373EVB Development Board +CONFIG_MCF532x -- define for all MCF532x CPUs +CONFIG_M5373 -- define for all Freescale MCF5373 CPUs +CONFIG_M5373EVB -- define for M5373EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CFG_DISCOVER_PHY -- enable PHY discovery +CFG_RX_ETH_BUFFER -- Set FEC Receive buffer +CFG_FAULT_ECHO_LINK_DOWN-- +CFG_FEC0_PINMUX -- Set FEC0 Pin configuration +CFG_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CFG_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5373EVB_config + make + +4. SCREEN DUMP +============== +4.1 M5373EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.0 (Nov 8 2007 - 12:44:08) + +CPU: Freescale MCF5373 (Mask:65 Version:1) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale FireEngine 5373 EVB +I2C: ready +DRAM: 32 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M5373EVB +netdev=eth0 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +u-boot=u-boot.bin +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 401/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x02000000 +flashstart = 0x00000000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +ethaddr = 00:E0:0C:BC:E5:60 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nand - NAND sub-system +nboot - boot from NAND device +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol +version - print monitor version +-> tftp 0x40800000 uImage +Using FEC0 device +TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'. +Load address: 0x40800000 +Loading: ################################################################# + ################################################################# + ########## +done +Bytes transferred = 2053270 (1f5496 hex) +-> bootm 0x40800000 +## Booting image at 40800000 ... + Image Name: Linux Kernel Image + Created: 2007-11-07 20:33:08 UTC + Image Type: M68K Linux Kernel Image (gzip compressed) + Data Size: 2053206 Bytes = 2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7 + + +uClinux/COLDFIRE(m537x) +COLDFIRE port done by Greg Ungerer, gerg(a)snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512 +NET: Registered protocol family 16 +USB-MCF537x: (HOST module) EHCI device is registered +USB-MCF537x: (OTG module) EHCI device is registered +USB-MCF537x: (OTG module) UDC device is registered +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +NET: Registered protocol family 2 +IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) +TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered +JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: module loaded +nbd: registered device at major 43 +usbcore: registered new interface driver ub FEC ENET Version 0.2 +fec: PHY @ 0x1, ID 0x20005c90 -- DP83848 +eth0: ethernet 00:e0:0c:bc:e5:60 +uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM": +0x00000000-0x0022b000 : "ROMfs" +uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit": +0x00000000-0x01000000 : "M53xx flash partition 1" +QSPI: spi->max_speed_hz 300000 +QSPI: Baud set to 255 +SPI: Coldfire master initialized +M537x - Disable UART1 when using Audio +udc: Freescale MCF53xx UDC driver version 27 October 2006 init +udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver +usbcore: registered new interface driver usbhid +drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems +mount: Mounting devpts on /dev/pts failed: No such device +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device: +Setting up networking on eth0: +info, udhcpc (v0.9.9-pre) started +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +debug, Sending discover... +debug, Sending discover... +debug, Sending select for 172.27.0.130... +info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers +route: SIOC[ADD|DEL]RT: No such process +adding dns 172.27.0.1 +Starting the boa webserver: +Setting time from ntp server: ntp.cs.strath.ac.uk +ntp.cs.strath.ac.uk: Unknown host + + +BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands. + +# diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 912753d..852d941 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -169,7 +169,7 @@ #endif #endif /* CONFIG_M5282 */ -#ifdef CONFIG_M5329 +#if defined(CONFIG_M5329) || defined(CONFIG_M5373) #include <asm/immap_5329.h> #include <asm/m5329.h> @@ -197,7 +197,7 @@ #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) -#endif /* CONFIG_M5329 */ +#endif /* CONFIG_M5329 && CONFIG_M5373 */ #ifdef CONFIG_M54455 #include <asm/immap_5445x.h> diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index 7ff0b93..7678406 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -378,91 +378,133 @@ typedef struct rcm { /* GPIO port registers */ typedef struct gpio_ctrl { /* Port Output Data Registers */ +#ifdef CONFIG_M5329 u8 podr_fech; /* 0x00 */ u8 podr_fecl; /* 0x01 */ +#else + u16 res00; /* 0x00 - 0x01 */ +#endif u8 podr_ssi; /* 0x02 */ u8 podr_busctl; /* 0x03 */ u8 podr_be; /* 0x04 */ u8 podr_cs; /* 0x05 */ u8 podr_pwm; /* 0x06 */ u8 podr_feci2c; /* 0x07 */ - u8 res1; /* 0x08 */ + u8 res08; /* 0x08 */ u8 podr_uart; /* 0x09 */ u8 podr_qspi; /* 0x0A */ u8 podr_timer; /* 0x0B */ - u8 res2; /* 0x0C */ +#ifdef CONFIG_M5329 + u8 res0C; /* 0x0C */ u8 podr_lcddatah; /* 0x0D */ u8 podr_lcddatam; /* 0x0E */ u8 podr_lcddatal; /* 0x0F */ u8 podr_lcdctlh; /* 0x10 */ u8 podr_lcdctll; /* 0x11 */ +#else + u16 res0C; /* 0x0C - 0x0D */ + u8 podr_fech; /* 0x0E */ + u8 podr_fecl; /* 0x0F */ + u16 res10[3]; /* 0x10 - 0x15 */ +#endif /* Port Data Direction Registers */ - u16 res3; /* 0x12 - 0x13 */ +#ifdef CONFIG_M5329 + u16 res12; /* 0x12 - 0x13 */ u8 pddr_fech; /* 0x14 */ u8 pddr_fecl; /* 0x15 */ +#endif u8 pddr_ssi; /* 0x16 */ u8 pddr_busctl; /* 0x17 */ u8 pddr_be; /* 0x18 */ u8 pddr_cs; /* 0x19 */ u8 pddr_pwm; /* 0x1A */ u8 pddr_feci2c; /* 0x1B */ - u8 res4; /* 0x1C */ + u8 res1C; /* 0x1C */ u8 pddr_uart; /* 0x1D */ u8 pddr_qspi; /* 0x1E */ u8 pddr_timer; /* 0x1F */ - u8 res5; /* 0x20 */ +#ifdef CONFIG_M5329 + u8 res20; /* 0x20 */ u8 pddr_lcddatah; /* 0x21 */ u8 pddr_lcddatam; /* 0x22 */ u8 pddr_lcddatal; /* 0x23 */ u8 pddr_lcdctlh; /* 0x24 */ u8 pddr_lcdctll; /* 0x25 */ - u16 res6; /* 0x26 - 0x27 */ + u16 res26; /* 0x26 - 0x27 */ +#else + u16 res20; /* 0x20 - 0x21 */ + u8 pddr_fech; /* 0x22 */ + u8 pddr_fecl; /* 0x23 */ + u16 res24[3]; /* 0x24 - 0x29 */ +#endif /* Port Data Direction Registers */ +#ifdef CONFIG_M5329 u8 ppd_fech; /* 0x28 */ u8 ppd_fecl; /* 0x29 */ +#endif u8 ppd_ssi; /* 0x2A */ u8 ppd_busctl; /* 0x2B */ u8 ppd_be; /* 0x2C */ u8 ppd_cs; /* 0x2D */ u8 ppd_pwm; /* 0x2E */ u8 ppd_feci2c; /* 0x2F */ - u8 res7; /* 0x30 */ + u8 res30; /* 0x30 */ u8 ppd_uart; /* 0x31 */ u8 ppd_qspi; /* 0x32 */ u8 ppd_timer; /* 0x33 */ - u8 res8; /* 0x34 */ +#ifdef CONFIG_M5329 + u8 res34; /* 0x34 */ u8 ppd_lcddatah; /* 0x35 */ u8 ppd_lcddatam; /* 0x36 */ u8 ppd_lcddatal; /* 0x37 */ u8 ppd_lcdctlh; /* 0x38 */ u8 ppd_lcdctll; /* 0x39 */ - u16 res9; /* 0x3A - 0x3B */ + u16 res3A; /* 0x3A - 0x3B */ +#else + u16 res34; /* 0x34 - 0x35 */ + u8 ppd_fech; /* 0x36 */ + u8 ppd_fecl; /* 0x37 */ + u16 res38[3]; /* 0x38 - 0x3D */ +#endif /* Port Clear Output Data Registers */ - u8 pclrr_fech; /* 0x3C */ - u8 pclrr_fecl; /* 0x3D */ +#ifdef CONFIG_M5329 + u8 res3C; /* 0x3C */ + u8 pclrr_fech; /* 0x3D */ + u8 pclrr_fecl; /* 0x3E */ +#else u8 pclrr_ssi; /* 0x3E */ +#endif u8 pclrr_busctl; /* 0x3F */ u8 pclrr_be; /* 0x40 */ u8 pclrr_cs; /* 0x41 */ u8 pclrr_pwm; /* 0x42 */ u8 pclrr_feci2c; /* 0x43 */ - u8 res10; /* 0x44 */ + u8 res44; /* 0x44 */ u8 pclrr_uart; /* 0x45 */ u8 pclrr_qspi; /* 0x46 */ u8 pclrr_timer; /* 0x47 */ - u8 res11; /* 0x48 */ - u8 pclrr_lcddatah; /* 0x49 */ - u8 pclrr_lcddatam; /* 0x4A */ - u8 pclrr_lcddatal; /* 0x4B */ +#ifdef CONFIG_M5329 + u8 pclrr_lcddatah; /* 0x48 */ + u8 pclrr_lcddatam; /* 0x49 */ + u8 pclrr_lcddatal; /* 0x4A */ + u8 pclrr_ssi; /* 0x4B */ u8 pclrr_lcdctlh; /* 0x4C */ u8 pclrr_lcdctll; /* 0x4D */ - u16 res12; /* 0x4E - 0x4F */ + u16 res4E; /* 0x4E - 0x4F */ +#else + u16 res48; /* 0x48 - 0x49 */ + u8 pclrr_fech; /* 0x4A */ + u8 pclrr_fecl; /* 0x4B */ + u8 res4C[5]; /* 0x4C - 0x50 */ +#endif /* Pin Assignment Registers */ +#ifdef CONFIG_M5329 u8 par_fec; /* 0x50 */ +#endif u8 par_pwm; /* 0x51 */ u8 par_busctl; /* 0x52 */ u8 par_feci2c; /* 0x53 */ @@ -472,15 +514,20 @@ typedef struct gpio_ctrl { u16 par_uart; /* 0x58 */ u16 par_qspi; /* 0x5A */ u8 par_timer; /* 0x5C */ +#ifdef CONFIG_M5329 u8 par_lcddata; /* 0x5D */ u16 par_lcdctl; /* 0x5E */ +#else + u8 par_fec; /* 0x5D */ + u16 res5E; /* 0x5E - 0x5F */ +#endif u16 par_irq; /* 0x60 */ - u16 res16; /* 0x62 - 0x63 */ + u16 res62; /* 0x62 - 0x63 */ /* Mode Select Control Registers */ u8 mscr_flexbus; /* 0x64 */ u8 mscr_sdram; /* 0x65 */ - u16 res17; /* 0x66 - 0x67 */ + u16 res66; /* 0x66 - 0x67 */ /* Drive Strength Control Registers */ u8 dscr_i2c; /* 0x68 */ @@ -490,7 +537,11 @@ typedef struct gpio_ctrl { u8 dscr_qspi; /* 0x6C */ u8 dscr_timer; /* 0x6D */ u8 dscr_ssi; /* 0x6E */ +#ifdef CONFIG_M5329 u8 dscr_lcd; /* 0x6F */ +#else + u8 res6F; /* 0x6F */ +#endif u8 dscr_debug; /* 0x70 */ u8 dscr_clkrst; /* 0x71 */ u8 dscr_irq; /* 0x72 */ diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h index 8316fcf..c1669dc 100644 --- a/include/asm-m68k/m5329.h +++ b/include/asm-m68k/m5329.h @@ -1118,6 +1118,7 @@ #define GPIO_PCLRR_LCDCTLL7 (0x80) /* Bit definitions and macros for GPIO_PAR_FEC */ +#ifdef CONFIG_M5329 #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) #define GPIO_PAR_FEC_7W_GPIO (0x00) @@ -1126,6 +1127,10 @@ #define GPIO_PAR_FEC_MII_GPIO (0x00) #define GPIO_PAR_FEC_MII_UART (0x01) #define GPIO_PAR_FEC_MII_FEC (0x03) +#else +#define GPIO_PAR_FEC_7W_FEC (0x08) +#define GPIO_PAR_FEC_MII_FEC (0x02) +#endif /* Bit definitions and macros for GPIO_PAR_PWM */ #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h new file mode 100644 index 0000000..6bfffa1 --- /dev/null +++ b/include/configs/M5373EVB.h @@ -0,0 +1,267 @@ +/* + * Configuation settings for the Freescale MCF5373 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5373EVB_H +#define _M5373EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef NANDFLASH_SIZE +# define CONFIG_CMD_NAND +#endif + +#define CFG_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5373EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#ifdef NANDFLASH_SIZE +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE CFG_CS2_BASE +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CFG_FLASH_BASE CFG_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x10000000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x20000000 +#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5373EVB_H */ -- 1.5.2

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[U-Boot-Users] [SH] Please pull git://www.denx.de/git/u-boot-sh.git/
by Nobuhiro Iwamatsu 15 Jan '08

15 Jan '08

The following changes since commit 5dd372a23d12003276dddf7f9604154fd522ae73: Wolfgang Denk (1): Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx are available in the git repository at: git://www.denx.de/git/u-boot-sh.git/ master Nobuhiro Iwamatsu (6): sh: Add MS7720SE to MAKEALL sh: Fix board name in MS7720SE's config.mk sh: Add maintainer of MS7720SE to the MAINTAINER file sh: Add support of map_physmem() and unmap_physmem() to SuperH sh: Add support SH7710/SH7712 pcmcia: Remove CONFIG_COMMANDS from marubun pcmcia driver Yoshihiro Shimoda (3): sh: Add support SH3 and SH7720 sh: Add support for SH7720 in serial_sh driver. sh: Add support for MS7720RP02 board MAINTAINERS | 4 + MAKEALL | 5 +- Makefile | 8 + board/ms7720se/Makefile | 51 ++++++++ board/ms7720se/config.mk | 34 +++++ board/ms7720se/lowlevel_init.S | 268 +++++++++++++++++++++++++++++++++++++++ board/ms7720se/ms7720se.c | 60 +++++++++ board/ms7720se/u-boot.lds | 108 ++++++++++++++++ cpu/sh3/Makefile | 49 +++++++ cpu/sh3/cache.c | 112 ++++++++++++++++ cpu/sh3/config.mk | 31 +++++ cpu/sh3/cpu.c | 84 ++++++++++++ cpu/sh3/interrupts.c | 42 ++++++ cpu/sh3/start.S | 77 +++++++++++ cpu/sh3/time.c | 103 +++++++++++++++ cpu/sh3/watchdog.c | 33 +++++ drivers/pcmcia/marubun_pcmcia.c | 6 +- drivers/serial/serial_sh.c | 36 ++++- include/asm-sh/cpu_sh3.h | 42 ++++++ include/asm-sh/cpu_sh7710.h | 64 +++++++++ include/asm-sh/cpu_sh7720.h | 207 ++++++++++++++++++++++++++++++ include/asm-sh/io.h | 27 ++++ include/configs/ms7720se.h | 134 +++++++++++++++++++ 23 files changed, 1574 insertions(+), 11 deletions(-) create mode 100644 board/ms7720se/Makefile create mode 100644 board/ms7720se/config.mk create mode 100644 board/ms7720se/lowlevel_init.S create mode 100644 board/ms7720se/ms7720se.c create mode 100644 board/ms7720se/u-boot.lds create mode 100644 cpu/sh3/Makefile create mode 100644 cpu/sh3/cache.c create mode 100644 cpu/sh3/config.mk create mode 100644 cpu/sh3/cpu.c create mode 100644 cpu/sh3/interrupts.c create mode 100644 cpu/sh3/start.S create mode 100644 cpu/sh3/time.c create mode 100644 cpu/sh3/watchdog.c create mode 100644 include/asm-sh/cpu_sh3.h create mode 100644 include/asm-sh/cpu_sh7710.h create mode 100644 include/asm-sh/cpu_sh7720.h create mode 100644 include/configs/ms7720se.h

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[U-Boot-Users] [PATCH] sh: Add support SH7710/SH7712
by Nobuhiro Iwamatsu 15 Jan '08

15 Jan '08

SH7710/SH7712 of SH3 CPU are supported. SH771X is called SH-Ether, and has the Ether controller in CPU. The driver of Ether is not included in this patch. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/serial/serial_sh.c | 31 ++++++++++----------- include/asm-sh/cpu_sh3.h | 4 ++- include/asm-sh/cpu_sh7710.h | 64 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+), 17 deletions(-) create mode 100644 include/asm-sh/cpu_sh7710.h diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index afba2d2..00a9b39 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -30,25 +30,20 @@ #error "Default SCIF doesn't set....." #endif -#if defined(CONFIG_SH3) -/* There are SH7720's register */ -#define SCSMR (volatile unsigned short *)(SCIF_BASE + 0x0) -#define SCBRR (volatile unsigned char *)(SCIF_BASE + 0x4) -#define SCSCR (volatile unsigned short *)(SCIF_BASE + 0x8) -#define SCFSR (volatile unsigned short *)(SCIF_BASE + 0x14) /* SCSSR */ -#define SCFCR (volatile unsigned short *)(SCIF_BASE + 0x18) -#define SCFDR (volatile unsigned short *)(SCIF_BASE + 0x1C) -#define SCFTDR (volatile unsigned char *)(SCIF_BASE + 0x20) -#define SCFRDR (volatile unsigned char *)(SCIF_BASE + 0x24) +/* Base register */ +#define SCSMR (vu_short *)(SCIF_BASE + 0x0) +#define SCBRR (vu_char *)(SCIF_BASE + 0x4) +#define SCSCR (vu_short *)(SCIF_BASE + 0x8) +#define SCFCR (vu_short *)(SCIF_BASE + 0x18) +#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) +#ifdef CONFIG_SH7720 /* SH7720 specific */ +#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#define SCSMR (vu_short *)(SCIF_BASE + 0x0) -#define SCBRR (vu_char *)(SCIF_BASE + 0x4) -#define SCSCR (vu_short *)(SCIF_BASE + 0x8) #define SCFTDR (vu_char *)(SCIF_BASE + 0xC) #define SCFSR (vu_short *)(SCIF_BASE + 0x10) #define SCFRDR (vu_char *)(SCIF_BASE + 0x14) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define SCFDR (vu_short *)(SCIF_BASE + 0x1C) #endif #if defined(CONFIG_SH4A) @@ -62,7 +57,11 @@ #define SCLSR (vu_short *)(SCIF_BASE + 0x24) #define LSR_ORER 1 #elif defined (CONFIG_SH3) -#define SCLSR SCFSR /* SCSSR */ +#ifdef CONFIG_SH7720 /* SH7720 specific */ +# define SCLSR SCFSR /* SCSSR */ +#else +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +#endif #define LSR_ORER 0x0200 #endif diff --git a/include/asm-sh/cpu_sh3.h b/include/asm-sh/cpu_sh3.h index 68679c0..6db38a2 100644 --- a/include/asm-sh/cpu_sh3.h +++ b/include/asm-sh/cpu_sh3.h @@ -31,7 +31,9 @@ #define CACHE_OC_NUM_ENTRIES 256 #define CACHE_OC_ENTRY_SHIFT 4 -#if defined(CONFIG_CPU_SH7720) +#if defined(CONFIG_CPU_SH7710) +#include <asm/cpu_sh7710.h> +#elif defined(CONFIG_CPU_SH7720) #include <asm/cpu_sh7720.h> #else #error "Unknown SH3 variant" diff --git a/include/asm-sh/cpu_sh7710.h b/include/asm-sh/cpu_sh7710.h new file mode 100644 index 0000000..e223f1c --- /dev/null +++ b/include/asm-sh/cpu_sh7710.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CPU_SH7710_H_ +#define _ASM_CPU_SH7710_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000000D + +/* MMU and Cache control */ +#define MMUCR 0xFFFFFFE0 +#define CCR 0xFFFFFFEC + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PETCR 0xA4050106 + +/* Port Data Registers */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 + +/* BSC */ +#define CMNCR 0xA4FD0000 +#define CS0BCR 0xA4FD0004 +#define CS2BCR 0xA4FD0008 +#define CS3BCR 0xA4FD000C +#define CS4BCR 0xA4FD0010 +#define CS5ABCR 0xA4FD0014 +#define CS5BBCR 0xA4FD0018 +#define CS6ABCR 0xA4FD001C +#define CS6BBCR 0xA4FD0020 +#define CS0WCR 0xA4FD0024 +#define CS2WCR 0xA4FD0028 +#define CS3WCR 0xA4FD002C +#define CS4WCR 0xA4FD0030 +#define CS5AWCR 0xA4FD0034 +#define CS5BWCR 0xA4FD0038 +#define CS6AWCR 0xA4FD003C +#define CS6BWCR 0xA4FD0040 + +/* SDRAM controller */ +#define SDCR 0xA4FD0044 +#define RTCSR 0xA4FD0048 +#define RTCNT 0xA4FD004C +#define RTCOR 0xA4FD0050 + +/* SCIF */ +#define SCSMR_0 0xA4400000 +#define SCIF0_BASE SCSMR_0 +#define SCSMR_0 0xA4410000 +#define SCIF1_BASE SCSMR_1 + +/* Timer */ +#define TSTR0 0xA412FE92 +#define TSTR TSTR0 +#define TCNT0 0xa412FE98 +#define TCR0 0xa412FE9C + +/* On chip oscillator circuits */ +#define FRQCR 0xA415FF80 +#define WTCNT 0xA415FF84 +#define WTCSR 0xA415FF86 + +#endif /* _ASM_CPU_SH7710_H_ */ -- 1.5.3.7

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[U-Boot-Users] [PATCH] sh: Add support of map_physmem() and unmap_physmem() to SuperH
by Nobuhiro Iwamatsu 15 Jan '08

15 Jan '08

This patch add the support of map_physmem() and unmap_physmem() used with Common Flash Interface(CFI) driver. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- include/asm-sh/io.h | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 03427ad..51fd10b 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -227,5 +227,32 @@ out: static inline void sync(void) { } + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +typedef unsigned long phys_addr_t; + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + #endif /* __KERNEL__ */ #endif /* __ASM_SH_IO_H */ -- 1.5.3.7

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[U-Boot-Users] [PATCH] sh: Add maintainer of MS7720SE to the MAINTAINER file
by Nobuhiro Iwamatsu 15 Jan '08

15 Jan '08

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- MAINTAINERS | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 40b2b51..239f5c3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -676,6 +676,10 @@ Nobuhiro Iwmaatsu <iwamatsu(a)nigauri.org> MS7750SE SH7750 MS7722SE SH7722 +Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> + + MS7720SE SH7720 + ######################################################################### # End of MAINTAINERS list # ######################################################################### -- 1.5.3.7

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