January 2008 - U-Boot

[U-Boot-Users] ygreoyg
by bouzera Ingrao 18 Jan '08

18 Jan '08

1 0

[U-Boot-Users] [PATCH v2 1/2] Add support for a Freescale non-CPM SPI controller
by Ben Warren 18 Jan '08

18 Jan '08

This patch adds support for the SPI controller found on Freescale PowerPC processors such as the MCP834x family. Additionally, a new config option, CONFIG_HARD_SPI, is added for general purpose SPI controller use. Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- Makefile | 2 + README | 8 +++ drivers/spi/Makefile | 46 ++++++++++++++ drivers/spi/mpc8xxx_spi.c | 138 +++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_83xx.h | 9 ++- include/asm-ppc/mpc8xxx_spi.h | 49 +++++++++++++++ lib_ppc/board.c | 16 +++++ 7 files changed, 264 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/Makefile create mode 100644 drivers/spi/mpc8xxx_spi.c create mode 100644 include/asm-ppc/mpc8xxx_spi.h diff --git a/Makefile b/Makefile index 1b3d2e6..8eb2a59 100644 --- a/Makefile +++ b/Makefile @@ -230,6 +230,7 @@ LIBS += drivers/net/libnet.a LIBS += drivers/net/sk98lin/libsk98lin.a LIBS += drivers/pci/libpci.a LIBS += drivers/pcmcia/libpcmcia.a +LIBS += drivers/spi/libspi.a ifeq ($(CPU),mpc83xx) LIBS += drivers/qe/qe.a endif @@ -377,6 +378,7 @@ TAG_SUBDIRS += drivers/pcmcia TAG_SUBDIRS += drivers/qe TAG_SUBDIRS += drivers/rtc TAG_SUBDIRS += drivers/serial +TAG_SUBDIRS += drivers/spi TAG_SUBDIRS += drivers/usb TAG_SUBDIRS += drivers/video diff --git a/README b/README index f2a4914..9a9e4de 100644 --- a/README +++ b/README @@ -1377,6 +1377,14 @@ The following options need to be configured: SPI configuration items (port pins to use, etc). For an example, see include/configs/sacsng.h. + CONFIG_HARD_SPI + + Enables a hardware SPI driver for general-purpose reads + and writes. As with CONFIG_SOFT_SPI, the board configuration + must define a list of chip-select function pointers. + Currently supported on some MPC8xxx processors. For an + example, see include/configs/mpc8349emds.h. + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile new file mode 100644 index 0000000..6b3898b --- /dev/null +++ b/drivers/spi/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libspi.a + +COBJS-y += mpc8xxx_spi.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c new file mode 100644 index 0000000..db29f84 --- /dev/null +++ b/drivers/spi/mpc8xxx_spi.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc. + * With help from the common/soft_spi and cpu/mpc8260 drivers + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi.h> +#include <asm/mpc8xxx_spi.h> + +#ifdef CONFIG_HARD_SPI + +#define SPI_EV_NE 0x80000000 >> 22 /* Receiver Not Empty */ +#define SPI_EV_NF 0x80000000 >> 23 /* Transmitter Not Full */ + +#define SPI_MODE_LOOP 0x80000000 >> 1 /* Loopback mode */ +#define SPI_MODE_REV 0x80000000 >> 5 /* Reverse mode - MSB first */ +#define SPI_MODE_MS 0x80000000 >> 6 /* Always master */ +#define SPI_MODE_EN 0x80000000 >> 7 /* Enable interface */ + +#define SPI_PRESCALER(reg, div) (reg)=((reg) & 0xfff0ffff) | ((div)<<16) +#define SPI_CHARLENGTH(reg, div) (reg)=((reg) & 0xff0fffff) | ((div)<<20) + +#define SPI_TIMEOUT 1000 + +void spi_init(void) +{ + volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; + + /* ------------------------------------------------ + * SPI pins on the MPC83xx are not muxed, so all we do is initialize + * some registers + * ------------------------------------------------ */ + spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; + SPI_PRESCALER(spi->mode, 1); /* Use SYSCLK / 8 (16.67MHz typ.) */ + spi->event = 0xffffffff; /* Clear all SPI events */ + spi->mask = 0x00000000; /* Mask all SPI interrupts */ + spi->com = 0; /* LST bit doesn't do anything, so disregard */ +} + +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar * dout, uchar * din) +{ + volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi; + unsigned int tmpdout, tmpdin, event; + int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0); + int tm, isRead = 0; + unsigned char charSize = 32; + + debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *) dout, *(uint *) din, bitlen); + + if (chipsel != NULL) + (*chipsel) (1); /* select the target chip */ + + spi->event = 0xffffffff; /* Clear all SPI events */ + + /* handle data in 32-bit chunks */ + while (numBlks--) { + tmpdout = 0; + charSize = (bitlen >= 32 ? 32 : bitlen); + + /* Shift data so it's msb-justified */ + tmpdout = *(u32 *) dout >> (32 - charSize); + + /* The LEN field of the SPMODE register is set as follows: + * + * Bit length setting + * l <= 4 3 + * 4 < l <= 16 l - 1 + * l > 16 0 + */ + + if (bitlen <= 16) + SPI_CHARLENGTH(spi->mode, bitlen <= 4 ? 3 : bitlen - 1); + else { + SPI_CHARLENGTH(spi->mode, 0); + /* Set up the next iteration if sending > 32 bits */ + bitlen -= 32; + dout += 4; + } + + spi->tx = tmpdout; /* Write the data out */ + debug("*** spi_xfer: ... %08x written\n", tmpdout); + + /* -------------------------------- + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * The NE event must be read and cleared first + * -------------------------------- */ + for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) { + event = spi->event; + if (event & SPI_EV_NE) { + tmpdin = spi->rx; + spi->event |= SPI_EV_NE; + isRead = 1; + + *(u32 *) din = (tmpdin << (32 - charSize)); + if (charSize == 32) { + /* Advance output buffer by 32 bits */ + din += 4; + } + } + /* Only bail when we've had both NE and NF events. + * This will cause timeouts on RO devices, so maybe + * in the future put an arbitrary delay after writing + * the device. Arbitrary delays suck, though... */ + if (isRead && (event & SPI_EV_NF)) + break; + } + if (tm >= SPI_TIMEOUT) + puts("*** spi_xfer: Time out during SPI transfer"); + + debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin); + } + + if (chipsel != NULL) + (*chipsel) (0); /* deselect the target chip */ + return 0; +} + +#endif /* CONFIG_HARD_SPI */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 34ea295..c16a098 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -30,6 +30,7 @@ #include <asm/types.h> #include <asm/fsl_i2c.h> +#include <asm/mpc8xxx_spi.h> /* * Local Access Window @@ -627,7 +628,7 @@ typedef struct immap { u8 res3[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res4[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ ios83xx_t ios; /* Sequencer */ @@ -661,7 +662,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; @@ -696,7 +697,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; @@ -741,7 +742,7 @@ typedef struct immap { u8 res2[0x900]; lbus83xx_t lbus; /* Local Bus Controller Registers */ u8 res3[0x1000]; - spi83xx_t spi; /* Serial Peripheral Interface */ + spi8xxx_t spi; /* Serial Peripheral Interface */ dma83xx_t dma; /* DMA */ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ u8 res4[0x80]; diff --git a/include/asm-ppc/mpc8xxx_spi.h b/include/asm-ppc/mpc8xxx_spi.h new file mode 100644 index 0000000..38f12b9 --- /dev/null +++ b/include/asm-ppc/mpc8xxx_spi.h @@ -0,0 +1,49 @@ +/* + * Freescale non-CPM SPI Controller + * + * Copyright 2008 Qstreams Networks, Inc. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_MPC8XXX_SPI_H_ +#define _ASM_MPC8XXX_SPI_H_ + +#include <asm/types.h> + +#if defined(CONFIG_MPC834X) || \ + defined(CONFIG_MPC8313) || \ + defined(CONFIG_MPC8315) || \ + defined(CONFIG_MPC837X) + +typedef struct spi8xxx +{ + u8 res0[0x20]; /* 0x0-0x01f reserved */ + u32 mode; /* mode register */ + u32 event; /* event register */ + u32 mask; /* mask register */ + u32 com; /* command register */ + u32 tx; /* transmit register */ + u32 rx; /* receive register */ + u8 res1[0xC8]; /* fill up to 0x100 */ +} spi8xxx_t; + +#endif + +#endif /* _ASM_MPC8XXX_SPI_H_ */ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 7b95246..8b4095c 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -87,6 +87,9 @@ void doc_init (void); defined(CONFIG_SOFT_I2C) #include <i2c.h> #endif +#if defined(CONFIG_HARD_SPI) +#include <spi.h> +#endif #if defined(CONFIG_CMD_NAND) void nand_init (void); #endif @@ -247,6 +250,16 @@ static int init_func_i2c (void) } #endif +#if defined(CONFIG_HARD_SPI) +static int init_func_spi (void) +{ + puts ("SPI: "); + spi_init (); + puts ("ready\n"); + return (0); +} +#endif + /***********************************************************************/ #if defined(CONFIG_WATCHDOG) @@ -329,6 +342,9 @@ init_fnc_t *init_sequence[] = { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) init_func_i2c, #endif +#if defined(CONFIG_HARD_SPI) + init_func_spi, +#endif #if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */ dtt_init, #endif -- 1.5.2.5

3 3

[U-Boot-Users] [PATCH] mpc86xx: Convert to using new law setup code
by Becky Bruce 18 Jan '08

18 Jan '08

This patch converts 86xx to the new law setup in C that Kumar posted recently. Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- board/freescale/mpc8641hpcn/Makefile | 2 +- board/freescale/mpc8641hpcn/law.c | 64 ++++++++++++++++++++++++++++++++++ cpu/mpc86xx/cpu_init.c | 7 ++++ cpu/mpc86xx/spd_sdram.c | 16 ++++++++- cpu/mpc86xx/start.S | 2 + include/configs/MPC8641HPCN.h | 1 + 6 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mpc8641hpcn/law.c diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 201da3e..e73e7ba 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o law.o SOBJS := init.o diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c new file mode 100644 index 0000000..245f420 --- /dev/null +++ b/board/freescale/mpc8641hpcn/law.c @@ -0,0 +1,64 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf800_0000 0xf80f_ffff CCSRBAR 1M + * 0xf810_0000 0xf81f_ffff PIXIS 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { +#if !defined(CONFIG_SPD_EEPROM) + SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), +#endif + SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(3, CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(5, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW_ENTRY(6, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW_ENTRY(7, (CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), +#if !defined(CONFIG_SPD_EEPROM) + SET_LAW_ENTRY(8, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), +#endif + SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4f8956e..ab5906d 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -49,6 +49,10 @@ void cpu_init_f(void) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); +#ifdef CONFIG_FSL_LAW + init_laws(); +#endif + /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary * addresses - these have to be modified later when FLASH size * has been determined @@ -114,5 +118,8 @@ void cpu_init_f(void) */ int cpu_init_r(void) { +#ifdef CONFIG_FSL_LAW + disable_law(0); +#endif return 0; } diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 54e40f1..bfea4b3 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -27,7 +27,7 @@ #include <i2c.h> #include <spd.h> #include <asm/mmu.h> - +#include <asm/fsl_law.h> #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void dma_init(void); @@ -1179,12 +1179,16 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV); +#else mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); mcm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR_INTERLEAVED | (LAWAR_SIZE & law_size_interleaved)); debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#endif debug("Interleaved memory size is 0x%08lx\n", memsize_total); #ifdef CONFIG_DDR_INTERLEAVE @@ -1239,12 +1243,16 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 1 space. */ +#ifdef CONFIG_FSL_LAW + set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1); +#else mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); mcm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & law_size_ddr1)); debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1); debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1); +#endif } #if (CONFIG_NUM_DDR_CONTROLLERS > 1) @@ -1269,6 +1277,11 @@ spd_sdram(void) /* * Set up LAWBAR for DDR 2 space. */ +#ifdef CONFIG_FSL_LAW + set_law(8, + (ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE), + law_size_ddr2, LAW_TRGT_IF_DDR_2); +#else if (ddr1_enabled) mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12) & 0xfffff); @@ -1280,6 +1293,7 @@ spd_sdram(void) | (LAWAR_SIZE & law_size_ddr2)); debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); +#endif } debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 6cf145f..99f96f8 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -283,8 +283,10 @@ in_flash: bl setup_ccsrbar #endif +#ifndef CONFIG_FSL_LAW bl law_entry sync +#endif /* run low-level CPU init code (from Flash) */ bl cpu_init_f diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ab875f0..be96696 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -49,6 +49,7 @@ #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -- 1.5.3.7

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[U-Boot-Users] [PATCH] mpc86xx: Rearrange start.S to allow use of new law code
by Becky Bruce 18 Jan '08

18 Jan '08

Rearrange start.S as follows: * split the BAT initialization so that only 2 BATs (for the boot page and stack) are programmed very early on. The rest are initialized later. * Move other BAT setup, ccsrbar setup, and law setup later in the code after translation has been enabled. These changes will facilitate the moving of law and BAT initialization to C code, and will aid with 36-bit physical addressing support. Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- cpu/mpc86xx/start.S | 122 +++++++++++++++++++++++++++++---------------------- 1 files changed, 69 insertions(+), 53 deletions(-) diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c83310a..6cf145f 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -235,17 +235,8 @@ in_flash: bl enable_ext_addr /* setup the bats */ - bl setup_bats - sync - -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) - /* setup ccsrbar */ - bl setup_ccsrbar -#endif + bl early_bats - /* setup the law entries */ - bl law_entry - sync /* * Cache must be enabled here for stack-in-cache trick. * This means we need to enable the BATS. @@ -281,6 +272,19 @@ in_flash: stwu r0, -4(r1) /* stack backtraces terminate cleanly */ GET_GOT /* initialize GOT access */ + + /* setup the rest of the bats */ + bl setup_bats + bl clear_tlbs + sync + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* setup ccsrbar */ + bl setup_ccsrbar +#endif + + bl law_entry + sync /* run low-level CPU init code (from Flash) */ bl cpu_init_f @@ -359,6 +363,7 @@ invalidate_bats: /* setup_bats - set them up to some initial state */ + /* Skip any BATS setup in early_bats */ .globl setup_bats setup_bats: @@ -454,42 +459,6 @@ setup_bats: mtspr DBAT4U, r3 isync - /* IBAT 5 */ - addis r4, r0, CFG_IBAT5L@h - ori r4, r4, CFG_IBAT5L@l - addis r3, r0, CFG_IBAT5U@h - ori r3, r3, CFG_IBAT5U@l - mtspr IBAT5L, r4 - mtspr IBAT5U, r3 - isync - - /* DBAT 5 */ - addis r4, r0, CFG_DBAT5L@h - ori r4, r4, CFG_DBAT5L@l - addis r3, r0, CFG_DBAT5U@h - ori r3, r3, CFG_DBAT5U@l - mtspr DBAT5L, r4 - mtspr DBAT5U, r3 - isync - - /* IBAT 6 */ - addis r4, r0, CFG_IBAT6L@h - ori r4, r4, CFG_IBAT6L@l - addis r3, r0, CFG_IBAT6U@h - ori r3, r3, CFG_IBAT6U@l - mtspr IBAT6L, r4 - mtspr IBAT6U, r3 - isync - - /* DBAT 6 */ - addis r4, r0, CFG_DBAT6L@h - ori r4, r4, CFG_DBAT6L@l - addis r3, r0, CFG_DBAT6U@h - ori r3, r3, CFG_DBAT6U@l - mtspr DBAT6L, r4 - mtspr DBAT6U, r3 - isync - /* IBAT 7 */ addis r4, r0, CFG_IBAT7L@h ori r4, r4, CFG_IBAT7L@l @@ -508,18 +477,65 @@ setup_bats: mtspr DBAT7U, r3 isync -1: - addis r3, 0, 0x0000 - addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */ + sync + blr + +/* + * early_bats: + * + * Set up bats needed early on - this is usually the BAT for the + * stack-in-cache and the Flash + */ + .globl early_bats +early_bats: + /* IBAT 5 */ + lis r4, CFG_IBAT5L@h + ori r4, r4, CFG_IBAT5L@l + lis r3, CFG_IBAT5U@h + ori r3, r3, CFG_IBAT5U@l + mtspr IBAT5L, r4 + mtspr IBAT5U, r3 isync + /* DBAT 5 */ + lis r4, CFG_DBAT5L@h + ori r4, r4, CFG_DBAT5L@l + lis r3, CFG_DBAT5U@h + ori r3, r3, CFG_DBAT5U@l + mtspr DBAT5L, r4 + mtspr DBAT5U, r3 + isync + + /* IBAT 6 */ + lis r4, CFG_IBAT6L@h + ori r4, r4, CFG_IBAT6L@l + lis r3, CFG_IBAT6U@h + ori r3, r3, CFG_IBAT6U@l + mtspr IBAT6L, r4 + mtspr IBAT6U, r3 + isync + + /* DBAT 6 */ + lis r4, CFG_DBAT6L@h + ori r4, r4, CFG_DBAT6L@l + lis r3, CFG_DBAT6U@h + ori r3, r3, CFG_DBAT6U@l + mtspr DBAT6L, r4 + mtspr DBAT6U, r3 + isync + blr + + .globl clear_tlbs +clear_tlbs: + addis r3, 0, 0x0000 + addis r5, 0, 0x4 + isync tlblp: - tlbie r3 + tlbie r3 sync - addi r3, r3, 0x1000 - cmp 0, 0, r3, r5 + addi r3, r3, 0x1000 + cmp 0, 0, r3, r5 blt tlblp - blr .globl enable_addr_trans -- 1.5.3.7

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[U-Boot-Users] Pull request: u-boot-ixp
by Jean-Christophe PLAGNIOL-VILLARD 18 Jan '08

18 Jan '08

Please pull u-boot-ixp The following changes since commit 74ac5facb988fc488a707db228b177ead63a6541: Wolfgang Denk (1): Merge branch 'inka4x0-ng' of /home/m8/git/u-boot/ are available in the git repository at: git://denx.de/git/u-boot-ixp.git master Jean-Christophe PLAGNIOL-VILLARD (4): Add missing file in gitignore and comments IXP: Add full baud-rate support for ixp42x, ixp45x and ixp46x ARM: support board-specific ethernet PHY init Allow CONFIG_AUTO_COMPLETE and command history CONFIG_CMDLINE_EDITING at the sametime Michael Schwingen (1): PATCH: load ixp42x NPE firmware from separate flash block, remove dead code .gitignore | 32 ++++++++++++++++++++++++++++++-- common/main.c | 26 ++++++++++++++++++++++++-- cpu/ixp/npe/IxNpeDl.c | 2 ++ cpu/ixp/npe/IxNpeDlImageMgr.c | 12 ++++++++---- cpu/ixp/serial.c | 24 ++++++++++-------------- include/.gitignore | 1 + lib_arm/board.c | 4 ++++ 7 files changed, 79 insertions(+), 22 deletions(-) Best Regards, J.

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18 Jan '08

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Re: [U-Boot-Users] [PATCH] ColdFire: Add MCF5275 cpu and M5275EVB support.
by Liew Tsi Chung 18 Jan '08

18 Jan '08

Matthew Do you test FEC, Timer and Flash work on this patch? Regards, TsiChung

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[U-Boot-Users] [PATCH] mpc83xx: Fix the fatal conflict of merge
by Dave Liu 17 Jan '08

17 Jan '08

The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 will cause the mpc8315erdb board can't boot up. The patch fix that bug, and remove the duplicated #ifdef CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for MPC8313E processor. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc83xx/cpu_init.c | 7 +------ cpu/mpc83xx/speed.c | 10 +++++----- include/mpc83xx.h | 10 +++------- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 3337d8c..e643037 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -73,11 +73,6 @@ void cpu_init_f (volatile immap_t * im) (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); #endif -#ifdef CFG_SPCR_TSECEP - /* eTSEC Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); -#endif - #ifdef CFG_ACR_RPTCNT /* Arbiter repeat count */ im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | @@ -85,7 +80,7 @@ void cpu_init_f (volatile immap_t * im) #endif #ifdef CFG_SPCR_TSECEP - /* all TSEC's Emergency priority */ + /* all eTSEC's Emergency priority */ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); #endif diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 61c9379..f598699 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -367,17 +367,17 @@ int get_clocks(void) #endif #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) { - case SCCR_SATACM_0: + switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { + case 0: sata_clk = 0; break; - case SCCR_SATACM_1: + case 1: sata_clk = csb_clk; break; - case SCCR_SATACM_2: + case 2: sata_clk = csb_clk / 2; break; - case SCCR_SATACM_3: + case 3: sata_clk = csb_clk / 3; break; default: diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 39cecf2..df052e3 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -725,6 +725,7 @@ #define SCCR_USBCM_3 0x00F00000 #elif defined(CONFIG_MPC8313) +/* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_0 0x00000000 @@ -732,13 +733,6 @@ #define SCCR_TSEC1CM_2 0x80000000 #define SCCR_TSEC1CM_3 0xC0000000 -#define SCCR_TSEC2CM 0x30000000 -#define SCCR_TSEC2CM_SHIFT 28 -#define SCCR_TSEC2CM_0 0x00000000 -#define SCCR_TSEC2CM_1 0x10000000 -#define SCCR_TSEC2CM_2 0x20000000 -#define SCCR_TSEC2CM_3 0x30000000 - #define SCCR_TSEC1ON 0x20000000 #define SCCR_TSEC1ON_SHIFT 29 #define SCCR_TSEC2ON 0x10000000 @@ -838,6 +832,8 @@ #define SCCR_PCIEXP2CM_3 0x000c0000 /* All of the four SATA controllers must have the same clock ratio */ +#define SCCR_SATA1CM 0x000000c0 +#define SCCR_SATA1CM_SHIFT 6 #define SCCR_SATACM 0x000000ff #define SCCR_SATACM_SHIFT 0 #define SCCR_SATACM_0 0x00000000 -- 1.5.3.5.643.g40e25

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[U-Boot-Users] RFC: new bootm syntax
by Bartlomiej Sieka 17 Jan '08

17 Jan '08

Hello, As part of adding support for the new uImage format, bootm command will be reworked quite a bit. Below is a note that summarizes bootm usage scenarios (present and planned), and defines extensions to bootm arguments' syntax. The note, or its portions, can be later on added to the tree as documentation. Comments and remarks will be much appreciated. TIA, Bartlomiej P.S. Syntax examples given are based on example .its files posted to the list by Marian Balakowicz on Wed, 19 Dec 2007 15:11:40 +0100 under "[U-Boot-Users] RFC: New uImage format bindings". New syntax for bootm ==================== As part of adding support for new uImage format, bootm command (and other commands as well) will have to understand new syntax of the arguments. This is necessary in order to specify objects contained in the new uImage, on which bootm has to operate. This note attempts to first summarize both current and future bootm usage scenarios, and then introduces new argument syntax. bootm usage scenarios --------------------- The following are the types of arguments to bootm: A address of old style single image B address of old style multi image (with two or three components) C address of new uImage D new uImage sub-image specification E new uImage configuration specification F address in memory Below is a summary of bootm usage scenarios, focused on booting a PowerPC Linux kernel. Some of the scenarios exist and are supported already, some will be extended/added along with the new uImage format. The purpose of the following list is to document a complete list of supported bootm usages. Note: U-Boot supports two methods of booting a PowerPC Linux kernel: old way, i.e., without passing the Flattened Device Tree (FDT), and new way, where the kernel is passed a pointer to the FDT. The boot method is indicated for each scenario. 1. bootm boot default image, equivalent to cases 2,3,8 Old uImage: 2. bootm A single image, kernel/standalone 3. bootm B multi image, kernel+initrd[+fdt] 4. bootm B - multi image, kernel[+fdt] 5. bootm A F single image, kernel+initrd/standalone+load_addr 6. bootm A F F single image, kernel+initrd+fdt 7. bootm A - F single image, kernel+fdt New uImage: 8. bootm C default configuration 9. bootm D kernel/standalone 10. bootm E specific configuration 11. bootm D D|F kernel+initrd/standalone+load_addr 12. bootm D D|F D|F kernel+initrd+fdt 13. bootm D - D|F kernel+fdt Additional remarks: Ad. 1. This is equivalent to cases 2,3,8, depending on what the default load address points to. - boot method: see cases 2,3,8 Ad. 2. If A is a kernel image, it is booted. If A is a standalone application image, it is loaded to the load address specified in the image, and started. - boot method: non-FDT Ad. 3. First and second components of B are assumed to be the kernel and the initrd, respectively. The kernel is booted with initrd. - boot method: depends on the number of components in B, and on whether U-Boot is compiled with OF support: | 2 components | 3 components | | (kernel, initrd) | (kernel, initrd, fdt) | --------------------------------------------------------------------- #ifdef CONFIG_OF_* | non-FDT | FDT | #ifndef CONFIG_OF_* | non-FDT | non-FDT | Ad. 4. Similar to case 3, but the kernel is booted without initrd. Second component of the multi image is irrelevant (it can be a dummy, 1-byte file). Note: currently, U-Boot compiled without OF support does not handle this case properly, this shall be fixed along with adding support for new uImage. - boot method: see case 3 Ad. 5. If A is a kernel image, then F is assumed to be an initrd address, and the kernel is booted with the initrd. If A is a standalone application image, F is assumed to be an address in memory that overrides load address specified in the image. Application is loaded to F and started. - boot method: non-FDT Ad. 6. A is assumed to be a kernel image. Arguments second and third are assumed to be addresses in memory of initrd and FDT, respectively. Kernel is booted with initrd. - boot method: FDT Ad. 7. A is assumed to be a kernel image and F is assumed to be FDT address in memory. Kernel is booted without initrd. - boot method: FDT Ad. 8. C is assumed to contain a default configuration, which is booted. - boot method: FDT or non-FDT, depending on whether the default configuration defines FDT Ad. 9. Equivalent to case 2, with the only difference being that the kernel/standalone application is given as a sub-image specification. - boot method: non-FDT Ad. 10. Boot configuration specified in E. - boot method: FDT or non-FDT, depending on whether the configuration given defines FDT Ad. 11. Equivalent to case 5. If the first argument is a kernel image, then the second one is assumed to define an initrd (either as a new uImage sub-image specification, or as a memory address), and the kernel is booted with the initrd. If the first argument is a standalone application, then the second argument should be an address in memory that overrides load address specified in the sub-image. Application is loaded to this new address and started. - boot method: non-FDT Ad. 12. Equivalent to case 6. D is assumed to define a kernel image. Arguments second and third are assumed to define initrd and FDT, respectively. Both initrd and FDT can be defined as either new uImage sub-image specification, or address in memory. Kernel is booted with initrd. - boot method: FDT Ad. 13. Equivalent to case 7. D is assumed to define a kernel image, and the third argument is assumed to define FDT (either as a new uImage sub-image specification, or as an address in memory). - boot method: FDT New argument syntax ------------------- New uImage support introduces two new forms for bootm arguments, with the following syntax: - D new uImage sub-image specification <addr>:<sub-image unit_name> - E new uImage configuration specification <addr>#<configuration unit_name> Examples: - boot kernel "kernel@1" stored in a new uImage located at 200000: bootm 200000:kernel@1 - boot configuration "cfg@1" from a new uImage located at 200000: bootm 200000#cfg@1 - boot "kernel@1" from a new uImage at 200000 with initrd "ramdisk@2" found in some other new uImage stored at address 800000: bootm 200000:kernel@1 800000:ramdisk@2 - boot "kernel@2" from a new uImage at 200000, with initrd "ramdisk@1" and FDT "fdt@1", both stored in some other new uImage located at 800000: bootm 200000:kernel@1 800000:ramdisk@1 800000:fdt@1 - boot kernel "kernel@2" with initrd "ramdisk@2", both stored in a new uImage at address 200000, with a raw FDT blob stored at address 600000: bootm 200000:kernel@2 200000:ramdisk@2 600000 - boot kernel "kernel@2" from new uImage at 200000 with FDT "fdt@1" from the same new uImage: bootm 200000:kernel@2 - 200000:fdt@1

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[U-Boot-Users] [PATCH v2 2/2] Implement hard SPI driver on MPC8349EMDS
by Ben Warren 17 Jan '08

17 Jan '08

This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board. This board has an ST M25P40 4Mbit EEPROM on its SPI bus Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- board/freescale/mpc8349emds/mpc8349emds.c | 29 +++++++++++++++++++++++++++++ include/configs/MPC8349EMDS.h | 10 ++++++++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 3d72eb7..3fb2a45 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -27,6 +27,7 @@ #include <mpc83xx.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#include <spi.h> #include <spd.h> #include <miiphy.h> #if defined(CONFIG_SPD_EEPROM) @@ -251,6 +252,34 @@ void sdram_init(void) } #endif +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_HARD_SPI + +#define SPI_CS_MASK 0x80000000 + +void spi_eeprom_chipsel(int cs) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + if(cs) + iopd->dat &= ~SPI_CS_MASK; + else + iopd->dat |= SPI_CS_MASK; +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_eeprom_chipsel, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#endif /* CONFIG_HARD_SPI */ + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 437a9a5..584c59d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,6 +355,16 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 +/* SPI */ +#define CONFIG_HARD_SPI /* SPI with hardware support*/ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ +#define CONFIG_FSL_SPI + +/* GPIOs. Used as SPI chip selects */ +#define CFG_GPIO1_PRELIM +#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -- 1.5.2.5

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