January 2008 - U-Boot

[U-Boot-Users] [PATCH 1/2] mpc85xx: Add support for SBC8548 (updated)
by Joe Hamman 09 Jan '08

09 Jan '08

Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman(a)embeddedspecialties.com> diff --git a/MAINTAINERS b/MAINTAINERS index b8c1fdc..ac11985 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -190,6 +190,7 @@ Howard Gray <mvsensor(a)matrix-vision.de> Joe Hamman <joe.hamman(a)embeddedspecialties.com> + sbc8548 MPC8548 sbc8641d MPC8641D Klaus Heydeck <heydeck(a)kieback-peter.de> diff --git a/MAKEALL b/MAKEALL index a02412b..bb97e2a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -328,6 +328,7 @@ LIST_85xx=" \ PM854 \ PM856 \ sbc8540 \ + sbc8548 \ sbc8560 \ stxgp3 \ stxssa \ diff --git a/Makefile b/Makefile index bde38ca..75841c0 100644 --- a/Makefile +++ b/Makefile @@ -1992,6 +1992,9 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 +sbc8548_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 + sbc8560_config \ sbc8560_33_config \ sbc8560_66_config: unconfig diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile new file mode 100644 index 0000000..1596525 --- /dev/null +++ b/board/sbc8548/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2004-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. +# Added support for Wind River SBC8560 board +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sbc8548/config.mk b/board/sbc8548/config.mk new file mode 100644 index 0000000..c9fa3ad --- /dev/null +++ b/board/sbc8548/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2004, 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# sbc8548 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S new file mode 100644 index 0000000..716057e --- /dev/null +++ b/board/sbc8548/init.S @@ -0,0 +1,247 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + .section .bootpg, "ax" + .globl tlb1_entry + +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xe4010000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff800000 16M TLB for 8MB FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Cacheable, non-guarded + * 0x0 256M DDR SDRAM + */ + #if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + #endif + + /* + * TLB 4: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Cacheable, non-guarded + * 0xf0000000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 16M Cacheable, non-guarded + * 0xf8000000 1M 7-segment LED display + * 0xf8100000 1M User switches + * 0xf8300000 1M Board revision + * 0xf8b00000 1M EEPROM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_EPLD_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_EPLD_BASE), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x0fff_ffff DDR 256M + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf8b0_0000 0xf80f_ffff EEPROM 1M + * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + + +#if !defined(CONFIG_SPD_EEPROM) + #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) + #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else + #define LAWBAR0 0 + #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 4 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + entry_end diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c new file mode 100644 index 0000000..7b44152 --- /dev/null +++ b/board/sbc8548/sbc8548.c @@ -0,0 +1,569 @@ +/* + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * + * Copyright 2004, 2007 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt <smcnutt(a)artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <spd.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram (void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + + printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", + (volatile)(*(u_char *)CFG_BD_REV) >> 4); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Fix CPU2 errata: A core hang possible while executing a + * msync instruction and a snoopable transaction from an I/O + * master tagged to make quick forward progress is present. + */ + ecm->eebpcr |= (1 << 16); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + ecm->eedr = 0xffffffff; /* clear ecm errors */ + ecm->eeer = 0xffffffff; /* enable ecm errors */ + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) + + uint idx; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or3 = CFG_OR3_PRELIM; + asm("msync"); + + lbc->br3 = CFG_BR3_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed_sdram init -- doesn't use serial presence detect. + * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. + ************************************************************************/ +long int fixed_sdram (void) +{ + #define CFG_DDR_CONTROL 0xc300c000 + + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = 0x0000007f; + ddr->cs1_bnds = 0x008000ff; + ddr->cs2_bnds = 0x00000000; + ddr->cs3_bnds = 0x00000000; + ddr->cs0_config = 0x80010101; + ddr->cs1_config = 0x80010101; + ddr->cs2_config = 0x00000000; + ddr->cs3_config = 0x00000000; + ddr->ext_refrec = 0x00000000; + ddr->timing_cfg_0 = 0x00220802; + ddr->timing_cfg_1 = 0x38377322; + ddr->timing_cfg_2 = 0x0fa044C7; + ddr->sdram_cfg = 0x4300C000; + ddr->sdram_cfg_2 = 0x24401000; + ddr->sdram_mode = 0x23C00542; + ddr->sdram_mode_2 = 0x00000000; + ddr->sdram_interval = 0x05080100; + ddr->sdram_md_cntl = 0x00000000; + ddr->sdram_data_init = 0x00000000; + ddr->sdram_clk_cntl = 0x03800000; + asm("sync;isync;msync"); + udelay(500); + + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif + +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. + */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } + +static struct pci_config_table pci_sbc8548_config_table[] = { + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, + mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, + mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, + mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, + mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, + mpc85xx_config_via_ac97, {0,0,0}}, + {}, +}; + +static struct pci_controller pci1_hose = { + config_table: pci_sbc8548_config_table}; +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +int first_free_busno=0; + +void +pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + struct pci_config_table *table; + + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333000) ? "33" : + (pci_speed == 66666000) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter" + ); + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + hose->region_count = 3; + + /* relocate config table pointers */ + hose->config_table = \ + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); + for (table = hose->config_table; table && table->vendor; table++) + table->config_device += gd->reloc_off; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + first_free_busno=hose->last_busno+1; + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + printf("PCI-X will only work at 66 MHz\n"); + + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); + } +#endif + } else { + printf (" PCI: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif + +#ifdef CONFIG_PCI2 +{ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } +} +#else + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ +#endif /* CONFIG_PCI2 */ + +#ifdef CONFIG_PCIE1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("\n PCIE connected to slot as %s (base address %x)", + pcie_ep ? "End Point" : "Root Complex", + (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); + } + printf ("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); + + first_free_busno=hose->last_busno+1; + + } else { + printf (" PCIE: disabled\n"); + } + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif + +} + +int last_stage_init(void) +{ + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_pci_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI1 + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif +#ifdef CONFIG_PCIE1 + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif +

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[U-Boot-Users] [PATCH] MPC8568E-MDS: reset UCCs to use them reliably
by Anton Vorontsov 09 Jan '08

09 Jan '08

In order to use GETH1 and GETH2 on the MPC8568E-MDS, we should reset UCCs. p.s Similar code exists in the Linux kernel board file (for capability reasons with older U-Boots), but should be removed some day. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/mpc8568mds/bcsr.c | 21 +++++++++++++++++++++ board/mpc8568mds/bcsr.h | 9 +++++++++ board/mpc8568mds/mpc8568mds.c | 3 +++ 3 files changed, 33 insertions(+), 0 deletions(-) diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c index aae0f98..791a50f 100644 --- a/board/mpc8568mds/bcsr.c +++ b/board/mpc8568mds/bcsr.c @@ -21,6 +21,8 @@ */ #include <common.h> +#include <asm/io.h> + #include "bcsr.h" void enable_8568mds_duart() @@ -54,3 +56,22 @@ void enable_8568mds_qe_mdio() bcsr[7] |= 0x01; } + +#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) +void reset_8568mds_uccs(void) +{ + volatile u8 *bcsr = (u8 *)(CFG_BCSR); + + /* Turn off UCC1 & UCC2 */ + out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); + out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN); + + /* Mode is RGMII, all bits clear */ + out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK | + BCSR_UCC2_MODE_MSK)); + + /* Turn UCC1 & UCC2 on */ + out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN); + out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN); +} +#endif diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h index aefd9bf..f7f70bc 100644 --- a/board/mpc8568mds/bcsr.h +++ b/board/mpc8568mds/bcsr.h @@ -90,6 +90,11 @@ 7 Flash write protect */ +#define BCSR_UCC1_GETH_EN (0x1 << 7) +#define BCSR_UCC2_GETH_EN (0x1 << 7) +#define BCSR_UCC1_MODE_MSK (0x3 << 4) +#define BCSR_UCC2_MODE_MSK (0x3 << 0) + /*BCSR Utils functions*/ void enable_8568mds_duart(void); @@ -97,4 +102,8 @@ void enable_8568mds_flash_write(void); void disable_8568mds_flash_write(void); void enable_8568mds_qe_mdio(void); +#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) +void reset_8568mds_uccs(void); +#endif + #endif /* __BCSR_H_ */ diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c index 818ff13..2b3f44f 100644 --- a/board/mpc8568mds/mpc8568mds.c +++ b/board/mpc8568mds/mpc8568mds.c @@ -106,6 +106,9 @@ int board_early_init_f (void) enable_8568mds_duart(); enable_8568mds_flash_write(); +#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) + reset_8568mds_uccs(); +#endif #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS) enable_8568mds_qe_mdio(); #endif -- 1.5.0.6

2 1

[U-Boot-Users] compilation problems with M5272C3
by David van Geest 09 Jan '08

09 Jan '08

Hi all, I'm trying to compile U-Boot for the M5272C3 board. I'm using m68k-elf-tools-20030314, and have downloaded u-boot using git clone git://www.denx.de/git/u-boot.git u-boot/ First, I run make distclean, that seems to work fine. Then I do the following: david@chiron:~/u-boot$ make M5272C3_config Configuring for M5272C3 board... david@chiron:~/u-boot$ make Generating include/autoconf.mk m68k-elf-gcc: /home/david/u-boot/include/autoconf.mk: No such file or directory m68k-elf-gcc: unrecognized option `-MQ' m68k-elf-gcc: Compilation of header file requested for dir in tools examples ; do make -C $dir _depend ; done make[1]: Entering directory `/home/david/u-boot/tools' ln -s ../common/environment.c environment.c ln -s ../lib_generic/crc32.c crc32.c ln -s ../lib_generic/sha1.c sha1.c make[1]: Leaving directory `/home/david/u-boot/tools' make[1]: Entering directory `/home/david/u-boot/tools' make[1]: Nothing to be done for `_depend'. make[1]: Leaving directory `/home/david/u-boot/tools' make[1]: Entering directory `/home/david/u-boot/examples' m68k-elf-gcc: hello_world.o: No such file or directory m68k-elf-gcc: unrecognized option `-MQ' m68k-elf-gcc: stubs.o: No such file or directory m68k-elf-gcc: unrecognized option `-MQ' make[1]: *** No rule to make target `.depend', needed by `_depend'. Stop. make[1]: Leaving directory `/home/david/u-boot/examples' make: *** [depend] Error 2 Any ideas on what's going on here? Do I need a different version of the m68k-elf-tools? Thanks, -David van Geest [ Rhythm Reloaded ] www.rhythmreloaded.com

2 2

[U-Boot-Users] [PATCH] mpc83xx: UEC: add support for Broadcom BCM5481 Gigabit PHY
by Anton Vorontsov 09 Jan '08

09 Jan '08

This patch adds basic support for Broadcom BCM5481 PHY, with the quirk needed for at least MPC8360E-RDK. Quirk comes from MPC8360E-RDK BSP source, I think author is Peter Barada <peterb(a)logicpd.com>, but I'm not sure. There are no openly available specifications for that PHY. Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- drivers/qe/uec_phy.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/qe/uec_phy.h | 5 +++ 2 files changed, 82 insertions(+), 0 deletions(-) diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index ca6faa6..6882d03 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -237,6 +237,44 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info) return 0; } +static int gbit_read_status(struct uec_mii_info *mii_info) +{ + u16 status; + int err; + + err = genmii_update_link(mii_info); + if (err) + return err; + + if (mii_info->autoneg) { + mii_info->pause = 0; + status = phy_read(mii_info, MII_1000BASETSTATUS); + if (status & (LPA_1000FULL | LPA_1000HALF)) { + mii_info->speed = SPEED_1000; + if (status & LPA_1000FULL) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + } else { + status = phy_read(mii_info, PHY_ANLPAR); + + if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + mii_info->duplex = DUPLEX_FULL; + else + mii_info->duplex = DUPLEX_HALF; + if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) + mii_info->speed = SPEED_100; + else + mii_info->speed = SPEED_10; + } + } + /* + * On non-aneg, we assume what we put in BMCR is the speed, + * though magic-aneg shouldn't prevent this case from occurring. + */ + return 0; +} + static int marvell_config_aneg (struct uec_mii_info *mii_info) { /* The Marvell PHY has an errata which requires @@ -319,6 +357,35 @@ static int genmii_read_status (struct uec_mii_info *mii_info) return 0; } +static int bcm_init(struct uec_mii_info *mii_info) +{ + gbit_config_aneg(mii_info); + +#ifdef CONFIG_MPC8360ERDK + { + u16 val; + int cnt = 50; + + /* Wait for aneg to complete. */ + do + val = phy_read(mii_info, PHY_BMSR); + while (--cnt && !(val & PHY_BMSR_AUTN_COMP)); + + /* Set RDX clk delay. */ + phy_write(mii_info, 0x18, 0x7 | (7 << 12)); + + val = phy_read(mii_info, 0x18); + /* Set RDX-RXC skew. */ + val |= (1<<8); + val |= (7 | (7 << 12)); + /* Write bits 14:0. */ + val |= (1<<15); + phy_write(mii_info, 0x18, val); + } +#endif + return 0; +} + static int marvell_read_status (struct uec_mii_info *mii_info) { u16 status; @@ -491,6 +558,15 @@ static struct phy_info phy_info_marvell = { .config_intr = &marvell_config_intr, }; +static struct phy_info phy_info_bcm5481 = { + .phy_id = 0x0143bca0, + .phy_id_mask = 0xffffff0, + .name = "Broadcom 5481", + .features = MII_GBIT_FEATURES, + .read_status = gbit_read_status, + .init = bcm_init, +}; + static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -504,6 +580,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161, &phy_info_dm9161a, &phy_info_marvell, + &phy_info_bcm5481, &phy_info_genmii, NULL }; diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h index e59a940..6f769fb 100644 --- a/drivers/qe/uec_phy.h +++ b/drivers/qe/uec_phy.h @@ -29,6 +29,11 @@ #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 +/* 1000BT status */ +#define MII_1000BASETSTATUS 0x0a +#define LPA_1000FULL 0x0400 +#define LPA_1000HALF 0x0200 + /* Cicada Extended Control Register 1 */ #define MII_CIS8201_EXT_CON1 0x17 #define MII_CIS8201_EXTCON1_INIT 0x0000 -- 1.5.2.2

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[U-Boot-Users] [PATCH resending] Align the QE UEC driver with commit 505be87
by Emil Medve 08 Jan '08

08 Jan '08

Commit 505be87 - NET: Proper return code handling in eth_init() function in file eth.c Signed-off-by: Emil Medve <Emilian.Medve(a)Freescale.com> --- Resending as the previous e-mail had a bad header drivers/qe/uec.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index dc2765b..d7d7ccc 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return 0; + return -EINVAL; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return 0; + return err; } - return uec->mii_info->link; + return !uec->mii_info->link; } static void uec_halt(struct eth_device* dev) -- 1.5.4-rc2.GIT

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[U-Boot-Users] [PATCH] Fix Ethernet init() return codes
by Ben Warren 08 Jan '08

08 Jan '08

Change return values of init() functions in all Ethernet drivers to conform to the following: >=0: Success <0: Failure All drivers going forward should return 0 on success. Current drivers that return 1 on success were left as-is to minimize changes. Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- cpu/ixp/npe/npe.c | 8 ++++---- cpu/mpc8xx/fec.c | 6 +++--- drivers/net/dc2114x.c | 4 ++-- drivers/net/eepro100.c | 4 ++-- drivers/net/macb.c | 4 ++-- drivers/net/pcnet.c | 4 ++-- drivers/net/rtl8139.c | 4 ++-- drivers/net/rtl8169.c | 5 +++-- drivers/net/tsec.c | 2 +- drivers/net/tsi108_eth.c | 4 ++-- drivers/net/uli526x.c | 6 +++--- net/eth.c | 2 +- 12 files changed, 27 insertions(+), 26 deletions(-) diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 7e4af44..a33b956 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -408,25 +408,25 @@ static int npe_init(struct eth_device *dev, bd_t * bis) if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register RX callback!\n"); - return 0; + return -1; } if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register TX callback!\n"); - return 0; + return -1; } npe_set_mac_address(dev); if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { printf("can't enable port!\n"); - return 0; + return -1; } p_npe->active = 1; - return 1; + return 0; } #if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 08a3715..1fd4d4e 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -588,7 +588,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) } if (i == FEC_RESET_DELAY) { printf ("FEC_RESET_DELAY timeout\n"); - return 0; + return -1; } /* We use strictly polling mode only @@ -708,7 +708,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) if (efis->actual_phy_addr == -1) { printf ("Unable to discover phy!\n"); - return 0; + return -1; } #else efis->actual_phy_addr = -1; @@ -751,7 +751,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) efis->initialized = 1; - return 1; + return 0; } diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index d5275dc..7238922 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -332,7 +332,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { printf("Error: Cannot reset ethernet controller.\n"); - return 0; + return -1; } #ifdef CONFIG_TULIP_SELECT_MEDIA @@ -382,7 +382,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis) send_setup_frame(dev, bis); - return 1; + return 0; } static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 738146e..96ed271 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -485,7 +485,7 @@ int eepro100_initialize (bd_t * bis) static int eepro100_init (struct eth_device *dev, bd_t * bis) { - int i, status = 0; + int i, status = -1; int tx_cur; struct descriptor *ias_cmd, *cfg_cmd; @@ -598,7 +598,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis) goto Done; } - status = 1; + status = 0; Done: return status; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 95cdc49..6657d22 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -423,12 +423,12 @@ static int macb_init(struct eth_device *netdev, bd_t *bd) #endif if (!macb_phy_init(macb)) - return 0; + return -1; /* Enable TX and RX */ macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); - return 1; + return 0; } static void macb_halt(struct eth_device *netdev) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 2af0e8f..4e270c9 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -402,7 +402,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis) if (i <= 0) { printf("%s: TIMEOUT: controller init failed\n", dev->name); pcnet_reset (dev); - return 0; + return -1; } /* @@ -410,7 +410,7 @@ static int pcnet_init(struct eth_device* dev, bd_t *bis) */ pcnet_write_csr (dev, 0, 0x0002); - return 1; + return 0; } static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 2367180..4c24805 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -273,10 +273,10 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) if (inb(ioaddr + MediaStatus) & MSRLinkFail) { printf("Cable not connected or other link failure\n"); - return(0); + return -1 ; } - return 1; + return 0; } /* Serial EEPROM section. */ diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 63ea2cc..0c9a401 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -620,7 +620,7 @@ static void rtl8169_init_ring(struct eth_device *dev) /************************************************************************** RESET - Finish setting up the ethernet interface ***************************************************************************/ -static void rtl_reset(struct eth_device *dev, bd_t *bis) +static int rtl_reset(struct eth_device *dev, bd_t *bis) { int i; u8 diff; @@ -649,7 +649,7 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis) if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { puts("Allocate RxDescArray or TxDescArray failed\n"); - return; + return -1; } rtl8169_init_ring(dev); @@ -669,6 +669,7 @@ static void rtl_reset(struct eth_device *dev, bd_t *bis) #ifdef DEBUG_RTL8169 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); #endif + return 0; } /************************************************************************** diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ca6284b..c1a2f07 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -232,7 +232,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) startup_tsec(dev); /* If there's no link, fail */ - return priv->link; + return (priv->link ? 0 : -1); } diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index 524e9da..a09115e 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -792,7 +792,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) (dev->enetaddr[0] << 16); if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) - return 0; + return -1; value = MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC | @@ -864,7 +864,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis) /* enable TX queue */ reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01; - return 1; + return 0; } /* diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 1267c57..8460f69 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -279,12 +279,12 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis) db->desc_pool_ptr = (uchar *)&desc_pool_array[0]; db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0]; if (db->desc_pool_ptr == NULL) - return 0; + return -1; db->buf_pool_ptr = &buf_pool[0]; db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0]; if (db->buf_pool_ptr == NULL) - return 0; + return -1; db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; db->first_tx_desc_dma = db->desc_pool_dma_ptr; @@ -331,7 +331,7 @@ static int uli526x_init_one(struct eth_device *dev, bd_t *bis) db->cr6_data |= ULI526X_TXTH_256; db->cr0_data = CR0_DEFAULT; uli526x_init(dev); - return 1; + return 0; } static void uli526x_disable(struct eth_device *dev) diff --git a/net/eth.c b/net/eth.c index 3373a05..92a91a1 100644 --- a/net/eth.c +++ b/net/eth.c @@ -430,7 +430,7 @@ int eth_init(bd_t *bis) do { debug ("Trying %s\n", eth_current->name); - if (!eth_current->init(eth_current,bis)) { + if (eth_current->init(eth_current,bis) >= 0) { eth_current->state = ETH_STATE_ACTIVE; return 0; -- 1.5.2.5

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[U-Boot-Users] Latest U-Boot breaks 83xx ethernet
by Timur Tabi 08 Jan '08

08 Jan '08

I've tried this on 8323E-MDS and an 8360E-MDS, so maybe it's only a QE thing, but the latest U-Boot from denx.de breaks Ethernet. Anyone else see this? U-Boot 1.3.1-281-g74ac5fac-dirty (Jan 8 2008 - 15:29:39) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c2, MPC8323E, Rev: 11 at 264 MHz, CSB: 132 MHz Board: Freescale MPC832XEMDS I2C: ready DRAM: 128 MB FLASH: 16 MB In: serial Out: serial Err: serial Net: UEC: PHY is Davicom DM9161A (181b8a0) FSL UEC0: Full Duplex FSL UEC0: Speed 100BT FSL UEC0: Link is up UEC: PHY is Davicom DM9161A (181b8a0) FSL UEC0, FSL UEC1 => ping $serverip Using FSL UEC1 device ping failed; host 192.168.1.1 is not alive -- Timur Tabi Linux kernel developer at Freescale

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[U-Boot-Users] [PATCH] NET: Proper return code handling in eth_init() function in file eth.c
by Upakul Barkakaty 08 Jan '08

08 Jan '08

NET: Proper return code handling in eth_init() function in file eth.c This patch modifies the return code handling in the eth_init() function, to be compatible with the handling of the return codes in the other network stack files. It now returns a 0 on Success and -1 on error. Signed-off-by: Upakul Barkakaty <upakul.barkakaty(a)conexant.com> diff -Naur a/net/eth.c b/net/eth.c --- a/net/eth.c 2007-11-26 09:53:55.000000000 +0530 +++ b/net/eth.c 2007-11-26 10:55:59.000000000 +0530 @@ -404,23 +404,23 @@ struct eth_device* old_current; if (!eth_current) - return 0; + return -1; old_current = eth_current; do { debug ("Trying %s\n", eth_current->name); - if (eth_current->init(eth_current, bis)) { + if (!eth_current->init(eth_current,bis)) + { eth_current->state = ETH_STATE_ACTIVE; - - return 1; + return 0; } debug ("FAIL\n"); eth_try_another(0); } while (old_current != eth_current); - return 0; + return -1; } void eth_halt(void)

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[U-Boot-Users] [PATCH] Align the QE UEC driver with commit
by Emil Medve 08 Jan '08

08 Jan '08

Signed-off-by: Emil Medve <Emilian.Medve(a)Freescale.com> --- drivers/qe/uec.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index dc2765b..d7d7ccc 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __FUNCTION__); - return 0; + return -EINVAL; } uec_set_mac_address(uec, dev->enetaddr); uec->the_first_run = 1; @@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd) err = uec_open(uec, COMM_DIR_RX_AND_TX); if (err) { printf("%s: cannot enable UEC device\n", dev->name); - return 0; + return err; } - return uec->mii_info->link; + return !uec->mii_info->link; } static void uec_halt(struct eth_device* dev) -- 1.5.4-rc2.GIT

1 0

[U-Boot-Users] Do we enable Interrupts in U-Boot?
by Chetan Nanda 08 Jan '08

08 Jan '08

Hi All, I am using a custom board (similar to MALTA) with MIPS - 4KEC processor on it. I use u-boot to load linux on our board. My Question is : Do we enable interrupt in u-boot code for UART and ETHERNET or we have running in Polling Mode? Thanks, nandac

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