January 2008 - U-Boot

[U-Boot-Users] How to define CONFIG_OF_FLAT_TREE?
by jie han 10 Jan '08

10 Jan '08

I define CONFIG_OF_FLAT_TREE support under u-boot.I just want to know how can I get/set the third address(the address of the device-tree blob) that we will use at bootm command?Thanks ahead, Sincerely, Jie --------------------------------- Never miss a thing. Make Yahoo your homepage.

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[U-Boot-Users] Email size limit
by Liew Tsi Chung 10 Jan '08

10 Jan '08

Wolfgang, Is the mailing list still limit to 40KB or 100KB? Thanks. Regards, TsiChung

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[U-Boot-Users] [PATCH] 86xx: Support 2GB DIMMs
by Jon Loeliger 10 Jan '08

10 Jan '08

From: Becky Bruce <bgill(a)freescale.com> Configure the number of bits used to address the banks inside the SDRAM device. The default register value of 0 means 2 bits to address 4 banks. Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks. Signed-off-by: Becky Bruce <bgill(a)freescale.com> --- cpu/mpc86xx/spd_sdram.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 265e033..54e40f1 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -196,7 +196,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -321,6 +321,10 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + #ifdef CONFIG_DDR_INTERLEAVE if (dimm_num != 1) { @@ -357,6 +361,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, #endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -386,6 +391,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -403,6 +409,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs1_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); @@ -422,6 +429,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs2_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -439,6 +447,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs3_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds); -- 1.5.2.1.126.g6abd0

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[U-Boot-Users] [Patch]resubmit PPC440EPx: Make Sequoia boot vxWorks
by Niklaus Giger 10 Jan '08

10 Jan '08

Signed-off-by: Niklaus Giger <niklaus.giger(a)netstal.com> --- vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) board/amcc/sequoia/init.S | 26 ++++++++++++++------------ include/configs/sequoia.h | 1 + 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index ff6ae66..306c92c 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -39,15 +39,8 @@ tlbtab: tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ -#ifndef CONFIG_NAND_SPL - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) -#else - tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) -#endif + /* vxWorks needs this as first entry for the Machine Check interrupt */ + tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE @@ -56,6 +49,18 @@ tlbtab: tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif + /* TLB-entry for EBC */ + tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + + /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ +#ifndef CONFIG_NAND_SPL + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) +#else + tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) +#endif + #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) @@ -67,9 +72,6 @@ tlbtab: tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) - /* TLB-entry for EBC */ - tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - /* TLB-entry for NAND */ tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 8929134..056c288 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -61,6 +61,7 @@ #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_TLB_FOR_BOOT_FLASH 0x0003 #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -- 1.5.2.5

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[U-Boot-Users] [PATCH] ppc4xx: Fix dflush() to restore DVLIM register
by Larry Johnson 10 Jan '08

10 Jan '08

Signed-off-by: Larry Johnson <lrj(a)acm.org> --- cpu/ppc4xx/start.S | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a730604..77c2aa4 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1700,6 +1700,7 @@ trap_reloc: rlwinm r8,r9,0,15,13 rlwinm r8,r8,0,17,15 mtmsr r8 + mfspr r8,dvlim addi r3,r0,0x0000 mtspr dvlim,r3 mfspr r3,ivpr @@ -1714,6 +1715,7 @@ trap_reloc: ..ag: dcbf r0,r3 addi r3,r3,-32 bdnz ..ag + mtspr dvlim,r8 sync mtmsr r9 blr

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[U-Boot-Users] [PATCH 0/8] bug fix for 83xx and common
by Dave Liu 10 Jan '08

10 Jan '08

Hello Kim and Wolfgang, Because Kim's tree has not update from main tree, so I'm based on the main tree. Kim, could you pick up these patch to your tree? if you can not, Wolfgang, would you like merge to main tree? Thanks, Dave The following changes since commit 422b1a01602b6e2fbf8444a1192c7ba31461fd4c of http://www.denx.de/git/u-boot.git [PATCH 1/8] common: Suppress the warning 'p_buf' [PATCH 2/8] mpc83xx: Remove cache config from config.h [PATCH 3/8] mpc83xx: Fix the typo in global data struct [PATCH 4/8] mpc83xx: Fix the typo in mpc83xx.h [PATCH 5/8] mpc83xx: Fix the wrong definition of MPC8315E [PATCH 6/8] mpc83xx: Reduce the latency of DDR [PATCH 7/8] mpc83xx: Make the code more readable [PATCH 8/8] mpc83xx: Fix the bug of 266MHz data rate DDR

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[U-Boot-Users] [PATCH 8/8] mpc83xx: Fix the bug of 266MHz data rate DDR
by Dave Liu 10 Jan '08

10 Jan '08

The DDR doesn't work on the 266MHz data rate, the patch fix the bug. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- cpu/mpc83xx/spd_sdram.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 29dd470..0acca47 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -574,9 +574,9 @@ long int spd_sdram() */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { - cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { + if (effective_data_rate == 266) { + cpo = 0x4; /* READ_LAT + 1/2 */ + } else if (effective_data_rate == 333 || effective_data_rate == 400) { cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ -- 1.5.3.5.643.g40e25

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[U-Boot-Users] [PATCH 7/8] mpc83xx: Make the code more readable
by Dave Liu 10 Jan '08

10 Jan '08

Format the code, make it more readable Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC837XEMDS.h | 19 +++++++++++++------ 1 files changed, 13 insertions(+), 6 deletions(-) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 0b4e562..2b84e9c 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -227,12 +227,19 @@ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ + | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ + | BR_V ) /* valid */ +#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_0b11 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD ) + /* 0xFE000FF7 */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ -- 1.5.3.5.643.g40e25

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[U-Boot-Users] [PATCH 6/8] mpc83xx: Reduce the latency of DDR
by Dave Liu 10 Jan '08

10 Jan '08

Reduce the AL from 2 to 1 clock to improve the performance. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC837XEMDS.h | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 46fc239..0b4e562 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -132,7 +132,7 @@ #else /* * Manually set up DDR parameters - * WHITE ELECTRONIC DESGGNS - W3HG64M72EEU403PD4 SO-DIMM + * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 */ #define CFG_DDR_SIZE 512 /* MB */ @@ -160,22 +160,22 @@ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) /* 0x3935d322 */ -#define CFG_DDR_TIMING_2 ( ( 2 << TIMING_CFG2_ADD_LAT_SHIFT ) \ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) - /* 0x231088c8 */ + /* 0x131088c8 */ #define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) /* 0x03E00100 */ #define CFG_DDR_SDRAM_CFG 0x43000000 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CFG_DDR_MODE ( ( 0x0450 << SDRAM_MODE_ESD_SHIFT ) \ +#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) - /* ODT 150ohm CL=3, AL=2 on SDRAM */ + /* ODT 150ohm CL=3, AL=1 on SDRAM */ #define CFG_DDR_MODE2 0x00000000 #endif -- 1.5.3.5.643.g40e25

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[U-Boot-Users] [PATCH 5/8] mpc83xx: Fix the wrong definition of MPC8315E
by Dave Liu 10 Jan '08

10 Jan '08

According to the latest user manual of MPC8315E, 1) The SVCOD of HRCWL is different than 837x 2) The SCCR has changes Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/mpc83xx.h | 48 ++++++++++++++++++++++++++++-------------------- 1 files changed, 28 insertions(+), 20 deletions(-) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 119f8b1..7299ca0 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -486,7 +486,15 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) +#elif defined(CONFIG_MPC8315) +#define HRCWL_SVCOD 0x30000000 +#define HRCWL_SVCOD_SHIFT 28 +#define HRCWL_SVCOD_DIV_2 0x00000000 +#define HRCWL_SVCOD_DIV_4 0x10000000 +#define HRCWL_SVCOD_DIV_8 0x20000000 +#define HRCWL_SVCOD_DIV_1 0x30000000 + +#elif defined(CONFIG_MPC837X) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -752,31 +760,31 @@ #define SCCR_TSEC2CM_2 0x20000000 #define SCCR_TSEC2CM_3 0x30000000 -#define SCCR_USBDRCM 0x00300000 -#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_USBDRCM 0x00c00000 +#define SCCR_USBDRCM_SHIFT 22 #define SCCR_USBDRCM_0 0x00000000 -#define SCCR_USBDRCM_1 0x00100000 -#define SCCR_USBDRCM_2 0x00200000 -#define SCCR_USBDRCM_3 0x00300000 +#define SCCR_USBDRCM_1 0x00400000 +#define SCCR_USBDRCM_2 0x00800000 +#define SCCR_USBDRCM_3 0x00c00000 -#define SCCR_PCIEXP1CM 0x00080000 -#define SCCR_PCIEXP2CM 0x00040000 +#define SCCR_PCIEXP1CM 0x00300000 +#define SCCR_PCIEXP2CM 0x000c0000 -#define SCCR_SATA1CM 0x0000c000 -#define SCCR_SATA1CM_SHIFT 14 -#define SCCR_SATACM 0x0000f000 -#define SCCR_SATACM_SHIFT 8 +#define SCCR_SATA1CM 0x00003000 +#define SCCR_SATA1CM_SHIFT 12 +#define SCCR_SATACM 0x00003c00 +#define SCCR_SATACM_SHIFT 10 #define SCCR_SATACM_0 0x00000000 -#define SCCR_SATACM_1 0x00005000 -#define SCCR_SATACM_2 0x0000a000 -#define SCCR_SATACM_3 0x0000f000 +#define SCCR_SATACM_1 0x00001400 +#define SCCR_SATACM_2 0x00002800 +#define SCCR_SATACM_3 0x00003c00 -#define SCCR_TDMCM 0x000000c0 -#define SCCR_TDMCM_SHIFT 6 +#define SCCR_TDMCM 0x00000030 +#define SCCR_TDMCM_SHIFT 4 #define SCCR_TDMCM_0 0x00000000 -#define SCCR_TDMCM_1 0x00000040 -#define SCCR_TDMCM_2 0x00000080 -#define SCCR_TDMCM_3 0x000000c0 +#define SCCR_TDMCM_1 0x00000010 +#define SCCR_TDMCM_2 0x00000020 +#define SCCR_TDMCM_3 0x00000030 #elif defined(CONFIG_MPC837X) /* SCCR bits - MPC837x specific */ -- 1.5.3.5.643.g40e25

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